Switching tube control circuit, switching tube control method and chip

Abstract

The invention discloses a switching tube control circuit which comprises at least one of a first pull-up branch, a first pull-down branch, a second pull-up branch and a second pull-down branch, and the first pull-up branch, the first pull-down branch, the second pull-up branch and the second pull-down branch operate or stop operating in response to an enable signal. When the first pull-up branch runs, a first pull-up current is output to charge the control end of the switching tube, when the first pull-down branch runs, a first pull-down current is output to discharge the control end of the switching tube, and when the second pull-up branch runs, a second pull-up current is output to charge the control end of the switching tube; the operation time of the second pull-up branch is shorter than that of the first pull-up branch, when the second pull-down branch operates, second pull-down current is output to discharge the control end of the switching tube, and the operation time of the second pull-down branch is shorter than that of the first pull-down branch. By means of the mode, independent control over the turn-on delay time and / or turn-off delay time of the switch tube can be achieved, and the system efficiency is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electronic circuits, and in particular to a switch control circuit, a switch control method, and a chip. Background Art

[0002] In the process of driving a transistor switch (such as a MOSFET switch), controlling the rise time, fall time, turn-on delay, and turn-off delay is of great significance, which can directly affect the speed and efficiency of the switch conversion. For example, shorter rise and fall times can reduce the losses during the switching process, thereby improving the system efficiency. Summary of the Invention

[0003] The embodiments of the present application provide a switch control circuit, a switch control method, and a chip, which can shorten the turn-on delay time and / or turn-off delay time of the switch to improve the system efficiency.

[0004] In a first aspect, the embodiments of the present application provide a switch control circuit. The first end and the second end of the non-control end of the switch are respectively connected to an input voltage bus and an output end, or the first end and the second end of the non-control end of the switch are respectively connected to the output end and the ground. The output end is connected to a load. The switch control circuit includes: a first pull-up branch, which is respectively connected to the control end of the switch and a driving power supply, and is configured to operate or stop operating in response to an enable signal. When the first pull-up branch operates, the first pull-up branch outputs a first pull-up current to charge the control end of the switch; a first pull-down branch, which is respectively connected to the control end of the switch, the second end of the non-control end of the switch, and the driving power supply, and is configured to operate or stop operating in response to the enable signal. When the first pull-down branch operates, the first pull-down branch outputs a first pull-down current to discharge the control end of the switch; at least one of a second pull-up branch and a second pull-down branch. The second pull-up branch is respectively connected to the control end of the switch, the second end of the non-control end of the switch, and the driving power supply. The second pull-up branch is configured to operate or stop operating in response to the enable signal. When the second pull-up branch operates, the second pull-up branch outputs a second pull-up current to charge the control end of the switch, and the operating time of the second pull-up branch is shorter than that of the first pull-up branch; the second pull-down branch is respectively connected to the control end of the switch, the second end of the non-control end of the switch, and the driving power supply. The second pull-down branch is configured to operate or stop operating in response to the enable signal. When the second pull-down branch operates, the second pull-down branch outputs a second pull-down current to discharge the control end of the switch, and the operating time of the second pull-down branch is shorter than that of the first pull-down branch.

[0005] In one or more embodiments, the second pull-up branch is further configured to start operating together with the first pull-up branch in response to the enable signal, and stop operating when the voltage difference between the control terminal of the switching transistor and the second terminal of the non-control terminal of the switching transistor is charged to a first preset voltage, so as to stop outputting the second pull-up current.

[0006] In one or more embodiments, the first preset voltage is greater than or equal to the turn-on threshold voltage of the switching transistor and less than or equal to the Miller plateau voltage of the switching transistor.

[0007] In one or more embodiments, the switching transistor control circuit includes a first current source and a first transistor, and the first pull-up branch includes a second transistor, a third transistor, a fourth transistor, and a first pull-up switch; the first current source is respectively connected to the third terminal of the first transistor, the first terminal of the first transistor, and the first terminal of the second transistor, the second terminals of the first transistor and the second transistor are both grounded, the third terminal of the second transistor is connected to the first terminal of the first pull-up switch, the second terminal of the first pull-up switch is respectively connected to the third terminal of the third transistor, the first terminal of the third transistor, and the first terminal of the fourth transistor, the second terminals of the third transistor and the fourth transistor are both connected to the driving power supply, and the third terminal of the fourth transistor is connected to the control terminal of the switching transistor; wherein, the first pull-up switch is controlled by the enable signal to be turned on or off.

[0008] In one or more embodiments, the second pull-up branch includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the first terminal of the fifth transistor is connected to the first terminal of the third transistor, the second terminal of the fifth transistor and the third terminal of the eighth transistor are both connected to the driving power supply, the third terminal of the fifth transistor is respectively connected to the third terminal of the sixth transistor, the first terminal of the sixth transistor, and the first terminal of the eighth transistor, the second terminal of the sixth transistor is respectively connected to the third terminal of the seventh transistor and the first terminal of the seventh transistor, the second terminal of the seventh transistor is connected to the second terminal of the non-control terminal of the switching transistor, and the second terminal of the eighth transistor is connected to the control terminal of the switching transistor.

[0009] In one or more embodiments, the switching transistor control circuit further includes a third pull-up branch;

[0010] The third pull-up branch is respectively connected to the second pull-up branch, the first end of the non-control end of the switching tube, and the second end of the non-control end of the switching tube. The third pull-up branch is configured to operate or stop operating in response to the enable signal. Wherein, when the third pull-up branch starts to operate, the third pull-up branch establishes a connection between the second pull-up branch and the second end of the non-control end of the switching tube, so that the second pull-up branch outputs the second pull-up current. During the operation of the third pull-up branch, when the voltage difference between the first end and the second end of the non-control end of the switching tube is less than the third preset voltage, the third pull-up branch disconnects the connection between the second pull-up branch and the second end of the non-control end of the switching tube, so that the second pull-up branch outputs the second pull-up current.

[0011] In one or more embodiments, the third pull-up branch includes a second pull-up switch and an eleventh transistor. The first end of the second pull-up switch is connected to the first end of the non-control end of the switching tube. The second end of the second pull-up switch is connected to the first end of the eleventh transistor. The second end of the eleventh transistor is connected to the second end of the non-control end of the switching tube. The third end of the eleventh transistor is connected to the second pull-up branch. Wherein, the pull-up switch is controlled by the enable signal to conduct or turn off.

[0012] In one or more embodiments, the second pull-up branch includes a ninth transistor, a tenth transistor, a first switch, and a first comparator. The first end of the ninth transistor is connected to the first end of the third transistor. The second end of the ninth transistor and the third end of the tenth transistor are both connected to the driving power supply. The third end of the ninth transistor is connected to the first end of the first switch. The second end of the first switch is connected to the first end of the tenth transistor. The second end of the tenth transistor is connected to the control end of the switching tube and the inverting input end of the first comparator. The non-inverting input end of the first comparator inputs the sum of the first preset voltage and the voltage of the second end of the non-control end of the switching tube. The output end of the first comparator outputs a signal for controlling the first switch, and the first switch conducts when the first comparator outputs a high level.

[0013] In one or more embodiments, the second pull-down branch is further configured to start operating together with the first pull-down branch in response to the enable signal, and stop operating when the control end of the switching tube is discharged until the voltage difference between the control end of the switching tube and the second end of the non-control end of the switching tube is equal to the second preset voltage, so as to stop outputting the second pull-down current.

[0014] In one or more embodiments, the second preset voltage is greater than or equal to the Miller plateau voltage of the switching tube.

[0015] In one or more embodiments, the second preset voltage is less than twice the turn-on threshold voltage of the switching transistor.

[0016] In one or more embodiments, the switching transistor control circuit includes a first current source and a first transistor, and the first pull-down branch includes a pull-down switch, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor; the first current source is respectively connected to the third terminal of the first transistor, the first terminal of the first transistor, and the first terminal of the twelfth transistor, the second terminals of the first transistor and the twelfth transistor are both grounded, the third terminal of the twelfth transistor is connected to the first terminal of the pull-down switch, the second terminal of the pull-down switch is respectively connected to the third terminal of the thirteenth transistor, the first terminal of the thirteenth transistor, and the first terminal of the fourteenth transistor, the second terminals of the thirteenth transistor and the fourteenth transistor are both connected to the driving power supply, the third terminal of the fourteenth transistor is respectively connected to the third terminal of the fifteenth transistor, the first terminal of the fifteenth transistor, and the first terminal of the sixteenth transistor, the second terminals of the fifteenth transistor and the sixteenth transistor are both connected to the second terminal of the non-control end of the switching transistor, and the third terminal of the sixteenth transistor is connected to the control end of the switching transistor; wherein, the second pull-down switch is controlled by the enable signal to be turned on or off.

[0017] In one or more embodiments, the second pull-down branch includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; the first terminal of the seventeenth transistor is connected to the first terminal of the thirteenth transistor, the second terminal of the seventeenth transistor is connected to the driving power supply, the third terminal of the seventeenth transistor is connected to the third terminal of the eighteenth transistor, the second terminal of the eighteenth transistor is respectively connected to the third terminal of the nineteenth transistor, the first terminal of the nineteenth transistor, and the first terminal of the twentieth transistor, the second terminals of the nineteenth transistor and the twentieth transistor are both connected to the second terminal of the non-control end of the switching transistor, and the third terminal of the twentieth transistor is respectively connected to the first terminal of the eighteenth transistor and the control end of the switching transistor.

[0018] In one or more embodiments, the second pull-down branch includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a second switch, and a second comparator; a first end of the twenty-first transistor is connected to a first end of the thirteenth transistor, a second end of the twenty-first transistor is connected to the driving power supply, a third end of the twenty-first transistor is connected to a first end of the second switch, a second end of the second switch is respectively connected to a third end of the twenty-second transistor, a first end of the twenty-second transistor, and a first end of the twenty-third transistor, a second end of the twenty-second transistor and a second end of the twenty-third transistor are both connected to a second end of a non-control end of the switching transistor, a third end of the twenty-third transistor is respectively connected to a non-inverting input terminal of the second comparator and a control end of the switching transistor, a sum of the second preset voltage and a voltage of the second end of the non-control end of the switching transistor is input to an inverting input terminal of the second comparator, a signal for controlling the second switch is output from an output terminal of the second comparator, and the second switch is turned on when the second comparator outputs a high level.

[0019] In a second aspect, an embodiment of the present application provides a method for controlling a switching transistor. A first end and a second end of a non-control end of the switching transistor are respectively connected to an input voltage bus and an output terminal, or the first end and the second end of the non-control end of the switching transistor are respectively connected to the output terminal and the ground, and the output terminal is connected to a load. The method for controlling the switching transistor includes: obtaining an enable signal; when the enable signal is converted to a first level, starting to output a first pull-up current and a second pull-up current to charge a control end of the switching transistor together; when the enable signal is converted to a second level, starting to output a first pull-down current and a second pull-down current to discharge the control end of the switching transistor together; when the enable signal is at the first level, stopping outputting the second pull-up current during a process of charging the control end of the switching transistor by outputting the first pull-up current, and / or when the enable signal is at the second level, stopping outputting the second pull-down current during a process of discharging the control end of the switching transistor by outputting the second pull-down current.

[0020] In one or more embodiments, the method further includes: after starting to output the second pull-up current to charge the control end of the switching transistor, when a voltage difference between the control end of the switching transistor and a second end of the non-control end of the switching transistor is equal to a first preset voltage, stopping charging the control end of the switching transistor through the second pull-up current, where the first preset voltage is less than or equal to a Miller plateau voltage of the switching transistor and greater than a turn-on threshold voltage of the switching transistor.

[0021] In one or more embodiments, the method further includes: starting to output the second pull-up current to charge the control terminal of the switching transistor at a moment when the voltage difference between the first end and the second end of the non-control terminal of the switching transistor is less than a third preset voltage during a period when the enabling signal is at a first level.

[0022] In one or more embodiments, the method further includes: after starting to output the second pull-down current to discharge the control terminal of the switching transistor, stopping discharging the control terminal of the switching transistor through the second pull-down current when the voltage difference between the control terminal of the switching transistor and the second end of the non-control terminal of the switching transistor is equal to a second preset voltage, where the second preset voltage is greater than or equal to the Miller plateau voltage of the switching transistor.

[0023] In one or more embodiments, the second preset voltage is less than twice the turn-on threshold voltage of the switching transistor.

[0024] In a third aspect, an embodiment of the present application provides a chip, including a switching transistor and the switching transistor control circuit as described above.

[0025] The beneficial effects of the present application are as follows: In the switching transistor control circuit of the embodiment of the present application, the first end and the second end of the non-control end of the switching transistor are respectively connected to the input voltage bus and the output end, or the first end and the second end of the non-control end of the switching transistor are respectively connected to the output end and the ground, and the output end is connected to the load. The switching transistor control circuit includes a first pull-up branch and a first pull-down branch. The first pull-up branch is respectively connected to the control end of the switching transistor and the driving power supply, and is configured to operate or stop operating in response to an enable signal. Among them, when the first pull-up branch operates, the first pull-up branch outputs a first pull-up current to charge the control end of the switching transistor. The first pull-down branch is respectively connected to the control end of the switching transistor, the second end of the non-control end of the switching transistor, and the driving power supply, and is configured to operate or stop operating in response to an enable signal. Among them, when the first pull-down branch operates, the first pull-down branch outputs a first pull-down current to discharge the control end of the switching transistor. When the switching transistor control circuit further includes a second pull-up branch, the second pull-up branch is respectively connected to the control end of the switching transistor, the second end of the non-control end of the switching transistor, and the driving power supply. The second pull-up branch is configured to operate or stop operating in response to an enable signal. Among them, when the second pull-up branch operates, the second pull-up branch outputs a second pull-up current to charge the control end of the switching transistor, and the operating time of the second pull-up branch is shorter than that of the first pull-up branch. Thus, the conduction delay time of the switching transistor can be shortened, and the conduction delay time of the switching transistor can be made controllable. When the switching transistor control circuit further includes a second pull-down branch, the second pull-down branch is respectively connected to the control end of the switching transistor, the second end of the non-control end of the switching transistor, and the driving power supply. The second pull-down branch is configured to operate or stop operating in response to an enable signal. Among them, when the second pull-down branch operates, the second pull-down branch outputs a second pull-down current to discharge the control end of the switching transistor, and the operating time of the second pull-down branch is shorter than that of the first pull-down branch. Thus, the turn-off delay time of the switching transistor can be shortened, and the turn-off delay time of the switching transistor can be made controllable. It can be seen that through the above method, the conduction delay time and / or the turn-off delay time of the switching transistor can be shortened to improve the system efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations are not intended to limit the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements.

[0027] Figure 1 is a schematic diagram of the composition block diagram of the switching transistor control circuit provided by the embodiment of the present application Figure 1 ;

[0028] Figure 2 is a schematic diagram of the composition block diagram of the switching transistor control circuit provided by the embodiment of the present application Figure 2 ;

[0029] Figure 3 Schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application Figure 1 ;

[0030] Figure 4 Schematic diagram of the composition block diagram of the switch tube control circuit provided by an embodiment of the present application Figure 3 ;

[0031] Figure 5 Schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application Figure 2 ;

[0032] Figure 6 Schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application Figure 3 ;

[0033] Figure 7 Is related to Figure 4 Schematic diagram of the corresponding circuit structure of the switch tube control circuit shown

[0034] Figure 8 Is provided by an embodiment of the present application in Figure 7 Schematic diagram of the circuit structure when the second pull-up branch, the second pull-down branch and the third pull-up branch are removed based on the shown circuit structure

[0035] Figure 9 Is provided by an embodiment of the present application Figure 8 Schematic diagram of each signal in the shown circuit structure

[0036] Figure 10 Is provided by an embodiment of the present application Figure 7 Schematic diagram of each signal in the shown circuit structure

[0037] Figure 11 Schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application Figure 4 ;

[0038] Figure 12 Schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application Figure 5 ;

[0039] Figure 13 Schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application Figure 6 ;

[0040] Figure 14 Schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application Figure 7 ;

[0041] Figure 15It is a schematic diagram of a partial circuit structure of the switch tube control circuit provided by an embodiment of the present application. Figure 8 ;

[0042] Figure 16 It is a flowchart of the switch tube control method provided by an embodiment of the present application. Detailed implementation manners

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and detailedly described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] It should be noted that when an element is expressed as "connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween.

[0045] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0046] Please refer to Figure 1 , Figure 1 which is a schematic diagram of the composition block diagram of the switch tube control circuit provided by an embodiment of the present application. As Figure 1 shown, taking the switch tube Q1 as the high-side switch as an example, the first end and the second end of the non-control end of the switch tube Q1 are respectively connected to the input voltage bus V BB and the output terminal V OUT is connected, and the output terminal V OUT is connected to the load 200, that is, the load 200 is connected between the output terminal V OUT and the ground GND. In this embodiment, taking the load 200 including the resistor R OUT connected in series with the inductor L OUT as an example. Among them, in the embodiment of the present application, taking the switch tube Q1 as an NMOS transistor as an example, the control end of the switch tube Q1 is the gate of the NMOS transistor, the first end of the non-control end of the switch tube Q1 is the drain of the NMOS transistor, and the second end of the non-control end of the switch tube Q1 is the source of the NMOS transistor. In addition, the switch tube Q1 can be any controllable switch, for example, an insulated gate bipolar transistor (IGBT) device, an integrated gate-commutated thyristor (IGCT) device, a gate turn-off thyristor (GTO) device, etc.

[0047] The switch tube control circuit 100 includes a first pull-up branch 10 and a first pull-down branch 20. The first pull-up branch 10 is respectively connected to the control end of the switch tube Q1 and the driving power supply V CP connected, where, takingFigure 1 Taking the switch Q1 in it as a high-side switch as an example, the driving power supply V CP is the input voltage bus V BB is a voltage source whose voltage value obtained by boosting through a charge pump is higher than the input voltage bus by at least the on-voltage threshold Vth of one switching transistor Q1. The first pull-up branch 10 is configured to operate or stop operating in response to the enable signal EN (for example, configuring the first pull-up branch 10 to operate when the enable signal EN is at a high level and stop operating when the enable signal EN is at a low level). Among them, when the first pull-up branch 10 is operating, the first pull-up branch 10 outputs a first pull-up current I c to charge the control terminal of the switching transistor Q1 to turn on the switching transistor Q1. The first pull-down branch 20 is respectively connected to the control terminal of the switching transistor Q1, the second end of the non-control terminal of the switching transistor Q1, and the driving power supply V CP and is connected. The first pull-down branch 20 is configured to operate or stop operating in response to the enable signal EN (for example, configuring the first pull-down branch 10 to operate when the enable signal EN is at a low level, that is, when the inverted signal of the enable signal EN is at a high level, and stop operating when the enable signal EN is at a high level, that is, when the inverted signal of the enable signal EN is at a low level). Among them, when the first pull-down branch 20 is operating, the first pull-down branch 20 outputs a first pull-down current I d to discharge the control terminal of the switching transistor Q1.

[0048] It can be understood that when the first pull-up branch 10 operates in response to the enable signal EN, the first pull-down branch 20 stops operating in response to the enable signal EN (in some embodiments, specifically, the first pull-down branch 20 stops operating in response to the inverted signal of the enable signal EN); when the first pull-up branch 10 stops operating in response to the enable signal EN, the first pull-down branch 20 operates in response to the enable signal EN (in some embodiments, specifically, the first pull-down branch 20 operates in response to the inverted signal of the enable signal EN).

[0049] When the switching transistor control circuit 100 further includes a second pull-up branch 30, the second pull-up branch 30 is respectively connected to the control terminal of the switching transistor Q1, the second end of the non-control terminal of the switching transistor Q1, and the driving power supply V CPis connected, and the second pull-up branch 30 is configured to operate or stop operating in response to the enable signal EN. (For example, in some embodiments, the second pull-up branch 30 can be configured to start operating when the enable signal EN transitions to a high level; after the second pull-up branch 30 starts operating, the second pull-up branch 30 can be stopped by configuring the enable signal EN to a low level, or the second pull-up branch 30 can be stopped in other ways. For example, after the second pull-up branch 30 starts operating, the enable signal EN remains at a high level, but the second pull-up branch 30 can automatically stop operating after operating for a period of time.). Wherein, when the second pull-up branch 30 is operating, the second pull-up branch 30 outputs a second pull-up current I c1 charges the control terminal of the switching transistor Q1 to turn on the switching transistor Q1. Thus, due to the presence of the first pull-up current I c and the second pull-up current I c1 simultaneously charging the control terminal of the switching transistor Q1, the turn-on delay time of the switching transistor Q1 can be shortened. At the same time, if the operating time of the second pull-up branch 30 is shorter than the operating time of the first pull-up branch 10, the turn-on delay time of the switching transistor Q1 can be independently adjusted by adjusting the operating time of the second pull-up branch 30 without affecting other switching characteristic parameters of the switching transistor Q1 (such as the drain-source voltage V DS and the fall time Tf of the switching transistor Q1, etc.). Thus, the turn-on delay time of the switching transistor Q1 can be independently controlled. In some embodiments, in response to the enable signal EN, the first pull-up branch 10 and the second pull-up branch 30 start operating simultaneously.

[0050] When the switching transistor control circuit 100 further includes a second pull-down branch 40, the second pull-down branch 40 is respectively connected to the control terminal of the switching transistor Q1, the second end of the non-control terminal of the switching transistor Q1, and the drive power supply V CP is connected, and the second pull-down branch 40 is configured to operate or stop operating in response to the enable signal EN. (For example, in some embodiments, the second pull-down branch 40 can be configured to start operating when the enable signal EN transitions to a low level; after the second pull-down branch 40 starts operating, the second pull-down branch 40 can be stopped by configuring the enable signal EN to a high level, or the second pull-down branch 40 can be stopped in other ways. For example, after the second pull-down branch 40 starts operating, the enable signal EN remains at a low level, but the second pull-down branch 40 can automatically stop operating after operating for a period of time.). Wherein, when the second pull-down branch 40 is operating, the second pull-down branch 40 outputs a second pull-down current I d1 discharges the control terminal of the switching transistor Q1 to turn off the switching transistor Q1. Thus, due to the presence of the first pull-down current I d and the second pull-down current I d1Meanwhile, the control terminal of the switching transistor Q1 is discharged, so that the turn-off delay time of the switching transistor Q1 can be shortened. At the same time, the operating time of the second pull-down branch 40 is shorter than that of the first pull-down branch 20, so that the turn-off delay time of the switching transistor Q1 can be independently adjusted by adjusting the operating time of the second pull-down branch 40 without affecting other switching characteristic parameters of the switching transistor Q1 (such as the rise time Tr of the drain-source voltage V DS of the switching transistor Q1, etc.), so that the turn-off delay time of the switching transistor Q1 is independently controllable. In some embodiments, in response to the enable signal EN, the first pull-down branch 20 and the second pull-down branch 40 start operating simultaneously.

[0051] Through the above process, the turn-on delay time and / or the turn-off delay time of the switching transistor Q1 can be shortened to improve the system efficiency. Moreover, the turn-on delay time and / or the turn-off delay time of the switching transistor Q1 can be made independently controllable.

[0052] It can be understood that the switching transistor control circuit 100 of the embodiments of the present application can be used not only to control the switching transistor Q1 disposed between the input voltage bus V BB and the output terminal V OUT , but also to control the switching transistor Q1 disposed between the output terminal V OUT and the ground GND. At this time, the load 200 is connected between the input voltage bus V BB and the output terminal V OUT . As shown in Figure 2 , the first end and the second end of the non-control terminal of the switching transistor Q1 are respectively connected to the output terminal V OUT and the ground GND. Figure 2 The working process of the block diagram shown is the same as that of Figure 1 , and will not be elaborated here.

[0053] In some embodiments, the second pull-up branch 20 is further configured to start operating together with the first pull-up branch 10 in response to the enable signal EN, and stop operating when the voltage difference between the control terminal of the switching transistor Q1 and the second end of the non-control terminal of the switching transistor Q1 is equal to the first preset voltage, so as to stop outputting the second pull-up current I c1 .

[0054] Specifically, by stopping the second pull-up branch 20 from outputting the second pull-up current I c1 in advance, while shortening the turn-on delay time of the switching transistor Q1, the second pull-up current I c1 is prevented from having an adverse effect on the subsequent conduction process in the switching transistor Q1.

[0055] Among them, the first preset voltage can be set based on the actual application scenario, and the embodiments of the present application do not make specific limitations thereto.

[0056] For example, in some embodiments, the first preset voltage is greater than or equal to the conduction threshold voltage of the switch tube Q1 and less than or equal to the Miller platform voltage of the switch tube Q1. By configuring the first preset voltage to be greater than or equal to the conduction threshold voltage of the switch tube Q1 and less than or equal to the Miller platform voltage of the switch tube Q1, the second pull-up branch 30 can stop working before the voltage difference between the control end of the switch tube Q1 and the second end of the non-control end of the switch tube Q1 rises to the Miller platform voltage, that is, stop outputting the second pull-up current I c1 , the second pull-up current I c1 Therefore, the voltage difference between the control end of the switch tube Q1 and the second end of the non-control end of the switch tube Q1 will not act on the switch tube Q1 during the period when the voltage difference between the control end of the switch tube Q1 and the second end of the non-control end of the switch tube Q1 is in the Miller platform voltage, thereby not affecting the rise time of the switch tube Q1 during the conduction process, and not affecting the electromagnetic interference EMI (Electromagnetic Interference) performance of the switch tube Q1 during the switching process.

[0057] Please refer to Figure 3 , Figure 3 A schematic diagram showing a partial circuit structure of a switch tube control circuit 100 is shown as an example. Figure 3 Take the circuit structure of the high-side switch of the switch tube Q1 as an example, wherein the switch tube Q1 is arranged at the input voltage bus V BB And the output terminal V OUT Between. Figure 3 As shown, the switch control circuit 100 includes a first current source I 1 With the first transistor M 1 The first pull-up branch 10 includes a second transistor M 2 , the third transistor M 3 , the fourth transistor M 4 With the first pull-up switch S 1 .

[0058] The first current source I 1 Respectively with the first transistor M 1 The third terminal of the first transistor M 1 The first end and the second transistor M 2 The first end of the first transistor M is connected 1 The second end of the second transistor M 2 The second ends of the second transistor M are grounded to GND. 2 The third terminal of the first pull-up switch S 1 The first end of the first pull-up switch S 1 The second end of the third transistor M 3 The third terminal of the third transistor M 3 The first end of the fourth transistor M 4is connected to the first end, and the third transistor M 3 The second end of and the fourth transistor M 4 The second ends of are all connected to the driving power supply V CP is connected, and the third end of the fourth transistor M 4 is connected to the control end of the switching transistor Q1. Among them, the first pull-up switch S 1 is turned on or off under the control of the enable signal EN.

[0059] In this embodiment, the second pull-up branch 30 includes the fifth transistor M 5 , the sixth transistor M 6 , the seventh transistor M 7 and the eighth transistor M 8 .

[0060] The first end of the fifth transistor M 5 is connected to the first end of the third transistor M 3 , the second end of the fifth transistor M 5 and the third end of the eighth transistor M 8 are all connected to the driving power supply V CP is connected, and the third end of the fifth transistor M 5 is respectively connected to the third end of the sixth transistor M 6 , the first end of the sixth transistor M 6 and the first end of the eighth transistor M 8 is connected, and the second end of the sixth transistor M 6 is respectively connected to the third end of the seventh transistor M 7 and the first end of the seventh transistor M 7 is connected, the second end of the seventh transistor M 7 is connected to the second end of the non-control end of the switching transistor Q1, and the second end of the eighth transistor M 8 is connected to the control end of the switching transistor Q1.

[0061] In some embodiments, as Figure 4 shown, the switching transistor control circuit 100 further includes a third pull-up branch 50. Among them, this embodiment takes adding the third pull-up branch 50 to the structure shown in Figure 1 as an example. The third pull-up branch 50 is respectively connected to the second pull-up branch 30, the first end of the non-control end of the switching transistor Q1 and the second end of the non-control end of the switching transistor Q1, and the third pull-up branch 50 is configured to operate or stop operating in response to the enable signal EN.

[0062] When the third pull-up branch 50 starts to operate, the third pull-up branch 50 establishes a connection between the second pull-up branch 30 and the second end of the non-control end of the switch tube Q1, so that the second pull-up branch 30 outputs a second pull-up current. During the operation of the third pull-up branch 50, when the voltage difference between the first end of the non-control end of the switch tube Q1 and the second end of the non-control end of the switch tube Q1 is less than a third preset voltage (such as when the switch tube Q1 is completely turned on), the third pull-up branch 50 disconnects the connection between the second pull-up branch 30 and the second end of the non-control end of the switch tube Q1, so that the second pull-up branch 30 outputs a second pull-up current I c1 The third preset voltage may be set based on the actual application scenario, and the present application embodiment does not impose any specific limitation on this. In some embodiments, in response to the enable signal EN, the first pull-up branch 10, the second pull-up branch 30 and the third pull-up branch 50 operate simultaneously.

[0063] Specifically, on the one hand, when the third pull-up branch 50 starts to operate, the first pull-up branch 10 and the second pull-up branch 30 also start to operate. Since the third pull-up branch 50 establishes a connection between the second pull-up branch 30 and the second end of the non-control end of the switch tube Q1, there is a first pull-up current I c With the second pull-up current I c1 At the same time, the control end of the switch tube Q1 is charged, so the turn-on delay time of the switch tube Q1 can be shortened. On the other hand, during the operation of the third pull-up branch 50, the second pull-up branch 30 will stop operating and stop outputting the second pull-up current earlier than the first pull-up branch 30. After the second pull-up branch 30 stops operating, if the voltage difference between the first end of the non-control end of the switch tube Q1 and the second end of the non-control end of the switch tube Q1 is less than the third preset voltage, the third pull-up branch 50 disconnects the second pull-up branch 30 from the second end of the non-control end of the switch tube Q1, so that the second pull-up branch 30 starts to output the second pull-up current I again. c1 , which can achieve the purpose of reducing the conduction loss of the switch tube Q1 during the conduction process.

[0064] Please refer to Figure 5 , Figure 5 An example is shown in Figure 3 The schematic diagram of the circuit structure in which the third pull-up branch 50 is added to the circuit structure shown in FIG. Figure 5 As shown, the third pull-up branch 50 includes a second pull-up switch S C1 With the eleventh transistor M 11 .

[0065] The second pull-up switch S C1 The first end of the second pull-up switch S C1 The second end of the eleventh transistor M 11is connected to the first end, and the eleventh transistor M 11 is connected to the second end of the non-control end of the switching transistor Q1, and the eleventh transistor M 11 is connected to the second pull-up branch 30 at its third end. Among them, the second pull-up switch S C1 is controlled to conduct or turn off by the enable signal EN. In some embodiments, in response to the enable signal EN, the second pull-up switch S C1 and the first pull-up switch S 1 conduct simultaneously (corresponding to the third pull-up branch 50 and the first pull-up branch 10 starting to operate simultaneously).

[0066] It can be understood that the second pull-down branch 40 may have a configuration similar to that of the second pull-up branch 30. Specifically, in some embodiments, the second pull-down branch 40 is further configured to start operating together with the first pull-down branch 20 in response to the enable signal EN, and stop operating when the voltage difference between the control end of the switching transistor Q1 and the second end of the non-control end of the switching transistor Q1 is discharged to equal the second preset voltage, so as to stop outputting the second pull-down current I d1 .

[0067] Specifically, by making the second pull-down branch 40 stop outputting the second pull-down current I in advance d1 , while shortening the turn-off delay time of the switching transistor Q1, it can prevent the second pull-down current I d1 from having an adverse effect on the subsequent turn-off process of the switching transistor Q1.

[0068] Among them, the second preset voltage can be set based on the actual application scenario, and the embodiments of the present application do not make specific limitations on this.

[0069] For example, in some embodiments, the second preset voltage is greater than or equal to the Miller plateau voltage of the switching transistor Q1. In other embodiments, the second preset voltage is less than twice the turn-on threshold voltage of the switching transistor Q1. By configuring the second preset voltage to be greater than or equal to the Miller plateau voltage of the switching transistor Q1 and, at the same time, the second preset voltage is less than twice the turn-on threshold voltage of the switching transistor Q1, it can be ensured that the second pull-down branch 40 is turned off before the voltage difference between the control end of the switching transistor Q1 and the second end of the non-control end of the switching transistor Q1 drops to the Miller plateau voltage, and the second pull-down current I d1 will not act on the switching transistor Q1 during the period when the voltage difference between the control end of the switching transistor Q1 and the second end of the non-control end of the switching transistor Q1 is at the Miller plateau voltage, thus not affecting the EMI performance during the turn-off process of the switching transistor Q1.

[0070] Please refer to Figure 6 , Figure 6 which exemplarily shows a schematic diagram of a partial circuit structure of the switching transistor control circuit 100. Figure 6Taking the switching transistor Q1 as the high-side switch as an example, where the switching transistor Q1 is disposed in the circuit structure between the input voltage bus V BB and the output terminal V OUT . As shown in Figure 6 , the switching transistor control circuit 100 includes a first current source I 1 and a first transistor M 1 . The first pull-down branch 20 includes a pull-down switch S 2 , a twelfth transistor M 12 , a thirteenth transistor M 13 , a fourteenth transistor M 14 , a fifteenth transistor M 15 and a sixteenth transistor M 16 .

[0071] The first current source I 1 is respectively connected to the third terminal of the first transistor M 1 , the first terminal of the first transistor M 1 and the first terminal of the twelfth transistor M 12 . The second terminal of the first transistor M 1 and the second terminal of the twelfth transistor M 12 are both grounded to GND. The third terminal of the twelfth transistor M 12 is connected to the first terminal of the pull-down switch S 2 . The second terminal of the pull-down switch S 2 is respectively connected to the third terminal of the thirteenth transistor M 13 , the first terminal of the thirteenth transistor M 13 and the first terminal of the fourteenth transistor M 14 . The second terminal of the thirteenth transistor M 13 and the second terminal of the fourteenth transistor M 14 are both connected to the driving power supply V CP . The third terminal of the fourteenth transistor M 14 is respectively connected to the third terminal of the fifteenth transistor M 15 , the first terminal of the fifteenth transistor M 15 and the first terminal of the sixteenth transistor M 16 . The second terminal of the fifteenth transistor M 15 and the second terminal of the sixteenth transistor M 16 are both connected to the second terminal of the non-control end of the switching transistor Q1. The third terminal of the sixteenth transistor M 16 is connected to the control end of the switching transistor Q1. Among them, the pull-down switch S 2 is controlled by the enable signal EN to be turned on or off. In some embodiments, when the first pull-up switch S 1 is turned on under the control of the enable signal EN, the pull-down switch S 2 is controlled by the inverted signal of the enable signal EN is turned off; when the first pull-up switch S 1 is turned off under the control of the enable signal EN, the pull-down switch S 2 is controlled by the inverted signal of the enable signal EN and is turned on.

[0072] In this embodiment, the second pull-down branch 40 includes the seventeenth transistor M 17 , the eighteenth transistor M 18 , the nineteenth transistor M 19 and the twentieth transistor M 20 .

[0073] The first end of the seventeenth transistor M 17 is connected to the first end of the thirteenth transistor M 13 . The second end of the seventeenth transistor M 17 is connected to the driving power supply V CP . The third end of the seventeenth transistor M 17 is connected to the third end of the eighteenth transistor M 18 . The second end of the eighteenth transistor M 18 is respectively connected to the third end of the nineteenth transistor M 19 , the first end of the nineteenth transistor M 19 and the first end of the twentieth transistor M 20 . The second end of the nineteenth transistor M 19 and the second end of the twentieth transistor M 20 are both connected to the second end of the non-control end of the switching transistor Q1. The third end of the twentieth transistor M 20 is respectively connected to the first end of the eighteenth transistor M 18 and the control end of the switching transistor Q1.

[0074] Combining Figure 5 with Figure 6 the circuit structure shown, the circuit structure shown in Figure 7 can be obtained. Figure 7 The circuit structure shown corresponds to the block diagram shown in Figure 4 . Removing the second pull-up branch 30, the second pull-down branch 40 and the third pull-up branch 50 from the circuit structure shown in Figure 7 , the circuit structure shown in Figure 8 can be obtained, which is the basic structure of the switching transistor drive circuit in the prior art.

[0075] The following will combine Figure 9 the schematic diagrams of the respective signals shown to illustrate the Figure 8 operating principle shown; and combine Figure 10 the schematic diagrams of the respective signals shown to illustrate the Figure 7The working principle shown will be described. Among them, Figure 9 Exemplarily shows Figure 8 A schematic diagram of each signal in the circuit structure shown, Figure 10 Exemplarily shows Figure 7 A schematic diagram of each signal in the circuit structure shown. As Figure 9 And Figure 10 Shown, in the vertical direction from top to bottom are the enable signal EN, the current I flowing through the switching transistor Q1 DS , the voltage difference V between the first end and the second end of the non-control end of the switching transistor Q1 DS (which is also the drain-source voltage V of the switching transistor Q1 DS ), the voltage difference V between the control end of the switching transistor Q1 and the second end of the non-control end of the switching transistor Q1 GS (which is also the gate-source voltage V of the switching transistor Q1 GS ), the current I at the control end of the switching transistor Q1 G , the power loss P on the switching transistor Q1 LOSS .

[0076] As Figure 8 And Figure 9 Shown, at time t0, the enable signal EN is at a low level, the gate-source voltage V of the switching transistor Q1 GS is 0, the switching transistor Q1 is in the off state, and the current I flowing through the switching transistor Q1 DS is also 0. At time t1, the enable signal EN converts to a high level, the first pull-up switch S 1 is controlled to conduct (the pull-down switch S 2 remains off), and the first pull-up branch 10 starts to output a fixed first pull-up current I c to charge the gate of the switching transistor Q1 (that is, the current I at the control end of the switching transistor Q1 G is the first pull-up current I c ). The gate-source voltage V of the switching transistor Q1 GS rises linearly, and the slope of its voltage rise is determined by the parasitic capacitance of the gate of the switching transistor Q1 and the first pull-up current I c . Among them, the parasitic capacitance of the gate of the switching transistor Q1 is composed of the parasitic capacitance between the gate and the drain of the switching transistor Q1 and the parasitic capacitance between the gate and the source of the switching transistor Q1. Until time t2, the gate-source voltage V of the switching transistor Q1 GS reaches the conduction threshold voltage V of the switching transistor Q1 GSth , the switching transistor Q1 starts to conduct, and the current I flowing through the switching transistor Q1 DS gradually increases from 0 as the gate-source voltage V GS increases. At time t3, the gate-source voltage V GS increases to the Miller Plateau voltage V GSp, the drain-source voltage V of the switching transistor Q1 DS begins to decline. The time interval from time t1 to time t3 can be expressed as:

[0077] Td_on = t3 - t1 = Ciss * V GSp / I c = (C GS + C GD ) * V GSp / I c (1).

[0078] Among them, Ciss is the capacitance value of the parasitic capacitance of the gate of the switching transistor Q1, C GS is the capacitance value of the parasitic capacitance between the gate and the drain of the switching transistor Q1, C GD is the capacitance value of the parasitic capacitance between the gate and the source of the switching transistor Q1. In practical applications, the period from when the enable signal EN transitions to a high level (i.e., time t1) to when the drain-source voltage V of the switching transistor Q1 DS begins to decline can be defined as the turn-on delay Td_on of the switching transistor Q1.

[0079] The gate-source voltage V of the switching transistor Q1 GS increases to the Miller plateau voltage V GSp and then no longer rises until the first pull-up current I c charges the voltage across the parasitic capacitance between the gate and the source of the switching transistor Q1 from V GSp - V BB to V GSp up to, i.e., time t4. During the period from time t3 to time t4, the drain-source voltage V of the switching transistor Q1 DS linearly declines from V BB . In practical applications, the period from time t3 to time t4 can be defined as the fall time Tf of the switching transistor Q1, which can be expressed as:

[0080] Tf = t4 - t3 = C GD * V BB / I c (2).

[0081] During the time interval from time t4 to time t5, the first pull-up current I c continues to charge the gate of the switching transistor Q1. The gate-source voltage V of the switching transistor Q1 GS rises linearly, and the on-resistance of the switching transistor Q1 further decreases until time t5 when the gate-source voltage of the switching transistor Q1 reaches V GS_MAX , approximately equal to the difference between the voltage of the driving power supply V CP and the voltage of the input voltage bus V BB .

[0082] The process of the switching transistor Q1 turning off starts at time t6. At this time, the enable signal EN transitions to a low level, pulling down the switch S 2 is controlled to conduct (the first pull-up switch S 1 is controlled to turn off), so that the first pull-down branch 20 outputs a first pull-down current I d and starts to discharge the gate of the switching transistor Q1 (that is, the current I G at the control terminal of the switching transistor Q1 at this time is the first pull-down current I d , and the direction is opposite to the first pull-up current I c , so it is denoted as -I d ). As the gate-source voltage V GS of the switching transistor Q1 decreases, the on-resistance of the switching transistor Q1 also slowly increases. At time t7, the gate-source voltage V GS of the switching transistor Q1 drops to the Miller plateau voltage V GSp , and the drain-source voltage V DS of the switching transistor Q1 starts to rise. In practical applications, the period from the time when the enable signal EN transitions to a low level (i.e., time t6) to the time when the drain-source voltage V DS of the switching transistor Q1 starts to rise rapidly can be defined as the turn-off delay Td_off of the switch. The time interval from time t6 to time t7 can be expressed as:

[0083] Td_off = t7 - t6 = Ciss * (V BB - V GSp ) / I d = (C GS + C GD ) * (V BB - V GSp ) / I d (3).

[0084] After the gate-source voltage V GS of the switching transistor Q1 drops to the Miller plateau voltage V GSp , it no longer continues to decrease until the first pull-down current I d charges the voltage across the parasitic capacitance between the gate and source of the switching transistor Q1 from -V GSp to V BB - V GSp (i.e., time t8). During the period from time t7 to time t8, the drain-source voltage V DS of the switching transistor Q1 linearly increases to V BB . In practical applications, the period from time t7 to time t8 is defined as the rise time Tr of the switching transistor Q1 and can be expressed as:

[0085] Tr = t8 - t7 = C GD * V BB / Id (4).

[0086] During the time interval from time t8 to time t10, the first pull-down current I d continues to discharge the gate of the switching transistor Q1, and the current I flowing through the switching transistor Q1 DS decreases linearly as the gate-source voltage V GS of the switching transistor Q1 decreases. Until time t9, as the gate-source voltage V GS decreases to the conduction threshold voltage V GSth of the switching transistor Q1, the switching transistor Q1 turns off, and the current I flowing through the switching transistor Q1 DS drops to 0. After that, the gate-source voltage V GS continues to decrease and drops to 0 at time t10, completing the turn-off.

[0087] From the perspective of loss analysis, Figure 8 the P LOSS curve depicts the losses at each stage during the conduction and turn-off processes of the switching transistor Q1. Among them, during the time periods from time t2 to time t4 and from time t7 to time t8, since the switching transistor Q1 is in the conduction and turn-off processes, the current I DS flowing through the switching transistor Q1 and the drain-source voltage V DS of the switching transistor are both non-zero, switching losses will occur. To reduce the switching losses, the switching speed of the switching transistor Q1 can be increased by increasing the current at the control terminal of the switching transistor Q1, so as to reduce the energy loss during each switching process.

[0088] During the time interval from time t4 to time t7, the switching transistor Q1 is already conducting, and the main loss is the conduction loss, which can be expressed as I DS *R DS_ON , where R DS_ON is the on-resistance of the switching transistor Q1. Among them, during the time period from time t4 to time t5, the gate-source voltage V GS of the switching transistor Q1 is still increasing, and the on-resistance of the switching transistor Q1 has not decreased to the resistance value in the fully conducting state, so the conduction loss is slightly higher than that during the time period from time t5 to time t6. Similarly, during the time period from time t6 to time t7, as the gate-source voltage V GS of the switching transistor Q1 decreases linearly, the on-resistance of the switching transistor Q1 also increases slowly, and the conduction loss during this period is also slightly higher than that during the time period from time t5 to time t6. To reduce the conduction loss of the switching transistor Q1 during the switching process, it can also be achieved by increasing the current at the control terminal of the switching transistor Q1 to shorten the lengths of the time periods from time t4 to time t5 and from time t6 to time t7.

[0089] In addition, within the time period from time t1 to time t2, since the enable signal EN has been converted to a high level but the switching transistor Q1 has not been turned on yet, this period contributes most of the dead time and also causes efficiency losses. Increasing the current at the control terminal of the switching transistor Q1 can effectively shorten the time from time t1 to time t2 to improve efficiency.

[0090] However, from the perspective of electromagnetic interference, a faster switching rate, shorter rise time Tr and fall time Tf will result in more harmonic components, which is not conducive to the control of the EMI of the switching transistor control circuit 100. At the same time, asymmetric rise time Tr and fall time Tf will also result in more complex harmonic components, affecting the EMI performance of the switch. From the previous formulas (2) and (4), it can be seen that the switching rate can be slowed down (increasing the rise time Tr and fall time Tf) by reducing the current at the control terminal of the switching transistor Q1, and by keeping the current at the control terminal of the switching transistor Q1 unchanged, that is, the first pull-up current I c and the first pull-down current I d being equal (i.e., I c = I d ) to make the rise time Tr and fall time Tf equal, thus achieving lower EMI.

[0091] Finally, from the perspective of delay, in some applications, such as when the switching transistor control circuit 100 is used as a motor drive circuit, it is required that the turn-on delay Td_on and turn-off delay Td_off of the switching transistor control circuit 100 be equal, so that the duty cycle of the enable signal EN can be accurately transmitted to the circuit driven by the switching transistor Q1. However, from the previous formulas (1) and (3), it can be obtained that:

[0092] Td_on / Td_off = V GSp *I d / [(V BB - V GSp )*I c (5)

[0093] Since the voltage of the input voltage bus V BB is often much higher than the Miller plateau voltage V GSp of the switching transistor Q1, only by configuring the first pull-down current I d to be significantly higher than the first pull-up current I c can the turn-on delay Td_on and turn-off delay Td_off be made equal.

[0094] In summary, starting from the requirement of switching efficiency, it is desired that the first pull-up current I c and the first pull-down current I dcan be as large as possible. From the perspective of electromagnetic interference, it is not desirable for the first pull-up current I c and the first pull-down current I d to be too large. However, the first pull-up current I c and the first pull-down current I d need to be equal. From the perspective of turn-on delay Td_on and turn-off delay Td_off, the first pull-down current I d needs to be significantly greater than the first pull-up current I c . Therefore, if the switch control circuit 100 is the Figure 8 circuit structure shown, then during each stage of the conduction and turn-off of the switch Q1, the gate of the switch Q1 is driven by a single first pull-up current I c and a single first pull-down current I d , which cannot simultaneously meet the requirements of efficiency, EMI, and delay. Based on this, the embodiment of the present application provides the Figure 7 circuit structure shown to simultaneously take into account the requirements of efficiency, EMI, and delay.

[0095] Specifically, as shown in Figure 7 and Figure 10 , at time t12, as the enable signal EN transitions to a high level, the first pull-up switch S 1 and the second pull-up switch S C1 conduct, and the first current source I 1 provides current to the first pull-up branch 10 and the second pull-up branch 30 simultaneously through the current mirrors composed of the first transistor M 1 , the second transistor M 2 , respectively, through the current mirrors composed of the third transistor M 3 , the fourth transistor M 4 , and the current mirrors composed of the third transistor M 3 , the fifth transistor M 5 . Among them, the first pull-up branch 10 starts to provide the first pull-up current I c to the gate of the switch Q1. The eleventh transistor M 11 conducts, the sixth transistor M 6 and the seventh transistor M 7 also conduct, and the gate of the sixth transistor M 6 is biased to the sum of the conduction threshold voltages V 6 of the sixth transistor M 7 and the seventh transistor M GSth . Since at time t11, the gate voltage of the switch Q1 is 0, the eighth transistor M 8 conducts, providing the second pull-up current I c1 to the gate of the switch Q1. The gate-source voltage V GSUnder the simultaneous action of the first pull-up current I 1 and the second pull-up current I c1 it rises rapidly until the gate-source voltage V GS of the switching transistor Q1 rises to the conduction threshold voltage V GSth of the switching transistor Q1 (i.e., at time t13), the gate-source voltage difference of the transistor M 8 can no longer support its conduction, and the second pull-up branch 30 starts to turn off and stops providing the second pull-up current I c1 . Since the Miller plateau voltage V GSp of the switching transistor Q1 must be higher than its conduction threshold voltage V GSth , the second pull-up branch 30 will complete the turn-off of the transistor M GS before the gate-source voltage V GSp of the switching transistor Q1 rises to the Miller plateau voltage V 8 (i.e., before time t14). The second pull-up current I c1 will not act on the switching transistor Q1 during the period when the gate-source voltage V GS of the switching transistor Q1 is at the Miller plateau voltage V GSp , thus not changing the fall time Tf of the switching transistor Q1, that is, not affecting the EMI performance during the switching process of the switching transistor Q1.

[0096] Due to the addition of the second pull-up current I c1 , the length of the time interval from time t12 to time t13 can be effectively shortened, that is, the turn-on delay time Td_on of the switching transistor Q1 is shortened. By configuring the second pull-up current I c1 , and the second pull-down current I d1 it is possible to make the turn-off delay Td_off and the turn-on delay Td_on equal. A shorter turn-on delay time Td_on can also reduce the dead time required for the circuit using the switching transistor Q1 and improve the efficiency of the circuit. In summary, by introducing the second pull-up branch 30 and configuring it to act on the switching transistor Q1 only before the gate-source voltage V GS of the switching transistor Q1 rises to the Miller plateau voltage V GSp , it is possible to simultaneously optimize efficiency, EMI, and delay.

[0097] In addition, in the embodiment including the third pull-up branch 50 shown in Figure 7 , at time t12, the second pull-up switch Sc1 conducts in response to the high level of the enable signal EN, and the eleventh transistor M 11 conducts. Subsequently, the sixth transistor M 6 and the seventh transistor M 7 also conduct, and the gate of the sixth transistor M 6 is biased to the sixth transistor M 6 and the seventh transistor M 7The turn-on threshold voltage V GSth The sum. Since at time t12, the gate voltage of the switching transistor Q1 is 0, the eighth transistor M 8 Turns on and provides a second pull-up current I c1 To the gate of the switching transistor Q1. The gate-source voltage V GS Of the switching transistor Q1 is in the first pull-up current I c And the second pull-up current I c1 Act simultaneously and rise rapidly until the gate-source voltage V GS Of the switching transistor Q1 rises to the turn-on threshold voltage V GSth Of the switching transistor Q1 (i.e., at time t13), the gate-source voltage difference of the transistor M 8 Can no longer support its conduction, and the second pull-up branch 30 starts to turn off and stops providing the second pull-up current I c1 . Since the Miller plateau voltage V GSp Of the switching transistor Q1 must be higher than its turn-on threshold voltage V GSth , the second pull-up branch 30 will complete the turn-off of the transistor M GS Before the gate-source voltage V GSp Of the switching transistor Q1 rises to the Miller plateau voltage V 8 (i.e., before time t14). The second pull-up current I c1 Will not act on the switching transistor Q1 during the gate-source voltage V GS Of the switching transistor Q1 is at the Miller plateau voltage V GSp , thus not changing the fall time Tf of the switching transistor Q1, that is, not affecting the EMI performance of the switching transistor Q1 during the switching process. During the time interval from time t14 to time t15, as the drain-source voltage V DS Of the switching transistor Q1 decreases, the voltage at the output terminal V OUT Gradually rises. When the drain-source voltage V DS Of the switching transistor Q1 is less than the turn-on threshold voltage V 11 Of the eleventh transistor M GSth (close to time t15 at this time), the eleventh transistor M 11 Turns off, and the gate of the eighth transistor M 8 Is pulled high again, and then starts to output the second pull-up current I c1 Again. During the time interval from time t15 to time t16, the gate-source voltage V GS Of the switching transistor Q1 is in the first pull-up current I c And the second pull-up current I c1 Act together and rise rapidly to reach saturation conduction in a shorter time, thus realizing the reduction of the conduction loss during the turn-on process of the switching transistor Q1. And when the enable signal EN is converted to a low level, the second pull-up switch S c1 Turns off, and the eleventh transistor M11 When it is turned off, there is no current in the third pull-up circuit 50, and it will not affect the functions of other circuits.

[0098] At time t17, as the enable signal EN transitions to a low level, the pull-down switch S 2 conducts, and the first current source I 1 provides current to the first pull-down branch 20 and the second pull-down branch 40 simultaneously through the current mirrors formed by the first transistor M 1 , the twelfth transistor M 12 , respectively, through the current mirrors formed by the thirteenth transistor M 13 , the fourteenth transistor M 14 , and the current mirrors formed by the thirteenth transistor M 13 , the seventeenth transistor M 17 . Among them, the first pull-down branch 20 starts to draw the first pull-down current I d (i.e., the first pull-down current I d discharges the gate of the switching transistor Q1). The eighteenth transistor M 18 conducts because the gate voltage of the switching transistor Q1 is relatively high, and starts to draw the second pull-down current I 19 from the gate of the switching transistor Q1 through the current mirror structure formed by the nineteenth transistor M 20 and the twentieth transistor M d1 (i.e., the second pull-down current I d1 discharges the gate of the switching transistor Q1). The gate-source voltage V GS of the switching transistor Q1 rapidly decreases under the simultaneous action of the two pull-down currents until the gate-source voltage V GS of the switching transistor Q1 drops to the sum of the conduction threshold voltages V 18 of the eighteenth transistor M 19 and the nineteenth transistor M GSth . At this time, the eighteenth transistor M 18 can no longer be saturated and conducting, and the second pull-down branch 40 starts to turn off and stops providing the second pull-down current I d1 . Since the Miller plateau voltage V GSp of the switching transistor Q1 often lies between 1.5 times the conduction threshold voltage V GSth and twice the conduction threshold voltage V GSth , the second pull-down branch 40 will turn off before the gate-source voltage V GS of the switching transistor Q1 drops to the Miller plateau voltage V GSp , and the second pull-down current I d1 will not exist when the gate-source voltage V GS of the switching transistor Q1 is at the Miller plateau voltage V GSpDuring the operation on the switching transistor Q1, the rising time Tr of the switching transistor Q1 is not changed, that is, the EMI performance of the switching transistor Q1 during the switching process is not affected.

[0099] Due to the addition of the second pull-down current I d1 , the length of the time interval from time t17 to time t18 can be effectively shortened, that is, the turn-off delay time Td_off of the switching transistor Q1 is shortened. By configuring the second pull-down current I d1 , the turn-off delay Td_off and the turn-on delay Td_on can be made equal. The shorter turn-off delay time Td_off can also reduce the conduction loss of the switching transistor Q1 during the turn-off process. In summary, by introducing the second pull-down circuit 40 and configuring it to act on the switching transistor Q1 only before the gate-source voltage V GS of the switching transistor Q1 drops to the Miller plateau voltage V GSp , the optimization of efficiency, EMI, and delay can be achieved simultaneously.

[0100] In summary, compared with Figure 8 , due to the addition of the second pull-down branch 40, the second pull-up branch 20, and the third pull-up branch 50, the current I G driving the gate of the switching transistor Q1 does not remain constant during the switching process, but has different driving currents in different time intervals.

[0101] Specifically, before time t13, the total pull-up current (I c + I c1 ) is provided by the first pull-up branch 10 and the second pull-up branch 30 together, which can quickly turn on the switching transistor Q1, thereby shortening the dead time required by the switching transistor control circuit 100 in the application and improving the efficiency of the circuit. In the time interval from time t13 to time t14, the second pull-up branch 30 is automatically turned off, and only the first pull-up branch 10 provides the first pull-up current I c . This makes the fall time Tf of the switching transistor Q1 controllable, thereby reducing the EMI generated by the switching transistor Q1 during the switching process. In the time interval from time t14 to time t15, due to the action of the third pull-up branch 50, the second pull-up branch 30 is automatically turned on again, and the total pull-up current is restored to I c + I c1 , and the pull-up current is provided by the first pull-up branch 10 and the second pull-up branch 30 together. The higher total pull-up current significantly shortens the time interval from time t14 to time t15, thereby reducing the conduction loss of the switching transistor Q1 during the turn-on process.

[0102] During the turn-off process of the switching transistor Q1, in the time interval from time t17 to time t18, the total pull-down current (I d + I d1) is provided jointly by the second pull-down branch 40 and the first pull-down branch 20. The output current I of the second pull-down branch 40 can be configured d1 , so that the time interval from time t17 to time t18 is shortened to be equal to the time interval from time t12 to time t14, thus realizing the matching of the turn-on delay Td_on and the turn-off delay Td_off of the switching circuit. At the same time, the shorter Td_off can also reduce the conduction loss of the switching transistor control circuit 100 during the turn-off process.

[0103] After time t18, the second pull-down branch 40 automatically stops operating as the gate-source voltage V of the switching transistor Q1 GS drops, and the total pull-down current resumes to I provided only by the first pull-down branch 20 d , thereby ensuring that the time interval from time t18 to time t19 is equal to the time interval from time t14 to time t15, and achieving the purpose of matching the rise time Tr and the fall time Tf, which is beneficial to reducing the EMI caused during the switching process of the switching transistor Q1.

[0104] In summary, Figure 7 the circuit shown can simply achieve segmented control of the drive current at each stage during the turn-on and turn-off processes of the switching transistor Q1, thereby simultaneously realizing the optimization of efficiency, EMI, and delay. It should be noted that Figure 7 the control of the second pull-down branch 40, the second pull-up branch 20, and the third pull-up branch 50 introduced in [[ ]] is automatically completed by the characteristics of the transistor circuit itself, without the need for complex control circuits (such as comparators, controllers, etc.). The simple and efficient circuit structure not only makes the cost of circuit implementation lower, but also has better robustness than complex control circuits.

[0105] In the foregoing embodiments, the present application constructs a circuit that automatically introduces and stops introducing an additional second pull-down current I GS and / or a second pull-up current I d1 automatically with the change of the gate-source voltage V of the switching transistor Q1 through a simple transistor circuit c1 . The purpose is to improve the pull-down or pull-up rate without affecting the rise time Tr and the fall time Tf, realize the shortening of the turn-on delay Td_on and the turn-off delay Td_off, and / or the matching of the turn-on delay Td_on and the turn-off delay Td_off.

[0106] However, it can be understood that, such as Figure 3 , Figure 5 and Figure 6The hardware structure of the shown switch control circuit is only an example. Moreover, the switch control circuit may have more or fewer components than those shown in the figure, two or more components may be combined, or it may have a different component configuration. The various components shown in the figure may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application-specific integrated circuits.

[0107] For example, Figure 11 Another circuit implementation of the second pull-up branch 30 is exemplarily shown. As Figure 11 shown, the second pull-up branch 30 includes the ninth transistor M 9 and the tenth transistor M 10 , the first switch S k1 and the first comparator U 1 .

[0108] The first end of the ninth transistor M 9 is connected to the first end of the third transistor M 3 . The second end of the ninth transistor M 9 and the third end of the tenth transistor M 10 are both connected to the driving power supply V CP . The third end of the ninth transistor M 9 is connected to the first end of the first switch S k1 . The second end of the first switch S k1 is connected to the first end of the tenth transistor M 10 . The second end of the tenth transistor M 10 is connected to the control end of the switch tube and the inverting input terminal of the first comparator U 1 . The non-inverting input terminal of the first comparator U 1 inputs the sum of the first preset voltage V S1 and the voltage of the second end of the non-control end of the switch tube Q1 (in this embodiment, it is the voltage of the output terminal V OUT ). The output terminal of the first comparator U 1 outputs a signal for controlling the first switch S k1 , and when the first comparator U 1 outputs a high level, the first switch S k1 conducts.

[0109] This embodiment uses the second comparator U 2 to monitor the gate-source voltage V GS of the switch tube Q1, and turns off the second pull-up branch 20 when it is greater than the first preset voltage V S1 , so as to achieve the purpose of changing the total pull-up current in segments.

[0110] Similarly, Figure 12Another circuit implementation of the second pull-down branch 40 is exemplarily shown. As Figure 12 shown, the second pull-down branch 40 includes the twenty-first transistor M 21 , the twenty-second transistor M 22 , the twenty-third transistor M 23 , the second switch S k2 and the second comparator U 2 .

[0111] The first end of the twenty-first transistor M 21 is connected to the first end of the thirteenth transistor M 13 , the second end of the twenty-first transistor M 21 is connected to the driving power supply V CP , the third end of the twenty-first transistor M 21 is connected to the first end of the second switch S k2 , the second end of the second switch S k2 is respectively connected to the third end of the twenty-second transistor M 22 , the first end of the twenty-second transistor M 22 and the first end of the twenty-third transistor M 23 , the second end of the twenty-second transistor M 22 and the second end of the twenty-third transistor M 23 are both connected to the second end of the non-control end of the switching transistor Q1, the third end of the twenty-third transistor M 23 is respectively connected to the non-inverting input terminal of the second comparator U 2 and the control terminal of the switching transistor Q1, the inverting input terminal of the second comparator U 2 inputs the sum of the second preset voltage V S2 and the voltage of the second end of the non-control end of the switching transistor Q1, the output terminal of the second comparator U 2 outputs a signal for controlling the second switch S k2 , and when the second comparator U 2 outputs a high level, the second switch S k2 is turned on.

[0112] This embodiment employs the first comparator U 1 to monitor the gate-source voltage V GS of the switching transistor Q1, and turns off the second pull-down branch 40 when it is less than the second preset voltage V S2 , thereby achieving the purpose of changing the total pull-down current in segments.

[0113] Again, in some embodiments, as Figure 13 shown, the third pull-up branch 50 further includes the first resistor R 1 , the second resistor R 2 and the zener diode Z 1The auxiliary circuit formed thereby. Among them, the first resistor R 1 is connected between the first end of the non-control end of the switching transistor Q1 and the second pull-up switch S C1 ; the second resistor R 2 is connected between the first end of the eleventh transistor M 11 and the ground GND; the anode of the voltage stabilizing diode Z 1 is grounded to GND, and the cathode of the voltage stabilizing diode Z 1 is connected to the first end of the eleventh transistor M 11 . Among them, the combination of the first resistor R 1 and the voltage stabilizing diode Z 1 is used to perform overvoltage protection on the first end of the eleventh transistor M 11 . The second resistor R 2 is mainly used to discharge the first end of the eleventh transistor M C1 when the second pull-up switch S 11 is turned off, and turn off the eleventh transistor M 11 . Similarly, the auxiliary circuit structure composed of the first resistor R 1 , the second resistor R 2 and the voltage stabilizing diode Z 1 can be used to protect and discharge each transistor in the second pull-up branch 30 and the second pull-down branch 40. For example, the tenth transistor M 10 and the eighth transistor M 8 in the second pull-up branch 30.

[0114] Also, in the circuit structures in the above embodiments, the switching transistor Q1 is a high-side switch, that is, the switching transistor Q1 is connected between the input voltage bus V BB and the output terminal V OUT . However, the switching transistor Q1 can also be a low-side switch, that is, the switching transistor Q1 is connected between the output terminal V OUT and the ground GND, as shown in Figure 14 and Figure 15 .

[0115] Please refer to Figure 16 , Figure 16 which is a flowchart of the switching transistor control method provided by the embodiment of the present application. Among them, the first end and the second end of the non-control end of the switching transistor are respectively connected to the input voltage bus and the output terminal, or the first end and the second end of the non-control end of the switching transistor are respectively connected to the output terminal and the ground, and the output terminal is connected to the load. As shown in Figure 16 , the switching transistor control method includes the following method steps:

[0116] Step 1601: Obtain an enable signal.

[0117] Step 1602: When the enable signal transitions to the first level, start outputting the first pull-up current and the second pull-up current together to charge the control terminal of the switching transistor.

[0118] Step 1603: When the enable signal transitions to the second level, start outputting the first pull-down current and the second pull-down current together to discharge the control terminal of the switching transistor.

[0119] Step 1604: When the enable signal is at the first level, during the process of outputting the first pull-up current to charge the control terminal of the switching transistor, stop outputting the second pull-up current, and / or when the enable signal is at the second level, during the process of outputting the second pull-down current to discharge the control terminal of the switching transistor, stop outputting the second pull-down current.

[0120] In some embodiments, the switching transistor control method includes the following method steps: After starting to output the second pull-up current to charge the control terminal of the switching transistor, when the voltage difference between the control terminal of the switching transistor and the second terminal of the non-control terminal of the switching transistor is equal to a first preset voltage, stop charging the control terminal of the switching transistor through the second pull-up current, where the first preset voltage is less than or equal to the Miller plateau voltage of the switching transistor and greater than the conduction threshold voltage of the switching transistor.

[0121] In some embodiments, the switching transistor control method includes the following method steps: At the moment when the voltage difference between the first terminal and the second terminal of the non-control terminal of the switching transistor is less than a third preset voltage during the period when the enable signal is at the first level, start outputting the second pull-up current to charge the control terminal of the switching transistor.

[0122] In some embodiments, the switching transistor control method includes the following method steps: After starting to output the second pull-down current to discharge the control terminal of the switching transistor, when the voltage difference between the control terminal of the switching transistor and the second terminal of the non-control terminal of the switching transistor is equal to a second preset voltage, stop discharging the control terminal of the switching transistor through the second pull-down current, where the second preset voltage is greater than or equal to the Miller plateau voltage of the switching transistor.

[0123] In some embodiments, the second preset voltage is less than twice the conduction threshold voltage of the switching transistor.

[0124] It should be understood that for the specific control of the switching transistor and the beneficial effects generated in the method embodiments, reference can be made to the corresponding descriptions in the embodiments of the above-mentioned switching transistor control circuit. For the sake of brevity, they are not elaborated here.

[0125] An embodiment of the present application further provides a chip, which includes a switching transistor and the switching transistor control circuit 100 in any embodiment of the present application. Wherein, the first end and the second end of the non-control end of the switching transistor are respectively connected to the input voltage bus and the output end, or the first end and the second end of the non-control end of the switching transistor are respectively connected to the output end and the ground, and the output end is connected to the load.

[0126] The above are only embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, is similarly included in the patent protection scope of the present application.

[0127] The above embodiments are only used to illustrate the technical solutions of the present application, rather than limiting them; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A switch tube control circuit, characterized in that: The first end and the second end of the non-control end of the switch tube are respectively connected to the input voltage bus and the output end, or the first end and the second end of the non-control end of the switch tube are respectively connected to the output end and the ground, and the output end is connected to the load. The switch tube control circuit includes: A first pull-up branch is connected to the control end of the switch tube and the driving power supply respectively, and is configured to operate or stop operating in response to an enable signal, wherein when the first pull-up branch operates, the first pull-up branch outputs a first pull-up current to charge the control end of the switch tube; A first pull-down branch is connected to the control end of the switch tube, the second end of the non-control end of the switch tube and the driving power supply respectively, and is configured to operate or stop operating in response to an enable signal, wherein when the first pull-down branch operates, the first pull-down branch outputs a first pull-down current to discharge the control end of the switch tube; at least one of a second pull-up branch and a second pull-down branch, the second pull-up branch being connected to the control end of the switch tube, the second end of the non-control end of the switch tube and the driving power supply respectively, the second pull-up branch being configured to operate or stop operating in response to the enable signal, wherein when the second pull-up branch operates, the second pull-up branch outputs a second pull-up current to charge the control end of the switch tube, and the operating time of the second pull-up branch is shorter than the operating time of the first pull-up branch; The second pull-down branch is respectively connected to the control end of the switch tube, the second end of the non-control end of the switch tube and the driving power supply, and the second pull-down branch is configured to run or stop running in response to the enable signal, wherein when the second pull-down branch is running, the second pull-down branch outputs a second pull-down current to discharge the control end of the switch tube, and the running time of the second pull-down branch is shorter than the running time of the first pull-down branch.

2. The switch tube control circuit according to claim 1, characterized in that: The second pull-up branch is also configured to start operating together with the first pull-up branch in response to the enable signal, and stop operating when the control end of the switch tube is charged to a voltage difference between the control end of the switch tube and the second end of the non-control end of the switch tube is equal to a first preset voltage, so as to stop outputting the second pull-up current.

3. The switch tube control circuit according to claim 2, characterized in that: The first preset voltage is greater than or equal to a turn-on threshold voltage of the switch tube and less than or equal to a Miller platform voltage of the switch tube.

4. The switch tube control circuit according to claim 2, characterized in that: The switch tube control circuit includes a first current source and a first transistor, and the first pull-up branch includes a second transistor, a third transistor, a fourth transistor and a first pull-up switch; The first current source is respectively connected to the third end of the first transistor, the first end of the first transistor and the first end of the second transistor, the second end of the first transistor and the second end of the second transistor are both grounded, the third end of the second transistor is connected to the first end of the first pull-up switch, the second end of the first pull-up switch is respectively connected to the third end of the third transistor, the first end of the third transistor and the first end of the fourth transistor, the second end of the third transistor and the second end of the fourth transistor are both connected to the driving power supply, and the third end of the fourth transistor is connected to the control end of the switch tube; The first pull-up switch is controlled by the enable signal to be turned on or off.

5. The switch tube control circuit according to claim 4, characterized in that: The second pull-up branch includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The first end of the fifth transistor is connected to the first end of the third transistor, the second end of the fifth transistor and the third end of the eighth transistor are both connected to the driving power supply, the third end of the fifth transistor is respectively connected to the third end of the sixth transistor, the first end of the sixth transistor and the first end of the eighth transistor, the second end of the sixth transistor is respectively connected to the third end of the seventh transistor and the first end of the seventh transistor, the second end of the seventh transistor is connected to the second end of the non-control end of the switch tube, and the second end of the eighth transistor is connected to the control end of the switch tube.

6. The switch tube control circuit according to any one of claims 1 to 5, characterized in that: The switch tube control circuit also includes a third pull-up branch; The third pull-up branch is respectively connected to the second pull-up branch, the first end of the non-control end of the switch tube, and the second end of the non-control end of the switch tube, and the third pull-up branch is configured to operate or stop operating in response to the enable signal; Wherein, when the third pull-up branch starts to operate, the third pull-up branch establishes a connection between the second pull-up branch and the second end of the non-control end of the switch tube, so that the second pull-up branch outputs the second pull-up current; During the operation of the third pull-up branch, when the voltage difference between the first end of the non-control end of the switch tube and the second end of the non-control end of the switch tube is less than a third preset voltage, the third pull-up branch disconnects the second pull-up branch from the second end of the non-control end of the switch tube, so that the second pull-up branch outputs the second pull-up current.

7. The switch tube control circuit according to claim 6, characterized in that: The third pull-up branch includes a second pull-up switch and an eleventh transistor; The first end of the second pull-up switch is connected to the first end of the non-control end of the switch tube, the second end of the second pull-up switch is connected to the first end of the eleventh transistor, the second end of the eleventh transistor is connected to the second end of the non-control end of the switch tube, and the third end of the eleventh transistor is connected to the second pull-up branch; The pull-up switch is controlled by the enable signal to be turned on or off.

8. The switch tube control circuit according to claim 4, characterized in that: The second pull-up branch includes a ninth transistor, a tenth transistor, a first switch and a first comparator; The first end of the ninth transistor is connected to the first end of the third transistor, the second end of the ninth transistor and the third end of the tenth transistor are both connected to the driving power supply, the third end of the ninth transistor is connected to the first end of the first switch, the second end of the first switch is connected to the first end of the tenth transistor, the second end of the tenth transistor is connected to the control end of the switch tube and the inverting input end of the first comparator, the non-inverting input end of the first comparator inputs the sum of the first preset voltage and the voltage of the second end of the non-control end of the switch tube, the output end of the first comparator outputs a signal to control the first switch, and the first switch is turned on when the first comparator outputs a high level.

9. The switch tube control circuit according to claim 1, characterized in that: The second pull-down branch is also configured to start operating together with the first pull-down branch in response to the enable signal, and stop operating when the control end of the switch tube is discharged to a voltage difference between the control end of the switch tube and a second end of the non-control end of the switch tube equal to a second preset voltage, so as to stop outputting the second pull-down current.

10. The switch tube control circuit according to claim 9, characterized in that: The second preset voltage is greater than or equal to the Miller platform voltage of the switch tube.

11. The switch tube control circuit according to claim 9 or 10, characterized in that: The second preset voltage is less than twice the turn-on threshold voltage of the switch tube.

12. The switch tube control circuit according to claim 9, characterized in that: The switch control circuit includes a first current source and a first transistor, and the first pull-down branch includes a pull-down switch, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; The first current source is respectively connected to the third end of the first transistor, the first end of the first transistor and the first end of the twelfth transistor, the second end of the first transistor and the second end of the twelfth transistor are both grounded, the third end of the twelfth transistor is connected to the first end of the pull-down switch, the second end of the pull-down switch is respectively connected to the third end of the thirteenth transistor, the first end of the thirteenth transistor and the first end of the fourteenth transistor, the second end of the thirteenth transistor and the second end of the fourteenth transistor are both connected to the driving power supply, the third end of the fourteenth transistor is respectively connected to the third end of the fifteenth transistor, the first end of the fifteenth transistor and the first end of the sixteenth transistor, the second end of the fifteenth transistor and the second end of the sixteenth transistor are both connected to the second end of the non-control end of the switch tube, and the third end of the sixteenth transistor is connected to the control end of the switch tube; The second pull-down switch is controlled by the enable signal to be turned on or off.

13. The switch tube control circuit according to claim 12, characterized in that: The second pull-down branch includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; The first end of the seventeenth transistor is connected to the first end of the thirteenth transistor, the second end of the seventeenth transistor is connected to the driving power supply, the third end of the seventeenth transistor is connected to the third end of the eighteenth transistor, the second end of the eighteenth transistor is respectively connected to the third end of the nineteenth transistor, the first end of the nineteenth transistor and the first end of the twentieth transistor, the second end of the nineteenth transistor and the second end of the twentieth transistor are both connected to the second end of the non-control end of the switch tube, and the third end of the twentieth transistor is respectively connected to the first end of the eighteenth transistor and the control end of the switch tube.

14. The switch tube control circuit according to claim 12, characterized in that: The second pull-down branch includes a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a second switch and a second comparator; The first end of the twenty-first transistor is connected to the first end of the thirteenth transistor, the second end of the twenty-first transistor is connected to the driving power supply, the third end of the twenty-first transistor is connected to the first end of the second switch, the second end of the second switch is respectively connected to the third end of the twenty-second transistor, the first end of the twenty-second transistor and the first end of the twenty-third transistor, the second end of the twenty-second transistor and the second end of the twenty-third transistor are both connected to the second end of the non-control end of the switch tube, the third end of the twenty-third transistor is respectively connected to the non-inverting input end of the second comparator and the control end of the switch tube, the inverting input end of the second comparator inputs the sum of the second preset voltage and the voltage of the second end of the non-control end of the switch tube, the output end of the second comparator outputs a signal to control the second switch, and the second switch is turned on when the second comparator outputs a high level.

15. A switch tube control method, characterized in that: The first end and the second end of the non-control end of the switch tube are connected to the input voltage bus and the output end respectively, or the first end and the second end of the non-control end of the switch tube are connected to the output end and the ground respectively, and the output end is connected to the load. The switch tube control method includes: Get the enable signal; When the enable signal is converted to the first level, the first pull-up current and the second pull-up current are output to charge the control terminal of the switch tube together; When the enable signal is converted to the second level, the first pull-down current and the second pull-down current are output to discharge the control end of the switch tube together; When the enable signal is at the first level, in the process of outputting the first pull-up current to charge the control end of the switch tube, the second pull-up current is stopped from being output, and / or, when the enable signal is at the second level, in the process of outputting the second pull-down current to discharge the control end of the switch tube, the second pull-down current is stopped from being output.

16. The switch control method according to claim 15, characterized in that: The method further comprises: After starting to output the second pull-up current to charge the control end of the switch tube, when the control end of the switch tube is charged to the point where the voltage difference between the control end of the switch tube and the second end of the non-control end of the switch tube is equal to a first preset voltage, stopping charging the control end of the switch tube through the second pull-up current, wherein the first preset voltage is less than or equal to the Miller platform voltage of the switch tube and greater than the turn-on threshold voltage of the switch tube.

17. The switch tube control method according to claim 15 or 16, characterized in that: The method further comprises: When the voltage difference between the first end of the non-control end of the switch tube and the second end of the non-control end of the switch tube is less than the third preset voltage during the period when the enable signal is at the first level, the second pull-up current starts to be output to charge the control end of the switch tube.

18. The switch control method according to claim 15, characterized in that: The method further comprises: After starting to output the second pull-down current to discharge the control end of the switch tube, when the control end of the switch tube is discharged until the voltage difference between the control end of the switch tube and the second end of the non-control end of the switch tube is equal to a second preset voltage, stopping discharging the control end of the switch tube through the second pull-down current, wherein the second preset voltage is greater than or equal to the Miller platform voltage of the switch tube.

19. The switch control method according to claim 18, characterized in that: The second preset voltage is less than twice the turn-on threshold voltage of the switch tube.

20. A chip, characterized in that: It comprises a switch tube and a switch tube control circuit as described in any one of claims 1 to 14.

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