Gate drive circuit of NMOS (N-channel Metal Oxide Semiconductor) tube and power switch circuit thereof

Abstract

The invention provides a gate drive circuit of an NMOS (N-channel Metal Oxide Semiconductor) tube, which is characterized in that when the NMOS tube needs to be turned on, the voltage of an output turn-on control signal is adjusted to a first-stage turn-on voltage, and the first-stage turn-on voltage is greater than a Miller platform voltage and less than a maximum turn-on drive voltage; only when the gate-source voltage of the NMOS tube is greater than or equal to the first threshold voltage, the voltage of the turn-on control signal is controlled to be the maximum turn-on driving voltage; when the NMOS tube needs to be turned off, the voltage of the output turn-off control signal is adjusted to be a first-stage turn-off voltage, the first-stage turn-on voltage is smaller than the threshold voltage of the NMOS tube and smaller than the minimum turn-off driving voltage, and the voltage of the turn-off control signal is controlled to be the minimum turn-off driving voltage only when the gate-source voltage of the NMOS tube is smaller than or equal to a second threshold voltage. Therefore, through a two-section type driving scheme, current overshoot suppression and voltage overshoot suppression of the NMOS tube are realized, and relatively high turn-on speed and turn-off speed are also taken into account.

Description

Technical Field

[0001] The present invention relates to the technical field of switch control, and particularly to a gate driving circuit of an NMOS transistor and its power switch circuit. Background Art

[0002] With the development of wide bandgap devices, switching transistors with lower on-resistance, faster switching speed and higher switching frequency have been widely used. Such switching transistors can effectively improve the efficiency and power density of the power supply system and are often used in high-frequency, medium and low-power applications.

[0003] As an example, such a switching transistor can be a SiC MOSFET. In high-frequency and high-efficiency application scenarios, the SiC MOSFET switch is prone to current overshoot and voltage overshoot during the turn-on and turn-off processes, which causes the switching device formed by the SiC MOSFET to be vulnerable to electromagnetic interference (EMI) and gate crosstalk. This problem also appears in other power switch devices.

[0004] Therefore, how to solve the technical problem of current overshoot and voltage overshoot during the turn-on and turn-off processes of the NMOS transistor has become an urgent technical problem in the industry. Summary of the Invention

[0005] The present invention provides a gate driving circuit of an NMOS transistor and its power switch circuit, aiming to solve the technical problem of current overshoot and voltage overshoot during the turn-on and turn-off processes of the NMOS transistor.

[0006] According to a first aspect of the present invention, an embodiment of the present invention provides a gate driving circuit of an NMOS transistor. The output end of the gate driving circuit is coupled to the control end of the NMOS transistor, and the input end of the gate driving circuit receives a gate control signal. The gate driving circuit includes:

[0007] A turn-on gate driving module, whose output end is coupled to the control end of the NMOS transistor, and whose input end receives the gate control signal, and is configured to:

[0008] When the gate control signal indicates turn-on, output a turn-on control signal to the control end of the NMOS transistor, and adjust the voltage of the turn-on control signal to a first-stage turn-on voltage, where the first-stage turn-on voltage is greater than the Miller plateau voltage and less than the maximum turn-on drive voltage;

[0009] And adjust the voltage of the turn-on control signal based on the gate-source voltage of the NMOS transistor, where:

[0010] Only when the gate-source voltage of the NMOS transistor is greater than or equal to the first threshold voltage, control the voltage of the turn-on control signal to be the maximum turn-on drive voltage, where the first threshold voltage is less than the first-stage turn-on voltage and greater than the Miller plateau voltage;

[0011] A gate drive module for turning off, whose output terminal is coupled to the control terminal of the NMOS transistor, and whose input terminal receives the gate control signal, is configured as follows:

[0012] When the gate control signal indicates turn-off, output a turn-off control signal to the control terminal of the NMOS transistor, and adjust the voltage of the turn-off control signal to the first-stage turn-off voltage, where the first-stage turn-off voltage is greater than the minimum turn-off drive voltage and less than the threshold voltage of the NMOS transistor;

[0013] And adjust the voltage of the turn-off control signal based on the gate-source voltage of the NMOS transistor, where:

[0014] Only when the gate-source voltage of the NMOS transistor is less than or equal to the second threshold voltage, control the voltage of the turn-off control signal to be the minimum turn-off drive voltage, where the second threshold voltage is greater than the first-stage turn-off voltage and less than the threshold voltage of the NMOS transistor.

[0015] Optionally, the turn-on gate drive module includes a turn-on stage signal control unit and a turn-on drive voltage control unit;

[0016] The input terminal of the turn-on stage signal control unit receives the gate control signal, its first output terminal is coupled to the first input terminal of the turn-on drive voltage control unit, its second output terminal is coupled to the second input terminal of the turn-on drive voltage control unit, and the output terminal of the turn-on drive voltage control unit is coupled to the control terminal of the NMOS transistor;

[0017] The turn-on stage signal control unit is configured to, if the gate control signal indicates turn-on and the gate-source voltage of the NMOS transistor is less than the first threshold voltage, output a first-stage turn-on control signal to the first input terminal of the turn-on drive voltage control unit; and

[0018] if the gate control signal indicates turn-on and the gate-source voltage of the NMOS transistor is greater than or equal to the first threshold voltage, output a second-stage turn-on control signal to the second input terminal of the turn-on drive voltage control unit;

[0019] The turn-on drive voltage control unit is configured to: if its first input terminal receives the first-stage turn-on control signal, adjust the voltage of the turn-on control signal to the first-stage turn-on voltage; and

[0020] If its second input terminal receives a second-stage turn-on control signal, the voltage of the turn-on control signal is controlled to be the maximum turn-on driving voltage.

[0021] Optionally, the turn-on driving voltage control unit includes a first-stage turn-on driving voltage control sub-unit, a second-stage turn-on driving voltage control sub-unit, and a first PMOS transistor;

[0022] The input terminal of the first-stage turn-on driving voltage control sub-unit is coupled to the first output terminal of the turn-on stage signal control unit. The receiving terminal of the first-stage turn-on driving voltage control sub-unit receives a first set voltage. The first terminal of the first-stage turn-on driving voltage control sub-unit is coupled to the gate of the first PMOS transistor. The second terminal of the first-stage turn-on driving voltage control sub-unit and the source of the first PMOS transistor receive the maximum turn-on driving voltage. The third terminal of the first-stage turn-on driving voltage control sub-unit and the drain of the first PMOS transistor are coupled to the control terminal of the NMOS transistor. Among them, the first set voltage is greater than the Miller plateau voltage and less than the maximum turn-on driving voltage;

[0023] The first-stage turn-on driving voltage control sub-unit is configured to: if it receives the first-stage turn-on control signal, adjust the voltage of the turn-on control signal to the first-stage turn-on voltage;

[0024] The input terminal of the second-stage turn-on driving voltage control sub-unit is coupled to the second output terminal of the turn-on stage signal control unit. Its first terminal is coupled to the gate of the first PMOS transistor, and the second terminal is grounded and configured to:

[0025] If it receives the second-stage turn-on control signal, control the voltage of the turn-on control signal to be the maximum turn-on driving voltage.

[0026] Optionally, the first-stage turn-on driving voltage control sub-unit includes:

[0027] A first transistor, a second transistor, a third transistor, a first resistor, a first diode, a fourth transistor, a fifth transistor, and a second diode;

[0028] The gate of the first transistor is coupled to the first output terminal of the turn-on stage signal control unit to receive the first-stage turn-on control signal, and the voltage of the first-stage turn-on control signal is a first voltage. The source of the first transistor is grounded, and the drain of the first transistor is coupled to the drain of the second transistor, the gate of the second transistor, and the gate of the third transistor. The sources of the second transistor, the third transistor, and the first end of the first resistor all receive the maximum turn-on drive voltage. The drain of the third transistor is coupled to the anode of the first diode, the drain of the fourth transistor, the gate of the fourth transistor, and the gate of the fifth transistor. The cathode of the first diode receives the first set voltage. The second end of the first resistor and the drain of the fifth transistor are both coupled to the gate of the first PMOS transistor. The sources of the fourth transistor and the fifth transistor are both coupled to the anode of the second diode, and the cathode of the second diode is coupled to the drain of the first PMOS transistor. Among them, the first transistor, the fourth transistor, and the fifth transistor are NMOS transistors, the second transistor and the third transistor are PMOS transistors, and the first diode and the second diode have the same specifications;

[0029] The first voltage is greater than the threshold voltage of the first transistor;

[0030] The first-stage turn-on voltage is equal to the first set voltage minus the threshold voltage of the fourth transistor.

[0031] Optionally, the first-stage turn-on drive voltage control sub-unit further includes: a second resistor and a third resistor;

[0032] The second resistor is connected in series between the drain of the first transistor and the drain of the second transistor, and the third resistor is connected in series between the drain of the third transistor and the drain of the fourth transistor.

[0033] Optionally, the first-stage turn-on drive voltage control sub-unit further includes: a first Zener diode;

[0034] The first end of the first Zener diode is coupled to the gate of the first PMOS transistor, and the second end is coupled to the source of the first PMOS transistor.

[0035] Optionally, the second-stage turn-on drive voltage control sub-unit further includes: a sixth transistor, a first inverter, and a second inverter;

[0036] The first terminal of the first inverter is coupled to the second output terminal of the turn-on stage signal control unit to receive the second-stage turn-on control signal. The second terminal of the first inverter is coupled to the first terminal of the second inverter. The second terminal of the second inverter is coupled to the gate of the sixth transistor. The drain of the sixth transistor is coupled to the gate of the first PMOS transistor. The source of the sixth transistor is grounded. The sixth transistor is an NMOS transistor.

[0037] Optionally, the turn-on stage signal control unit includes: a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first comparator, and a first logic gate circuit diagram;

[0038] The first terminal of the fourth resistor receives the gate-source voltage of the NMOS transistor. The second terminal of the fourth resistor is coupled to the positive input terminal of the first comparator and the first terminal of the fifth resistor. The second terminal of the fifth resistor is grounded;

[0039] The first terminal of the sixth resistor receives the first threshold voltage. The second terminal of the sixth resistor is coupled to the negative input terminal of the first comparator and the first terminal of the seventh resistor. The second terminal of the seventh resistor is grounded;

[0040] The output terminal of the first comparator is coupled to the first input terminal of the first logic gate circuit. The second input terminal of the first logic gate circuit receives the gate control signal. The first output terminal of the first logic gate circuit outputs the first-stage turn-on control signal. The second output terminal of the first logic gate circuit outputs the second-stage turn-on control signal.

[0041] Optionally, the gate turn-off drive module includes a turn-off stage signal control unit and a turn-off drive voltage control unit;

[0042] The input terminal of the turn-off stage signal control unit receives the gate control signal. Its first output terminal is coupled to the first input terminal of the turn-off drive voltage control unit. Its second output terminal is coupled to the second input terminal of the turn-off drive voltage control unit. The output terminal of the turn-off drive voltage control unit is coupled to the control terminal of the NMOS transistor;

[0043] The turn-off stage signal control unit is configured to, if the gate control signal indicates turn-off and the gate-source voltage of the NMOS transistor is greater than or equal to the second threshold voltage, output a first-stage turn-off control signal to the first input terminal of the turn-off drive voltage control unit; and

[0044] if the gate control signal indicates turn-off and the gate-source voltage is less than or equal to the first threshold voltage, output a second-stage turn-off control signal to the second input terminal of the turn-off drive voltage control unit;

[0045] The turn-off drive voltage control unit is configured to: when its first input terminal receives the first-stage turn-off control signal, adjust the voltage of the turn-off control signal to the first-stage turn-off voltage; and

[0046] when its second input terminal receives the second-stage turn-off control signal, control the voltage of the turn-off control signal to be the minimum turn-off drive voltage.

[0047] Optionally, the turn-off drive voltage control unit includes a first-stage turn-off drive voltage control subunit, a second-stage turn-off drive voltage control subunit, and a first NMOS transistor;

[0048] The input terminal of the first-stage turn-off drive voltage control subunit is coupled to the first output terminal of the turn-off stage signal control unit. The receiving terminal of the first-stage turn-off drive voltage control subunit receives a second set voltage. The first terminal of the first-stage turn-off drive voltage control subunit is coupled to the gate of the first NMOS transistor. The second terminal of the first-stage turn-off drive voltage control subunit and the source of the first NMOS transistor receive the minimum turn-off drive voltage. The third terminal of the first-stage turn-off drive voltage control subunit and the drain of the first NMOS transistor are coupled to the control terminal of the NMOS transistor, wherein the second set voltage is less than the threshold voltage of the NMOS transistor and greater than the minimum turn-off drive voltage;

[0049] The first-stage turn-off drive voltage control subunit is configured to: when receiving the first-stage turn-off control signal, adjust the voltage of the turn-off control signal to the first-stage turn-off voltage;

[0050] The input terminal of the second-stage turn-off drive voltage control subunit is coupled to the second output terminal of the turn-off stage signal control unit. Its first terminal is coupled to the gate of the first NMOS transistor. Its second terminal receives the power supply voltage and is configured to:

[0051] when receiving the second-stage turn-off control signal, control the voltage of the turn-off control signal to be the minimum turn-off drive voltage.

[0052] Optionally, the first-stage turn-off drive voltage control subunit includes:

[0053] a seventh transistor, an eighth transistor, a ninth transistor, a third diode, a fourth diode, and an eighth resistor;

[0054] The gate of the seventh transistor is coupled to the first output terminal of the turn-off stage signal control unit to receive the first-stage turn-off control signal. The voltage of the first-stage turn-off control signal is the second voltage, and the second voltage is greater than the threshold voltage of the seventh transistor. The source of the seventh transistor is grounded, and the drain of the seventh transistor is coupled to the drain of the eighth transistor, the gate of the eighth transistor, the gate of the ninth transistor, and the cathode of the third diode. The anode of the third diode receives the second set voltage. The sources of the eighth transistor and the ninth transistor are both coupled to the cathode of the fourth diode, and the anode of the fourth diode is coupled to the drain of the first NMOS transistor. The drain of the ninth transistor and the first end of the eighth resistor are coupled to the gate of the first NMOS transistor, and the second end of the eighth resistor receives the minimum turn-off drive voltage. Among them, the seventh transistor is an NMOS transistor, and the eighth transistor and the ninth transistor are PMOS transistors;

[0055] The first-stage turn-off voltage is equal to the second set voltage plus the absolute value of the threshold voltage of the eighth transistor.

[0056] Optionally, the first-stage turn-off drive voltage control sub-unit further includes: a ninth resistor;

[0057] The ninth resistor is connected in series between the drain of the seventh transistor and the drain of the eighth transistor.

[0058] Optionally, the first-stage turn-off drive voltage control sub-unit further includes: a second Zener diode;

[0059] The first end of the second Zener diode is coupled to the gate of the first NMOS transistor, and the second end receives the minimum turn-off drive voltage.

[0060] Optionally, the second-stage turn-off drive voltage control sub-unit includes: a third inverter and a tenth transistor;

[0061] The first end of the third inverter is coupled to the second output terminal of the turn-off stage signal control unit to receive the second-stage turn-off control signal. The second end of the third inverter is coupled to the gate of the tenth transistor. The drain of the tenth transistor is coupled to the gate of the first NMOS transistor. The source of the tenth transistor receives the power supply voltage. The tenth transistor is a PMOS transistor.

[0062] Optionally, the turn-off stage signal control unit includes: a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second comparator, and a second logic gate circuit;

[0063] The first end of the tenth resistor receives the gate-source voltage of the NMOS transistor, the second end of the tenth resistor is coupled to the non-inverting input terminal of the second comparator and the first end of the eleventh resistor, and the second end of the eleventh resistor is grounded;

[0064] The first end of the twelfth resistor receives the second threshold voltage, the second end of the twelfth resistor is coupled to the inverting input terminal of the second comparator and the first end of the thirteenth resistor, and the second end of the thirteenth resistor is grounded;

[0065] The output terminal of the second comparator is coupled to the first input terminal of the second logic gate circuit, the second input terminal of the second logic gate circuit receives the gate control signal, the first output terminal of the second logic gate circuit outputs the first-stage turn-off control signal, and the second output terminal of the second logic gate circuit outputs the second-stage turn-off control signal.

[0066] According to a second aspect of the present invention, there is provided a power switch circuit including an NMOS transistor and the gate driving circuit of the above-mentioned NMOS transistor;

[0067] The output terminal of the gate driving circuit is coupled to the control terminal of the NMOS transistor.

[0068] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0069] The present invention provides a gate driving circuit for an NMOS transistor and its power switch circuit. When the NMOS transistor needs to be turned on, the voltage of the output turn-on control signal is adjusted to the first-stage turn-on voltage, which is greater than the Miller platform voltage and less than the maximum turn-on driving voltage, and the voltage of the turn-on control signal is controlled to be the maximum turn-on driving voltage only when the gate-source voltage of the NMOS transistor is greater than or equal to the first threshold voltage; when the NMOS transistor needs to be turned off, the voltage of the output turn-off control signal is adjusted to the first-stage turn-off voltage, which is less than the threshold voltage of the NMOS transistor and less than the minimum turn-off driving voltage, and the voltage of the turn-off control signal is controlled to be the minimum turn-off driving voltage only when the gate-source voltage of the NMOS transistor is less than or equal to the second threshold voltage. Therefore, the present invention realizes the suppression of current overshoot and voltage overshoot of the NMOS transistor through a two-stage driving scheme, and also takes into account a relatively fast turn-on speed and turn-off speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0071] Figure 1 It is a schematic structural diagram of a power switch circuit in the prior art;

[0072] Figure 2 It is a schematic structural diagram of another power switch circuit in the prior art;

[0073] Figure 3 It is a schematic structural diagram of the gate drive circuit of the NMOS transistor in an embodiment of the present invention;

[0074] Figure 4 It is a schematic structural diagram of the turn-on gate drive module in an embodiment of the present invention;

[0075] Figure 5 It is a schematic structural diagram of the turn-on drive voltage control unit in an embodiment of the present invention;

[0076] Figure 6 It is a schematic structural diagram of the first first-stage turn-on drive voltage control sub-unit in an embodiment of the present invention;

[0077] Figure 7 It is a schematic structural diagram of the second first-stage turn-on drive voltage control sub-unit in an embodiment of the present invention;

[0078] Figure 8 It is a schematic structural diagram of the third first-stage turn-on drive voltage control sub-unit in an embodiment of the present invention;

[0079] Figure 9 It is a schematic structural diagram of the second-stage turn-on drive voltage control sub-unit in an embodiment of the present invention;

[0080] Figure 10 It is a schematic structural diagram of the turn-on stage signal control unit in an embodiment of the present invention;

[0081] Figure 11 It is a schematic structural diagram of the turn-off gate drive module in an embodiment of the present invention;

[0082] Figure 12 It is a schematic structural diagram of the turn-off drive voltage control unit in an embodiment of the present invention;

[0083] Figure 13 It is a schematic structural diagram of the first first-stage turn-off drive voltage control sub-unit in an embodiment of the present invention;

[0084] Figure 14 Schematic diagram of the second first-stage turn-off drive voltage control sub-unit in an embodiment of the present invention;

[0085] Figure 15 Schematic diagram of the third first-stage turn-off drive voltage control sub-unit in an embodiment of the present invention;

[0086] Figure 16 Schematic diagram of the second-stage turn-off drive voltage control sub-unit in an embodiment of the present invention;

[0087] Figure 17 Schematic diagram of the turn-off stage signal control unit in an embodiment of the present invention;

[0088] Figure 18 Operating waveform diagram of the NMOS transistor of the present invention during the turn-on process;

[0089] Figure 19 Operating waveform diagram of the NMOS transistor of the present invention during the turn-off process.

[0090] Description of reference numerals:

[0091] 10 - Feedback loop;

[0092] 100 - Turn-on gate drive module;

[0093] 200 - Turn-off gate drive module;

[0094] 110 - Turn-on stage signal control unit;

[0095] 120 - Turn-on drive voltage control unit;

[0096] 121 - First-stage turn-on drive voltage control sub-unit;

[0097] 122 - Second-stage turn-on drive voltage control sub-unit;

[0098] 210 - Turn-off stage signal control unit;

[0099] 220 - Turn-off drive voltage control unit;

[0100] 221 - First-stage turn-off drive voltage control sub-unit;

[0101] 222 - Second-stage turn-off drive voltage control sub-unit;

[0102] MN - NMOS transistor;

[0103] Mh1 - First loop transistor;

[0104] Mh2 - Second loop transistor;

[0105] Mh3 - Third loop transistor;

[0106] Mh4 - Fourth loop transistor;

[0107] Dh1 - First loop diode;

[0108] ibias - Current source;

[0109] CS - High - voltage capacitor;

[0110] CSNB - First capacitor;

[0111] CDC - Second capacitor;

[0112] HVDC - High - voltage direct current voltage;

[0113] Vsw - Switching voltage;

[0114] VDD - Power supply voltage;

[0115] GND - Ground voltage;

[0116] MP1 - First PMOS transistor;

[0117] MN1 - First NMOS transistor;

[0118] M1 - First transistor;

[0119] M2 - Second transistor;

[0120] M3 - Third transistor;

[0121] M4 - Fourth transistor;

[0122] M5 - Fifth transistor;

[0123] M6 - Sixth transistor;

[0124] M7 - Seventh transistor;

[0125] M8 - Eighth transistor;

[0126] M9 - Ninth transistor;

[0127] M10 - Tenth transistor;

[0128] R1 - First resistor;

[0129] R2 - Second resistor;

[0130] R3 - Third resistor;

[0131] R4 - Fourth resistor;

[0132] R5 - The fifth resistor;

[0133] R6 - The sixth resistor;

[0134] R7 - The seventh resistor;

[0135] R8 - The eighth resistor;

[0136] R9 - The ninth resistor;

[0137] R10 - The tenth resistor;

[0138] R11 - The eleventh resistor;

[0139] R12 - The twelfth resistor;

[0140] R13 - The thirteenth resistor;

[0141] D1 - The first diode;

[0142] D2 - The second diode;

[0143] D3 - The third diode;

[0144] D4 - The fourth diode;

[0145] DZ1 - The first Zener diode;

[0146] DZ2 - The second Zener diode;

[0147] NOT1 - The first inverter;

[0148] NOT2 - The second inverter;

[0149] NOT3 - The third inverter;

[0150] CMP1 - The first comparator;

[0151] CMP2 - The second comparator;

[0152] N1 - The first logic gate circuit;

[0153] N2 - The second logic gate circuit;

[0154] V on - The first set voltage;

[0155] V off - The second set voltage;

[0156] In - The gate control signal;

[0157] Von_phase1 - The first - stage turn - on control signal;

[0158] Von_phase2 - The second - stage turn - on control signal;

[0159] Voff_phase1 - The first - stage turn - off control signal;

[0160] Voff_phase2 - The second - stage turn - off control signal;

[0161] on_phase - The turn - on control signal;

[0162] off_phase - The turn - off control signal;

[0163] V GS - The gate - source voltage of the NMOS transistor;

[0164] V GH - The maximum turn - on drive voltage;

[0165] V GL - The minimum turn - off drive voltage;

[0166] V MP - The Miller - plateau voltage

[0167] V1 - The first threshold voltage;

[0168] V2 - The second threshold voltage. Detailed implementation manners

[0169] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0170] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above - mentioned accompanying drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non - exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily need to be limited to those clearly listed steps or units, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0171] Next, the technical solutions of the present invention will be described in detail with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0172] As described in the background art, it is difficult for the prior art to solve the technical problems of current overshoot and voltage overshoot in the turn-on process and turn-off process of the NMOS transistor in the power switch circuit. The following will be described in detail with reference to the drawings.

[0173] In a traditional power switch circuit, the gate drive circuit uses a preset turn-on drive voltage and a preset turn-off drive voltage to drive the turn-on and turn-off of the NMOS transistor. During the turn-on and turn-off processes of the NMOS transistor, the magnitude of the output drive voltage of the gate drive circuit remains unchanged.

[0174] In this case, during the turn-on process of the NMOS transistor, since the turn-on drive voltage is constant and is the maximum turn-on drive voltage, the NMOS transistor quickly changes from the off state to the on state, which will result in a very high rate of change of current. The drain current waveform of the NMOS transistor will exceed the current value of the rated current of the load, that is, the problem of current overshoot occurs;

[0175] During the turn-off process of the NMOS transistor, since the turn-off drive voltage is fixed and is the minimum turn-off drive voltage, the NMOS transistor quickly changes from the on state to the off state. At this time, due to the inductive characteristics of the load or the existence of parasitic inductance, the drain-source voltage of the NMOS transistor will appear a voltage spike, exceeding the normal range of the bus voltage, that is, the problem of voltage overshoot occurs.

[0176] In response to the above problems, in a specific solution, the gate of the NMOS transistor receives a gate drive signal through a relatively large gate drive resistor. The gate drive resistor can control the charging and discharging speed of the gate of the NMOS transistor, thereby suppressing current overshoot and voltage overshoot during the turn-on process and turn-off process of the NMOS transistor.

[0177] However, in this solution, the existence of the gate drive resistor will result in large losses in the power switch circuit and cannot effectively reduce the power density. Moreover, in the drive solution using a relatively large gate drive resistor, there will also be a problem that the turn-on time and turn-off time of the NMOS transistor are relatively longer.

[0178] In another specific solution, please refer to Figure 1 , Figure 1 shows a power switch circuit, wherein:

[0179] The gate of the NMOS transistor MN is coupled to the first end of the feedback loop 10. The source of the NMOS transistor MN is respectively coupled to the second end of the feedback loop 10 and grounded to GND. The drain of the NMOS transistor MN is coupled to the third end of the feedback loop. The feedback loop 10 senses the change in the drain-source voltage of the NMOS transistor MN through the high-voltage capacitor CS therein. Furthermore, when there are current overshoot and voltage overshoot in the NMOS transistor, the drive current output to the gate of the NMOS transistor MN is reduced to suppress the current overshoot and voltage overshoot during the turn-on and turn-off processes of the NMOS transistor. Among them, the first loop transistor Mh1, the second loop transistor Mh2, the third loop transistor Mh3, the fourth loop transistor Mh4, the current source ibias, and the high-voltage capacitor CS constitute the feedback loop 10.

[0180] Although this solution can achieve the suppression of current overshoot and voltage overshoot of the NMOS transistor, it has high requirements for bandwidth and there are theoretical problems of delay and stability. Therefore, the switching overlap time is long, which is not conducive to high-frequency use.

[0181] In another specific solution, please refer to Figure 2 , Figure 2 which shows a power switch circuit with a half-bridge structure, where:

[0182] Both ends of the first capacitor CSNB and both ends of the second capacitor CCD are respectively coupled to the first end and the second end of the half-bridge structure to form a buffer circuit. Among them, the first end and the second end of the half-bridge structure receive the high-voltage DC voltage HVDC and the ground voltage GND respectively, and the third end of the half-bridge structure receives the switching voltage Vsw. Among them, the buffer circuit can have various forms. Figure 2 Taking the CSNB peripheral buffer circuit as an example.

[0183] This technical solution suppresses the current overshoot and voltage overshoot during the turn-on and turn-off processes of the NMOS transistor by adding the buffer circuit around the two power switch circuits. However, the peripheral buffer circuit solution introduces many discrete devices, resulting in a complex peripheral circuit, occupying a large area, and increasing the system cost.

[0184] In view of this, the present invention provides a gate drive circuit for an NMOS transistor. When the NMOS transistor needs to be turned on, the voltage of the output turn-on control signal is adjusted to a first-stage turn-on voltage, which is greater than the Miller plateau voltage and less than the maximum turn-on drive voltage. And only when the gate-source voltage of the NMOS transistor is greater than or equal to the first threshold voltage, the voltage of the turn-on control signal is controlled to be the maximum turn-on drive voltage. When the NMOS transistor needs to be turned off, the voltage of the output turn-off control signal is adjusted to a first-stage turn-off voltage, which is less than the threshold voltage of the NMOS transistor and less than the minimum turn-off drive voltage. And only when the gate-source voltage of the NMOS transistor is less than or equal to the second threshold voltage, the voltage of the turn-off control signal is controlled to be the minimum turn-off drive voltage. Thus, through the two-stage drive scheme, the present invention realizes the suppression of current overshoot and voltage overshoot of the NMOS transistor, and also takes into account the relatively fast turn-on speed and turn-off speed.

[0185] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0186] Please refer to Figure 3 , an embodiment of the present invention provides a gate drive circuit for an NMOS transistor MN. The output end of the gate drive circuit is coupled to the control end of the NMOS transistor MN. The input end of the gate drive circuit receives a gate control signal In. The gate drive circuit includes:

[0187] A turn-on gate drive module 100, whose output end is coupled to the control end of the NMOS transistor MN, and whose input end receives the gate control signal In, is configured to:

[0188] When the gate control signal In represents turn-on, an turn-on control signal on_phase is output to the control end of the NMOS transistor MN, and the voltage of the turn-on control signal on_phase is adjusted to a first-stage turn-on voltage, which is greater than the Miller plateau voltage V MP , and less than the maximum turn-on drive voltage V GH ;

[0189] And the voltage of the turn-on control signal on_phase is adjusted based on the gate-source voltage of the NMOS transistor MN, where:

[0190] Only when the gate-source voltage of the NMOS transistor MN is greater than or equal to the first threshold voltage V1, the voltage of the turn-on control signal on_phase is controlled to be the maximum turn-on drive voltage V GH , the first threshold voltage V1 is less than the first-stage turn-on voltage and greater than the Miller plateau voltage V MP ;

[0191] The turn-off gate driving module 200, whose output terminal is coupled to the control terminal of the NMOS transistor MN, and whose input terminal receives the gate control signal In, is configured as follows:

[0192] When the gate control signal In represents a turn-off, an off-phase control signal is output to the control terminal of the NMOS transistor MN, and the voltage of the off-phase control signal is adjusted to a first-stage turn-off voltage, and the first-stage turn-off voltage is greater than the minimum turn-off driving voltage V GL , and less than the threshold voltage of the NMOS transistor MN;

[0193] And the voltage of the off-phase control signal is adjusted based on the gate-source voltage of the NMOS transistor MN, where:

[0194] Only when the gate-source voltage of the NMOS transistor MN is less than or equal to the second threshold voltage V2, the voltage of the off-phase control signal is controlled to be the minimum turn-off driving voltage V GL , and the second threshold voltage V2 is greater than the first-stage turn-off voltage and less than the threshold voltage of the NMOS transistor MN.

[0195] As an example, the NMOS transistor provided by the present invention is a SiC MOSFET. Of course, the present invention is not limited thereto, and it may also be a GaN MOSFET, etc. Those skilled in the art can select a suitable NMOS transistor for control according to needs.

[0196] Taking the NMOS transistor as a SiC MOSFET as an example, when the rated current of the SiC MOSFET is 10A to 40A, the maximum turn-on driving voltage V GH usually ranges from 15V to 18V, the minimum turn-off driving voltage V GL usually ranges from -5V to 0V, the Miller plateau voltage V MP usually ranges from 6V to 10V, the threshold voltage of the SiC MOSFET is 5V to 10V, where the first-stage turn-on voltage is 10 to 15V, and the first-stage turn-off voltage is 0V to 5V; of course, it should be understood that the present invention is not limited thereto, and those skilled in the art can select the appropriate maximum turn-on driving voltage V GH , the minimum turn-off driving voltage V GL , the Miller plateau voltage V MP , the first-stage turn-on voltage and the first-stage turn-off voltage according to the type of the NMOS transistor as needed.

[0197] The working state of the NMOS transistor of the present invention will now be described:

[0198] During the turn-on process of the NMOS transistor MN, current overshoot occurs in the time period when the gate voltage of the NMOS transistor MN is less than the first threshold voltage. Among them, the time period when the gate voltage of the NMOS transistor MN is less than the first threshold voltage is the first stage of the turn-on process, and the time period when the gate voltage of the NMOS transistor MN is greater than or equal to the first threshold voltage is the second stage of the turn-on process.

[0199] Among them, the first threshold voltage V1 is slightly less than the turn-on voltage of the first stage, and the first threshold voltage V1 is 0.9 times the turn-on voltage of the first stage. Of course, it should be understood that the present invention is not limited thereto, and those skilled in the art can set the first threshold voltage according to requirements.

[0200] During the turn-off process of the NMOS transistor MN, voltage overshoot occurs in the time period when the gate voltage of the NMOS transistor MN is greater than the second threshold voltage V2. Among them, the time period when the gate voltage of the NMOS transistor MN is greater than the second threshold voltage is the first stage of the turn-off process, and the time period when the gate voltage of the NMOS transistor MN is less than or equal to the second threshold voltage is the second stage of the turn-off process.

[0201] Among them, the second threshold voltage V2 is slightly greater than the turn-off voltage of the second stage, and the second threshold voltage V2 is 1.1 times the turn-on voltage of the second stage. Of course, it should be understood that the present invention is not limited thereto, and those skilled in the art can set the second threshold voltage according to requirements.

[0202] It can be seen that when the turn-on signal comes, the NMOS transistor MN is driven to turn on at the turn-on voltage of the first stage during the first stage of the turn-on process. The turn-on voltage of the first stage is determined by the first set voltage Von, and both the first set voltage Von and the turn-on voltage of the first stage are greater than the Miller plateau voltage V MP and less than the maximum drive voltage V GH , during the first stage of the turn-on process, the driving strength of the NMOS transistor MN is relatively small, so that the current overshoot of the NMOS transistor MN during the turn-on process can be reduced. During the second stage of the turn-on process, the driving voltage of the gate drive circuit for the NMOS transistor MN is switched to the maximum turn-on drive voltage to accelerate the turn-on process.

[0203] The turn-off process has a similar control process. The NMOS transistor MN is driven to turn off at the turn-off voltage of the first stage during the first stage of the turn-off process. The turn-off voltage of the first stage is determined by the second set voltage V off The decision is that the first-stage turn-off voltage and the second set voltage V off All is greater than the minimum turn-off drive voltage V GL and less than the threshold voltage V of the NMOS transistor TH . In the first stage of the turn-off process, the driving strength received by the NMOS transistor MN is relatively small, so that the voltage overshoot during the turn-off process can be reduced. In the second stage of the turn-on process, the driving voltage of the gate driving circuit for the NMOS transistor is switched to the minimum turn-off drive voltage V GL to accelerate the turn-off process.

[0204] Therefore, through the two-stage driving scheme of the present invention, the suppression of current overshoot and voltage overshoot of the NMOS transistor is achieved, and at the same time, a relatively fast turn-on speed and turn-off speed are taken into account.

[0205] Now, the internal structure of the turn-on gate driving module 100 will be further elaborated.

[0206] In one embodiment, please refer to Figure 4 . The turn-on gate driving module 100 includes a turn-on stage signal control unit 110 and a turn-on drive voltage control unit 120;

[0207] The input end of the turn-on stage signal control unit 110 receives the gate control signal In, its first output end is coupled to the first input end of the turn-on drive voltage control unit 120, its second output end is coupled to the second input end of the turn-on drive voltage control unit 120, and the output end of the turn-on drive voltage control unit 120 is coupled to the control end of the NMOS transistor MN;

[0208] The turn-on stage signal control unit 110 is configured to: if the gate control signal In indicates turn-on and the gate-source voltage of the NMOS transistor MN is less than the first threshold voltage V1, then output a first-stage turn-on control signal Von_phase1 to the first input end of the turn-on drive voltage control unit 120; and

[0209] if the gate control signal In indicates turn-on and the gate-source voltage of the NMOS transistor MN is greater than or equal to the first threshold voltage V1, then output a second-stage turn-on control signal Von_phase2 to the second input end of the turn-on drive voltage control unit 120;

[0210] The turn-on drive voltage control unit 120 is configured to: if its first input end receives the first-stage turn-on control signal Von_phase1, then adjust the voltage of the turn-on control signal to the first-stage turn-on voltage; and

[0211] If its second input terminal receives a second-stage turn-on control signal Von_phase2, then the voltage of the turn-on control signal is controlled to be the maximum turn-on drive voltage V GH 。

[0212] In a specific embodiment, please refer to Figure 5 The turn-on drive voltage control unit 120 includes a first-stage turn-on drive voltage control sub-unit 121, a second-stage turn-on drive voltage control sub-unit 122, and a first PMOS transistor MP1;

[0213] The input terminal of the first-stage turn-on drive voltage control sub-unit 121 is coupled to the first output terminal of the turn-on stage signal control unit 110. The receiving terminal of the first-stage turn-on drive voltage control sub-unit 121 receives a first set voltage Von. The first terminal of the first-stage turn-on drive voltage control sub-unit 121 is coupled to the gate of the first PMOS transistor MP1. The second terminal of the first-stage turn-on drive voltage control sub-unit 121 and the source of the first PMOS transistor MP1 receive the maximum turn-on drive voltage V GH 。 The third terminal of the first-stage turn-on drive voltage control sub-unit 121 and the drain of the first PMOS transistor MP1 are coupled to the control terminal of the NMOS transistor MN. Among them, the first set voltage Von is greater than the Miller plateau voltage V MP , and less than the maximum turn-on drive voltage V GH ;

[0214] The first-stage turn-on drive voltage control sub-unit 121 is configured to: if it receives the first-stage turn-on control signal Von_phase1, then adjust the voltage of the turn-on control signal on_phase to the first-stage turn-on voltage;

[0215] The input terminal of the second-stage turn-on drive voltage control sub-unit 121 is coupled to the second output terminal of the turn-on stage signal control unit 110. Its first terminal is coupled to the gate of the first PMOS transistor MP1, and the second terminal is grounded to GND, and is configured to:

[0216] If it receives the second-stage turn-on control signal Von_phase2, then control the voltage of the turn-on control signal on_phase to be the maximum turn-on drive voltage V GH 。

[0217] Among them, since a relatively high voltage will appear in the gate drive circuit of the NMOS transistor MN during the turn-on process of the power switch circuit, the first PMOS transistor MP1 is a high-voltage-resistant transistor.

[0218] Among them, in a specific embodiment, the turn-on voltage of the first stage is determined by the first set voltage V on However, it is difficult to reach the first set voltage, and the turn-on voltage of the first stage is usually slightly less than the first set voltage V on . Now, the internal structure of the first-stage turn-on drive voltage control sub-unit 121 in the turn-on drive voltage control unit 120 will be specifically described:

[0219] In a specific embodiment, please refer to Figure 6 , the first-stage turn-on drive voltage control sub-unit 121 includes:

[0220] A first transistor M1, a second transistor M2, a third transistor M3, a first resistor R1, a first diode D1, a fourth transistor M4, a fifth transistor M5, and a second diode D2;

[0221] The gate of the first transistor M1 is coupled to the first output terminal of the turn-on stage signal control unit 110 to receive the first-stage turn-on control signal Von_phase1, and the voltage of the first-stage turn-on control signal Von_phase1 is the first voltage. The source of the first transistor M1 is grounded to GND, and the drain of the first transistor M1 is coupled to the drain of the second transistor M2, the gate of the second transistor M2, and the gate of the third transistor M3. The source of the second transistor M2, the source of the third transistor M3, and the first end of the first resistor R1 all receive the maximum turn-on drive voltage V GH , the drain of the third transistor M3 is coupled to the positive electrode of the first diode D1, the drain of the fourth transistor M4, the gate of the fourth transistor M4, and the gate of the fifth transistor M5. The negative electrode of the first diode D1 receives the first set voltage V on , the second end of the first resistor R1 and the drain of the fifth transistor M5 are both coupled to the gate of the first PMOS transistor MP1. The source of the fourth transistor M4 and the source of the fifth transistor M5 are both coupled to the positive electrode of the second diode D2, and the negative electrode of the second diode D2 is coupled to the drain of the first PMOS transistor MP1; among them, the first transistor M1, the fourth transistor M4, and the fifth transistor M5 are NMOS transistors, the second transistor M2 and the third transistor M3 are PMOS, and the first diode D1 and the second diode D2 have the same specifications;

[0222] The first voltage is greater than the threshold voltage of the first transistor M1;

[0223] The turn-on voltage of the first stage is equal to the first set voltage V onSubtract the threshold voltage of the fourth transistor M4.

[0224] Wherein, during the turn-on process of the NMOS transistor MN, a relatively high voltage will appear in the gate drive circuit of the NMOS transistor MN. Therefore, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are high-voltage-resistant transistors. Of course, it should be understood that the present invention is not limited thereto, and those skilled in the art can select appropriate types of transistors as the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 according to requirements.

[0225] Wherein, the first voltage is 4V to 6V. Of course, the present invention is not limited thereto, and the first voltage only needs to satisfy being greater than the threshold voltage of the first transistor M1 and not damaging the first transistor M1.

[0226] Wherein, when the first transistor M1 receives the first-stage turn-on control signal Von_phase1, the drain voltage of the first PMOS transistor MP1 and the gate voltage of the NMOS transistor MN are at the minimum turn-off drive voltage V GL , since the first-stage turn-on control signal Von_phase1 is configured as the first voltage, the first transistor M1 conducts, and a first current is generated in the branch of the first transistor M1 and the second transistor M2. After the first transistor M1 conducts, the current mirrors formed by the second transistor M2 and the third transistor M3 and the current mirrors formed by the fourth transistor M4 and the fifth transistor M5 copy the first current to the branch where the third resistor R3 is located, resulting in a decrease in the gate voltage of the first PMOS transistor MP1. The first PMOS transistor MP1 conducts. After the first PMOS transistor MP1 conducts, the drain voltage of the first PMOS transistor MP1 and the gate voltage of the NMOS transistor MN rapidly increase, and the drain voltage of the fourth transistor M4 also increases with the increase in the drain voltage of the first PMOS transistor MP1. During this process, the first diode D1 remains reverse-biased until the drain voltage of the fourth transistor M4 is greater than the first set voltage V on plus the voltage of the first diode D1, and the first diode D1 conducts. At this time, most of the first current flows along the third transistor M3 and the positive electrode of the first diode D1 to the negative electrode of the first diode D1, and a small part of the first current flows to the drain of the fourth transistor M4. Therefore, the drain voltage of the first PMOS transistor MP1 and the gate voltage of the NMOS transistor MN are stabilized at the first-stage drive voltage during the first stage of the turn-on process. Wherein, the formula for the first-stage drive voltage is:

[0227] V OUTH = V on + V D1 - V GS4 - V D2 (1)

[0228] Among them, V OUTH is the turn-on voltage of the first stage, V D1 is the voltage V of the first diode D1 D2 is the voltage of the second diode D2, V GS4 is the gate-source voltage of the fourth transistor M4

[0229] In a specific embodiment, since only a small amount of the first current flows through the fourth transistor M4, the gate-source voltage of the fourth transistor M4 is the threshold voltage V TH4 of the fourth transistor M4; and the voltages of the first diode D1 and the second diode D2 are equal, so the formula for the turn-on voltage of the first stage can be expressed as:

[0230] V OUTH = V on - V TH4 (2)

[0231] Among them, V TH4 is the threshold voltage of the fourth transistor M4

[0232] As a preferred embodiment, please refer to Figure 7 , the turn-on drive voltage control sub-unit 121 of the first stage further includes: a second resistor R2 and a third resistor R3;

[0233] The second resistor R2 is connected in series between the drain of the first transistor M1 and the drain of the second transistor M2, and the third resistor R3 is connected in series between the drain of the third transistor M3 and the drain of the fourth transistor M4

[0234] Among them, the second resistor R2 and the third resistor R3 are used to limit the current magnitude in the turn-on drive voltage control sub-unit 121 of the first stage to prevent excessive current from damaging the components therein

[0235] As a preferred embodiment, please refer to Figure 8 , the turn-on drive voltage control sub-unit 121 of the first stage further includes: a first Zener diode DZ1;

[0236] The first end of the first Zener diode DZ1 is coupled to the gate of the first PMOS transistor MP1, and the second end is coupled to the source of the first PMOS transistor MP1

[0237] Among them, the first Zener diode DZ1 can stabilize the gate voltage of the first PMOS transistor MP1.

[0238] Now, the internal specific structure of the second-stage turn-on drive voltage control sub-unit 122 in the turn-on drive voltage control unit 120 will be described:

[0239] As an implementation manner, please refer to Figure 9 , the second-stage turn-on drive voltage control sub-unit 122 includes: a sixth transistor M6, a first inverter NOT1, and a second inverter NOT2;

[0240] The first end of the first inverter NOT1 is coupled to the second output end of the turn-on stage signal control unit 110 to receive the second-stage turn-on control signal Von_phase2. The second end of the first inverter NOT1 is coupled to the first end of the second inverter NOT2. The second end of the second inverter NOT2 is coupled to the gate of the sixth transistor M6. The drain of the sixth transistor M6 is coupled to the gate of the first PMOS transistor MP1. The source of the sixth transistor M6 is grounded to GND. The sixth transistor is an NMOS transistor.

[0241] Among them, when the first inverter NOT1 and the second inverter NOT2 receive the second-stage turn-on control signal Von_phase2, the voltage of the second-stage turn-on control signal Von_phase2 is configured to be greater than the threshold voltage of the sixth transistor M6, so that the sixth transistor conducts. After the sixth transistor M6 conducts, the first PMOS transistor MP1 conducts, and the drain voltage of the first PMOS transistor MP1, which is also the gate voltage of the NMOS transistor MN, rises to the maximum turn-on drive voltage V GH .

[0242] Among them, during the turn-on process of the NMOS transistor MN, a relatively high voltage will appear in the gate drive circuit of the NMOS transistor MN. Therefore, the sixth transistor M6 is a high-voltage-resistant transistor. Of course, it should be understood that the present invention is not limited thereto, and those skilled in the art can select a suitable type of transistor as the sixth transistor M6 according to requirements.

[0243] Now, the internal structure of the turn-on stage signal control unit 110 in the turn-on drive voltage control unit 100 will be specifically described:

[0244] As a specific implementation manner, please refer to Figure 10, the turn-on stage signal control unit 110 includes: a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first comparator CMP1, and a first logic gate circuit N1;

[0245] The first end of the fourth resistor R4 receives the gate-source voltage of the NMOS transistor MN, the second end of the fourth resistor R4 is coupled to the non-inverting input terminal of the first comparator and the first end of the fifth resistor R5, and the second end of the fifth resistor R5 is grounded to GND;

[0246] The first end of the sixth resistor R6 receives the first threshold voltage V1, the second end of the sixth resistor R6 is coupled to the inverting input terminal of the first comparator and the first end of the seventh resistor R7, and the second end of the seventh resistor R7 is grounded to GND;

[0247] The output terminal of the first comparator CMP1 is coupled to the first input terminal of the first logic gate circuit N1, the second input terminal of the first logic gate circuit N1 receives the gate control signal In, the first output terminal of the first logic gate circuit N1 outputs the first-stage turn-on control signal Von_phase1, and the second output terminal of the first logic gate circuit N1 outputs the second-stage turn-on control signal Von_phase2.

[0248] Now, in combination with the following formulas (3), (4), and (5), the suppression effect of the current overshoot of driving the NMOS transistor MN by a two-stage driving method during the turn-on process of the NMOS transistor MN of the present invention will be described:

[0249] During the first stage of the turn-on process of the NMOS transistor MN, the drain current of the NMOS transistor MN is:

[0250]

[0251] where, I Don represents the drain current of the NMOS transistor MN during the first stage of the turn-on process of the NMOS transistor MN, t represents time, g represents the transconductance of the NMOS transistor MN, R G represents the gate drive resistance of the NMOS transistor MN, C G is the gate capacitance of the NMOS transistor MN, and V TH represents the threshold voltage of the NMOS transistor MN.

[0252] The first current overshoot during the turn-on process of the NMOS transistor MN in the present invention is:

[0253]

[0254] Among them, I OS1 represents the first current overshoot, and ∝ represents being proportional to;

[0255] In the conventional scheme of driving the NMOS transistor MN to turn on using a preset turn-on driving voltage, the maximum turn-on driving voltage V is always used during the turn-on process GH to drive the NMOS transistor MN to turn on, and its second current overshoot during the turn-on process of the NMOS transistor MN is:

[0256]

[0257] Among them, I OS2 represents the second current overshoot;

[0258] The turn-on voltage in the first stage is less than the maximum turn-on driving voltage V GH , and the first current overshoot is less than the second current overshoot.

[0259] It can be seen that the gate drive circuit of the NMOS transistor MN of the present invention can effectively suppress the current overshoot during the turn-on process of the NMOS transistor MN.

[0260] In the first stage of the turn-on process of the present invention, the turn-on voltage in the first stage is used to drive the NMOS transistor MN to turn on. The turn-on speed of the NMOS transistor MN of the present invention is less than that of the NMOS transistor in the conventional scheme. However, in the second stage of the turn-on process of the present invention, the maximum turn-on driving voltage V GH is used to drive the NMOS transistor MN to turn on, so the turn-on speed of the NMOS transistor MN of the present invention is also taken into account.

[0261] Now, the internal structure of the turn-off gate drive module 200 will be specifically described:

[0262] In one embodiment, please refer to Figure 11 , the turn-off gate drive module 200 includes a turn-off stage signal control unit 210 and a turn-off drive voltage control unit 220;

[0263] The input end of the turn-off stage signal control unit 210 receives the gate control signal In, its first output end is coupled to the first input end of the turn-off drive voltage control unit 220, its second output end is coupled to the second input end of the turn-off drive voltage control unit 220, and the output end of the turn-off drive voltage control unit 220 is coupled to the control end of the NMOS transistor MN;

[0264] The turn-off stage signal control unit 210 is configured to, if the gate control signal In represents turn-off and the gate-source voltage of the NMOS transistor MN is greater than or equal to the second threshold voltage V2, output a first-stage turn-off control signal Voff_phase1 to the first input terminal of the turn-off drive voltage control unit 220; and

[0265] if the gate control signal In represents turn-off and the gate-source voltage of the NMOS transistor MN is less than or equal to the first threshold voltage V1, output a second-stage turn-off control signal Voff_phase2 to the second input terminal of the turn-off drive voltage control unit 220;

[0266] The turn-off drive voltage control unit 220 is configured to: if the first-stage turn-off control signal Voff_phase1 is received at its first input terminal, adjust the voltage of the turn-off control signal off_phase to the first-stage turn-off voltage; and

[0267] if the second-stage turn-off control signal Voff_phase2 is received at its second input terminal, control the voltage of the turn-off control signal off_phase to be the minimum turn-off drive voltage V GL .

[0268] In a specific embodiment, please refer to Figure 12 , the turn-off drive voltage control unit 220 includes a first-stage turn-off drive voltage control sub-unit 221, a second-stage turn-off drive voltage control sub-unit 222, and a first NMOS transistor MN1;

[0269] The input terminal of the first-stage turn-off drive voltage control sub-unit 221 is coupled to the first output terminal of the turn-off stage signal control unit 210, the receiving terminal of the first-stage turn-off drive voltage control sub-unit 221 receives a second set voltage V off , the first terminal of the first-stage turn-off drive voltage control sub-unit 221 is coupled to the gate of the first NMOS transistor MN1, the second terminal of the first-stage turn-off drive voltage control sub-unit 221 and the source of the first NMOS transistor MN1 receive the minimum turn-off drive voltage V GL , the third terminal of the first-stage turn-off drive voltage control sub-unit 221 and the drain of the first NMOS transistor MN1 are coupled to the gate of the NMOS transistor MN, wherein the second set voltage V off is less than the threshold voltage of the NMOS transistor MN and greater than the minimum turn-off drive voltage V GL ;

[0270] The first-stage turn-off drive voltage control sub-unit 221 is configured to: if receiving the first-stage turn-off control signal Voff_phase1, adjust the voltage of the turn-off control signal to the first-stage turn-off voltage;

[0271] The input end of the second-stage turn-off drive voltage control sub-unit 222 is coupled to the second output end of the turn-off stage signal control unit 210, its first end is coupled to the gate of the first NMOS transistor MN1, and its second end receives the power supply voltage VDD, and is configured to:

[0272] If receiving the second-stage turn-off control signal Voff_phase2, control the voltage of the turn-off control signal off_phase to be the minimum turn-off drive voltage V GL .

[0273] Now, the specific internal structure of the first-stage turn-off drive voltage control sub-unit 221 will be described.

[0274] As a specific embodiment, please refer to Figure 13 , the first-stage turn-off drive voltage control sub-unit 221 includes:

[0275] The seventh transistor M7, the eighth transistor M8, the ninth transistor M9, the third diode D3, the fourth diode D4, and the eighth resistor R8;

[0276] The gate of the seventh transistor M7 is coupled to the first output end of the turn-off stage signal control unit 210, receives the first-stage turn-off control signal Voff_phase1, the voltage of the first-stage turn-off control signal Voff_phase1 is the second voltage, the second voltage is greater than the threshold voltage of the seventh transistor M7, the source of the seventh transistor M7 is grounded to GND, the drain of the seventh transistor M7 is coupled to the drain of the eighth transistor M8, the gate of the eighth transistor M8, the gate of the ninth transistor M9, and the negative electrode of the third diode D3, the positive electrode of the third diode D3 receives the second set voltage V off , the sources of the eighth transistor M8 and the ninth transistor M9 are both coupled to the negative electrode of the fourth diode D4, the positive electrode of the fourth diode D4 is coupled to the drain of the first NMOS transistor MN1, the drain of the ninth transistor M9 and the first end of the eighth resistor R8 are coupled to the gate of the first NMOS transistor MN1, and the second end of the eighth resistor R8 receives the minimum turn-off drive voltage V GL ; wherein, the seventh transistor M7 is an NMOS transistor, and the eighth transistor M8 and the ninth transistor M9 are PMOS transistors;

[0277] The first-stage turn-off voltage is equal to the second set voltage V off plus the absolute value of the threshold voltage of the eighth transistor M10.

[0278] Wherein, during the turn-off process of the NMOS transistor MN, a relatively high voltage will appear in the gate drive circuit of the NMOS transistor MN. Therefore, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are high-voltage-resistant transistors. Of course, it should be understood that the present invention is not limited thereto, and those skilled in the art can select appropriate types of transistors as the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 according to requirements.

[0279] Wherein, the second voltage is: 4V to 5V. Of course, it should be understood that the present invention is not limited thereto, and the second voltage only needs to satisfy being greater than the threshold voltage of the seventh transistor M7.

[0280] Wherein, when the seventh transistor M7 receives the first-stage turn-off control signal Voff_phase1, the drain of the first NMOS transistor MN1, that is, the gate voltage of the NMOS transistor MN, is at the maximum turn-on drive voltage V GH , since the voltage of the first-stage turn-off signal Off_phase is the second voltage, and the second voltage is greater than the threshold voltage of the seventh transistor M7, the seventh transistor M7 conducts, and a second current is generated in the branch of the seventh transistor M7 and the eighth transistor M8. The second current is copied to the branch where the eighth resistor R8 is located through the eighth transistor M8 and the ninth transistor M9, the gate voltage of the first NMOS transistor MN1 increases, the first NMOS transistor MN1 conducts, the drain voltage of the first NMOS transistor MN1, that is, the gate voltage of the NMOS transistor MN, decreases, and the drain voltage of the eighth transistor M8 decreases as the drain voltage of the first NMOS transistor MN1 decreases. During this process, the third diode D3 always remains reverse-biased until the drain voltage of the eighth transistor M8 is less than the second set voltage V off minus the voltage of the third diode D3, the third diode D3 conducts. At this time, the driving ability of the first NMOS transistor MN1 is limited, and the drain voltage of the first MOS transistor is controlled at the first-stage turn-off voltage. The formula for the first-stage turn-off voltage is:

[0281] V OUTL = V Off + V D3 - |V GS8 |- V D4 (6)

[0282] Among them, V OUTH is the turn-off voltage of the first stage, V D3 is the voltage of the third diode D3, V D4 is the voltage of the fourth diode D4, V GS8 is the gate-source voltage of the eighth transistor M8.

[0283] In a specific embodiment, since only a small amount of the second current flows through the eighth transistor M4, the gate-source voltage of the eighth transistor M8 is the threshold voltage V TH8 ;

[0284] And the voltage of the third diode D3 is equal to the voltage of the fourth diode D4, so the formula for the turn-off voltage of the first stage can be expressed as:

[0285] V OUTL = V off -|V TH8 | (7)

[0286] Among them, V OUTL is the turn-on voltage of the first stage, V TH8 is the threshold voltage of the eighth transistor M8.

[0287] As a preferred embodiment, please refer to Figure 14 , the first-stage turn-off drive voltage control sub-unit 221 further includes: a ninth resistor R9;

[0288] The ninth resistor R9 is connected in series between the drain of the seventh transistor M7 and the drain of the eighth transistor M8.

[0289] Among them, the ninth resistor R9 is used to limit the current in the first-stage turn-off drive voltage control sub-unit 221 to prevent excessive current in the circuit from damaging the devices in the first-stage turn-off drive voltage control sub-unit 221.

[0290] As a preferred embodiment, please refer to Figure 15 , the first-stage turn-off drive voltage control sub-unit 221 further includes: a second Zener diode DZ2;

[0291] The first end of the second Zener diode DZ2 is coupled to the gate of the first NMOS transistor MN1, and the second end receives the minimum turn-off drive voltage V GL .

[0292] Among them, the second Zener diode DZ2 is used to stabilize the gate voltage of the first NMOS transistor MN1.

[0293] Now, the specific internal structure of the second-stage turn-off drive voltage control sub-unit 222 will be described.

[0294] In a specific embodiment, please refer to Figure 16 , the second-stage turn-off drive voltage control sub-unit 222 includes: a third inverter NOT3 and a tenth transistor M10;

[0295] The first terminal of the third inverter NOT3 is coupled to the second output terminal of the turn-off stage signal control unit 210 to receive the second-stage turn-off control signal Voff_phase2. The second terminal of the third inverter NOT3 is coupled to the gate of the tenth transistor M10. The drain of the tenth transistor M10 is coupled to the gate of the first NMOS transistor MN1. The source of the tenth transistor M10 receives the power supply voltage VDD. The tenth transistor M10 is a PMOS transistor.

[0296] Wherein, the voltage of the second-stage turn-off signal Off_phase is the second voltage. The third inverter NOT3 configures the voltage of the second-stage turn-off signal to be less than the threshold voltage of the tenth transistor M10. The tenth transistor M10 is turned on, pulling down the drain voltage of the tenth transistor M10 and the gate voltage of the first NMOS transistor MN1. The first NMOS transistor MN1 is turned on, and the drain voltage of the first NMOS transistor MN1 and the gate voltage of the NMOS transistor MN are pulled down to the minimum turn-off drive voltage V GL .

[0297] Now, the internal structure of the turn-off stage signal control unit 210 in the turn-off gate drive module 200 will be described.

[0298] As a specific embodiment, please refer to Figure 17 , the turn-off stage signal control unit 210 includes: a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, a second comparator CMP2, and a second logic gate circuit N2;

[0299] The first terminal of the tenth resistor R10 receives the gate-source voltage of the NMOS transistor MN. The second terminal of the tenth resistor R10 is coupled to the non-inverting input terminal of the second comparator CMP2 and the first terminal of the eleventh resistor R11. The second terminal of the eleventh resistor R11 is grounded to GND;

[0300] The first end of the twelfth resistor R12 receives the second threshold voltage V2. The second end of the twelfth resistor R12 is coupled to the inverting input terminal of the second comparator CMP2 and the first end of the thirteenth resistor R13. The second end of the thirteenth resistor R13 is grounded to GND;

[0301] The output terminal of the second comparator CMP2 is coupled to the first input terminal of the second logic gate circuit N2. The second input terminal of the second logic gate circuit N2 receives the gate control signal In. The first output terminal of the second logic gate circuit N2 outputs the first-stage turn-off control signal Voff_phase1, and the second output terminal of the second logic gate circuit N2 outputs the second-stage turn-off control signal Voff_phase2.

[0302] Now, in combination with the following formula (8), formula (9), and formula (10), the suppression effect of the voltage overshoot of the NMOS transistor MN of the present invention during the turn-off process by means of two-stage driving will be described:

[0303] During the first stage in the turn-off process of the NMOS transistor MN, the formula for the drain current of the NMOS transistor MN is:

[0304]

[0305] where, I Doff represents the drain current of the NMOS transistor MN during the first stage in the turn-off process of the NMOS transistor MN;

[0306] The first voltage overshoot of the NMOS transistor MN in the present invention during the turn-off process is:

[0307]

[0308] where, V OS1 represents the first voltage overshoot;

[0309] In the traditional scheme of driving the turn-off of the NMOS transistor MN using a preset turn-off driving voltage, the minimum turn-off driving voltage V GL is always used to drive the turn-off of the NMOS transistor MN during the turn-off process. The second voltage overshoot of the NMOS transistor MN during the turn-off process is:

[0310]

[0311] where, V OS2 represents the second voltage overshoot;

[0312] The first-stage turn-off voltage is greater than the minimum turn-off driving voltage V GL, so the first voltage overshoot is less than the second voltage overshoot.

[0313] It can be seen that the gate driving circuit of the NMOS transistor MN of the present invention can effectively suppress the voltage overshoot of the NMOS transistor MN during the turn-off process.

[0314] In the first stage of the turn-off process of the present invention, the first-stage turn-off voltage is used to drive the NMOS transistor MN to turn off. The turn-off speed of the NMOS transistor MN of the present invention is less than that of the NMOS transistor in the traditional solution. However, in the second stage of the turn-off process of the present invention, the minimum turn-off driving voltage V GL is used to drive the NMOS transistor MN to turn off, so the turn-off speed of the NMOS transistor MN of the present invention is also taken into account.

[0315] Now, in combination with Figures 18 - 19 the working effect of the gate driving circuit of the present invention will be described. Among them, Figure 18 shows the working waveform diagram of the NMOS transistor during the turn-on process, Figure 19 shows the working waveform diagram of the NMOS transistor during the turn-off process.

[0316] Among them, please refer to Figure 18 , in Figure 18 the example of:

[0317] The abscissa t can be understood as time;

[0318] V GS can be understood as the drain-source voltage of the NMOS transistor MN;

[0319] I D can be understood as the drain current of the NMOS transistor MN;

[0320] V DS can be understood as the gate-source voltage of the NMOS transistor MN;

[0321] The black line can be understood as the curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN changing with time in the traditional solution where the maximum turn-on driving voltage V GH is always used to drive the NMOS transistor MN to turn on during the turn-on process of the NMOS transistor MN;

[0322] The green line can be understood as the curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN changing with time when the present invention uses the corresponding first-stage turn-on voltage to drive the NMOS transistor MN to turn on with the first set voltage V on being 10V;

[0323] The blue line can be understood as the change curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN over time when, in the turn-on process of the NMOS transistor in the present invention, the first set voltage V on is 11V and the NMOS transistor MN is turned on using the corresponding turn-on voltage in the first stage;

[0324] The red line can be understood as the change curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN over time when, in the turn-on process of the NMOS transistor in the present invention, the first set voltage V on is 12V and the NMOS transistor MN is turned on using the corresponding turn-on voltage in the first stage;

[0325] In the example of Figure 18 , during the time period from t1 to t2, when the first set voltage V on in the present invention is 10V, 11V, or 12V, and the NMOS transistor is turned on using the corresponding turn-on voltage in the first stage, the first current overshoot at the drain of the NMOS transistor MN in the present invention is less than the second current overshoot at the drain of the NMOS transistor MN in the conventional scheme of turning on the NMOS transistor MN using the maximum turn-on drive voltage V GH ;

[0326] During the time period from t2 to t3, the present invention uses the maximum turn-on drive voltage V GH to turn on the NMOS transistor MN to accelerate the turn-on speed of the NMOS transistor MN.

[0327] Among them, please refer to Figure 19 , in the example of Figure 19 :

[0328] The abscissa t can be understood as time;

[0329] V GS can be understood as the drain-source voltage of the NMOS transistor MN;

[0330] I D can be understood as the drain current of the NMOS transistor MN;

[0331] V DS can be understood as the gate-source voltage of the NMOS transistor MN;

[0332] The black line can be understood as the change curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN over time in the conventional scheme of always using the minimum turn-off drive voltage V GL to turn off the NMOS transistor MN;

[0333] The green line can be understood as the second set voltage V of the present invention off is 1V. When the NMOS transistor MN is turned off by driving with the corresponding first-stage turn-on voltage, the curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN changing with time;

[0334] The blue line can be understood as the second set voltage V of the present invention off is 3V. When the NMOS transistor MN is turned off by driving with the corresponding first-stage turn-on voltage, the curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN changing with time;

[0335] The red line can be understood as the second set voltage V of the present invention off is 5V. When the NMOS transistor MN is turned off by driving with the corresponding first-stage turn-on voltage, the curves of the drain-source voltage, drain current, and gate-source voltage of the NMOS transistor MN changing with time;

[0336] In Figure 19 the example of, in the time period from t4 to t5, in the present invention, when the second set voltage V off is 1V, 3V or 5V, respectively, during the process of turning off the NMOS transistor by driving with the corresponding first-stage turn-on voltage, the first voltage overshoot at the drain of the NMOS transistor MN in the present invention is less than that when using the minimum turn-off drive voltage V GL during the process of turning off the NMOS transistor MN;

[0337] In the time period from t5 to t6, the present invention uses the minimum turn-off drive voltage V GL to drive the NMOS transistor MN to turn off, so as to accelerate the turn-off speed of the NMOS transistor MN.

[0338] It can be seen that through the two-stage drive scheme of the present invention, the current overshoot suppression and voltage overshoot suppression of the NMOS transistor are realized, and the faster turn-on speed and turn-off speed are also taken into account.

[0339] In addition, a power switch circuit, the power switch circuit includes SiC MOS or GaN MOS and the gate drive circuit of the above-mentioned NMOS transistor MN;

[0340] The output end of the gate drive circuit is coupled to the control end of the NMOS transistor.

[0341] In summary, the present invention provides a gate drive circuit and a power switch circuit for an NMOS transistor. When the NMOS transistor needs to be turned on, the voltage of the output turn-on control signal is adjusted to a first-stage turn-on voltage, which is greater than the Miller plateau voltage and less than the maximum turn-on drive voltage. And only when the gate-source voltage of the NMOS transistor is greater than or equal to the first threshold voltage, the voltage of the turn-on control signal is controlled to be the maximum turn-on drive voltage. When the NMOS transistor needs to be turned off, the voltage of the output turn-off control signal is adjusted to a first-stage turn-off voltage, which is less than the threshold voltage of the NMOS transistor and less than the minimum turn-off drive voltage. And only when the gate-source voltage of the NMOS transistor is less than or equal to the second threshold voltage, the voltage of the turn-off control signal is controlled to be the minimum turn-off drive voltage. Thus, through the two-stage drive scheme, the present invention realizes the suppression of current overshoot and voltage overshoot of the NMOS transistor, and also takes into account a relatively fast turn-on speed and turn-off speed.

[0342] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A gate drive circuit for an NMOS tube, characterized in that: The output end of the gate driving circuit is coupled to the control end of the NMOS tube, and the input end of the gate driving circuit receives a gate control signal. The gate driving circuit includes: The gate drive module is turned on, the output end of which is coupled to the control end of the NMOS tube, and the input end of which receives the gate control signal, and is configured as follows: When the gate control signal is characterized as being turned on, an on control signal is output to the control end of the NMOS tube, and the voltage of the on control signal is adjusted to a first-stage on voltage, where the first-stage on voltage is greater than the Miller platform voltage and less than the maximum on drive voltage; The voltage of the turn-on control signal is adjusted based on the gate-source voltage of the NMOS tube, wherein: Only when the gate-source voltage of the NMOS tube is greater than or equal to a first threshold voltage, the voltage of the turn-on control signal is controlled to be the maximum turn-on driving voltage, the first threshold voltage is less than the first stage turn-on voltage and greater than the Miller platform voltage; The gate drive module is turned off, the output end of which is coupled to the control end of the NMOS tube, and the input end of which receives the gate control signal, and is configured as follows: When the gate control signal is characterized as off, outputting a turn-off control signal to the control end of the NMOS tube, and adjusting the voltage of the turn-off control signal to a first-stage turn-off voltage, wherein the first-stage turn-off voltage is greater than a minimum turn-off driving voltage and less than a threshold voltage of the NMOS tube; The shutdown control signal voltage is adjusted based on the gate-source voltage of the NMOS tube, wherein: Only when the gate-source voltage of the NMOS tube is less than or equal to the second threshold voltage, the voltage of the shutdown control signal is controlled to be the minimum shutdown drive voltage, and the second threshold voltage is greater than the first stage shutdown voltage and less than the threshold voltage of the NMOS tube.

2. The gate drive circuit of the NMOS tube according to claim 1, characterized in that: The opening gate driving module includes an opening phase signal control unit and an opening driving voltage control unit; The input end of the turn-on phase signal control unit receives the gate control signal, the first output end thereof is coupled to the first input end of the turn-on driving voltage control unit, the second output end thereof is coupled to the second input end of the turn-on driving voltage control unit, and the output end of the turn-on driving voltage control unit is coupled to the control end of the NMOS tube; The on-stage signal control unit is configured to output a first-stage on-control signal to a first input terminal of the on-drive voltage control unit if the gate control signal indicates on-state and the gate-source voltage of the NMOS tube is less than the first threshold voltage; as well as If the gate control signal indicates that the transistor is turned on, and the gate-source voltage of the NMOS transistor is greater than or equal to the first threshold voltage, a second-stage turn-on control signal is output to the second input terminal of the turn-on drive voltage control unit; The on-drive voltage control unit is configured to: if the first input terminal thereof receives a first-stage on-control signal, adjust the voltage of the on-control signal to a first-stage on-voltage; as well as If the second input terminal receives the second-stage on-control signal, the voltage of the on-control signal is controlled to be the maximum on-drive voltage.

3. The gate drive circuit of the NMOS tube according to claim 2, characterized in that: The on-state driving voltage control unit comprises a first-stage on-state driving voltage control subunit, a second-stage on-state driving voltage control subunit and a first PMOS tube; The input end of the first-stage turn-on driving voltage control subunit is coupled to the first output end of the turn-on stage signal control unit, the receiving end of the first-stage turn-on driving voltage control subunit receives a first set voltage, the first end of the first-stage turn-on driving voltage control subunit is coupled to the gate of the first PMOS tube, the second end of the first-stage turn-on driving voltage control subunit and the source of the first PMOS tube receive the maximum turn-on driving voltage, the third end of the first-stage turn-on driving voltage control subunit and the drain of the first PMOS tube are coupled to the control end of the NMOS tube, wherein the first set voltage is greater than the Miller platform voltage and less than the maximum turn-on driving voltage; The first-stage opening driving voltage control subunit is configured to: if the first-stage opening control signal is received, adjust the voltage of the opening control signal to the first-stage opening voltage; The input end of the second-stage on-drive voltage control subunit is coupled to the second output end of the on-stage signal control unit, the first end of which is coupled to the gate of the first PMOS tube, and the second end is grounded, and is configured as follows: If the second-stage on-control signal is received, the voltage of the on-control signal is controlled to be the maximum on-driving voltage.

4. The gate drive circuit of the NMOS tube according to claim 3, characterized in that: The first stage of opening the driving voltage control subunit includes: A first transistor, a second transistor, a third transistor, a first resistor, a first diode, a fourth transistor, a fifth transistor and a second diode; The gate of the first transistor is coupled to the first output terminal of the turn-on stage signal control unit, receives the turn-on control signal of the first stage, and the voltage of the turn-on control signal of the first stage is a first voltage, the source of the first transistor is grounded, the drain of the first transistor is coupled to the drain of the second transistor, the gate of the second transistor and the gate of the third transistor, the source of the second transistor, the source of the third transistor and the first end of the first resistor all receive the maximum turn-on driving voltage, the drain of the third transistor is coupled to the anode of the first diode, the drain of the fourth transistor, the gate of the fourth transistor and the gate of the fifth transistor, the cathode of the first diode receives the first setting voltage, the second end of the first resistor and the drain of the fifth transistor are coupled to the gate of the first PMOS tube, the source of the fourth transistor and the source of the fifth transistor are coupled to the anode of the second diode, and the cathode of the second diode is coupled to the drain of the first PMOS tube; wherein the first transistor, the fourth transistor and the fifth transistor are NMOS tubes, the second transistor and the third transistor are PMOS tubes, and the specifications of the first diode and the second diode are the same; The first voltage is greater than a threshold voltage of the first transistor; The first stage turn-on voltage is equal to the first set voltage minus the threshold voltage of the fourth transistor.

5. The gate drive circuit of the NMOS tube as claimed in claim 4, characterized in that: The first-stage opening driving voltage control subunit further includes: a second resistor and a third resistor; The second resistor is connected in series between the drain of the first transistor and the drain of the second transistor, and the third resistor is connected in series between the drain of the third transistor and the drain of the fourth transistor.

6. The gate drive circuit of the NMOS tube according to claim 4, characterized in that: The first-stage opening driving voltage control subunit further includes: a first Zener diode; A first end of the first Zener diode is coupled to the gate of the first PMOS tube, and a second end of the first Zener diode is coupled to the source of the first PMOS tube.

7. The gate drive circuit of the NMOS tube according to claim 3, characterized in that: The second-stage opening driving voltage control subunit further includes: a sixth transistor, a first inverter and a second inverter; The first end of the first inverter is coupled to the second output end of the turn-on stage signal control unit to receive the second stage turn-on control signal, the second end of the first inverter is coupled to the first end of the second inverter, the second end of the second inverter is coupled to the gate of the sixth transistor, the drain of the sixth transistor is coupled to the gate of the first PMOS tube, and the source of the sixth transistor is grounded, wherein the sixth transistor is an NMOS tube.

8. The gate drive circuit of the NMOS tube as claimed in claim 2, characterized in that: The opening stage signal control unit includes: a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first comparator and a first logic gate circuit diagram; The first end of the fourth resistor receives the gate-source voltage of the NMOS tube, the second end of the fourth resistor is coupled to the non-inverting input terminal of the first comparator and the first end of the fifth resistor, and the second end of the fifth resistor is grounded; The first end of the sixth resistor receives the first threshold voltage, the second end of the sixth resistor is coupled to the inverting input end of the first comparator and the first end of the seventh resistor, and the second end of the seventh resistor is grounded; The output end of the first comparator is coupled to the first input end of the first logic gate circuit, the second input end of the first logic gate circuit receives the gate control signal, the first output end of the first logic gate circuit outputs the first stage turn-on control signal, and the second output end of the first logic gate circuit outputs the second stage turn-on control signal.

9. The gate drive circuit of the NMOS tube according to claim 1, characterized in that: The shutdown gate drive module includes a shutdown phase signal control unit and a shutdown drive voltage control unit; The input end of the shutdown phase signal control unit receives the gate control signal, the first output end thereof is coupled to the first input end of the shutdown driving voltage control unit, the second output end thereof is coupled to the second input end of the shutdown driving voltage control unit, and the output end of the shutdown driving voltage control unit is coupled to the control end of the NMOS tube; The turn-off phase signal control unit is configured to output a first-stage turn-off control signal to a first input terminal of the turn-off drive voltage control unit if the gate control signal is characterized as turn-off and the gate-source voltage of the NMOS tube is greater than or equal to the second threshold voltage; as well as If the gate control signal is characterized as off, and the gate-source voltage is less than or equal to the first threshold voltage, outputting a second-stage off control signal to the second input terminal of the off drive voltage control unit; The shutdown driving voltage control unit is configured to: if the first input terminal thereof receives the first stage shutdown control signal, adjust the voltage of the shutdown control signal to the first stage shutdown voltage; as well as If the second input terminal receives the second-stage shutdown control signal, the voltage of the shutdown control signal is controlled to be the minimum shutdown driving voltage.

10. The gate drive circuit of the NMOS tube according to claim 9, characterized in that: The shutdown driving voltage control unit includes a first-stage shutdown driving voltage control subunit, a second-stage shutdown driving voltage control subunit and a first NMOS tube; The input end of the first-stage shutdown driving voltage control subunit is coupled to the first output end of the shutdown stage signal control unit, the receiving end of the first-stage shutdown driving voltage control subunit receives a second set voltage, the first end of the first-stage shutdown driving voltage control subunit is coupled to the gate of the first NMOS tube, the second end of the first-stage shutdown driving voltage control subunit and the source of the first NMOS tube receive the minimum shutdown driving voltage, the third end of the first-stage shutdown driving voltage control subunit and the drain of the first NMOS tube are coupled to the control end of the NMOS tube, wherein the second set voltage is less than the threshold voltage of the NMOS tube and greater than the minimum shutdown driving voltage; The first-stage shutdown driving voltage control subunit is configured to: if the first-stage shutdown control signal is received, adjust the voltage of the shutdown control signal to the first-stage shutdown voltage; The input end of the second-stage shutdown driving voltage control subunit is coupled to the second output end of the shutdown stage signal control unit, the first end thereof is coupled to the gate of the first NMOS tube, and the second end thereof receives the power supply voltage, and is configured as follows: If the second-stage shutdown control signal is received, the voltage of the shutdown control signal is controlled to be the minimum shutdown driving voltage.

11. The gate drive circuit of the NMOS tube according to claim 10, characterized in that: The first-stage shutdown driving voltage control subunit includes: a seventh transistor, an eighth transistor, a ninth transistor, a third diode, a fourth diode and an eighth resistor; The gate of the seventh transistor is coupled to the first output terminal of the shutdown phase signal control unit, and receives the first phase shutdown control signal, the voltage of the first phase shutdown control signal is a second voltage, the second voltage is greater than the threshold voltage of the seventh transistor, the source of the seventh transistor is grounded, the drain of the seventh transistor is coupled to the drain of the eighth transistor, the gate of the eighth transistor, the gate of the ninth transistor and the cathode of the third diode, the anode of the third diode receives the second set voltage, the source of the eighth transistor and the source of the ninth transistor are both coupled to the cathode of the fourth diode, the anode of the fourth diode is coupled to the drain of the first NMOS tube, the drain of the ninth transistor and the first end of the eighth resistor are coupled to the gate of the first NMOS tube, and the second end of the eighth resistor receives the minimum shutdown driving voltage; wherein the seventh transistor is an NMOS tube, and the eighth transistor and the ninth transistor are both PMOS tubes; The first stage turn-off voltage is equal to the second set voltage plus the absolute value of the threshold voltage of the eighth transistor.

12. The gate drive circuit of the NMOS tube according to claim 11, characterized in that: The first-stage shutdown driving voltage control subunit further includes: a ninth resistor; The ninth resistor is connected in series between the drain of the seventh transistor and the drain of the eighth transistor.

13. The gate drive circuit of the NMOS tube according to claim 11, characterized in that: The first-stage shutdown driving voltage control subunit further includes: a second Zener diode; A first end of the second Zener diode is coupled to the gate of the first NMOS tube, and a second end thereof receives the minimum turn-off driving voltage.

14. The gate drive circuit of the NMOS tube according to claim 10, characterized in that: The second-stage off-driving voltage control subunit comprises: a third inverter and a tenth transistor; The first end of the third inverter is coupled to the second output end of the shutdown phase signal control unit to receive the second phase shutdown control signal, the second end of the third inverter is coupled to the gate of the tenth transistor, the drain of the tenth transistor is coupled to the gate of the first NMOS tube, and the source of the tenth transistor receives the power supply voltage, wherein the tenth transistor is a PMOS tube.

15. The gate driving circuit of the NMOS tube according to claim 9, characterized in that: The shutdown phase signal control unit includes: a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a second comparator and a second logic gate circuit; The first end of the tenth resistor receives the gate-source voltage of the NMOS tube, the second end of the tenth resistor is coupled to the non-inverting input terminal of the second comparator and the first end of the eleventh resistor, and the second end of the eleventh resistor is grounded; The first end of the twelfth resistor receives the second threshold voltage, the second end of the twelfth resistor is coupled to the inverting input terminal of the second comparator and the first end of the thirteenth resistor, and the second end of the thirteenth resistor is grounded; The output of the second comparator is coupled to the first input of the second logic gate circuit, the second input of the second logic gate circuit receives the gate control signal, the first output of the second logic gate circuit outputs the first stage shutdown control signal, and the second output of the second logic gate circuit outputs the second stage shutdown control signal.

16. A power switching circuit, characterized in that: A gate drive circuit comprising an NMOS tube and the NMOS tube according to any one of claims 1 to 15; The output end of the gate driving circuit is coupled to the control end of the NMOS tube.

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