Driving circuit, circuit system and electronic equipment
By designing a driving circuit containing a dynamic compensation module, the voltage tailing problem of power tube during the opening process is solved, and effective suppression of voltage tailing and avoidance of EMI problems are achieved.
Patent Information
- Application Number
- CN202411946636.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2025-05-30
AI Technical Summary
There is a voltage tailing problem in the power tube during the opening process. The prior art may easily cause serious EMI problems or poor suppression effect when suppressing this problem.
A driving circuit is designed, including a driving module and a dynamic compensation module. The dynamic compensation module outputs a dynamic compensation current that is negatively correlated with the power tube gate voltage according to the input drive control signal to suppress voltage tailing.
It effectively suppresses the voltage tailing problem of the power switch during the opening process, avoids the occurrence of EMI problems, and improves the conduction speed and efficiency of the power tube.
Smart Images
Figure CN120074480A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic circuits, and in particular to a driving circuit, a circuit system and an electronic device. Background Art
[0002] With the development of wide bandgap devices, power transistors, as power switches, have been developed and applied very rapidly in recent years. Since the reverse transfer capacitance of the power transistor has serious nonlinearity during the conduction process of the power transistor, there will be an obvious voltage tail problem during the turn-on process of the power transistor, thus increasing the turn-on loss of the power switch.
[0003] However, when the prior art suppresses the voltage tail during the conduction of the power transistor, it will either cause serious EMI problems or have a poor suppression effect. Summary of the Invention
[0004] Embodiments of the present invention provide a driving circuit, a circuit system and an electronic device to effectively suppress the voltage tail problem existing during the turn-on process of the power switch without generating EMI problems.
[0005] To solve the above technical problems, the technical solution of the present invention provides a driving circuit, the driving circuit is used to drive a power transistor, the drain terminal of the power transistor is coupled to the ground, and the source terminal of the power transistor is coupled to a load power supply terminal through a load unit; the driving circuit includes:
[0006] A driving module, configured to:
[0007] Inject a conduction current into the gate of the power transistor according to the input driving control signal being in a first state to turn on the power transistor;
[0008] Extract a turn-off current from the gate of the power transistor according to the input driving control signal being in a second state to turn off the power transistor;
[0009] A dynamic compensation module, configured to output a dynamic compensation current to the gate of the power transistor according to the input driving control signal being in a first state, and the dynamic compensation current is negatively correlated with the gate voltage.
[0010] The first state is a high level, the second state is a low level, the dynamic compensation module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor and a first inverter, the power transistor is a gallium nitride single transistor, and the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are all NMOS transistors;
[0011] The input terminal of the first inverter and the gate of the first MOS transistor are both coupled to the drive control signal. The drain of the first MOS transistor and the drain of the third MOS transistor are both coupled to the internal supply voltage. The source of the first MOS transistor is respectively coupled to the drain of the second MOS transistor, the gate of the third MOS transistor, and the drain of the fourth MOS transistor. The gate of the second MOS transistor and the source of the third MOS transistor are both coupled to the gate of the power transistor. The source of the second MOS transistor and the source of the fourth MOS transistor are both coupled to the ground terminal. The gate of the fourth MOS transistor is coupled to the output terminal of the first inverter.
[0012] Optionally, the first state is a high level, the second state is a low level. The dynamic compensation module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a first inverter. The power transistor is an NMOS transistor or an N-channel IGBT transistor. Moreover, the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all NLDMOS transistors;
[0013] The input terminal of the first inverter and the gate of the first MOS transistor are both coupled to the drive control signal. The drain of the first MOS transistor and the drain of the third MOS transistor are both coupled to the internal supply voltage. The source of the first MOS transistor is respectively coupled to the drain of the second MOS transistor, the gate of the third MOS transistor, and the drain of the fourth MOS transistor. The gate of the second MOS transistor and the source of the third MOS transistor are both coupled to the gate of the power transistor. The source of the second MOS transistor and the source of the fourth MOS transistor are both coupled to the ground terminal. The gate of the fourth MOS transistor is coupled to the output terminal of the first inverter.
[0014] Optionally, the first transconductance ratio is less than the first threshold value. The first transconductance ratio is used to characterize the transconductance ratio of the first MOS transistor and the second MOS transistor.
[0015] Optionally, the formula for the first threshold value n1 is:
[0016]
[0017] where n1 is used to characterize the first threshold value, VDR is used to characterize the internal supply voltage, Vth1 is used to characterize the threshold voltage of the first MOS transistor, Vth2 is used to characterize the threshold voltage of the second MOS transistor, Vth3 is used to characterize the threshold voltage of the third MOS transistor, and VMP is used to characterize the Miller voltage of the power transistor.
[0018] Optionally, the first state is a high level, the second state is a low level, the dynamic compensation module includes: a first resistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a first inverter. The power transistor is a gallium nitride single transistor, and the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all NMOS transistors;
[0019] The input end of the first inverter is coupled to the drive control signal. The first end of the first resistor and the drain of the third MOS transistor are both coupled to the internal power supply voltage. The second end of the first resistor is respectively coupled to the drain of the second MOS transistor, the gate of the third MOS transistor, and the drain of the fourth MOS transistor. The gate of the second MOS transistor and the source of the third MOS transistor are both coupled to the gate of the power transistor. The source of the second MOS transistor and the source of the fourth MOS transistor are both coupled to the ground terminal; the gate of the fourth MOS transistor is coupled to the output end of the first inverter.
[0020] Optionally, the first state is a high level, the second state is a low level, the dynamic compensation module includes: a first resistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a first inverter. The power transistor is an NMOS transistor or an N-channel IGBT transistor, and the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all NLDMOS transistors;
[0021] The input end of the first inverter is coupled to the drive control signal. The first end of the first resistor and the drain of the third MOS transistor are both coupled to the internal power supply voltage. The second end of the first resistor is respectively coupled to the drain of the second MOS transistor, the gate of the third MOS transistor, and the drain of the fourth MOS transistor. The gate of the second MOS transistor and the source of the third MOS transistor are both coupled to the gate of the power transistor. The source of the second MOS transistor and the source of the fourth MOS transistor are both coupled to the ground terminal; the gate of the fourth MOS transistor is coupled to the output end of the first inverter.
[0022] Optionally, the first impedance product is less than a second threshold, and the first impedance product is used to represent the product of the resistance value of the first resistor and the transconductance of the second MOS transistor.
[0023] Optionally, the formula for the second threshold is:
[0024]
[0025] Wherein, n2 is used to represent the second threshold, VDR is used to represent the internal supply voltage, Vth1 is used to represent the threshold voltage of the first MOS transistor, Vth2 is used to represent the threshold voltage of the second MOS transistor, Vth3 is used to represent the threshold voltage of the third MOS transistor, and VMP is used to represent the Miller voltage of the power transistor.
[0026] Optionally, the driving module includes: a pull-up resistor, a pull-down resistor, a pull-up PMOS transistor, and a pull-down NMOS transistor;
[0027] The gate of the pull-up PMOS transistor is coupled to the output terminal of the first inverter, the source of the pull-up PMOS transistor is connected to the internal supply voltage, the drain of the pull-up PMOS transistor is coupled to the first end of the pull-up resistor, the second end of the pull-up resistor is respectively coupled to the gate of the power transistor and the first end of the pull-down resistor, the second end of the pull-down resistor is coupled to the drain of the pull-down NMOS transistor, the gate of the pull-down NMOS transistor is also coupled to the output terminal of the first inverter, and the source of the pull-down NMOS transistor is coupled to the ground terminal.
[0028] The technical solution of the present invention further provides a circuit system including the driving circuit.
[0029] The technical solution of the present invention further provides an electronic device including the circuit system.
[0030] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:
[0031] For the driving circuit provided by the technical solution of the present invention, since the dynamic compensation module outputs a dynamic compensation current that is negatively correlated with the gate voltage of the power transistor during the conduction process of the power transistor. Also, because the nonlinearity of the reverse transfer capacitance of the power transistor during the conduction process causes the gate voltage of the power transistor to drop, the dynamic compensation module can adjust the magnitude of the dynamic compensation current according to the drop amplitude of the gate voltage, thereby effectively suppressing the voltage tailing problem. And before the gate voltage reaches the critical voltage, the dynamic compensation current output by the dynamic compensation module can also accelerate the conduction speed of the power transistor and make the dynamic compensation current zero after the gate voltage reaches the critical voltage, thus avoiding EMI problems during the Miller plateau period.
[0032] Furthermore, by only setting 4 transistors, the voltage tailing is solved without using high-voltage devices, thus saving the circuit cost.
[0033] Further, set the ratio of the first transconductance to be less than a first threshold or the product of the second impedance to be less than a second threshold, so that the dynamic compensation module can output a dynamic compensation current that is positively correlated with the magnitude of the gate voltage drop in a timely manner according to the drop of the gate voltage, thereby improving the suppression effect on the voltage tailing of the power transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0034] Figure 1 is a waveform diagram between the reverse transfer voltage and the source-drain voltage of the power transistor;
[0035] Figure 2 is a schematic circuit structure diagram of the driving circuit provided by an embodiment of the present invention Figure 1 ;
[0036] Figure 3 is a schematic circuit structure diagram of the driving circuit provided by an embodiment of the present invention Figure 2 ;
[0037] Figure 4 is a waveform diagram of various parameters of the power transistor during the conduction process provided by an embodiment of the present invention;
[0038] Figure 5 is a waveform diagram of the dynamic compensation current and the gate voltage of the power transistor under different ratios of the first transconductance in an embodiment of the present invention;
[0039] Figure 6 is a schematic circuit structure diagram of the driving circuit provided by an embodiment of the present invention Figure 3 。 DETAILED DESCRIPTION OF THE EMBODIMENTS
[0040] In application scenarios where a power transistor is used as a power switch, such as MOS transistors, IGBT transistors, or gallium nitride single transistors, etc., during the conduction process of the power transistor, the gate voltage of the power transistor will continuously rise from zero and maintain at the Miller voltage for a period of time after rising to the Miller voltage. This stage is called the Miller plateau period. During the Miller plateau period, the source-drain voltage of the power transistor will linearly decrease from a fixed value to zero. After the source-drain voltage drops to a certain threshold, the reverse transfer capacitance of the power transistor will surge due to its severe nonlinearity, as Figure 1 shown.
[0041] Among them, the formula for the drop of the gate voltage is as follows:
[0042]
[0043] Among them, Vdrop is used to characterize the drop amplitude of the gate voltage, Ion is used to characterize the injection current of the power transistor gate, Coss is used to characterize the output capacitance of the power transistor, gfs is used to characterize the transconductance of the power transistor, CrssL is used to characterize the reverse transfer capacitance of the power transistor before the surge, and CrssH is used to characterize the reverse transfer capacitance of the power transistor after the surge.
[0044] The formula for the rate of decrease of the source-drain voltage is as follows:
[0045]
[0046] Among them, dvDS / dt is used to characterize the rate of decrease of the source-drain voltage.
[0047] It can be seen from formula (1) and formula (2) that the surge of the reverse transfer capacitance of the power transistor will simultaneously cause the drop of the gate voltage and the decrease of the rate of decrease of the source-drain voltage, thereby causing the voltage tail of the power transistor conduction, slowing down the conduction rate of the power transistor, and further increasing the conduction power consumption of the power transistor.
[0048] To solve the above problem of voltage tail during the conduction of the power transistor, the prior art usually adopts the following solutions:
[0049] 1. Drive the power transistor with a constant large current. It can be seen from formula (2) that driving with a large current can increase the rate of decrease of the source-drain voltage. When the reverse transfer capacitance increases, the decrease of the rate of decrease of the source-drain voltage can be effectively suppressed. However, a large current will also increase the gate voltage of the power transistor, resulting in an excessive rate of decrease of the source-drain voltage. And it can be found from formula (1) that a large drive current will also increase the drop amplitude of the gate voltage, thus causing serious EMI problems.
[0050] 2. Compare the source-drain voltage of the power transistor with a set reference voltage. When the source-drain voltage is lower than the set reference voltage, the power transistor is turned on with a small current. When the source-drain voltage is higher than the set reference voltage, the power transistor is turned on with a preset large current, thereby suppressing the voltage tail. However, the preset reference voltage and the preset large current cannot well follow the non-linear change of the reverse transfer capacitance, thus affecting the suppression effect of the voltage tail.
[0051] In view of this, the embodiments of the present invention provide a new drive circuit to effectively suppress the voltage tail problem existing during the turn-on process of the power switch without generating EMI problems.
[0052] Among them, Figure 2 is a schematic circuit structure of the drive circuit provided by the embodiments of the present invention Figure 1 .
[0053] Please refer toFigure 2 , the driving circuit provided by the embodiment of the present invention is used to drive the power transistor M1. The drain terminal of the power transistor M1 is coupled to the ground terminal, and the source terminal of the power transistor M1 is coupled to the load power supply terminal VDC through a load unit. The driving circuit includes: a driving module 10 and a dynamic compensation module 20.
[0054] The driving module 10 is configured to: inject a conduction current ION into the gate of the power transistor M1 according to the input driving control signal V1 being in a first state to turn on the power transistor M1; and extract a turn-off current IOFF from the gate of the power transistor M1 according to the input driving control signal V1 being in a second state to turn off the power transistor M1.
[0055] The dynamic compensation module 20 is configured to: output a dynamic compensation current Ienh to the gate of the power transistor M1 according to the input driving control signal V1 being in a first state, and the dynamic compensation current Ienh is negatively correlated with the [unspecified value].
[0056] The driving module 10 and the dynamic compensation module 20 are both integrated on the same chip.
[0057] Since the dynamic compensation current Ienh output by the dynamic compensation module 20 is negatively correlated with the gate voltage VG, therefore, it is possible to effectively suppress the voltage tailing problem existing during the turn-on process of the power switch without generating EMI problems, and accelerate the turn-on of the power transistor M1. The specific principle is as follows:
[0058] The driving module 10 turns on the power transistor M1. From the initial stage of the turn-on of the power transistor M1 to the Miller plateau period, the source-drain voltage VDS of the power transistor M1 remains at a fixed value, while the gate voltage VG of the power transistor M1 gradually increases from zero.
[0059] At the initial stage of the turn-on of the power transistor M1, the dynamic compensation module 20 outputs a relatively large dynamic compensation current Ienh to accelerate the turn-on of the power transistor M1. As the gate voltage VG continuously increases, the dynamic compensation current Ienh continuously decreases. When the gate voltage VG increases to the Miller voltage of the power transistor M1, the dynamic compensation current Ienh approaches zero and can be ignored. Therefore, the EMI problem of the power transistor M1 caused by the excessive Miller voltage of the power transistor M1 is avoided.
[0060] After entering the Miller plateau period, the source-drain voltage VDS of the power transistor M1 starts to linearly decrease. When the reverse transfer capacitance of the power transistor M1 surges non-linearly due to the decrease in the source-drain voltage VDS, according to formula (1), the gate voltage VG of the power transistor M1 will drop. At this time, the dynamic compensation module 20 will adaptively increase the dynamic compensation current Ienh according to the drop amplitude of the gate voltage VG, thereby effectively suppressing the voltage tailing problem.
[0061] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.
[0062] Among them, Figure 3 is a schematic circuit structure diagram of the drive circuit provided by the embodiment of the present invention Figure 2 . Figure 4 is a waveform diagram of each parameter of the power transistor during the conduction process provided by the embodiment of the present invention.
[0063] Please refer to Figure 3 , as a specific embodiment, the first state of the drive control signal V1 is a high level, its second state is a low level, and the power transistor M1 is a gallium nitride single transistor.
[0064] The dynamic compensation module 20 includes: a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a first inverter INV.
[0065] The input terminal of the first inverter INV and the gate of the first NMOS transistor MN1 are both coupled to the drive control signal V1. The drain of the first NMOS transistor MN1 and the drain of the third NMOS transistor MN3 are both coupled to the internal supply voltage Vdd. The source of the first NMOS transistor MN1 is respectively coupled to the drain of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3, and the drain of the fourth NMOS transistor MN4. The gate of the second NMOS transistor MN2 and the source of the third NMOS transistor MN3 are both coupled to the gate of the power transistor M1. The source of the second NMOS transistor MN2 and the source of the fourth NMOS transistor MN4 are both coupled to the ground terminal. The gate of the fourth NMOS transistor MN4 is coupled to the output terminal of the first inverter INV.
[0066] The driving module 10 includes: a pull-up resistor R1, a pull-down resistor R2, a pull-up PMOS transistor MP1, and a pull-down NMOS transistor MN5.
[0067] The gate of the pull-up PMOS transistor MP1 is coupled to the output terminal of the first inverter INV. The source of the pull-up PMOS transistor MP1 is connected to the internal supply voltage Vdd. The drain of the pull-up PMOS transistor MP1 is coupled to the first end of the pull-up resistor R1. The second end of the pull-up resistor R1 is respectively coupled to the gate of the power transistor M1 and the first end of the pull-down resistor R2. The second end of the pull-down resistor R2 is coupled to the drain of the pull-down NMOS transistor MN5. The gate of the pull-down NMOS transistor MN5 is also coupled to the output terminal of the first inverter INV. The source of the pull-down NMOS transistor MN5 is coupled to the ground terminal.
[0068] The working principle of the above embodiment in the conduction stage is as follows:
[0069] Please refer to Figure 3 and Figure 4 , at the beginning of the first time period t1, the drive control signal V1 switches from the second state to the first state. The gate of the pull-up PMOS transistor MP1 is connected to a low level and is turned on. The gate of the pull-down NMOS transistor MN5 is connected to a low level and is turned off. The conduction current ION flows through the pull-up resistor R1. The conduction current ION is transmitted from the pull-up resistor R1 to the gate of the power transistor M1 to turn on the power transistor M1.
[0070] At the same time, the gate of the fourth NMOS is turned off due to being connected to a low level; the gate of the first NMOS transistor MN1 is turned on due to being connected to a high level. Also, Figure 3It is known that at the initial stage of the conduction of the power transistor M1, the gate voltage VG of the power transistor M1 is zero and the gate of the second NMOS transistor MN2 is coupled to the gate of the power transistor M1. Therefore, the second NMOS transistor MN2 is not conducted, so that the source voltage of the first NMOS transistor MN1, i.e., the gate voltage of the third NMOS transistor MN3, is continuously pulled up by the internal supply voltage Vdd. Also, since the source of the third NMOS transistor MN3 is also coupled to the gate of the power transistor M1, the gate-source voltage of the third NMOS transistor MN3 increases, so that the third NMOS transistor MN3 outputs a continuously increasing dynamic compensation current Ienh to increase the conduction rate of the power transistor M1 in the first time period.
[0071] In the second time period t2, when the gate voltage VG of the power transistor M1 starts to increase due to the dynamic compensation current Ienh and the conduction current ION, the second NMOS transistor MN2 also starts to be conducted, thereby gradually pulling down the gate voltage of the third NMOS transistor MN3. Therefore, the gate-source voltage of the third NMOS transistor MN3 continuously decreases, so that the dynamic compensation current Ienh continuously decreases. When the gate-source voltage of the third NMOS transistor MN3 is less than its own threshold voltage, the dynamic compensation current Ienh decreases to zero. Figure 4 It can be seen that before the gate voltage VG of the power transistor M1 increases to the Miller voltage of the power transistor M1, the dynamic compensation current Ienh can already be ignored. Thus, before the reverse transfer capacitance of the power transistor M1 undergoes a non-linear surge resulting in a drop in the gate voltage VG, the dynamic compensation current Ienh will not accelerate the rate of decrease of the source-drain voltage VDS of the power transistor M1, and thus will not cause EMI problems.
[0072] In the third time period, when the reverse transfer capacitance of the power transistor M1 undergoes a non-linear surge due to the decrease in the source-drain voltage VDS, the gate voltage VG of the power transistor M1 will drop. The drop in the gate voltage VG will reduce the current flowing through the second NMOS transistor MN2, thereby increasing the gate voltage of the third NMOS transistor MN3. Since the gate voltage of the third NMOS transistor MN3 increases and the source voltage decreases, the dynamic compensation current Ienh flowing through the third NMOS transistor MN3 increases.
[0073] The formulas for the drop amplitude of the gate voltage VG and the dynamic compensation current Ienh are as follows:
[0074]
[0075] Among them, Ienh is used to characterize the dynamic compensation current, n is used to characterize the transconductance ratio of the first NMOS transistor and the second NMOS transistor, that is, the first transconductance ratio, gm 1 is the transconductance of the first NMOS transistor, gm 2 is the transconductance of the second NMOS transistor, g m3 is the transconductance of the third NMOS transistor.
[0076] Then, substituting formula (4) into formula (3), and substituting both formula (4) and formula (3) into formula (2), the optimized formula is obtained as follows:
[0077]
[0078] Since in practical applications, C OSS is much larger than C rssH , so the constant k is much larger than 1. Thus, under the compensation of the dynamic compensation current Ienh, not only the drop amplitude of the gate voltage VG is reduced to 1 / k times of the original, but also the decrease rate of the source-drain voltage VDS remains almost unchanged, effectively suppressing the voltage tailing phenomenon of the power transistor M1, and further greatly reducing the on-state power consumption of the power transistor M1.
[0079] Taking the gallium nitride single transistor GS66508T as an example, C rssH ≈60 - 70 pF. When the source-drain voltage VDS is small, that is, when the voltage tailing phenomenon occurs, C OSS ≈200 - 500 pF. And n is generally between 1 - 5, so k is at least greater than 4, which is sufficient to effectively suppress the voltage tailing.
[0080] In the fourth time period, after the voltage tailing problem is suppressed and the Miller plateau period of the power transistor M1 ends, the gate voltage VG of the power transistor M1 continues to increase. Therefore, the gate voltage VG of the second NMOS transistor MN2 increases, the current flowing through the second NMOS transistor MN2 increases, the gate voltage of the third NMOS transistor MN3 decreases, and the source voltage of the third NMOS transistor MN3 increases. So the gate-source voltage of the third NMOS transistor MN3 drops until the third NMOS transistor MN3 is turned off, and the dynamic compensation current Ienh is 0 A.
[0081] As described above, the larger the gate voltage VG of the power transistor M1, the smaller the dynamic compensation current Ienh. When the gate voltage VG reaches the critical voltage, the third NMOS transistor MN3 is turned off and the dynamic compensation current Ienh becomes zero. If the Miller voltage of the power transistor M1 exceeds the critical voltage and the difference between the critical voltage and the Miller voltage is greater than the drop amplitude of the gate voltage VG, the dynamic compensation current Ienh cannot be triggered, resulting in the inability to suppress the voltage tail of the power transistor M1. Or although the difference between the critical voltage and the Miller voltage is less than the drop amplitude of the gate voltage VG, when the critical voltage is less than the Miller voltage, causing the gate voltage VG to drop, the dynamic compensation module 20 cannot output the dynamic compensation current Ienh that is positively correlated with the drop amplitude in a timely manner, thereby affecting the effect of suppressing the voltage tail, as Figure 5 shown.
[0082] The critical voltage is specifically determined by the first transconductance ratio. The smaller the first transconductance ratio, the larger the critical voltage. Therefore, a critical first threshold needs to be set for the first transconductance ratio to ensure that the dynamic compensation module can output the dynamic compensation current that is positively correlated with the drop amplitude of the gate voltage in a timely manner during the Miller plateau period of different power transistors. The derivation process of the first threshold is as follows:
[0083] To ensure that the dynamic compensation module 20 can respond to the drop of the gate voltage VG in a timely manner and output the dynamic compensation current Ienh. Therefore, it can be assumed that the critical voltage is the Miller voltage, that is, when the gate voltage VG rises to the Miller voltage, the dynamic compensation current Ienh is exactly zero or almost zero. At this time, the third MOS transistor should be exactly in the critical conduction state. Therefore:
[0084] V DR -V th，1 -n1(V MP -V th2 )-V th3 =V MP Equation (8)
[0085] V 1 =V DR -V th，1 -n1(V MP -V th2 ) Equation (9)
[0086] Combining Equation (8) and Equation (9), the formula for the first threshold can be obtained as follows:
[0087]
[0088] Wherein, n1 is used to represent the first threshold, V1 is used to represent the gate voltage of the third NMOS transistor, VDR is used to represent the internal supply voltage, Vth1 is used to represent the threshold voltage of the first NMOS transistor, Vth2 is used to represent the threshold voltage of the second NMOS transistor, Vth3 is used to represent the threshold voltage of the third NMOS transistor, and VMP is used to represent the Miller voltage of the power transistor.
[0089] Based on the first transconductance ratio being less than the first threshold, the smaller the first transconductance ratio, the larger the range in which the dynamic compensation module 20 can suppress the drop of the compensation gate voltage VG.
[0090] Of course, the critical voltage can also be set to other voltages other than the Miller voltage, and can be specifically selected according to requirements, which is not limited herein. Since the first threshold is determined according to the critical voltage, the first threshold is also not limited.
[0091] The working principle of the above embodiment in the turn-off stage is as follows:
[0092] The drive control signal V1 switches from the first state to the second state. The gate of the pull-up PMOS transistor MP1 is connected to a high level and is turned off. The gate of the pull-down NMOS transistor MN5 is connected to a high level and is turned on. The turn-off current IOFF flows from the gate of the power transistor M1 through the pull-down resistor R2 and to the ground terminal to turn off the power transistor M1.
[0093] Meanwhile, the gate of the fourth NMOS is turned on due to being connected to a high level to pull down the gate of the third NMOS transistor MN3 to the ground terminal, thereby turning off the third NMOS transistor MN3. And the gate of the first NMOS transistor MN1 is turned off due to being connected to a low level. Therefore, the dynamic compensation module 20 does not function during the turn-off of the power transistor M1. Since the power consumption of the MOS transistor in the static state is extremely low, the static power consumption of the dynamic compensation module 20 during the turn-off of the power transistor M1 is greatly reduced.
[0094] It should be noted that when the gallium nitride single transistor is used as the power transistor M1, the internal supply voltage Vdd of the drive circuit is usually about 5V to 10V. Therefore, the transistor in the dynamic compensation module 20 can be an NMOS transistor. If the power transistor M1 is a silicon carbide transistor, an IGBT transistor, or a super junction MOS transistor, etc., the internal supply voltage Vdd of the drive circuit is usually above 18V. Therefore, the transistor in the dynamic compensation module 20 needs to be replaced with an LDMOS transistor to withstand high voltage.
[0095] Wherein, Figure 6 is a schematic circuit structure of the drive circuit provided by the embodiment of the present invention Figure 3 .
[0096] Please refer to Figure 6 , in another embodiment, the devices in the driving module 10 are replaced with a pull-up current source Isource1, a pull-down current source Isource2, and a first switching unit 11;
[0097] The negative pole of the pull-up current source Isource1 is coupled to the internal power supply voltage Vdd, and the positive pole of the pull-up current source Isource1 is coupled to the first end of the first switching unit 11;
[0098] The negative pole of the pull-down current source Isource2 is coupled to the second end of the first switching unit 11, and the positive pole of the pull-down current source Isource2 is coupled to the ground terminal;
[0099] The control terminal of the first switching unit 11 is connected to the drive control signal V1. If the drive control signal V1 is in the first state, the first end of the first switch is connected to the gate of the power transistor M1; if the drive control signal V1 is in the second state, the second end of the first switch is connected to the gate of the power transistor M1.
[0100] Wherein, the first state of the drive control signal V1 is a high level, and its second state is a low level
[0101] The devices in the dynamic compensation module 20 are replaced with a first resistor R3, a second MOS transistor MN2, a third MOS transistor MN3, a fourth MOS transistor MN4, and a first inverter INV;
[0102] The input terminal of the first inverter INV is coupled to the drive control signal V1. The first end of the first resistor R3 and the drain of the third MOS transistor MN3 are both coupled to the internal power supply voltage Vdd. The second end of the first resistor R3 is respectively coupled to the drain of the second MOS transistor MN2, the gate of the third MOS transistor MN3, and the drain of the fourth MOS transistor MN4. The gate of the second MOS transistor MN2 and the source of the third MOS transistor MN3 are both coupled to the gate of the power transistor M1. The source of the second MOS transistor MN2 and the source of the fourth MOS transistor MN4 are both coupled to the ground terminal; the gate of the fourth MOS transistor MN4 is coupled to the output terminal of the first inverter INV;
[0103] The second MOS transistor MN2, the third MOS transistor MN3, and the fourth MOS transistor MN4 are all NMOS transistors, or the first MOS transistor, the second MOS transistor MN2, the third MOS transistor MN3, and the fourth MOS transistor MN4 are all LDMOS transistors.
[0104] Except that the first transconductance ratio in the previous embodiment is replaced by the first impedance product, the working principle of this embodiment is the same as that of the previous embodiment, which will not be elaborated here. Among them, the first impedance product is used to characterize the product of the first resistance values of the transconductance of the second NMOS transistor.
[0105] If the power transistor M1 is a gallium nitride single transistor, the second MOS transistor MN2, the third MOS transistor MN3, and the fourth MOS transistor MN4 are all NMOS transistors.
[0106] If the power transistor M1 is an N-channel MOS transistor or an N-channel IGBT transistor, the second MOS transistor MN2, the third MOS transistor MN3, and the fourth MOS transistor MN4 are all LDMOS transistors.
[0107] It should be noted that the first MOS transistor in the previous embodiment is replaced by the first resistor R3 in this embodiment, so the static power consumption of the dynamic compensation module 20 during the turn-off period of the power transistor M1 will increase.
[0108] In summary, the driving circuit provided by the embodiment of the present invention outputs a dynamic compensation current negatively correlated with the gate voltage of the power transistor during the conduction period of the power transistor, so as to output a dynamic compensation current positively correlated with the falling amplitude of the gate voltage when the gate voltage of the power transistor drops due to the non-linear surge of the reverse transfer capacitance, so as to effectively suppress the non-linearity of the source-drain voltage drop of the power transistor, thereby suppressing the voltage tailing problem of the power transistor. And before the gate voltage reaches the critical voltage, the dynamic compensation current output by the dynamic compensation module can also accelerate the conduction speed of the power transistor, and make the dynamic compensation current zero after the gate voltage reaches the critical voltage, thereby avoiding EMI problems during the Miller plateau period of the power transistor.
[0109] Furthermore, only four transistors are provided to solve the voltage tailing problem, and no high-voltage devices are used, thus saving the circuit cost.
[0110] Furthermore, the first transconductance ratio is set to be less than the first threshold, so that the dynamic compensation module can timely output a dynamic compensation current positively correlated with the magnitude of the drop of the gate voltage according to the drop of the gate voltage, thereby improving the suppression effect on the voltage tailing of the power transistor.
[0111] The embodiment of the present invention also provides a circuit system, including the driving circuit.
[0112] The embodiment of the present invention also provides an electronic device, including the circuit system.
[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A driving circuit, characterized in that: The driving circuit is used to drive the power tube, the drain end of the power tube is coupled to the ground, and the source end of the power tube is coupled to the load power supply end through the load unit; the driving circuit includes: Driver modules for: According to the input drive control signal being in the first state, injecting a conduction current into the gate of the power tube to turn on the power tube; According to the input drive control signal being in the second state, extracting a turn-off current from the gate of the power tube to turn off the power tube; The dynamic compensation module is used to output a dynamic compensation current to the gate of the power tube according to the input drive control signal being in the first state, and the dynamic compensation current is negatively correlated with the gate voltage.
2. The driving circuit according to claim 1, characterized in that: The first state is a high level, the second state is a low level, the dynamic compensation module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a first inverter, the power tube is a single gallium nitride tube, and the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all NMOS tubes; The input end of the first inverter and the gate of the first MOS tube are both coupled to the driving control signal, the drain of the first MOS tube and the drain of the third MOS tube are both coupled to the internal power supply voltage, and the source of the first MOS tube is respectively coupled to the drain of the second MOS tube, the gate of the third MOS tube and the drain of the fourth MOS tube; The gate of the second MOS tube and the source of the third MOS tube are both coupled to the gate of the power tube, the source of the second MOS tube and the source of the fourth MOS tube are both coupled to the ground; the gate of the fourth MOS tube is coupled to the output end of the first inverter.
3. The driving circuit according to claim 1, characterized in that: The first state is a high level, the second state is a low level, the dynamic compensation module includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube and a first inverter, the power tube is an NMOS tube or an N-channel IGBT tube, and the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all NLDMOS tubes; The input end of the first inverter and the gate of the first MOS tube are both coupled to the driving control signal, the drain of the first MOS tube and the drain of the third MOS tube are both coupled to the internal power supply voltage, and the source of the first MOS tube is respectively coupled to the drain of the second MOS tube, the gate of the third MOS tube and the drain of the fourth MOS tube; The gate of the second MOS tube and the source of the third MOS tube are both coupled to the gate of the power tube, the source of the second MOS tube and the source of the fourth MOS tube are both coupled to the ground; the gate of the fourth MOS tube is coupled to the output end of the first inverter.
4. The driving circuit according to claim 2 or 3, characterized in that: The first transconductance ratio is less than a first threshold value, and the first transconductance ratio is used to characterize the ratio of the transconductances of the first MOS transistor and the second MOS transistor.
5. The driving circuit according to claim 4, characterized in that: The formula of the first threshold is: Among them, n1 is used to characterize the first threshold, VDR is used to characterize the internal power supply voltage, Vth1 is used to characterize the threshold voltage of the first MOS tube, Vth2 is used to characterize the threshold voltage of the second MOS tube, Vth3 is used to characterize the threshold voltage of the third MOS tube, and VMP is used to characterize the Miller voltage of the power tube.
6. The driving circuit according to claim 1, characterized in that: The first state is a high level, the second state is a low level, the dynamic compensation module includes: a first resistor, a second MOS tube, a third MOS tube, a fourth MOS tube and a first inverter, the power tube is a single gallium nitride tube, and the second MOS tube, the third MOS tube and the fourth MOS tube are all NMOS tubes; The input end of the first inverter is coupled to the driving control signal, the first end of the first resistor and the drain of the third MOS tube are coupled to the internal power supply voltage, the second end of the first resistor is respectively coupled to the drain of the second MOS tube, the gate of the third MOS tube and the drain of the fourth MOS tube, the gate of the second MOS tube and the source of the third MOS tube are coupled to the gate of the power tube, the source of the second MOS tube and the source of the fourth MOS tube are coupled to the ground; the gate of the fourth MOS tube is coupled to the output end of the first inverter.
7. The driving circuit according to claim 1, characterized in that: The first state is a high level, the second state is a low level, the dynamic compensation module includes: a first resistor, a second MOS tube, a third MOS tube, a fourth MOS tube and a first inverter, the power tube is an NMOS tube or an N-channel IGBT tube, and the second MOS tube, the third MOS tube and the fourth MOS tube are all NLDMOS tubes; The input end of the first inverter is coupled to the driving control signal, the first end of the first resistor and the drain of the third MOS tube are coupled to the internal power supply voltage, the second end of the first resistor is respectively coupled to the drain of the second MOS tube, the gate of the third MOS tube and the drain of the fourth MOS tube, the gate of the second MOS tube and the source of the third MOS tube are coupled to the gate of the power tube, the source of the second MOS tube and the source of the fourth MOS tube are coupled to the ground; the gate of the fourth MOS tube is coupled to the output end of the first inverter.
8. The driving circuit according to claim 6 or 7, characterized in that: The first impedance product is smaller than a second threshold value, and the first impedance product is used to represent the product of the resistance value of the first resistor and the transconductance of the second MOS tube.
9. The driving circuit according to claim 4, characterized in that: The formula for the second threshold is: Among them, n2 is used to characterize the second threshold, VDR is used to characterize the internal power supply voltage, Vth1 is used to characterize the threshold voltage of the first MOS tube, Vth2 is used to characterize the threshold voltage of the second MOS tube, Vth3 is used to characterize the threshold voltage of the third MOS tube, and VMP is used to characterize the Miller voltage of the power tube.
10. The driving circuit according to claim 2, 3, 6 or 7, characterized in that: The driving module includes: a pull-up resistor, a pull-down resistor, a pull-up PMOS tube and a pull-down NMOS tube; The gate of the pull-up PMOS tube is coupled to the output end of the first inverter, the source of the pull-up PMOS tube is connected to the internal power supply voltage, the drain of the pull-up PMOS tube is coupled to the first end of the pull-up resistor, the second end of the pull-up resistor is respectively coupled to the gate of the power tube and the first end of the pull-down resistor, the second end of the pull-down resistor is coupled to the drain of the pull-down NMOS tube, the gate of the pull-down NMOS tube is also coupled to the output end of the first inverter, and the source of the pull-down NMOS tube is coupled to the ground.
11. A circuit system, characterized in that: The driving circuit comprises the driving circuit according to any one of claims 1 to 10.
12. An electronic device, characterized in that: A circuit system comprising the circuit system of claim 11.