Auxiliary tube parameter difference type high-end ideal diode

Abstract

The invention discloses an auxiliary tube parameter difference type high-end ideal diode, a circuit comprises a PMOS tube V1, a PMOS tube V3, an input end power supply VCC and a transistor auxiliary tube group, a drain electrode of the PMOS tube V1 is connected to the input end power supply VCC, and a source electrode of the PMOS tube V1 is connected to an output end power supply Vout; the auxiliary transistor group and the PMOS transistor V3 are respectively arranged at two ends of a drain electrode and a source electrode of the PMOS transistor V1 to form a voltage comparator, and the PMOS transistor V3 controls the on and off of the PMOS transistor V1. Compared with the prior art, the auxiliary tube parameter difference type high-end ideal diode has the advantage that the auxiliary tube parameter difference type high-end ideal diode is provided.

Description

Technical Field

[0001] The present invention relates to the technical field of power diodes, and specifically refers to a high-end ideal diode with different auxiliary transistor parameters. Background Art

[0002] In electronic products, due to the one-way conduction characteristic of diodes, which has the function of preventing reverse flow, diodes are used more and more frequently and are one of the indispensable devices. However, the forward voltage drop (V F ) of a diode is about 0.6V. Although the forward voltage drop (V F ) of a Schottky diode is about 0.2 - 0.3V, which has a relatively small voltage drop and is popular among many designers. Although the Schottky diode can meet some requirements in circuit design, for circuits that require an extremely low forward voltage drop, the voltage drop of the Schottky diode is still greater than that of the MOS transistor, making it difficult to meet the needs of such circuits. For some voltage-sensitive circuits, MOS transistors with low impedance characteristics are more preferred to improve the reliability of the product. Therefore, it is necessary to develop a one-way conduction device (ideal diode) with an extremely low forward voltage drop to reduce the power loss of the circuit and improve the power supply efficiency. Therefore, a low-loss ideal diode is needed to further reduce the voltage drop, and it has the functions of preventing reverse flow and protecting the previous stage, minimizing the loss and extending the battery working time.

[0003] According to the control of the power supply polarity, it is divided into High Side (high-end, high-side, high-edge) load switches and Low Side (low-end, low-side, low-edge) load switches, which are respectively similar to controlling the live wire and neutral wire of the mains 220V. High-side load switch: It connects or disconnects the power supply (battery or adapter) to a specific load through the control of an external enable signal. Compared with the low-side load switch, the high-side load switch "flows out" current to the load, while the low-side load switch connects or disconnects the load to the negative electrode, so it "draws in" current from the load. The low-end ideal diode, as a low-end drive switch, is installed between the load and the negative electrode of the power supply to control the conduction or disconnection of the negative electrode of the power supply, so it "draws in" current from the load.

[0004] The main combination forms of high-end ideal diodes are: PMOS main transistor + PNP pair transistors, PMOS main transistor + PMOS pair transistors, etc. In addition, the following is the technical implementation solution of the high-end ideal diode that is closest to the present invention.

[0005] The technical solution of PMOS main transistor + PNP pair transistors (auxiliary transistors), the prior art patent (one-way conduction device, patent number: TW200537799A), belongs to high-end ideal diodes.

[0006] PMOS main transistor + PMOS complementary transistor (auxiliary transistor) technical solution, existing technology patent (an ultra-low loss ideal diode, patent number: CN201821304820.X), which belongs to the realization of a high-end ideal diode using a PMOS main transistor.

[0007] Summary of two technical solutions: PMOS main transistor + PNP complementary transistor (auxiliary transistor), PMOS main transistor + PMOS complementary transistor (auxiliary transistor): When the PMOS main transistor is forward-biased, the PMOS (PNP) transistor V2 conducts, the PMOS (PNP) transistor V3 cuts off, and the PMOS main transistor V1 conducts; when the PMOS main transistor is reverse-biased, the PMOS (PNP) transistor V3 conducts, the PMOS (PNP) transistor V2 cuts off, and the PMOS main transistor V1 cuts off, realizing a high-end ideal diode.

[0008] Matched Pairs Transistor, abbreviated as complementary transistor, is to fabricate two transistors of the same type (NPN transistor, PNP transistor, NMOS transistor or PMOS transistor) with extremely similar parameters on the same substrate and encapsulated in a single chip. The temperatures of the two transistors will affect each other, and the ambient temperature has the same effect on the two transistors.

[0009] The noise figure, characteristic curve, amplification factor, etc. of the two transistors are required to be as consistent as possible. The consistency can be achieved within 10%, or even 1%. In this case, by connecting the circuit in a specific way, the noise of the transistor itself, the zero drift caused by temperature, the influence of the common-mode signal on the differential-mode signal, etc. can be offset to a large extent. Matched Pairs Transistor can be applied to Current Mirror, Differential Amplifier circuit, balanced amplifier, mixer, detector and limiter, etc. NPN transistors and PNP transistors are applied to push-pull emitter followers, etc.

[0010] For example, the single-chip dual-channel NPN complementary transistors MAT01GHZ and SSM2212RZ of AD company; CMKT2222A integrated dual-channel NPN transistors; BSS84DW-7-F and CTLDM304P-M832DS integrated dual-channel PMOS transistors, CMKT2907A integrated dual PNP transistors, etc. are not listed one by one.

[0011] AD company's NPN complementary transistor MAT01GHZ matching degree: V BE Typical value is 40μV, maximum is 200μV, temperature drift is 0.15μV / ℃, amplification factor h FEThe typical value is 1.0% and the maximum is 8.0%, achieving a very good matching degree, which can be called a high-matching pair of transistors. The disadvantage is that the price is very expensive. The unit price of a single piece in a well-known domestic electronic component mall exceeds ￥90 (tax included), and the unit price of 100 pieces exceeds ￥75 (tax included). For overseas purchasing agents, the minimum order is 15 pieces: the unit price of a single piece exceeds ￥180 (tax included), and the unit price of 1000 pieces exceeds ￥160 (tax included). The matching degree of the NPN pair of transistors MAT01AH / 883 in the same series of AD Company: the amplification factor h FE The typical value = 0.7% and the maximum is 3.0%. For overseas purchasing agents, the minimum order is 1 piece: the unit price of a single piece exceeds ￥1000 (tax included), and the unit price of 5 pieces exceeds ￥940 (tax included).

[0012] The matching degree of the NPN pair of transistors SSM2212RZ of AD Company: V BE The typical value is 10 μV and the maximum is 100 μV. The temperature drift is 0.03 μV / °C, and the typical value of the current gain = 0.5%. It achieves a good matching degree and can be called a high-matching pair of transistors. The disadvantage is that the price is very expensive. The unit price of a single piece in a well-known domestic electronic mall exceeds ￥60 (tax included), and the unit price of 100 pieces exceeds ￥50 (tax included).

[0013] The dual transistors packaged together can achieve a pair of devices with a relatively high matching degree. The advantage is that no costly fine-tuning is required. Considering factors such as price, generally, the dual transistors packaged together are selected. However, the matching degree is generally higher than that of single transistors and can be used in higher-precision occasions; for high-matching pairs of transistors, the matching degree can be within 1%. Due to the complexity of the processing technology, the price is naturally expensive, and ordinary products can hardly afford it. In addition, the R & D cost of high-matching pairs of transistors is high, there are few manufacturers, few models, few options for selection, and few demands. The price is in a monopoly state and has been high, and the application range is greatly restricted. Therefore, it is necessary to make a compromise between price and matching degree (performance).

[0014] The above two technical solutions require the parameters of the PNP auxiliary transistor or the PMOS auxiliary transistor to be consistent. If the parameters of the auxiliary transistor are inconsistent, it cannot be used in some high-precision occasions. For the problem of inconsistent parameters of the auxiliary transistor, it is necessary to design a high-end ideal diode with different parameters of the auxiliary transistor, using conventional and cheap transistors (the parameters of the auxiliary transistor are inconsistent) to achieve a pair of transistors with a high "matching degree", and even exceed the high-matching pair of transistors in terms of price and performance, etc., and then control the on and off of the PMOS main transistor, and enrich the implementation methods of high-end ideal diodes. Summary of the Invention

[0015] The technical problem to be solved by the present invention is to overcome the above technical defects and provide a high-end ideal diode with different parameters of the auxiliary transistor.

[0016] To solve the above technical problems, the technical solution provided by the present invention is as follows: A high-end ideal diode with different auxiliary tube parameters, the circuit includes a PMOS transistor V1, a PMOS transistor V3, an input power supply VCC, and a transistor auxiliary tube group. The drain of the PMOS transistor V1 is connected to the input power supply VCC, and the source is connected to the output power supply Vout;

[0017] The transistor auxiliary tube group and the PMOS transistor V3 are respectively arranged at both ends of the drain and source of the PMOS transistor V1 to form a voltage comparator, and the PMOS transistor V3 controls the conduction and cut-off of the PMOS transistor V1.

[0018] Preferably, the transistor auxiliary tube group includes multiple diodes connected in series in sequence;

[0019] The diode group has six diodes D1 to D6. The anode of the diode D1 is connected to the input power supply VCC, the cathode of the diode D6 is connected to the gate of the PMOS transistor V3, and the cathode of the diode D6 is also connected to the resistor R1 and grounded;

[0020] The drain of the PMOS transistor V3 is grounded through the resistor R2, the source is connected to the source of the PMOS transistor V1, and the gate of the PMOS transistor V1 is connected to the drain of the PMOS transistor V3 and the resistor R2.

[0021] Preferably, the transistor auxiliary tube group includes multiple diodes connected in series in sequence and a PNP transistor V2;

[0022] The diode has five diodes D1 to D5. The anode of the diode D1 is connected to the input power supply VCC, and the cathode of the diode D5 is connected to the emitter of the PNP transistor V2;

[0023] The collector of the PNP transistor V2 is connected to the resistor R1 and grounded, the base is connected to the gate of the PMOS transistor V3, and is also connected to the resistor R1;

[0024] The drain of the PMOS transistor V3 is grounded through the resistor R2, the source is connected to the source of the PMOS transistor V1, and the gate of the PMOS transistor V1 is connected to the drain of the PMOS transistor V3 and the resistor R2.

[0025] The advantages of the present invention compared with the prior art are as follows: The auxiliary tubes used in this circuit are PMOS transistors + multiple diodes or PMOS transistors + PNP transistors + multiple diodes, which are common components, with low prices, a large number of selected models, many manufacturers, and basically no correlation between the parameters of the two. The parameter requirements for the auxiliary tubes are very loose, and the diodes, PNP transistors, and PMOS transistors have natural conduction threshold voltage differences. It only requires that the conduction threshold voltage of the PMOS transistor satisfies V TE = V F <-V TP(MIN)That's all. This requirement is relatively easy to achieve. The combined auxiliary transistors composed of PMOS transistors, PNP transistors, and diodes are used in the high-end ideal diode circuit. The circuit is simple and the cost is very low (the cost may be less than one-thousandth of that of the high-matching pair of transistors, greatly saving costs), and the practicability is very strong. Description of the Drawings

[0026] Figure 1 is the schematic diagram of the high-end ideal diode composed of the existing technology PMOS main transistor + PNP pair of transistors;

[0027] Figure 2 is the schematic diagram of the high-end ideal diode composed of the existing technology PMOS main transistor + PMOS pair of transistors;

[0028] Figure 3 is the implementation of the high-end ideal diode (one) with the PMOS transistor + multiple diodes forming the auxiliary transistor in the present invention;

[0029] Figure 4 is the implementation of the high-end ideal diode (two) with the PMOS transistor + PNP transistor + multiple diodes forming the auxiliary transistor in the present invention;

[0030] Figure 5 is Figure 4 forward conduction simulation;

[0031] Figure 6 is Figure 4 reverse cut-off simulation;

[0032] Figure 7 is Figure 5 forward conduction simulation;

[0033] Figure 8 is Figure 5 reverse cut-off simulation. Detailed Implementation Modes

[0034] The present invention will be further described in detail below with reference to the drawings.

[0035] Implementation Mode 1: Implementation of the high-end ideal diode (one) with the PMOS transistor + multiple diodes forming the auxiliary transistor

[0036] As Figure 3 shown in the schematic diagram, assume that the forward voltage drop of a single diode is V F (or U on ), the forward voltage drop of two diodes in series is 2×V F (or 2×U on ), and the forward voltage drop of n diodes in series is n×V F (or n×U on ). Therefore, considering n diodes in series, satisfying |V TP | < n×V F (or n×Uon ) This condition is obviously easy to achieve. Considering the low power consumption requirement and that the gate of PMOS transistor V3 hardly needs gate current, the current-limiting resistor can take a relatively large value, such as R = 100 kΩ, that is, the conduction current is relatively small, and the corresponding diode conduction voltage drop is the turn-on voltage U on = 0.4V - 0.5V. Considering the actual situation, the minimum value V TP(MIN) = -1.5V, the maximum value V TP(MAX) = -2.5V, n×V F = n×U on = n×0.5V > |V TP | = V TP(MAX) , it is required that n≥6, and n = 6 is taken.

[0037] Figure 3 In the circuit shown, when PMOS transistor V1 is forward-biased, that is, A > B, n diodes conduct, and Y = VCC - n×U on , V3 GS = Y - B = VCC - n×U on - Vout = VCC - n×U on - (VCC - V F ) = V F - n×U on > V TP When this is the case, PMOS transistor V3 is cut off, V1G≈0V, V1 GS = V1G - B = 0V - (VCC - V F ) = V F - VCC < V TP , the drain-source channel of PMOS main transistor V1 conducts, and there is a certain conduction voltage drop V1 DS < V F , Vout = VCC - V1 DS , V3 GS = Y - B = VCC - n×U on - (VCC - V1 DS ) = V1 DS - n×U on > V TP , PMOS transistor V3 is in the cut-off state.

[0038] When PMOS transistor V1 is reverse-biased, that is, A < B, n diodes conduct, and Y = VCC - n×U on , for PMOS transistor V3 to conduct, it needs to satisfy V3 GS = Y - B = VCC - n×U on - Vout < V TP , that is, Vout > VCC - n×U on - V TPalways holds. Since Vout ≥ VCC, that is, -n×U on -V TP ≤ 0V, -V TP ≤ n×U on , the value of n is related to V TP and U on and satisfies n×U on -V1 DS <V TP <n×U on ; After the V3 transistor conducts, V1G ≈ B = Vout, V1 GS = V1G - B ≈ 0V > V TP , the power supply VCC1 is isolated from the external power supply VCC2, and the current of the external power supply cannot flow back into the power supply VCC1, achieving the purpose of protecting the power supply VCC1.

[0039] Embodiment 2: A PMOS transistor + a PNP transistor + multiple diodes form an auxiliary transistor to implement a high-side ideal diode (II)

[0040] Similarly, referring to Technical Solution 1, inserting multiple diodes in series and combining them with a PNP transistor and a PMOS transistor to form a comparison circuit, satisfying |V TP | < n×V F (or n×U on ) This condition is obviously easy to achieve. Considering the low-power consumption requirement and that the gate of the PMOS transistor V3 hardly requires gate current, the current-limiting resistor can be set to a relatively large value, such as R = 100 kΩ, that is, the conduction current is relatively small, and the corresponding diode conduction voltage drop is the turn-on voltage U on = 0.4V - 0.5V. Considering the actual situation, the minimum value of V TP(MIN) = -1.5V, the maximum value of V TP(MAX) = -2.5V, n×V F > |V TP |, it is required that n ≥ 6, and n - 1 = 5 diodes are inserted, such as Figure 4 Schematic diagram.

[0041] When the PMOS transistor V1 is forward-biased, that is, A > B, n - 1 = 5 diodes conduct, and Y = VCC - n×U on ,

[0042] V3 GS = Y - B = VCC - n×U on - Vout = VCC - n×U on -(VCC - V F ) = V F - n×U on > V TP When, the PMOS transistor V3 is cut off.

[0043] V1G≈0V, V1 GS = V1G - B = 0V - (VCC - V F ) = V F -VCC < V TP , the drain-source channel of PMOS in charge of V1 is turned on, and there is a certain on-voltage drop V1 DS <V F , Vout = VCC - V1 DS , V3 GS = Y - B = VCC - n×U on -(VCC - V1 DS ) = V1 DS -n×U on >V TP , PMOS transistor V3 is in the cut-off state.

[0044] When PMOS transistor V1 is reverse-biased, i.e., A < B, n - 1 = 5 diodes are turned on, and Y = VCC - n×U on , for PMOS transistor V3 to be turned on, it is necessary to satisfy V3 GS = Y - B = VCC - n×U on -Vout < V TP , that is, Vout > VCC - n×U on -V TP always holds. Since Vout > VCC, that is, -n×U on -V TP ≤ 0V, -V TP ≤ n×U on , the value of n is related to V TP and U on , satisfying n×U on -V1 DS < -V TP < n×U on ; after V3 transistor is turned on, V1G ≈ B = Vout, V1 GS = V1G - B ≈ 0V > V TP , PMOS in charge of V1 is cut off, the power supply VCC1 is isolated from the external power supply VCC2, and the current of the external power supply cannot flow back into the power supply VCC1, achieving the purpose of protecting the power supply VCC1.

[0045] According to Figures 3 to 4 the circuit schematic diagram, simulation tests are carried out using the simulation software Multisim (version V14.0) of National Instruments Corporation. The PMOS transistor is selected from the devices of ON Semiconductor Corporation, and the model is NVTFS5124PLTAG. The minimum value of the on-threshold voltage V TP(MIN) = -1.5V, the maximum value V TP(MAX)= -2.5V, no typical value of V is given TP , the conduction current can reach -6A, and the on-resistance R DS(ON) = 0.26Ω (V GS = -10V), R DS(ON) = 0.38Ω (V GS = -4.5V); The diodes use components from Motorola, model number 1N4001. The specific simulation tests are as follows.

[0046] Simulation of Embodiment 1

[0047] The forward bias simulation test diagram is as shown in Figure 5 , VCC = 12.0V, the voltage difference between the gate and source of V1 tube V1 GS = V1G - B = 192mV - 11.7V ≈ 0V - 11.7V = -11.7V < V TP , the drain-source channel of V1 tube is conducting, and the conduction current is 1.17A.

[0048] The reverse bias simulation test diagram is as shown in Figure 6 , VCC = 12.0V, VCC2 = 12.001V, V3 tube is conducting, V1G = 12V, the voltage difference between the gate and source of V1 tube V1 GS = V1G - B = 12V - 12V ≈ 0V < V TP , the drain-source channel of V1 tube is cut off, the current output from VCC2 to the high-end ideal diode is -12.0μA (test point PR4), and the current output from VCC1 is 95.4μA (test point PR3), which can be ignored.

[0049] Summary: When V1 tube is conducting, diodes D1 - D6 are conducting; when V1 tube is cut off, diodes D1 - D6 are cut off. Therefore, the conduction and cut-off of diodes D1 - D6 have the same direction characteristics as V1 tube.

[0050] Since the conduction threshold voltage (forward voltage) of ordinary diodes is less than the minimum value of the conduction threshold voltage of signal-type PMOS tubes |V TN(MIN) |, and the PMOS conduction threshold voltage |V TP |, satisfying |V TP | < n × V F (or n × U on ), it is not sufficient to turn on the PMOS tube. Therefore, the natural difference in the conduction threshold voltages of diodes and PMOS tubes can be utilized, without the need to ensure the parameter consistency of diodes and PMOS tubes, expanding the application range.

[0051] The PMOS transistor + multiple diodes form an auxiliary transistor, which better realizes the function of the high-side ideal diode. It belongs to the PMOS auxiliary transistor V3 at the back end of the comparator, and the output V1G signal controls the conduction and cut-off of the PMOS main transistor V1: when the potential of the power supply VCC (point A) is greater than the potential of the high side of the load Vout (point B), the PMOS main transistor V1 conducts; otherwise, the PMOS main transistor V1 cuts off, preventing the current of the high side of the load Vout from flowing back to the power supply VCC circuit through the PMOS main transistor V1, which is equivalent to a high-side ideal diode.

[0052] Simulation of Embodiment 2

[0053] Forward bias simulation test, VCC = 12.0V, the voltage difference V1 between the gate and source of the V1 transistor GS = V1G - B = 192mV - 11.7V ≈ 0V - 11.7V = -11.7V < V TP The drain-source channel of the V1 transistor conducts, and the conduction current is 1.17A (test points PR3, PR5). The simulation is as Figure 7 shown.

[0054] The reverse bias simulation test diagram is as Figure 8 shown, VCC = 12.0V, VCC2 = 12.001V, the voltage difference V1 between the gate and source of the V1 transistor GS = V1G - B = 12V - 12V ≈ 0V > V TP The drain-source channel of the V1 transistor cuts off. The current output from VCC2 to the high-side ideal diode is -11.8 μA (test point PR4), and the output current of VCC1 is 71.4 nA (test point PR3), which can be ignored.

[0055] Since the conduction threshold voltage (forward voltage) of the PNP transistor is less than the minimum value V of the conduction threshold voltage of the signal-type PMOS transistor TP(MIN) The conduction threshold voltage V of the emitter junction of the PNP transistor TE = V F < -V TP(MIN) Therefore, the natural difference in the conduction threshold voltage of the emitter junction of the PNP transistor and the PMOS transistor can be utilized, and it is not necessary to ensure the consistency of the parameters of the emitter junction of the PNP transistor and the PMOS transistor, which expands the application range.

[0056] The PMOS transistor + PNP transistor + multiple diodes form an auxiliary transistor, which better realizes the function of the high-side ideal diode. It belongs to the PMOS auxiliary transistor V3 at the back end of the voltage comparator, and the output V1G signal controls the conduction and cut-off of the PMOS main transistor V1: when the potential of the power supply VCC (point A) is greater than the potential of the high side of the load Vout (point B), the PMOS main transistor V1 conducts; otherwise, the PMOS main transistor V1 cuts off, preventing the current of the high side of the load Vout from flowing back to the power supply VCC circuit through the PMOS main transistor V1, which is equivalent to a high-side ideal diode.

[0057] Advantages of the present invention: The auxiliary transistor used in this circuit is a PMOS transistor + multiple diodes or a PMOS transistor + a PNP transistor + multiple diodes. These are common components, with low cost, a wide variety of selection models, many manufacturers, and their parameters are basically not related to each other. The parameter requirements for the auxiliary transistor are very loose. Moreover, there are natural differences in the conduction threshold voltages among the diodes, PNP transistors, and PMOS transistors. It only requires that the conduction threshold voltage of the PMOS transistor satisfies V TE = V F < -V TP(MIN) That's all. This requirement is relatively easy to achieve. The combined auxiliary transistor composed of PMOS transistors, PNP transistors, and diodes is used in the high-end ideal diode circuit. The circuit is simple, and the cost is very low (the cost may be less than one-thousandth of that of the high-matching pair of transistors, greatly saving costs), and the practicability is very strong.

[0058] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations based on the concept of the present invention without creative labor. Therefore, all technical solutions that can be obtained by those skilled in the art in the technical field based on the concept of the present invention through logical analysis, reasoning, or limited experiments on the basis of the prior art shall fall within the protection scope determined by the claims.

Claims

1. A high-end ideal diode with auxiliary tube parameter difference, characterized in that: The circuit comprises a PMOS tube V1, a PMOS tube V3, an input power supply VCC and a transistor auxiliary tube group, wherein the drain of the PMOS tube V1 is connected to the input power supply VCC, and the source is connected to the output power supply Vout; The transistor auxiliary tube group and the PMOS tube V3 are respectively arranged at the drain and source ends of the PMOS tube V1 to form a voltage comparator. The PMOS tube V3 controls the conduction and cutoff of the PMOS tube V1.

2. The auxiliary tube parameter difference type high-end ideal diode according to claim 1, characterized in that: The transistor auxiliary tube group includes a plurality of diodes connected in series in sequence; The diode group is provided with six diodes D1 to D6, the anode of the diode D1 is connected to the input power supply VCC, the cathode of the diode D6 is connected to the gate of the PMOS tube V3, and the cathode of the diode D6 is also connected to the resistor R1 to ground; The drain of the PMOS tube V3 is grounded through the resistor R2, the source is connected to the source of the PMOS tube V1, and the gate of the PMOS tube V1 is connected to the drain of the PMOS tube V3 and the resistor R2.

3. The auxiliary tube parameter difference type high-end ideal diode according to claim 1, characterized in that: The transistor auxiliary tube group includes a plurality of diodes and a PNP tube V2 connected in series in sequence; The diode is provided with five diodes D1 to D5, the anode of the diode D1 is connected to the input power supply VCC, and the cathode of the diode D5 is connected to the emitter of the PNP tube V2; The collector of the PNP tube V2 is connected to the resistor R1 and grounded, and the base is connected to the gate of the PMOS tube V3 and is also connected to the resistor R1; The drain of the PMOS tube V3 is grounded through the resistor R2, the source is connected to the source of the PMOS tube V1, and the gate of the PMOS tube V1 is connected to the drain of the PMOS tube V3 and the resistor R2.

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