Lookup table structure, programmable logic unit and FPGA device
By using four LUT4s in FPGA devices to realize the functions of LUT6, a flexible lookup table structure is designed, which solves the performance degradation caused by the increase in the number of gate arrays in FPGA devices, and achieves higher resource utilization and faster working speed.
Patent Information
- Application Number
- CN202510194303.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-20
- Publication Date
- 2025-05-30
AI Technical Summary
With the enhancement of application system functions and the increase in scale, the increase in the number of gate arrays in FPGA devices leads to degradation in performance, including increased chip area, increased power consumption and slowdown, limiting system performance.
By using 4 LUT4s to implement the functions of LUT6, a lookup table structure is designed, including 4 four-input lookup tables and 3 gaters. Different lookup table structure patterns can be selected in different application scenarios, thereby achieving higher flexibility and logical implementation capabilities.
It improves the utilization rate of wiring resources, reduces the resource area, increases the working speed of FPGA chips, and can use limited resources to complete more functions and applications.
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Figure CN120074504A_ABST
Abstract
Description
Technical Field
[0001] This document relates to integrated circuit technology, especially a look-up table structure, a programmable logic unit, and an FPGA device. Background Art
[0002] A Field-Programmable Gate Array (FPGA) is a semi-custom circuit chip. Compared with an application-specific integrated circuit, the FPGA has higher flexibility. Through the synthesis of a hardware description language, a circuit design can be quickly implemented through the FPGA, shortening the R & D design process.
[0003] In an FPGA, a programmable logic unit includes two parts, namely a programmable function unit and a programmable interconnection unit. The programmable function unit includes a look-up table structure (LUT), an addition / subtraction carry chain, and a timing logic unit. An N-input look-up table structure can implement any N-input combinational logic. For example, a four-input look-up table structure, a four-input look-up table, and a six-input look-up table structure LUT6. Generally, for a small-scale FPGA, the four-input look-up table structure has better logic resource utilization efficiency. For a larger-scale FPGA or more complex logic, due to the complexity of the routing resources, a look-up table structure with more inputs is preferably used, such as the LUT6 structure.
[0004] A Field-Programmable Gate Array (FPGA) is a logic device with rich hardware resources, powerful parallel processing capabilities, and flexible reconfigurability. These characteristics have enabled the FPGA to be more and more widely used in many fields such as data processing, communication, and networking.
[0005] With the enhancement of the functions and the increase in the scale of application systems, the number of gate arrays of programmable logic devices is required to increase day by day, such as the widespread application of ten-million-gate-level FPGAs. The increase in the number of gates of the FPGA enhances the function implementation ability and increases the functions, but will cause a corresponding decrease in its performance. Such as an increase in chip area, a higher power consumption, and a slower speed, etc., which will restrict the performance of the entire system. Therefore, it is necessary not only to reduce the process size and increase the number of gate arrays, but also to improve the application ability of each logic block.
[0006] Improving the flexibility, logic implementation, and arithmetic ability of the look-up table can effectively improve the utilization rate of routing resources, reduce the occupied area of resources, and at the same time can increase the working speed of the chip, and complete more functions and applications with limited resources. Summary of the Invention
[0007] An embodiment of the present application provides a look-up table structure, a programmable logic unit, and an FPGA device.
[0008] A look-up table structure includes 4 four-input look-up tables lut4_1, lut4_2, lut4_3, and lut4_4; and 3 multiplexers mux4, mux5, and mux7; where: When the working mode of the look-up table structure is a six-input look-up table mode, each four-input look-up table receives four-bit data signals IN0 of the six-input look-up table and outputs its respective output signal; where the output signals of lut4_1 and lut4_2 are input signals of mux4, and the output signals of lut4_3 and lut4_4 are input signals of mux5; Under the control of the fifth data signal of the six-input look-up table, mux4 and mux5 respectively output their respective output signals according to their input signals as input signals of mux7; Under the control of the sixth data signal of the six-input look-up table, mux7 outputs an output signal according to the received input signal as the output result of the six-input look-up table.
[0009] A programmable logic unit includes the look-up table structure described above and a carry chain structure, where the carry chain structure includes 4 cascaded arithmetic logic units ALU, and each ALU has 1 corresponding four-input look-up table; where each ALU receives its respective carry input signal and the output signal of its respective four-input look-up table and outputs an output signal.
[0010] An FPGA device includes the look-up table structure described above or the programmable logic unit described above.
[0011] In the embodiment of the present application, the function of LUT6 is implemented by using 4 LUT4s, which can implement the logic function of a six-input look-up table or the logic function of two five-input look-up tables or the logic function of four four-input look-up tables, with higher flexibility. Different look-up table structure modes can be selected in different application scenarios, so as to achieve flexible logic implementation capabilities and computing capabilities, effectively improve the utilization rate of wiring resources, reduce the occupied area of resources, and at the same time improve the working speed of the FPGA chip, and complete more functions and applications with limited resources.
[0012] Other features and advantages of the present application will be described in the subsequent specification, and, in part, will be obvious from the specification, or will be understood by implementing the present application. Other advantages of the present application can be realized and obtained through the solutions described in the specification and the drawings. Description of the Drawings
[0013] The accompanying drawings are used to provide an understanding of the technical solution of the present application and form a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation to the technical solution of the present application.
[0014] Figure 1 It is a schematic diagram of the internal structure of LUT4; Figure 2 It is Figure 1 a schematic diagram of the truth table of the LUT4 shown; Figure 3 It is Figure 2 a schematic diagram of the Karnaugh map corresponding to the truth table in; Figure 4 It is a schematic diagram of the lookup table structure provided by the embodiment of the present application; Figure 5 It is Figure 4 a schematic diagram of the structure of the lookup table structure in the four-input lookup table mode in; Figure 6 It is Figure 4 a schematic diagram of the structure of the lookup table structure in the five-input lookup table mode in; Figure 7 It is Figure 4 a schematic diagram of the structure of the lookup table structure in the six-input lookup table mode in; Figure 8 It is a schematic diagram of the connection between the lookup table structure and the carry chain structure provided by the embodiment of the present application; Figure 9 It is Figure 8 a schematic diagram of the structure of LUT4 in the structure shown; Figure 10 It is a schematic diagram of the structure of LUT2 provided by the embodiment of the present application; Figure 11 It is a schematic diagram of the structure of the programmable logic unit in the embodiment of the present application; Figure 12 It is a schematic diagram of the deployment of the FPGA device provided by the embodiment of the present application; Figure 13 It is a schematic diagram of the wiring deployment method of the lookup table structure in the FPGA device in the embodiment of the present application; Figure 14 It is Figure 13 a schematic diagram of the application of the structure shown; Figure 15 It is Figure 14 a schematic diagram of the deployment of the structure shown; Figure 16 It is Figure 15 a schematic diagram of the signal flow direction when the structure shown works in the LUT6 working mode; Figure 17 It is Figure 15Schematic diagram of signal flow when the shown structure works in the LUT5 working mode; Figure 18 is Figure 15 Schematic diagram of the working mode of the MUX in the shown structure; Figure 19 is Figure 18 The first schematic diagram of signal flow in the shown structure; Figure 20 is Figure 18 The second schematic diagram of signal flow in the shown structure; Figure 21 is Figure 18 The third schematic diagram of signal flow in the shown structure. Detailed implementation manners
[0015] This application describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be obvious to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope covered by the embodiments described in this application. Although many possible feature combinations are shown in the drawings and discussed in the detailed implementation manners, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.
[0016] This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in this application can also be combined with any conventional features or elements to form a unique invention solution. Any feature or element of any embodiment can also be combined with features or elements from other invention solutions to form another unique invention solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented alone or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalent replacements, the embodiments are not subject to other limitations. In addition, various modifications and changes can be made within the protection scope of the appended claims.
[0017] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of steps described. As will be understood by those of ordinary skill in the art, other step orders are possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, as those skilled in the art can readily understand that these orders can vary and still remain within the spirit and scope of the embodiments of the present application.
[0018] Figures 1 to 3 collectively describe the working principle and logical implementation of LUT4 in an FPGA device: Figure 1 is a schematic diagram of the structure of LUT4. As Figure 1 shown, a LUT4 consists of 16 storage units (RAM0 - RAM15) and 5 4-to-1 multiplexers (MUX). The input variables b and a are used to control the lower 4-to-1 MUX, determining which input will be passed to the higher MUX. The input variables c and d are used to control the higher 4-to-1 MUX, determining which output of the lower mux will be passed to the higher MUX. Specifically, when the input {d, c, b, a} is 0000, the output of LUT4 is the value of RAM0; when the input {d, c, b, a} is 0001, the output of LUT4 is the value of RAM1; when the input {d, c, b, a} is 0010, the output of LUT4 is the value of RAM2; and so on. When the input {d, c, b, a} is 1111, the output of LUT4 is the value of RAM15. Thus, the output of LUT4 is finally generated.
[0019] Figure 2 is Figure 1 a schematic diagram of the truth table of the LUT4 shown. As Figure 2 shown, Figure 2 the truth table shown lists all possible input combinations (a, b, c, d) and their corresponding outputs. In this truth table, each row represents a unique combination composed of the input variables a, b, c, d, and the columns show the output states of LUT4 under that input combination.
[0020] Figure 3 is Figure 2 a schematic diagram of the Karnaugh map corresponding to the truth table in. Among them, the Karnaugh map is a graphical tool for simplifying Boolean functions. As Figure 3As shown, in the Karnaugh map, each cell of RAM0 - RAM15 can be configured as 0 or 1 to implement a specific logic function. For example, Figure 3 the configuration in can implement the logic function F =!(a + b + c + d)+(d & b), where:
[0021] !(a + b + c + d) represents the negation of the logical OR of a, b, c, and d, that is, when all inputs are 0, this part is 1.
[0022] d & b represents the logical AND of d and b, that is, when both d and b are 1, this part is 1.
[0023] The entire expression F is the logical OR of these two parts, meaning that as long as any one of these parts is 1, the output F is 1. By appropriately configuring the RAM cells in the Karnaugh map, the required logic function can be achieved.
[0024] This configuration method allows the LUT4 to implement any 4 - variable Boolean function and is the basis for implementing complex logic circuits in FPGA devices. By reasonably configuring the LUT4, various logic functions can be effectively implemented and the circuit performance can be optimized.
[0025] Figure 4 is a schematic diagram of the lookup table structure provided by the embodiment of this application. As Figure 4 shown, the lookup table structure includes 4 four - input lookup tables (LUT4) and 7 multiplexers. Specifically, these 4 LUT4s are lut4_1, lut4_2, lut4_3, and lut4_4 respectively, and the 7 MUXs are mux1, mux2, mux3, mux4, mux5, mux6, and mux7.
[0026] The lookup table structure in this embodiment can be configured into multiple working modes, including six - input lookup table mode, two five - input lookup table modes, four four - input lookup table modes, and a mode that simultaneously implements two four - input lookup tables and one five - input lookup table.
[0027] In Figure 4 's structure, the input signals of each LUT4 are configured as follows: lut4_1 directly receives IN0 as the input signal; The input signal of lut4_2 can select IN0 or IN1, and the final selection is determined by mux1 according to the control signal Lut_mode<0>; The input signal of lut4_3 can select IN0 or IN2, and the final selection is determined by mux2 according to the control signal Lut_mode<1>. The input signal of lut4_4 can select IN0, IN2 or IN3, and the final selection is determined by mux3 according to the control signal Lut_mode<1:0>.
[0028] Among them, IN0, IN1, IN2 and IN3 are all four-bit data signals. For example, IN0 can be represented as a0, b0, c0 and d0; IN1 is a1, b1, c1 and d1; IN2 is a2, b2, c2 and d2; IN3 is a3, b3, c3 and d3.
[0029] The output signal configuration of each LUT4 is as follows: The output signal of lut4_1 can be output independently (corresponding to F40 in Figure 4 ), or as an input signal of mux4; The output signal of lut4_2 can be output independently (corresponding to F41 in Figure 4 ), or as another input signal of mux4; The output signal of lut4_3 can be output independently (corresponding to F42 in Figure 4 ), or as an input signal of mux5; The output signal of lut4_4 can be output independently (corresponding to F43 in Figure 4 ), or as another input signal of mux5.
[0030] In the Figure 4 structure, the fifth data signal of the lookup table structure is used to control mux4 and mux5: In the five-input lookup table mode, the values of the fifth data signals corresponding to mux4 and mux5 are different; In the six-input lookup table mode, the values of the fifth data signals corresponding to mux4 and mux5 are the same.
[0031] In the Figure 4 structure, the fifth data signal value of mux4 is a preset value, and mux6 is used to control the fifth data signal value of mux5. Specifically, mux6 has two signal input terminals, one of which receives a value that is the same as the value received by the control terminal of mux4, and the other signal input terminal is different from the value received by the control terminal of mux4. The final output signal of mux6 is determined by the control signal Lut_mode<1>.
[0032] For example, when the fifth data signal corresponding to the control terminal of mux4 is a1, the data signal at one signal input terminal of mux6 is a1, and the data signal at the other signal input terminal is a3. When Lut_mode<1> indicates that the current operation is in the five-input lookup table mode, mux6 will output the data signal a3; when Lut_mode<1> indicates that the current operation is in the six-input lookup table mode, mux6 will output the data signal a1.
[0033] In Figure 4 's structure, the output signal of mux4 can be output independently (corresponding to Figure 4 's F50), or used as one input signal of mux7; the output signal of mux5 can be output independently (corresponding to Figure 4 's F51), or used as the other input signal of mux7.
[0034] mux7 receives the output signals of mux4 and mux5, and under the control of the sixth data signal in the lookup table structure, selects the output signal of mux4 or mux5 as the final output signal (corresponding to Figure 4 's F60). This design enables the lookup table structure to flexibly adapt to different working modes and application requirements.
[0035] Taking the working mode of the lookup table structure as the four-input lookup table mode as an example for illustration: Figure 5 For Figure 4 is the schematic diagram of the lookup table structure in the four-input lookup table mode. In this working mode, among the 7 multiplexers in the lookup table structure, only 3 are involved in the operation, namely mux1, mux2, and mux3. The specific configuration is as follows: The control signal of mux1, lut_mode<0>=0, selects IN1 as the input signal of lut4_2; The control signal of mux2, lut_mode<1>=0, selects IN2 as the input signal of lut4_3; The control signal of mux3, lut_mode<1:0>=00, selects IN3 as the input signal of lut4_4.
[0036] Based on the above configuration, all 4 LUT4s work as independent four-input lookup tables, as Figure 5 shown: lut4_1 receives the four-bit data signal IN0 and outputs the signal F40 as the output result of the first four-input lookup table; lut4_2 receives the four-bit data signal IN1 and outputs the signal F41 as the output result of the second four-input lookup table; The lut4_3 receives a four-bit data signal IN2 and outputs a signal F42 as the output result of the third four-input lookup table. The lut4_4 receives a four-bit data signal IN3 and outputs a signal F43 as the output result of the fourth four-input lookup table.
[0037] If IN0 is represented as a0, b0, c0, and d0, IN1 is represented as a1, b1, c1, and d1, IN2 is represented as a2, b2, c2, and d2, and IN3 is represented as a3, b3, c3, and d3, then the input signals and output signals of the 4 independently operating LUT4s are as follows: The input signals of the first LUT4 (lut4_1) are a0, b0, c0, and d0, and the output signal is F40; The input signals of the second LUT4 (lut4_2) are a1, b1, c1, and d1, and the output signal is F41; The input signals of the third LUT4 (lut4_3) are a2, b2, c2, and d2, and the output signal is F42; The input signals of the fourth LUT4 (lut4_4) are a3, b3, c3, and d3, and the output signal is F43.
[0038] Taking the five-input lookup table mode as an example for illustration: Figure 6 For Figure 4 is the schematic diagram of the lookup table structure in the five-input lookup table mode. In this operating mode, all muxes except mux7 in the lookup table structure participate in the operation. The specific configuration is as follows: The control signal lut_mode<0> of mux1 = 1, selecting IN0 as the input signal of lut4_2; The control signal lut_mode<1> of mux2 = 0, selecting IN2 as the input signal of lut4_3; The control signal lut_mode<1:0> of mux3 = 01, selecting IN2 as the input signal of lut4_4; The control signal lut_mode<1> of mux6 = 0, selecting a3 as the control signal of mux5, as the fifth-bit data signal of the second LUT5, where the control signal of mux4 is a1, as the fifth-bit data signal of the first LUT5.
[0039] Based on the above configuration, 4 LUT4s operate as 2 independent five-input lookup tables, as Figure 6 shown: lut4_1 and lut4_2 respectively receive four-bit data signals IN0 and output their respective signals; mux4 receives the output signals of lut4_1 and lut4_2, and under the control of the fifth-bit data signal a1 in the first five-input lookup table, outputs a signal according to the received input signals as the output result F50 of the first five-input lookup table. lut4_3 and lut4_4 respectively receive four-bit data signals IN2 and output their respective signals; mux5 receives the output signals of lut4_3 and lut4_4, and under the control of the fifth-bit data signal a3 in the second five-input lookup table, outputs a signal according to the received input signals as the output result F51 of the second five-input lookup table.
[0040] If IN0 is represented as a0, b0, c0, and d0, and IN2 is represented as a2, b2, c2, and d2, the input signals of the 2 independently operating LUT5s are as follows: The five-bit data signals of the first LUT5 are a0, b0, c0, d0, and a1, and the output signal is F50; The five-bit data signals of the second LUT5 are a2, b2, c2, d2, and a3, and the output signal is F51.
[0041] Taking the six-input lookup table mode as an example for illustration: Figure 7 For Figure 4 the structural schematic diagram of the lookup table structure in the six-input lookup table mode. In this operating mode, all 7 muxes in the lookup table structure are involved in the operation. The specific configuration is as follows: The control signal lut_mode<0> of mux1 = 1, selecting IN0 as the input signal of lut4_2; The control signal lut_mode<1> of mux2 = 1, selecting IN0 as the input signal of lut4_3; The control signal lut_mode<1:0> of mux3 = 10, selecting IN0 as the input signal of lut4_4; The control signal lut_mode<1> of mux6 = 1, selecting a1 as the control signal of mux5, as the fifth-bit data signal of LUT6, which is consistent with the control signal a1 of mux4.
[0042] Based on the above configuration, 4 LUT4s work as 1 six-input lookup table, as Figure 7 shown: lut4_1, lut4_2, lut4_3, and lut4_4 all receive a four-bit data signal IN0 and output their respective signals. Among them, the output signals of lut4_1 and lut4_2 are the input signals of mux4, and the output signals of lut4_3 and lut4_4 are the input signals of mux5. Under the control of the fifth-bit data signal a1, mux4 and mux5 respectively output their respective signals according to their input signals, which serve as the input signals of mux7. Under the control of the sixth-bit data signal b1, mux7 outputs a signal according to the received input signal, which serves as the output result F60 of the six-input look-up table.
[0043] If IN0 is represented as a0, b0, c0, and d0, the six-bit data signal of LUT6 is a0, b0, c0, d0, a1, and b1, and the output signal is F60.
[0044] Compare with Figures 5 to 7 the structure shown, it can be seen that Figure 5 the structure shown is provided with 16 input terminals to receive the data signals of 4 LUT4s. Figure 6 the structure shown is provided with 10 input terminals to receive the data signals of 2 LUT5s. Figure 7 the structure shown is provided with 6 input terminals to receive the data signal of 1 LUT6. As the number of set input terminals decreases, the required wiring resources decrease, making it more suitable for large-scale programming application scenarios. For example, Figure 5 the structure shown has more flexible programmable characteristics. Figure 6 the structure shown is more suitable for medium-scale programming application scenarios. Figure 7 the structure shown is more suitable for large-scale programming application scenarios.
[0045] In practical applications, when the programming logic is subdivided from the top-level circuit downwards, it is generally divided into large, medium, and small-scale logics. Based on the characteristics of the programming work, the appropriate look-up table structure working mode can be selected according to different scales of programming logic, which can take into account both the wiring resources and the programming logic resources, so as to achieve a better compromise between the wiring resources and the programming logic resources.
[0046] In addition, the present application also provides a Programmable Logic Unit (PLU), including the look-up table structure, carry chain structure, and timing logic unit described above.
[0047] The carry chain structure is described below: Figure 8 is a connection schematic diagram of the look-up table structure and the carry chain structure provided by the embodiment of the present application. As Figure 8As shown, the carry chain structure consists of four cascaded Arithmetic Logic Units (ALUs), namely alu_1, alu_2, alu_3, and alu_4.
[0048] Each ALU is equipped with a corresponding four-input Look-Up Table (LUT4). In the Figure 8 structure shown, alu_1 is associated with lut4_1, alu_2 is associated with lut4_2, alu_3 is associated with lut4_3, and alu_4 is associated with lut4_4. Each ALU receives its corresponding carry input signal and the output signal of the four-input Look-Up Table, and outputs the corresponding result signal.
[0049] In the Figure 8 structure shown, each ALU is equipped with a LUT4, which enables each ALU to work either in cooperation with other ALUs or independently.
[0050] Specifically, each ALU includes a multiplexer mux8 and an exclusive-OR function unit. Among them: For the current ALU, mux8 receives the carry input signal CIN of the current ALU and the output signal LUT2_o of the two-input Look-Up Table logic output by the four-input Look-Up Table of the current ALU. Under the control of the output signal LUT4_o of the four-input Look-Up Table logic output by the four-input Look-Up Table of the current ALU, it outputs the carry output signal COUT of the current ALU as one of the output signals of the current ALU.
[0051] For the current ALU, the exclusive-OR function unit receives the carry input signal CIN of the current ALU and the output signal LUT4_o of the four-input Look-Up Table logic output by the four-input Look-Up Table of the current ALU, and outputs the calculation result signal Fs as one of the output signals of the current ALU.
[0052] From the above, it can be seen that when the current ALU works independently, the exclusive-OR function unit can be used as an adder or a subtractor; when the current ALU works in cooperation with other ALUs, mux8 can be used to output their respective carry output signals, which are cascaded to form a multi-bit adder or subtractor.
[0053] For alu_1, it can use the internal mux8 to output the carry output signal COUT; or, use the internal exclusive-OR function unit to output the calculation result signal Fs<0>.
[0054] For alu_2, it receives the carry output signal COUT from alu_1 as its carry input signal CIN, and uses the internal mux8 to output the carry output signal COUT; or, uses the internal exclusive-OR function unit to output the calculation result signal Fs<1>.
[0055] For alu_3, it receives the carry output signal COUT from alu_2 as its carry input signal CIN, and uses the internal mux8 to output the carry output signal COUT; alternatively, it uses the internal exclusive - OR functional unit to output the calculation result signal Fs<2>.
[0056] For alu_4, it receives the carry output signal COUT from alu_3 as its carry input signal CIN, and uses the internal mux8 to output the carry output signal COUT; alternatively, it uses the internal exclusive - OR functional unit to output the calculation result signal Fs<3>.
[0057] In practical applications, it is possible to select and enable some ALUs in the carry chain to complete the calculation operation according to the implementation requirements. For example, only enable alu_1, or only enable alu_1 and alu_2, or only enable alu_1, alu_2 and alu_3, so as to achieve effective utilization of resources and reduce waste of resources; in addition, multiple ALUs can also be cascaded to form a multi - bit arithmetic unit.
[0058] In the ALU, the processing logic of the exclusive - OR functional unit is sum[i]=LUT4[i]^Carry[i - 1], which means that the sum output (sum) of the i - th bit is obtained by performing an exclusive - OR (XOR) operation on the LUT4 logic output (LUT4[i]) of the i - th bit and the carry of the previous bit (Carry[i - 1]). The processing logic of mux8 is Carry[i]=LUT4[i]*Carry[i - 1]+(!LUT4[i])*LUT2[i], which means that the carry (Carry) of the i - th bit is obtained by ANDing the LUT4 logic output of the i - th bit with the carry of the previous bit and then adding the LUT2 logic output of the i - th bit, where i is a positive integer.
[0059] When implementing the adder function, LUT4[i]= a[i]^b[i]; LUT2[i]=a[i] or b[i]; Carry[0]=0.
[0060] When implementing the subtractor function, LUT4[i]= a[i]^(!b[i]), LUT2[i]=a[i] or!b[i]; Carry[0]=1.
[0061] In Figure 8 As shown, z represents the processing result of LUT4_o.
[0062] In Figure 8 In the shown structure, the lookup table structure and the carry chain structure can form the basic units of an adder or a subtractor. The cascading of the above - mentioned multiple basic units can form adders and subtractors with higher bit widths.
[0063] Figure 9 is Figure 8 a schematic diagram of the structure of the LUT4 in the structure shown. As Figure 9 shown, the four-input lookup table includes a multiplexer mux9 and 4 two-input lookup tables. Among them: Each two-input lookup table LUT2 receives the data signals of 2 signal input ends among the four signal input ends of the four-input lookup table, and outputs its respective output signal, and the output signal of one two-input lookup table is output to the corresponding ALU.
[0064] mux9 receives the output signals of the four two-input lookup tables, and under the control of the data signals of the remaining 2 signal input ends among the four signal input ends of the four-input lookup table, outputs an output signal as the output result LUT4_o of the four-input lookup table logic. In Figure 9 the structure shown, the output signals of the 4 LUT2s serve as the input signals of mux9, and under the control of the two-bit data signals {c, d}, output the output signal LUT4_o.
[0065] Figure 10 is a schematic diagram of the structure of the LUT2 provided by the embodiment of the present application. As Figure 10 shown, within each LUT2 unit, the data stored in the four RAM units (RAM0, RAM1, RAM2, RAM3) is used as the input signal of the multiplexer mux11. Under the control of the two-bit data signals {a, b}, mux11 generates an output signal LUT2_o. Specifically, when it is necessary to implement LUT2[i]=a, the settings of the RAM units are RAM0 = 0, RAM1 = 1, RAM2 = 0, RAM3 = 1; and when implementing LUT2[i]=b, the settings of the RAM units are RAM0 = 0, RAM1 = 0, RAM2 = 1, RAM3 = 1.
[0066] Figure 11 is a schematic diagram of the programmable logic unit in the embodiment of the present application. As Figure 11 shown, the output signal of the lookup table structure can be used as an independent output, corresponding to the OF signal in the figure; and the output signal of the carry chain structure can also be used as an independent output (corresponding to Figure 11 the Carry_out signal in).
[0067] In addition, the programmable logic unit further includes a multiplexer mux10. mux10 receives the output signal of the lookup table structure and the output signal of the carry chain structure, and selects one of them as the output signal of the programmable logic unit according to the need (corresponding to Figure 11 the F signal in).
[0068] Continue to refer to Figure 11, the programmable logic unit further includes a timing logic unit. Under the control of the clock signal clk, the timing logic unit generates an output signal using its input signal (corresponding to the Q signal in Figure 11 ). The input signal of the timing logic unit can be the output signal of the lookup table structure or a preset timing input signal (corresponding to the slogic_in signal in Figure 11 ).
[0069] Specifically, the programmable logic unit further includes a multiplexer mux11. Mux11 receives the output signal of the lookup table structure and the timing input signal, and selects one of them as the input signal of the timing logic unit according to the need. Such a design allows flexible control of the behavior of the timing logic unit to adapt to different logic requirements.
[0070] In addition, an FPGA device is provided in an embodiment of the present application. The FPGA device includes the lookup table structure described above or the programmable logic unit described above.
[0071] Figure 12 is a deployment schematic diagram of the FPGA device provided in the embodiment of the present application. As shown in Figure 12 , there are routing channels in the east-west (EW) direction and north-south (SN) direction inside the FPGA device. See the arrows in Figure 12 . These channels are used to provide the required data signals and clock signals for the programmable logic unit. The gating structure is responsible for transmitting the data signals and clock signals on the routing channels to the programmable logic unit.
[0072] Figure 13 is a schematic diagram of the routing deployment method of the lookup table structure in the FPGA device in the embodiment of the present application. As shown in Figure 13 , the input signal of the lookup table structure originates from the output of the gating structure in Figure 12 . The input of this lookup table structure can be a combination logic of 4 inputs, 5 inputs, or 6 inputs.
[0073] When the lookup table structure is in the LUT5 mode, since only IN0 and IN2, the 1st bit of IN1, and the 1st bit of IN3 are selected as inputs, the remaining multiplexers (mux) of IN1 and IN3 can act as an interconnection bridge between the wirings. This can achieve line interconnection between the north-south buses, line interconnection between the east-west buses, or line interconnection between the north-south and east-west buses.
[0074] When the LUT6 mode is selected, since only the 1st to 2nd bits of IN0 and IN1 are selected as inputs, the remaining multiplexers of IN1, IN2, and IN3 can be used as an interconnection bridge between the wirings to achieve a similar interconnection function.
[0075] In practical applications, users can flexibly select different LUT modes according to their own logic scale and wiring complexity to optimize the utilization rate of logic resources and the wiring interoperability.
[0076] Figure 14 For Figure 13 the application schematic diagram of the structure shown. As Figure 14 shown, the FPGA device is provided with a gating structure, where the input bus of the gating structure is respectively connected to the output buses of the east-west winding and the north-south winding output buses, and the output end is connected to the lookup table structure. At the same time, the output end is connected to the input buses of the east-west winding and the north-south winding. The gating structure obtains data signals from the output buses of the east-west winding and the north-south winding, and outputs the received signals to the lookup table structure as the data signals of the lookup table structure in different working modes. In the six-input lookup table mode or the five-input lookup table mode, some gating structures can be used as bridges to connect the north-south winding or the east-west winding signals. For example, in the six-input lookup table mode, the gating structures corresponding to IN1<2>, IN1<3>, IN2<0>, IN2<1>, IN2<2>, IN2<3>, IN3<0>, IN3<1>, IN3<2> and IN3<3> can be used as bridges. For example, in the five-input lookup table mode, the gating structures corresponding to IN1<1>, IN1<2>, IN1<3>, IN3<1>, IN3<2> and IN3<3> can be used as bridges.
[0077] The data signals from the east-west winding and the north-south winding are selected by the multiplexer MUX in the gating structure and sent to IN0<0> to IN3<3> respectively, and then enter the LUT. In the LUT5 and LUT6 modes, the remaining input multiplexers (such as the multiplexer of the IN1<2> line) can be used as bridging multiplexers and connected to the bridging buses of the east-west and north-south directions to achieve the interoperability of the east-west wiring and the north-south wiring.
[0078] In the logic programming with a smaller logic scale, the maximum utilization of logic resources can be achieved by configuring the LUT4 mode. In the case of a larger logic scale, the maximum utilization of wiring resources can be achieved.
[0079] Figure 15 For Figure 14 the deployment schematic diagram of the structure shown. As Figure 15As shown, the lookup table structure is provided with signal input terminals for 4-way four-bit data signals, a total of 16 signal input terminals, namely, the signal input terminal of IN0<0>, the signal input terminal of IN0<1>, the signal input terminal of IN0<2>, the signal input terminal of IN0<3>, the signal input terminal of IN1<0>, the signal input terminal of IN1<1>, the signal input terminal of IN1<2>, the signal input terminal of IN1<3>, the signal input terminal of IN2<0>, the signal input terminal of IN2<1>, the signal input terminal of IN2<2>, the signal input terminal of IN2<3>, the signal input terminal of IN3<0>, the signal input terminal of IN3<1>, the signal input terminal of IN3<2>, and the signal input terminal of IN3<3>.
[0080] In Figure 15 In the structure shown, the gating structure includes a gater MUX corresponding to each signal input terminal. Each MUX can obtain its respective data signal from the output bus of the east-west winding and the output bus of the north-south winding, and under the control of the control signal sent by the control structure, gate a path of signal as the data signal of its corresponding signal input terminal.
[0081] The 12 signal input terminals corresponding to the 3 four-bit data signals IN1, IN2, and IN3, a total of 12 MUXs. Among them, a connection point is provided between the output terminal of each of the 12 MUXs and its corresponding signal input terminal. The connection point is connected to 2 sub-paths in the east-west winding input bus, or, connected to 2 sub-paths in the north-south winding input bus, or, respectively connected to 1 sub-path in the east-west winding input bus and 1 sub-path in the north-south winding input bus.
[0082] Among them, when any signal input terminal in the lookup table structure does not need to input a signal, the MUX corresponding to the signal that does not participate in the lookup table operation serves as a bridging MUX. The bridging MUX outputs the received signal to the sub-paths of the input buses of the respective north-south winding and east-west winding through the connection point.
[0083] Specifically, for the MUXs corresponding to the signal input terminals from IN1<0> to IN1<3>, the MUXs corresponding to the signal input terminals from IN2<0> to IN2<3>, and the MUXs corresponding to the signal input terminals from IN3<0> to IN3<3>, these MUXs can also serve as bridging MUXs. In Figure 15 In the structure shown, a connection point D is provided between these MUXs and their respective signal input terminals. Among them, the connection point D is respectively connected to 1 sub-path in the input bus of the east-west winding and 1 sub-path in the input bus of the north-south winding, so that the signal output by the MUX can realize data input through the input bus of the east-west winding or the input bus of the north-south winding.
[0084] InFigure 15 In the structure shown, the output terminals of the bridging MUXes that implement the bridging function are respectively connected to one sub-line in the input bus of the east-west routing and one sub-line in the input bus of the north-south routing. However, this is not limited to this. In actual applications, they can be respectively connected to two sub-lines in the input bus of the east-west routing, or respectively connected to two sub-lines in the input bus of the north-south routing.
[0085] When the working mode of the lookup table structure is the six-input lookup table mode, the MUXes corresponding to the 4 signal input terminals of the four-bit data signal IN0 receive the four-bit data signals of the six-input lookup from their respective input terminals and output them through their respective input terminals; and, among the 12 signal input terminals corresponding to the 3 four-bit data signals IN1, IN2, and IN3, the MUXes corresponding to 2 signal input terminals receive the fifth-bit data signal and the sixth-bit data signal of the six-input lookup from their respective input terminals and output them through their respective input terminals.
[0086] Figure 16 For Figure 15 Schematic diagram of the signal flow when the structure shown works in the LUT6 working mode. As Figure 16 shown, the signal input terminals of IN0<0>, IN0<1>, IN0<2>, IN0<3>, IN1<0>, and IN1<1>, a total of 6 signal input terminals, are used as the signal input terminals of LUT6. Since the remaining signal input terminals do not participate in the operation of the lookup table structure, the MUXes corresponding to the remaining signal input terminals can be used as bridging MUXes.
[0087] For example, in Figure 16 the structure shown, the MUX corresponding to the signal input terminal of IN1<2> and the MUX corresponding to the signal input terminal of IN3<0>; where: For the MUX corresponding to the signal input terminal of IN1<2>, this MUX obtains a signal from the output bus of the east-west routing and sends the received signal to the input bus of the north-south routing through connection point D.
[0088] For the MUX corresponding to the signal input terminal of IN3<0>, this MUX obtains a signal from the output bus of the north-south routing and sends the received signal to the input bus of the east-west routing through connection point D.
[0089] From the above example, it can be seen that as a bridging MUX, it can achieve the intercommunication between the signals transmitted on the bus in the east-west routing and the signals transmitted on the bus in the north-south routing.
[0090] When the working mode of the lookup table structure is the five-input lookup table mode, the four MUXs corresponding to the four signal input terminals of the four-bit data signal IN0 receive the four-bit data signals of the first five-input lookup table from their respective input terminals and output them through their respective output terminals; the four MUXs corresponding to the four signal input terminals of the four-bit data signal IN2 receive the four-bit data signals of the second five-input lookup table from their respective input terminals and output them through their respective output terminals; among the eight signal input terminals of the two four-bit data signals IN1 and IN3, one of the two MUXs corresponding to the two signal input terminals receives the fifth-bit data signal of the first five-input lookup table from their respective output terminals and outputs it through their respective output terminals, and the other MUX receives the fifth-bit data signal of the second five-input lookup table from their respective output terminals and outputs it through their respective output terminals.
[0091] Figure 17 is Figure 15 a schematic diagram of the signal flow when the structure shown works in the LUT5 working mode. As Figure 17 shown, the signal input terminals of IN0<0>, IN0<1>, IN0<2>, IN0<3>, and IN1<0>, a total of five signal input terminals, are used as the signal input terminals of the first LUT5. The signal input terminals of IN2<0>, IN2<1>, IN2<2>, IN2<3>, and IN3<0>, a total of five signal input terminals, are used as the signal input terminals of the second LUT5. Since the remaining signal input terminals do not participate in the operation of the lookup table structure, the MUXs corresponding to the remaining signal input terminals can be used as bridging MUXs.
[0092] For example, in Figure 17 the structure shown, the MUX corresponding to the signal input terminal of IN1<2> and the MUX corresponding to the signal input terminal of IN3<1>; where: For the MUX corresponding to the signal input terminal of IN1<2>, this MUX obtains a signal from the output bus of the east-west wire and sends the received signal to the input bus of the north-south wire through the connection point D.
[0093] For the MUX corresponding to the signal input terminal of IN3<1>, this MUX obtains a signal from the output bus of the north-south wire and sends the received signal to the input bus of the east-west wire through the connection point D.
[0094] From the above example, it can be seen that as a bridging MUX, it can realize the interconnection between the signals transmitted on the bus in the east-west wire and the signals transmitted on the bus in the north-south wire.
[0095] Similarly, it can be known that when the working mode of the lookup table structure is a four-input lookup table mode, the 4 signal input terminals corresponding to the four-bit data signal IN0 of each MUX receive the four-bit data signal of the first four-input lookup table from their respective output terminals and output through their respective output terminals; the 4 signal input terminals corresponding to the four-bit data signal IN1 of each MUX receive the four-bit data signal of the second four-input lookup table from their respective output terminals and output through their respective output terminals; the 4 signal input terminals corresponding to the four-bit data signal IN2 of each MUX receive the four-bit data signal of the third four-input lookup table from their respective output terminals and output through their respective output terminals; the 4 signal input terminals corresponding to the four-bit data signal IN3 of each MUX receive the four-bit data signal of the fourth four-input lookup table from their respective output terminals and output through their respective output terminals.
[0096] Figure 18 For Figure 15 a schematic diagram of the working mode of the MUX in the structure shown. As Figure 18 shown, the north-south winding output bus has N + 1 sub-lines, and the east-west winding output bus has M + 1 sub-lines, where both N and M are positive integers.
[0097] In Figure 18 the structure shown, the control signal is used to output a switch control signal, where the switch control signal includes control signals corresponding one-to-one to the sub-lines in the north-south winding output bus, and control signals corresponding one-to-one to the sub-lines in the east-west winding output bus; Specifically, the control structure is an SRAM, which stores control signals SRAM0_0~N and control signals SRAM1_0~M, and is used to control the conduction states of the N + 1 sub-lines in the north-south winding output bus by the control signals SRAM0_0~N, and control the conduction states of the M + 1 sub-lines in the east-west winding output bus by the control signals SRAM1_0~M. Among them: For each MUX, only one of the control signals SRAM0_0~N has a value of 1, and the rest have values of 0, and at the same time, the control signals SRAM1_0~M are all 0, so that only 1 sub-line signal in the north-south winding output bus is output to the BUF at any time; or, only one of the control signals SRAM1_0~M has a value of 1, and the rest have values of 0, and at the same time, the control signals SRAM0_0~N are all 0, so that only 1 sub-line signal in the east-west winding output bus is output to the BUF at any time.
[0098] Based on the above mechanism, the MUX receives signals from the north-south winding output bus and the east-west winding output bus respectively, and selects and outputs one path of signal to the lookup table structure.
[0099] Figure 19 For Figure 18The first schematic diagram of the signal flow direction in the shown structure. As Figure 19 shown, the signal output to the lookup table structure can come from one sub-line of the north-south winding output bus (e.g., the sub-line corresponding to the control signal SRAM0_0); or, from one sub-line of the east-west winding output bus (e.g., the sub-line corresponding to any signal among the control signals SRAM1_1~M).
[0100] Figure 20 For Figure 18 the second schematic diagram of the signal flow direction in the shown structure. As Figure 20 shown, the signal from one sub-line of the east-west winding output bus (e.g., the sub-line corresponding to any signal among the control signals SRAM1_1~M) can be output to the north-south winding input bus after passing through the BUF; or, output to the east-west winding input bus.
[0101] Figure 21 For Figure 18 the third schematic diagram of the signal flow direction in the shown structure. As Figure 20 shown, the signal from one sub-line of the north-south winding output bus (e.g., the sub-line corresponding to the control signal SRAM0_1) can be output to the north-south winding input bus after passing through the BUF; or, output to the east-west winding input bus.
[0102] From the above analysis, it can be seen that the bridging MUX uses an additional MUX to achieve signal intercommunication between different winding directions. For example, the north-south and east-west windings can exchange signals through the MUX, thus realizing signal transmission in different directions. This design provides a high degree of flexibility, allowing dynamic selection and transmission of signals between different windings, and at the same time can improve the reliability and maintainability of the circuit. Specifically, it is reflected in the following aspects: 1. Resource optimization: By using the MUX, the required physical connections can be reduced, thus saving space and cost.
[0103] 2. Signal routing: The MUX allows flexible routing between different signal paths, which is particularly important for complex circuit designs.
[0104] 3. Scalability: This design can be easily extended to accommodate more input signals or more winding directions.
[0105] 4. Fault isolation: If there is a problem with a certain winding or signal path, other paths can be selected through the MUX, thus improving the reliability of the system.
[0106] 5. Simplified design: By centralizing the selection of control signals, the logic design of the entire system can be simplified, making maintenance and upgrade easier.
[0107] Those of ordinary skill in the art will understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations. In the hardware implementation, the division between the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be executed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.
Claims
1. A lookup table structure, characterized in that: It includes four four-input lookup tables lut4_1, lut4_2, lut4_3 and lut4_4; and three selectors mux4, mux5 and mux7; wherein: When the working mode of the lookup table structure is the six-input lookup table mode, each four-input lookup table receives the four-bit data signal IN0 of the six-input lookup table and outputs its own output signal; wherein the output signal of lut4_1 and the output signal of lut4_2 are the input signals of mux4, and the output signal of lut4_3 and the output signal of lut4_4 are the input signals of mux5; Under the control of the fifth bit data signal of the six-input lookup table, mux4 and mux5 respectively output their own output signals according to their own input signals as the input signals of mux7; Under the control of the sixth bit data signal of the six-input lookup table, mux7 outputs an output signal according to the received input signal as the output result of the six-input lookup table.
2. The lookup table structure according to claim 1, characterized in that: When the working mode of the lookup table structure is a five-input lookup table mode, the lookup table structure has two five-input lookup tables; wherein: lut4_1 and lut4_2 both receive the four-bit data signal of the first five-input lookup table and output their respective output signals; mux4 receives the output signal of lut4_1 and the output signal of lut4_2, and under the control of the fifth-bit data signal in the first five-input lookup table, outputs the output signal according to the received input signal as the output result of the first five-input lookup table; LUT4_3 and LUT4_4 both receive the four-bit data signal of the second five-input lookup table and output their own output signals; MUX5 receives the output signal of LUT4_3 and the output signal of LUT4_4, and under the control of the fifth-bit data signal in the second five-input lookup table, outputs the output signal according to the received input signal as the output result of the second five-input lookup table.
3. The lookup table structure according to claim 2, characterized in that: The four-bit data signal of lut4_2 can be switched to IN0 or IN1, the four-bit data signal of lut4_3 is IN0 or IN2, and the four-bit data signal of lut4_4 is IN0 or IN2 or IN3; When the operation mode of the lookup table structure is a five-input lookup table mode, the four-bit data signal of the first five-input lookup table is IN0, and the four-bit data signal of the second five-input lookup table is IN2.
4. The lookup table structure according to claim 2, characterized in that: The lookup table structure also includes a gate mux6; mux6 receives the fifth data signal in the first five-input lookup table and the fifth data signal in the second five-input lookup table, and when the working mode is the six-input lookup table mode, outputs the fifth data signal in the first five-input lookup table as the control signal of mux5; when the working mode is the five-input lookup table mode, outputs the fifth data signal in the second five-input lookup table as the control signal of mux5.
5. The lookup table structure according to any one of claims 2 to 4, characterized in that: When the working mode of the lookup table structure is a four-input lookup table mode, the lookup table structure includes four four-input lookup tables; wherein: lut4_1 receives a four-bit data signal and outputs an output signal as the output result of the first four-input lookup table; lut4_2 receives a four-bit data signal and outputs an output signal as the output result of the second four-input lookup table; lut4_3 receives a four-bit data signal and outputs an output signal as the output result of the third four-input lookup table; lut4_4 receives a four-bit data signal and outputs an output signal as the output result of the fourth four-input lookup table.
6. The lookup table structure according to claim 5, characterized in that: The four-bit data signal of lut4_2 can be switched to IN0 or IN1, the four-bit data signal of lut4_3 is IN0 or IN2, and the four-bit data signal of lut4_4 is IN0 or IN2 or IN3; When the operation mode of the lookup table structure is the four-input lookup table mode, the four-bit data signal received by lut4_1 is IN0, the four-bit data signal received by lut4_2 is IN1, the four-bit data signal received by lut43 is IN2, and the four-bit data signal received by lut4_4 is IN3.
7. The lookup table structure according to claim 6, characterized in that: The lookup table structure also includes three gates, namely mux1, mux2 and mux3; wherein: mux1 receives a four-bit data signal IN0 and a four-bit data signal IN1, and outputs a four-bit data signal IN0 when the working mode of the lookup table structure is a six-input lookup table mode or a five-input lookup table mode; and outputs a four-bit data signal IN1 when the working mode of the lookup table structure is a four-input lookup table mode; mux2 receives a four-bit data signal IN0 and a four-bit data signal IN2, and outputs a four-bit data signal IN0 when the working mode of the lookup table structure is a six-input lookup table mode; and outputs a four-bit data signal IN2 when the working mode of the lookup table structure is not a six-input lookup table mode; mux3 receives four-bit data signal IN0, four-bit data signal IN2 and four-bit data signal IN3, and outputs four-bit data signal IN0 when the working mode of the lookup table structure is six-input lookup table mode; outputs four-bit data signal IN2 when the working mode of the lookup table structure is five-input lookup table mode; outputs four-bit data signal IN3 when the working mode of the lookup table structure is four-input lookup table mode.
8. A programmable logic unit, characterized in that: It comprises a lookup table structure and a carry chain structure as described in any one of claims 1 to 5, wherein the carry chain structure comprises four cascaded arithmetic logic units ALU, wherein each ALU has a corresponding four-input lookup table; wherein each ALU receives a respective carry input signal and an output signal of a respective four-input lookup table, and outputs an output signal.
9. The programmable logic unit according to claim 8, characterized in that: Each ALU includes a gate mux8 and an XOR function unit; wherein: For the current ALU, mux8 receives the carry input signal of the current ALU and the output signal of the two-input lookup table logic output by the four-input lookup table of the current ALU, and outputs the carry output signal of the current ALU as an output signal of the current ALU under the control of the output signal of the four-input lookup table logic output by the four-input lookup table of the current ALU; For the current ALU, the XOR functional unit receives the carry input signal of the current ALU and the output signal of the four-input lookup table logic output by the four-input lookup table of the current ALU, and outputs a calculation result signal as another output signal of the current ALU.
10. The programmable logic unit according to claim 9, characterized in that: Each four-input lookup table includes a gate mux9 and four two-input lookup tables; where: Each two-input lookup table receives data signals from two of the four signal input terminals in the four-input lookup table and outputs respective output signals, wherein the output signal of one of the two-input lookup tables is output to a corresponding ALU; mux9 receives the output signals of four two-input lookup tables, and under the control of the data signals of the remaining two signal input terminals of the four signal input terminals in the four-input lookup table, outputs the output signal as the output result of the four-input lookup table logic.
11. The programmable logic unit according to claim 8, characterized in that: The programmable logic unit further includes a gate mux10; wherein: mux10 receives the output signal of the lookup table structure and the output signal of the carry chain structure, and selects the output signal of the lookup table structure or the output signal of the carry chain structure as the output signal of the programmable logic unit.
12. The programmable logic unit according to any one of claims 8 to 11, characterized in that: The programmable logic unit also includes a sequential logic unit; in; The sequential logic unit outputs an output signal using an input signal of the sequential logic unit under the control of a clock signal, wherein the input signal of the sequential logic unit can be switched to an output signal of the lookup table structure or a preset sequential input signal.
13. The programmable logic unit according to claim 12, characterized in that: The programmable logic unit further includes a gate mux11, mux11 receives the output signal of the lookup table structure and the timing input signal, and selects the output signal of the lookup table structure or the timing input signal as the input signal of the sequential logic unit.
14. An FPGA device, characterized in that: The FPGA device includes a lookup table structure as described in any one of claims 1 to 7 or a programmable logic unit as described in any one of claims 8 to 13.
15. The FPGA device according to claim 14, characterized in that: The FPGA device also includes a gating structure; wherein: The selection structure has one end connected to the east-west winding and the north-south winding respectively, and the other end connected to the lookup table structure, and is used to obtain signals from the east-west winding input bus and the north-south winding input bus, and output the received signals to the lookup table structure as data signals of the lookup table structure in different working modes.
16. The FPGA device according to claim 15, characterized in that: The gating structure is provided with 16 gates MUX corresponding to the 16 signal input terminals of the lookup table structure, wherein the 16 signal input terminals are 4 signal input terminals of the 4 four-bit data signals IN0, IN1, IN2, and IN3 respectively; The input end of each MUX is connected to the east-west winding output bus and the north-south winding output bus, and the output end is connected to the corresponding signal output end; wherein: When the operation mode of the lookup table structure is the six-input lookup table mode, the MUXs corresponding to the four signal input terminals of the four-bit data signal IN0 receive the four-bit data signal of the six-input lookup from their respective input terminals and output through their respective input terminals; the MUXs corresponding to two signal input terminals of the three four-bit data signals IN1, IN2 and IN3, a total of 12 signal input terminals, receive the fifth-bit data signal and the sixth-bit data signal of the six-input lookup from their respective input terminals and output through their respective input terminals; When the working mode of the lookup table structure is the five-input lookup table mode, the MUXs corresponding to the four signal input terminals of the four-bit data signal IN0 receive the four-bit data signal of the first five-input lookup table from their respective input terminals and output it through their respective output terminals; the MUXs corresponding to the four signal input terminals of the four-bit data signal IN2 receive the four-bit data signal of the second five-input lookup table from their respective input terminals and output it through their respective output terminals; one of the MUXs corresponding to two of the eight signal input terminals of the two four-bit data signals IN1 and IN3 receives the fifth-bit data signal of the first five-input lookup table from their respective output terminals and outputs it through their respective output terminals, and the other MUX receives the fifth-bit data signal of the second five-input lookup table from their respective output terminals and outputs it through their respective output terminals; When the working mode of the lookup table structure is the four-input lookup table mode, the MUXs corresponding to the four signal input terminals of the four-bit data signal IN0 receive the four-bit data signal of the first four-input lookup table from their respective output terminals and output it through their respective output terminals; the MUXs corresponding to the four signal input terminals of the four-bit data signal IN1 receive the four-bit data signal of the second four-input lookup table from their respective output terminals and output it through their respective output terminals; the MUXs corresponding to the four signal input terminals of the four-bit data signal IN2 receive the four-bit data signal of the third four-input lookup table from their respective output terminals and output it through their respective output terminals; the MUXs corresponding to the four signal input terminals of the four-bit data signal IN3 receive the four-bit data signal of the fourth four-input lookup table from their respective output terminals and output it through their respective output terminals.
17. The FPGA device according to claim 16, characterized in that: There are 12 MUXs corresponding to the 12 signal input terminals of the three four-bit data signals IN1, IN2 and IN3, wherein a connection point is provided between the output terminal of each MUX of the 12 MUXs and the corresponding signal input terminal, and the connection point is connected to two sub-routes in the east-west winding input bus, or connected to two sub-routes in the north-south winding input bus, or respectively connected to one sub-routes in the north-south winding input bus and one sub-routes in the east-west winding input bus; Among them, when any signal input end in the lookup table structure does not need an input signal, the MUX corresponding to the signal that does not participate in the lookup table function acts as a bridge MUX, wherein the bridge MUX outputs the received signal through the connection point to the sub-paths of the input buses of the corresponding north-south winding and east-west winding.
18. The FPGA device according to claim 16, characterized in that: The FPGA device also includes a control structure, wherein: The control structure is used to output switch control signals, wherein the switch control signals include control signals corresponding one-to-one to the sub-routes in the north-south winding output bus, and control signals corresponding one-to-one to the sub-routes in the east-west winding output bus; For each MUX, only one of the control signals corresponding to the sub-routes in the north-south winding output bus and the sub-routes in the east-west winding output bus is valid, so that the north-south winding output bus or the east-west winding output bus has only one sub-routes signal as output.