Satellite-borne baseband equipment high-speed data receiving method and system based on FPGA
By using the system clock in the satellite-based baseband device for synchronous sampling and data cache across the clock domain, the cache abnormality caused by overloading clock load and load device power switch is solved, and a higher general design and reliability are achieved.
Patent Information
- Application Number
- CN202510280711.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-11
- Publication Date
- 2025-05-30
AI Technical Summary
When the satellite-based baseband device receives high-speed data, the overload of the clock affects the FPGA layout and wiring, and the load device switches on and off, causing cache read and write abnormalities, making it difficult to realize a general design.
Through the parameterization of the reception link, the system clock is used to complete the cross-clock domain sampling processing of high-speed data, optimize the layout and routing of clock resources, and implement data cache in the FPGA to ensure safe and orderly storage of data.
It simplifies the development time of product design, improves the degree of universalization of equipment, optimizes the layout and wiring of FPGAs, and improves the design performance and reliability of the product.
Smart Images
Figure CN120074642A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data reception, and in particular to a high-speed data reception method and system for on-board baseband equipment based on FPGA. Background Art
[0002] On-board baseband equipment is mainly used to receive, process and transmit data collected by satellites and information characterizing the state of the satellites themselves. As satellite functions become more complex, the carried payload equipment becomes more diverse, and the transmission rate becomes faster. The interface between the on-board baseband equipment and the payload equipment adopts a source synchronous interface with a higher transmission rate. This interface is accompanied by a co-frequency clock from the output side of the payload equipment, which is basically consistent with the data delay and can provide higher transmission capacity. In addition, the source synchronous interface can further improve the transmission rate through parallelism. Generally, on-board baseband equipment uses the parallel processing ability of FPGA to receive various payload data for processing. However, with the increase in payload equipment, the diversification of interfaces and the limitation of FPGA resources, the challenge of general-purpose design for link reception becomes more and more serious.
[0003] Currently, the commonly used method directly writes data into the cache using the accompanying clock. The accompanying clock has too much load, which is not conducive to the layout and wiring of FPGA, thus affecting the overall performance. In addition, due to different application requirements of payload equipment, power-on and power-off operations may occur. During the power-on and power-off process of the payload equipment, the accompanying clock is unstable, which may lead to abnormal cache reading and writing. Summary of the Invention
[0004] Aiming at the above problems, the purpose of the present invention is to provide a high-speed data reception method and system for on-board baseband equipment based on FPGA. By parameterizing the settings of the receiving link, the development time of product design is simplified, and the generalization degree of the equipment is improved. Using the system clock to complete the cross-clock domain synchronous sampling processing of high-speed data is conducive to optimizing the layout and wiring of clock resources, and improving the design performance and reliability of the product.
[0005] The above invention purpose of the present invention is achieved through the following technical solutions: A high-speed data reception method for on-board baseband equipment based on FPGA includes the following steps: S1: Based on the fact that the on-board baseband equipment needs to receive high-speed data from different payload equipment, and the interfaces of different payload equipment are diverse and the data characteristics are different, parameter configurations are respectively performed for each receiving link of the on-board baseband equipment; S2: A source synchronous interface is adopted between the spaceborne baseband device and the payload device. The source synchronous interface is accompanied by a co-frequency accompanying clock f0. The accompanying clock f0 is used to complete the synchronization and serial-to-parallel conversion of the input data, so as to utilize the characteristics of the accompanying clock f0 to preliminarily process the data in the initial stage of data transmission and prepare for subsequent further processing. S3: The synchronization of the input data is completed using the system clock f1, and the input data is converted into a form synchronized with the system clock f1 to improve the stability and reliability of data processing. S4: The caching of the input data is completed using the system clock f1 to avoid potential problems brought by the accompanying clock f0 and ensure that the data is safely and orderly stored in the cache.
[0006] Further, in step S1, parameter configurations are respectively performed for each receiving link of the spaceborne baseband device. The parameters include: The sampling edge P1 of the accompanying clock f0, the input data width P2, the cache width P3, the signal valid identification width P4, the data detection period P5, and the packet synchronization identification P6. Among them, the sampling edge P1 is used to determine at which edge of the accompanying clock f0 the input data is sampled. The input data width P2 represents the width of the input data. The cache width P3 determines the width of data storage in the cache. The signal valid identification width P4 is used to judge whether the data is valid. The data detection period P5 is used to detect whether input data is received within a certain time. The packet synchronization identification P6 is used for data synchronization processing to ensure the correct reception and processing of data.
[0007] Further, the data reception of the spaceborne baseband device is implemented using FPGA. The parameter settings of each high-speed data receiving link can use any one of the methods including static setting and dynamic setting; it is recommended to use static setting for the input data width P2 and the cache width P3.
[0008] Further, in step S2, the synchronization and serial-to-parallel conversion of the input data are completed using the accompanying clock f0. Specifically: S21: Sample the input data according to the sampling edge P1, including the data gating F signal, which indicates whether the data is received. If there is no data gating F signal, it is default set that all data is received. S22: Perform data shifting according to the input data width P2 and the cache width P3 when the data gating F occurs. The data is temporarily stored in the data register, and the depth of the data register is the same as the cache width P3. Among them, the input data width P2 and the cache width P3 are powers of 2, and the cache width P3 should be more than twice the input data width P2. S23: Use a shift counter to perform cyclic counting on the data shift operation. If the packet synchronization flag P6 is valid, clear the shift counter every time the data gating F is invalid to re-synchronize; otherwise, do not clear it. S24: When the value of the shift counter is 2 * the cache bit width P3 / the input data bit width P2, latch the data in the data register and store it in the data latch D. The depth of the data latch D is the same as the cache bit width P3. S25: Use an identification counter to perform counting during the data input process. Clear the counter when the shift counter value is 2 * the cache bit width P3 / the input data bit width P2; hold the data when it is the cache bit width P3 / the input data bit width P2; otherwise, perform incremental counting, and set the value to the signal valid identification width P4 after the identification counter is reset. S26: When the identification counter is less than the signal valid identification width P4, set the signal output valid flag C to valid; otherwise, set it to invalid, where the signal valid identification width P4 should be greater than the integer value of f0 / f1.
[0009] Further, in step S3, use the system clock f1 to complete the synchronization of the input data, specifically: S31: Use the system clock f1 to perform secondary synchronization on the data D and the signal output valid flag C output in step S2. S32: Perform edge parsing on the synchronized signal output valid flag C to parse out the rising edge. S33: Output and latch D1 the synchronized data at the rising edge. This data is synchronized with the system clock f1. S34: Generate a new signal output valid flag C1 for the output data. This flag is synchronized with the system clock f1 and has a width of 1 system clock. S35: Generate a timing counter based on the data detection period P5 and the system clock f1. When the signal output valid flag C1 for the output data is valid, clear the counter; otherwise, keep counting until it reaches the maximum value and then stop, where the maximum count value is generated by the data detection period P5. S36: Detect the value of the timing counter. If it is the maximum value, it means that no input data has been received within the set time range; otherwise, it means that there is data input.
[0010] Further, in step S4, use the system clock f1 to complete the caching of the input data, specifically: S41: Write the data D1 and the valid flag C1 output in step S3 into the cache using the system clock f1. The cache is generally a FIFO or dual-port RAM. S42: Set the interrupt priority according to the data volume in the cache and wait for further data processing.
[0011] Further, the system clock f1 and the accompanying clock f0 satisfy the following condition: f1 ≥ 4 * f0 / (P3 / P2).
[0012] A high-speed data receiving system for an on-board baseband device based on FPGA for implementing the high-speed data receiving method of the on-board baseband device based on FPGA as described above, including: A parameter configuration module, which configures parameters for each receiving link of the on-board baseband device respectively based on the fact that the on-board baseband device needs to receive high-speed data from different payload devices, and the interfaces of different payload devices are diverse and the data characteristics are different. An accompanying clock synchronization and serial-parallel conversion module. A source synchronous interface is adopted between the on-board baseband device and the payload device. The source synchronous interface is accompanied by a co-frequency accompanying clock f0. Use the accompanying clock f0 to complete the synchronization and serial-parallel conversion of the input data, so as to utilize the characteristics of the accompanying clock f0 to perform preliminary processing on the data in the initial stage of data transmission and prepare for subsequent further processing. A system clock data synchronization module, which uses the system clock f1 to complete the synchronization of the input data and converts the input data into a form synchronized with the system clock f1 to improve the stability and reliability of data processing. A system clock data caching module, which uses the system clock f1 to complete the caching of the input data to avoid potential problems brought by the accompanying clock f0 and ensure that the data is stored in the cache safely and orderly.
[0013] A computer device includes a memory and one or more processors. Computer code is stored in the memory. When the computer code is executed by the one or more processors, the one or more processors execute the method as described above.
[0014] A computer-readable storage medium stores computer code. When the computer code is executed, the method as described above is executed.
[0015] Compared with the prior art, the present invention has at least one of the following beneficial effects: (1) A high-speed data receiving method for an on-board baseband device based on FPGA provided by the present invention simplifies the development time of product design and improves the generalization degree of the device through parameterized setting of the receiving link.
[0016] (2)The high-speed data receiving method for on-board baseband equipment based on FPGA provided by the present invention uses the system clock to complete the synchronous sampling process of high-speed data, which is beneficial to optimizing the layout and routing of clock resources and improving the design performance and reliability of the product. Description of the Drawings
[0017] Figure 1 is the overall flowchart of the high-speed data receiving method for on-board baseband equipment based on FPGA of the present invention; Figure 2 is a schematic diagram of a typical application of the high-speed data receiving method for on-board baseband equipment based on FPGA of the present invention. Detailed Embodiments
[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some, but not all, of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0019] Those skilled in the art of the present technology can understand that unless specifically stated otherwise, the singular forms "a", "an", "the", and "said" used herein may also include the plural forms. It should be further understood that the term "comprising" used in the description of the present invention means the presence of the described features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.
[0020] First Embodiment As Figure 1 shown, this embodiment provides a high-speed data receiving method for on-board baseband equipment based on FPGA, including the following steps: S1: Based on the fact that the on-board baseband equipment needs to receive high-speed data from different payload devices, and the interfaces of different payload devices are diverse and the data characteristics are different, parameter configurations are respectively performed for each receiving link of the on-board baseband equipment.
[0021] S2: A source synchronous interface is adopted between the on-board baseband equipment and the payload device. The source synchronous interface is accompanied by a co-frequency accompanying clock f0. The accompanying clock f0 is used to complete the synchronization and serial-to-parallel conversion of the input data, so as to utilize the characteristics of the accompanying clock f0 to perform preliminary processing on the data in the initial stage of data transmission and prepare for subsequent further processing.
[0022] S3: Use the system clock f1 to complete the synchronization of the input data, and convert the input data into a form synchronized with the system clock f1 to improve the stability and reliability of data processing; S4: Use the system clock f1 to complete the caching of the input data to avoid potential problems caused by the accompanying clock f0 and ensure that the data is stored securely and orderly in the cache.
[0023] Further, in step S1, parameter configurations are performed separately for each receiving link of the spaceborne baseband device. The parameters include: The sampling edge P1 of the accompanying clock f0, the input data bit width P2, the cache bit width P3, the signal valid identification width P4, the data detection period P5, and the packet synchronization identification P6; Among them, the sampling edge P1 is used to determine at which edge of the accompanying clock f0 the input data is sampled. The input data bit width P2 represents the width of the input data. The cache bit width P3 determines the width of data storage in the cache. The signal valid identification width P4 is used to determine whether the data is valid. The data detection period P5 is used to detect whether input data is received within a certain time. The packet synchronization identification P6 is used for data synchronization processing to ensure the correct reception and processing of data.
[0024] Further, the data reception of the spaceborne baseband device is implemented by an FPGA, and the parameter settings of each high-speed data receiving link use any one of the methods including static setting and dynamic setting; It is recommended to use static settings for the input data bit width P2 and the cache bit width P3.
[0025] Further, in step S2, use the accompanying clock f0 to complete the synchronization and serial-to-parallel conversion of the input data. Specifically: S21: Sample the input data according to the sampling edge P1, including the data gating F signal, which indicates whether the data is received. If there is no data gating F signal, it is default set that all data is received; S22: Perform data shifting according to the input data bit width P2 and the cache bit width P3 when the data gating F is valid. The data is temporarily stored in the data register, and the depth of the data register is the same as the cache bit width P3. Among them, the input data bit width P2 and the cache bit width P3 are powers of 2, and the cache bit width P3 should be more than twice the input data bit width P2; S23: Use a shift counter to perform cyclic counting on the data shifting operation. If the packet synchronization identification P6 is valid, the shift counter is cleared and resynchronized each time the data gating F is invalid; otherwise, it is not cleared; S24: When the value of the shift counter is 2 * the buffer bit width P3 / the input data bit width P2, latch the data in the data register and store it in the data latch D. The depth of the data latch D is the same as the buffer bit width P3. S25: During the data input process, use the identification counter to count. When the value of the shift counter is 2 * the buffer bit width P3 / the input data bit width P2, clear this counter; when the value is the buffer bit width P3 / the input data bit width P2, hold the data; otherwise, perform an increment count, and after the identification counter is reset, set the value to the signal valid identification width P4. S26: When the identification counter is less than the signal valid identification width P4, set the signal output valid identification C to valid; otherwise, set it to invalid, where the signal valid identification width P4 should be greater than the integer value of f0 / f1.
[0026] Further, in step S3, use the system clock f1 to complete the synchronization of the input data. Specifically: S31: Use the system clock f1 to perform secondary synchronization on the data D and the signal output valid identification C output in step S2. S32: Perform edge parsing on the synchronized signal output valid identification C to parse out the rising edge. S33: At the rising edge, perform output latching D1 on the synchronized data. This data is synchronized with the system clock f1. S34: Generate a new signal output valid identification C1 for the output data. This identification is synchronized with the system clock f1 and has a width of 1 system clock. S35: Generate a timing counter based on the data detection period P5 and the system clock f1. When the signal output valid identification C1 for the output data is valid, clear this counter; otherwise, keep counting until it reaches the maximum value and then stop, where the maximum count value is generated by the data detection period P5. S36: Detect the value of the timing counter. If it is the maximum value, it means that no input data has been received within the set time range; otherwise, it means that there is data input.
[0027] Further, in step S4, use the system clock f1 to complete the buffering of the input data. Specifically: S41: Use the system clock f1 to write the data D1 and the valid identification C1 output in step S3 into the buffer. The buffer is generally a FIFO or dual-port RAM. S42: Set the interrupt priority according to the data volume in the buffer and wait for further data processing.
[0028] Furthermore, the system clock f1 and the companion clock f0 satisfy the following condition: f1 ≥ 4 * f0 / (P3 / P2).
[0029] Second Embodiment In this embodiment, Figure 2 as shown, a typical application of a high-speed data receiving method for a spaceborne baseband device based on FPGA is provided. After the spaceborne baseband device receives 4-channel high-speed data from payload devices, AOS encoding is completed. Among them, Device 1 inputs a companion clock of 100 MHz, with a bit width of 1 bit, and the rising edge aligns with the data transition; Device 2 inputs a companion clock of 80 MHz, with a bit width of 2 bits, and the rising edge aligns with the data transition; Device 3 inputs a companion clock of 75 MHz, with a bit width of 4 bits, and the rising edge aligns with the data transition; Device 4 inputs a companion clock of 30 MHz, with a bit width of 8 bits, and the falling edge aligns with the data transition.
[0030] Furthermore, in this embodiment, the data reception of the spaceborne baseband device is implemented using FPGA. Since the interface rate of the payload device is fixed and does not require dynamic adjustment, the parameters of the receiving link are set in a static manner.
[0031] Furthermore, in this embodiment, the system clock is 40 MHz. The parameter settings of each receiving link are shown in Table 1: Table 1 Parameter Settings of Each Link Furthermore, in step S2, the companion clock is used to complete the synchronization and serial-to-parallel conversion of the input data, including the following steps: S21: Links 1, 2, and 3 sample the input data and the data gating signal F at the falling edge of the companion clock, and Link 4 samples the input data and the data gating signal F at the rising edge of the companion clock. Among them, the low level of the gating indicates valid data, and the high level indicates invalid data.
[0032] S22: According to the data bit width P2 and the buffer bit width P3, data shifting is performed when the data input is valid. The data is temporarily stored in the data register shftreg, and the depth of the data register is the same as the buffer bit width P3. The data register shftreg is designed as follows, shftreg <= shftreg((P3 - 1 - P2) downto 0) & Din; S23: Perform a loop count on the data shifting operation (shift counter shftcnt). If the packet synchronization flag P6 is valid, the shift counter is cleared each time the data valid flag is invalid for re-synchronization; otherwise, it is not cleared.
[0033] S24: When the shift counter value is 2P3 / P2, latch the data in the data register and store it in the data latch D. The depth of the data latch is the same as the cache bit width P3. S25: Count during the data input process (identification counter). Clear the counter when the shift counter value is 2P3 / P2; hold the data when it is equal to P3 / P2; otherwise, increment the count. After the identification counter is reset, the set value is P4.
[0034] S26: When the identification counter is less than P4, the signal valid identification C is valid; otherwise, it is invalid. The parameter P4 should be greater than the integer value of f0 / f1.
[0035] Furthermore, in step S3, use the system clock f1 to complete the synchronization of the input data, including the following steps: S31: Use the system clock to perform secondary synchronization on the data D and the valid identification C output in step S2.
[0036] S32: Perform edge parsing on the synchronized identification C to parse out the rising edge.
[0037] S33: Perform output latching on the synchronized data D at the rising edge. The data is synchronized with the system clock.
[0038] S34: Generate a signal valid identification for the output data. The identification is synchronized with the system clock and has a width of 1 system clock.
[0039] S35: Generate a timing counter based on the data detection period P5 and the system clock. When receiving the signal valid identification of the output data, clear the counter; otherwise, keep counting until it reaches the maximum value and then stop.
[0040] S36: Detect the value of the timing counter. If it is the maximum value, it means that no input data has been received within the set time range; otherwise, it means that there is data input.
[0041] Furthermore, in step S4, use the system clock f1 to complete the caching of the input data, including the following steps: S41: Use the system clock to write the data D1 and the valid identification C1 output in step S3 into the cache FIFO.
[0042] S42: Set the interrupt priority according to the data volume in the cache. When the data in the FIFO exceeds the length of one AOS frame data area, generate a low-priority request signal Pri0. When the data in the FIFO exceeds the length of two AOS frame data areas, generate a high-priority request signal Pri1. The AOS framing module completes the scheduling and framing according to the priority of each link.
[0043] Furthermore, the system clock and the accompanying clock should meet the following conditions: f1≥4*f0 / (P3 / P2) In this embodiment, the system clock is 40 MHz. The compliance analysis of the accompanying clock of each receiving link with the system clock is shown in Table 2 as follows: Table 2 Compliance Analysis of System Clock and Accompanying Clocks of Each Link Third Embodiment This embodiment provides a high-speed data receiving system for an on-board baseband device based on FPGA, which is used to execute the high-speed data receiving method of the on-board baseband device based on FPGA in the first embodiment. The system includes: A parameter configuration module 1, which, based on the fact that the on-board baseband device needs to receive high-speed data from different payload devices, and the interfaces of different payload devices are diverse and the data characteristics are different, performs parameter configuration for each receiving link of the on-board baseband device respectively; An accompanying clock synchronization and serial-parallel conversion module 2. A source synchronous interface is adopted between the on-board baseband device and the payload device. The source synchronous interface is accompanied by a co-frequency accompanying clock f0. The accompanying clock f0 is used to complete the synchronization and serial-parallel conversion of the input data, so as to utilize the characteristics of the accompanying clock f0 to perform preliminary processing on the data in the initial stage of data transmission and prepare for subsequent further processing; A system clock data synchronization module 3, which uses the system clock f1 to complete the synchronization of the input data and converts the input data into a form synchronized with the system clock f1 to improve the stability and reliability of data processing; A system clock data caching module 4, which uses the system clock f1 to complete the caching of the input data to avoid potential problems brought by the accompanying clock f0 and ensure that the data is stored in the cache safely and orderly.
[0044] A computer-readable storage medium stores computer code. When the computer code is executed, the above method is executed. Those of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory (ROM, Read Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disc, etc.
[0045] The above are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the concept of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements should also be regarded as within the protection scope of the present invention.
[0046] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.
[0047] It should be noted that the above embodiments can be freely combined as needed. The above are only the preferred embodiments of the present invention. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can also be made, and these improvements and refinements should also be regarded as within the protection scope of the present invention.
Claims
1. A high-speed data receiving method for a satellite-borne baseband device based on FPGA, characterized in that: The following steps are involved: S1: Based on the need for the onboard baseband device to receive high-speed data from different payload devices, and the interfaces of different payload devices are diverse and the data characteristics are different, parameter configuration is performed for each receiving link of the onboard baseband device respectively; S2: A source synchronous interface is used between the onboard baseband device and the payload device. The source synchronous interface is accompanied by a companion clock f0 of the same frequency. The companion clock f0 is used to complete the synchronization and serial-to-parallel conversion of the input data, so as to utilize the characteristics of the companion clock f0 to perform preliminary processing on the data at the initial stage of data transmission, in preparation for subsequent further processing; S3: using the system clock f1 to complete the synchronization of the input data, converting the input data into a form synchronized with the system clock f1 to improve the stability and reliability of data processing; S4: Use the system clock f1 to complete the caching of the input data to avoid potential problems caused by the companion clock f0 and ensure that the data is stored in the cache safely and orderly.
2. The high-speed data receiving method for satellite-borne baseband equipment based on FPGA according to claim 1, characterized in that: In step S1, parameter configuration is performed for each receiving link of the satellite-borne baseband device, and the parameters include: The sampling edge P1 of the accompanying clock f0, the input data bit width P2, the cache bit width P3, the signal valid mark width P4, the data detection period P5 and the packet synchronization mark P6; Among them, the sampling edge P1 is used to determine at which edge of the companion clock f0 to sample the input data, the input data bit width P2 represents the width of the input data, the cache bit width P3 determines the width of data storage in the cache, the signal valid identification width P4 is used to determine whether the data is valid, the data detection period P5 is used to detect whether the input data is received within a certain period of time, and the packet synchronization identifier P6 is used for synchronous processing of data to ensure correct reception and processing of data.
3. The high-speed data receiving method for satellite-borne baseband equipment based on FPGA according to claim 2, characterized in that: The data reception of the satellite-borne baseband device is implemented by FPGA, and the parameter setting of each high-speed data receiving link is implemented by any method including static setting and dynamic setting; It is recommended to use static settings for the input data bit width P2 and the cache bit width P3.
4. The high-speed data receiving method for satellite-borne baseband equipment based on FPGA according to claim 2, characterized in that: In step S2, the companion clock f0 is used to complete the synchronization and serial-to-parallel conversion of the input data, specifically: S21: sampling the input data according to the sampling edge P1, including a data gating F signal, which indicates whether the data is received. If there is no data gating F signal, it is set by default that all data is received; S22: performing data shifting at the data gating F according to the input data bit width P2 and the cache bit width P3, and temporarily storing the data in a data register, wherein the data register depth is the same as the cache bit width P3, wherein the input data bit width P2 and the cache bit width P3 are powers of 2, and the cache bit width P3 should be more than twice the input data bit width P2; S23: the data shift operation is cyclically counted using a shift counter. If the packet synchronization flag P6 is valid, the shift counter is cleared to zero each time the data gating F is invalid, and resynchronization is performed; Otherwise, it will not be cleared; S24: When the value of the shift counter is 2*the cache bit width P3 / the input data bit width P2, the data of the data register is latched and stored in the data latch D, and the depth of the data latch D is the same as the cache bit width P3; S25: during the data input process, the identification counter is used to count, and if the shift counter value is 2*the cache bit width P3 / the input data bit width P2, the counter is cleared; if the cache bit width P3 / the input data bit width P2, the data is kept; otherwise, the counting is incremented, and the identification counter is reset and set to the signal valid identification width P4; S26: When the flag counter is smaller than the signal valid flag width P4, the signal output valid flag C is set to be valid, otherwise it is invalid, wherein the signal valid flag width P4 should be larger than the integer value of f0 / f1.
5. The high-speed data receiving method for satellite-borne baseband equipment based on FPGA according to claim 4, characterized in that: In step S3, the input data is synchronized using the system clock f1, specifically: S31: using the system clock f1 to perform secondary synchronization on the data D outputted in step S2 and the signal output valid flag C; S32: performing edge analysis on the synchronized signal valid flag C to parse out the rising edge; S33: outputting and latching the synchronized data D1 at the rising edge, the data being synchronized with the system clock f1; S34: Generate a new signal valid flag C1 of the output data, which is synchronized with the system clock f1 and has a width of 1 system clock; S35: generating a timing counter according to the data detection cycle P5 and the system clock f1, and clearing the counter when the signal valid identification C1 of the received output data is valid, otherwise the counter keeps counting until the maximum value is reached, wherein the maximum value is generated by the data detection cycle P5; S36: Detect the value of the timing counter. If it is the maximum value, it means that no input data is received within the set time range. Otherwise, it means that data is input.
6. The high-speed data receiving method for satellite-borne baseband equipment based on FPGA according to claim 5, characterized in that: In step S4, the system clock f1 is used to complete the caching of the input data, specifically: S41: using the system clock f1 to write the data D1 and the valid flag C1 output in step S3 into a cache, which is generally a FIFO or a dual-port RAM; S42: Setting interrupt priority according to the amount of data in the cache, pending further data processing.
7. The high-speed data receiving method for satellite-borne baseband equipment based on FPGA according to claim 1, characterized in that: The system clock f1 and the companion clock f0 satisfy the following conditions: f1≥4*f0 / (P3 / P2).
8. A high-speed data receiving system for a satellite-borne baseband device based on FPGA for executing the high-speed data receiving method for a satellite-borne baseband device based on FPGA as claimed in any one of claims 1 to 7, characterized in that: include: A parameter configuration module, based on the need for the satellite-borne baseband device to receive high-speed data from different payload devices, and the different payload devices have diverse interfaces and different data characteristics, performs parameter configuration for each receiving link of the satellite-borne baseband device respectively; Accompanying clock synchronization and serial-to-parallel conversion module, a source synchronous interface is used between the onboard baseband device and the payload device, the source synchronous interface is accompanied by a companion clock f0 of the same frequency, and the companion clock f0 is used to complete the synchronization and serial-to-parallel conversion of the input data, so as to utilize the characteristics of the companion clock f0 to perform preliminary processing on the data in the initial stage of data transmission, in preparation for subsequent further processing; A system clock data synchronization module, which uses the system clock f1 to complete the synchronization of the input data and converts the input data into a form synchronized with the system clock f1 to improve the stability and reliability of data processing; The system clock data cache module uses the system clock f1 to complete the cache of the input data to avoid potential problems caused by the companion clock f0 and ensure that the data is stored in the cache safely and orderly.
9. A computer device comprising a memory and one or more processors, wherein the memory stores computer codes, and when the computer codes are executed by the one or more processors, the one or more processors execute the method according to any one of claims 1 to 7. 10 . A computer-readable storage medium storing a computer code. When the computer code is executed, the method according to claim 1 is executed.