Frequency Synchronization Method and System Based on Time Synchronization and Phase-Locked Loop

Abstract

The present invention relates to the field of wireless communication technologies, and discloses a frequency synchronization method and system based on time synchronization and a phase-locked loop. The method includes: acquiring a received signal and performing analog-to-digital conversion and down-conversion processing to generate a digital signal and performing frame synchronization, acquiring a valid digital signal, and inputting the valid digital signal into a phase-locked loop for frequency synchronization to generate a frequency deviation locked by the phase-locked loop and first correction data; performing phase ambiguity correction on the first correction data to generate second correction data and performing time synchronization to generate a plurality of optimal interpolation signals and interpolation resampling times; comparing the interpolation resampling times with the original clock time at the receiving end to calculate a carrier frequency deviation; and judging whether the phase-locked loop is mislocked by calculating the difference between the frequency deviation locked by the phase-locked loop and the carrier frequency deviation, so as to obtain an optimal interpolation signal or correct the optimal interpolation signal. The present invention improves the accuracy of frequency deviation estimation, and improves the frequency synchronization accuracy and robustness in a low signal-to-noise ratio environment.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and particularly to a frequency synchronization method and system based on time synchronization combined with a phase-locked loop. Background Art

[0002] In a wireless communication system, carrier frequency synchronization is a core technical link to ensure communication quality. Due to factors such as the physical characteristics difference of crystal oscillators at the transceiver end and the Doppler effect, carrier frequency offset generally exists in actual communication scenarios. Currently, the mainstream frequency synchronization technology usually uses the pilot method for frequency offset estimation and combines a phase-locked loop (PLL) for carrier phase tracking to achieve frequency synchronization. However, the pilot method not only occupies additional bandwidth resources, but also has unsatisfactory performance in estimating frequency deviation in a low signal-to-noise ratio environment. On the other hand, the phase-locked loop is greatly affected by noise. When performing frequency correction, its loop noise bandwidth B L needs to be balanced between suppressing noise and fast convergence. Under low signal-to-noise ratio conditions, if B L is set too large, the phase-locked loop is easily affected by noise and leads to unstable locking; if set too small, when the signal frequency deviation is large, it is difficult for the phase-locked loop to quickly pull into the locking range; in addition, even if a variable step size B L is set, it is still difficult to ensure that the phase-locked loop can be stably locked and continuously tracked under low signal-to-noise ratio conditions. Summary of the Invention

[0003] Aiming at the above deficiencies in the prior art, the present invention provides a frequency synchronization method and system based on time synchronization combined with a phase-locked loop, which is used to solve the problems that in the existing wireless communication system, using the pilot method for carrier synchronization results in occupying extra bandwidth resources, poor performance in estimating frequency deviation in a low signal-to-noise ratio environment, and the trade-off in setting the loop noise bandwidth B L of the phase-locked loop, which leads to unstable locking or difficulty in quickly pulling into the locking range when the frequency deviation is large.

[0004] To achieve the above invention objective, the technical solution adopted by the present invention is as follows:

[0005] A frequency synchronization method based on time synchronization combined with a phase-locked loop, comprising the following steps:

[0006] S1. Receive an intermediate frequency or radio frequency signal transmitted by a transmitting end, and perform analog-to-digital conversion and down-conversion processing to generate a digital signal;

[0007] S2. Based on the frame header of the frame structure, perform frame synchronization on the digital signal to receive a valid digital signal;

[0008] S3. Input the valid digital signal into a phase-locked loop for frequency synchronization, correct the valid digital signal with frequency offset, and generate a frequency deviation locked by the phase-locked loop and a first correction data;

[0009] S4. Correct the phase ambiguity of the first correction data based on the frame structure pilot to generate second correction data;

[0010] S5. Perform time synchronization on the second correction data to generate a number of optimal interpolation signals and interpolation resampling times;

[0011] S6. Compare the interpolation resampling time with the original clock time at the receiving end to obtain a clock accumulation error sequence, and calculate the clock frequency deviation between the transmitting end and the receiving end based on the clock accumulation error sequence;

[0012] S7. Calculate the carrier frequency deviation based on the clock frequency deviation between the transmitting end and the receiving end;

[0013] S8. Calculate the difference between the frequency deviation locked by the phase-locked loop and the carrier frequency deviation, and determine whether the difference is much larger than the set threshold. If so, the phase-locked loop is mislocked and step S9 is executed; otherwise, the optimal interpolation signal is output;

[0014] S9. Perform frequency deviation correction on the optimal interpolation signal to generate a corrected optimal interpolation signal.

[0015] A system applying the frequency synchronization method based on time synchronization combined with a phase-locked loop includes:

[0016] A signal receiving and processing module, configured to receive an intermediate frequency or radio frequency signal transmitted by a transmitting end, perform analog-to-digital conversion to generate a digital baseband signal, and then perform down-conversion processing on the digital baseband signal to generate a digitized signal;

[0017] A frame synchronization module, configured to receive the digitized signal and perform frame synchronization on the digitized signal by using the frame header of the frame structure to receive a valid digitized signal;

[0018] A phase-locked loop frequency synchronization module, configured to receive the valid digitized signal, input the valid digitized signal into the phase-locked loop for frequency synchronization, and generate a frequency deviation locked by the phase-locked loop and the first correction data by correcting the data with frequency offset;

[0019] A phase ambiguity correction module, configured to receive the first correction data and correct the phase ambiguity of the first correction data based on the pilot of the frame structure to generate second correction data;

[0020] A time synchronization module, configured to receive the second correction data and perform time synchronization to generate a number of optimal interpolation signals and interpolation resampling times;

[0021] A time offset estimation module, configured to receive the interpolation resampling time and the original clock time at the receiving end, compare them, and calculate the clock frequency deviation between the transmitting end and the receiving end by obtaining a clock accumulation error sequence;

[0022] A carrier frequency offset estimation module, which is used to receive the clock frequency deviation between the transmitter and the receiver and calculate the carrier frequency deviation;

[0023] A phase-locked loop false lock module, which is used to receive the carrier frequency deviation and the frequency deviation locked by the phase-locked loop, calculate the difference between the frequency deviation locked by the phase-locked loop and the carrier frequency deviation, judge whether the difference is much larger than the set threshold, if so, the phase-locked loop is falsely locked, and correct the frequency deviation of the best interpolation signal, otherwise, output the best interpolation signal.

[0024] The present invention has the following beneficial effects:

[0025] 1. The frequency synchronization method and system based on time synchronization combined with a phase-locked loop proposed by the present invention perform time synchronization calculation in the method, introduce a time synchronization module in the system, calculate the frequency deviation of the signal by obtaining the clock frequency deviation, and can obtain a relatively accurate frequency deviation estimation without using additional pilots, improving the frequency deviation estimation performance;

[0026] 2. The digital down-conversion technology is used to coarsely correct the frequency, so that the frequency offset of the received signal is reduced to a range where the PLL is easy to lock, and the loop noise bandwidth parameter B of the phase-locked loop is optimized L , and a relatively small loop noise bandwidth parameter B can be set L to reduce the influence of noise, thereby improving the frequency synchronization accuracy and robustness in a low signal-to-noise ratio environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic flow chart of the frequency synchronization method based on time synchronization combined with a phase-locked loop proposed by the present invention;

[0028] Figure 2 is a schematic diagram of the frame structure in the embodiment;

[0029] Figure 3 is a schematic diagram of the clock accumulation error sequence in the embodiment;

[0030] Figure 4 is a schematic diagram of the structure of the frequency synchronization system based on time synchronization combined with a phase-locked loop in the embodiment;

[0031] Figure 5 is a schematic diagram of the structure of the time synchronization module in the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0032] The specific embodiments of the present invention will be described below to facilitate those skilled in the art of this technology to understand the present invention. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art of this technology, as long as various changes are within the spirit and scope of the present invention defined and determined by the appended claims, these changes are obvious, and all inventions created using the concept of the present invention are within the scope of protection.

[0033] As Figure 1 shown, the frequency synchronization method based on time synchronization combined with a phase-locked loop includes the following steps S1 - S9:

[0034] S1. Receive the intermediate frequency or radio frequency signal transmitted by the transmitting end, and perform analog-to-digital conversion and down-conversion processing to generate a digital signal.

[0035] Specifically, step S1 specifically includes S11 - S12:

[0036] S11. Receive the intermediate frequency or radio frequency signal transmitted by the transmitting end, and perform analog-to-digital conversion to generate a digital baseband signal.

[0037] S12. Perform down-conversion processing on the digital baseband signal to generate a digital signal.

[0038] In this embodiment, the purpose of performing analog-to-digital conversion and down-conversion processing is to convert the received intermediate frequency or radio frequency signal into a digital signal to adapt to subsequent digital signal processing. Specifically, first, the analog signal is converted into a digital baseband signal through analog-to-digital conversion (ADC) for digital processing; subsequently, through down-conversion processing, the signal spectrum is shifted to the baseband, thereby reducing the signal processing complexity, reducing the computational burden, filtering out high-frequency noise interference, and improving the signal-to-noise ratio (SNR) of the signal. This processing process optimizes subsequent synchronization and other operations, enabling the system to efficiently and stably recover the original data and being applicable to wireless communication receiving systems in complex environments.

[0039] S2. Based on the frame header of the frame structure, perform frame synchronization on the digital signal to receive a valid digital signal.

[0040] Specifically, the frame header is composed of a sequence for frame synchronization, and the sequence length is S symbols.

[0041] In this embodiment, the frame header of the frame structure can adopt sequences such as Zadoff-Chu sequence, M sequence, Gold sequence, PN sequence, etc. to detect the synchronization signal and achieve frame synchronization.

[0042] Specifically, the frame structure further includes several data segments, each data segment having a length of D symbols. When performing frame synchronization, the receiving end uses the frame header to perform matching detection on the received digitized signal. If the frame header matches successfully, the current data stream is aligned to the start position of the frame. At the same time, the receiving end stores the data according to the frame structure to generate several valid digitized signals.

[0043] In this embodiment, the purpose of the receiving end storing data according to the frame structure is to ensure correct frame division, thereby generating several valid digitized signals. At the same time, in a wireless communication system, since the receiving end cannot determine whether a signal has arrived before receiving the signal, it is always in a receiving state to continuously perform signal capture, and perform signal data capture based on the form of the frame structure. The purpose is to eliminate invalid data and retain valid data (valid digitized signals). Invalid data is the random noise received before the valid data arrives at the receiving device, and valid data is the meaningful received signal data that conforms to the frame structure. Only valid data can be used for subsequent synchronization and demodulation operations.

[0044] The frame structure is as Figure 2 shown, including 1 frame header, 1 pilot, and several data segments. Among them, the frame header segment is composed of a sequence for frame synchronization, and the sequence length is S characters; the pilot, with a length of P characters, uses digital modulation signals such as BPSK and QPSK for subsequent steps to correct phase ambiguity; each data segment is a data payload, with a length of D characters, and it uses digital modulation signals such as BPSK and QPSK.

[0045] S3. Input the valid digitized signal into a phase-locked loop for frequency synchronization, and correct the valid digitized signal with frequency offset to generate the frequency deviation locked by the phase-locked loop and the first correction data.

[0046] S4. Based on the pilot of the frame structure, correct the phase ambiguity of the first correction data to generate the second correction data.

[0047] Specifically, the length of the pilot is P symbols.

[0048] In this embodiment, phase ambiguity is the phase distortion caused by frequency offset or clock error during the phase-locked loop (PLL) correction process, resulting in the inability to accurately recover the phase information of the received signal.

[0049] S5. Perform time synchronization on the second correction data to generate several optimal interpolation signals and interpolation resampling times.

[0050] Specifically, step S5 specifically includes S51 - S56:

[0051] S51. Perform resampling at the fractional interval level on the second correction data to generate the optimal interpolation signal, that is:

[0052]

[0053] Among them, represents the index of the resampled interpolation signal, represents the resampling period after interpolation, represents the index of the fixed sampling signal at the receiving end, represents the fixed sampling period at the receiving end, represents the impulse response of the interpolation filter, represents the optimal interpolation signal, represents the second correction data.

[0054] In this embodiment, the polyphase decomposition interpolation method based on the Farrow structure is adopted to perform fractional-interval resampling on the input second correction data signal to generate the optimal interpolation signal. Therefore, through this method, signals can be obtained at non-integer multiple time points, realizing more accurate timing adjustment, reducing timing errors and jitters caused by the mismatch between the fixed sampling period and the symbol period, thereby improving the accuracy and stability of timing synchronization and providing an optimized input signal for subsequent synchronization detection and error compensation.

[0055] S52. Based on the optimal interpolation signal, calculate the timing error signal according to the error characteristics of the resampled values of the adjacent symbol I / Q two paths, that is:

[0056]

[0057] Among them, represents the timing error signal of the th resampled interpolation signal, represents the th resampled interpolation signal's channel timing error signal, represents the th resampled interpolation signal's channel timing error signal, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's Road resampling value, Indicates the th resampling interpolation signal's road resampling value.

[0058] In this embodiment, the Gardner timing error detection method is adopted. Based on the optimal interpolation signal, according to the error characteristics of the resampling values of the adjacent symbol I / Q two paths, the timing error signal is calculated. As a non-data-aided timing synchronization method, the core principle of the Gardner timing error detection method is to dynamically estimate and correct the timing deviation through the signal change characteristics of the interpolation points between symbols. This method constructs an error signal by using the optimal sampling points of adjacent symbols and the interpolation signals of the intermediate points therebetween, and generates an error signal by multiplying the difference in amplitude change (slope) between the intermediate sampling point and the adjacent symbol. When the timing is advanced, the error is positive; when the timing is lagged, the error is negative; when the ideal synchronization is achieved, the error approaches zero. The error signal is filtered by a loop filter and then drives the interpolation controller to adjust the sampling phase, gradually eliminating the timing deviation.

[0059] S53. Smoothly filter the timing error signal and calculate the control word, that is:

[0060]

[0061] Wherein, , represents the filtering coefficient, represents the output term of the proportional path, , respectively represent the control words at the th, th moments.

[0062] In this embodiment, the timing error signal is smoothly filtered to reduce noise interference, and at the same time, the control word is calculated for subsequent calculation of the interpolation base point and the fractional interval.

[0063] S54. Calculate the interpolation base point and the fractional interval according to the control word, that is:

[0064]

[0065] Wherein, represents the counter value at the th moment, represents the counter value at the th moment, represents the modulo operation, represents the interpolation base point, represents the fractional interval.

[0066] In this embodiment, the interpolation base point is the integer symbol time at which the current interpolation sampling is located, and the fractional interval is the offset of the resampling point relative to the integer symbol time. Calculating the interpolation base point and the fractional interval can dynamically adjust the interpolation position, solving the problem of non-ideal synchronization between the sampling clock at the receiving end and the symbol clock at the sending end. The interpolation base point ensures the stability of the interpolation reference position, and the fractional interval provides fine-tuning ability. The combination of the two can accurately adjust the symbol timing, thereby ensuring the best interpolation resampling time and improving the synchronization accuracy.

[0067] S55. Calculate the interpolation resampling time according to the interpolation base point and the fractional interval, that is:

[0068]

[0069] Wherein, represents the interpolation resampling time.

[0070] S56. Based on the interpolation resampling time, repeatedly execute steps S51 - S55 until the second correction data is completely received, and obtain a number of optimal interpolation signals and interpolation resampling times.

[0071] S6. Compare the interpolation resampling time with the original clock time at the receiving end to obtain a clock accumulation error sequence, and calculate the clock frequency deviation between the transmitting end and the receiving end based on the clock accumulation error sequence.

[0072] Specifically, step S6 specifically includes S61 - S65:

[0073] S61. Compare the interpolation resampling time with the original clock time at the receiving end to obtain a clock accumulation error sequence, that is:

[0074]

[0075] Wherein, represents the clock accumulation error sequence of the th resampled interpolation signal, represents the original clock time at the receiving end of the th resampled interpolation signal, represents the interpolation resampling time of the th resampled interpolation signal.

[0076] In this embodiment, the clock accumulation error sequence is as Figure 3 shown. The abscissa is time, that is, the time taken for the signal to pass through time synchronization, and the ordinate is the clock accumulation error. The array composed of the time cumulative error is the clock cumulative error sequence.

[0077] S62. Randomly select two error data points at different times on the clock accumulated error sequence, define them as the first index point and the second index point, where the first index point is greater than the second index point, and calculate the mean value of the clock accumulated errors corresponding to the first index point and the second index point, that is:

[0078]

[0079] Among them, represents the mean value of the clock accumulated error, represents the operation of calculating the mean value, represents the second index point, represents the first index point, represents the index window interval between the first index point and the second index point.

[0080] In this embodiment, is the operation of calculating the mean value, that is, taking the mean value of a section of data, and this section of data contains multiple measured data points to reduce the influence of noise and improve the estimation accuracy.

[0081] S63. Calculate the actual time interval corresponding to the first index point and the second index point, that is:

[0082]

[0083] Among them, represents the actual time interval.

[0084] S64. According to the mean value of the clock accumulated errors corresponding to the first index point and the second index point, and the actual time interval corresponding to the first index point and the second index point, calculate the clock drift rate, that is:

[0085]

[0086] Among them, represents the clock drift rate.

[0087] S65. Based on the upsampling multiple and the sampling clock period of the receiving end, calculate the clock frequency deviation between the transmitting end and the receiving end, that is:

[0088]

[0089] Among them, represents the clock frequency deviation, represents the upsampling multiple.

[0090] S7. Based on the clock frequency deviation between the transmitting end and the receiving end, calculate the carrier frequency deviation.

[0091] In this embodiment, since in wireless communication, the carrier frequency is determined by the clock of the transmitting end Generated, so the clock frequency deviation will cause the carrier frequency deviation. Therefore, the formula for calculating the carrier frequency deviation is: , where represents the carrier frequency deviation, represents the carrier frequency, represents the clock at the transmitting end.

[0092] S8. Calculate the difference between the frequency deviation locked by the phase-locked loop and the carrier frequency deviation, and determine whether this difference is much larger than the set threshold. If so, the phase-locked loop is mislocked, and step S9 is executed; otherwise, the optimal interpolation signal is output.

[0093] In this embodiment, it is judged whether the phase-locked loop is unlocked according to the relative movement of the wireless communication transmitting and receiving end devices. The Doppler frequency offset range of ground mobile communication is about 0 Hz to 1000 Hz. If the frequency deviation locked by the phase-locked loop and the carrier frequency deviation The difference is much larger than 1000 Hz, it can be judged that the phase-locked loop is mislocked.

[0094] S9. Perform frequency deviation correction on the optimal interpolation signal to generate a corrected optimal interpolation signal.

[0095] Specifically, step S9 specifically includes S91 - S93:

[0096] S91. Use digital down-conversion method to correct the frequency offset of the optimal interpolation signal to obtain the coarse frequency offset correction data.

[0097] S92. Input the coarse frequency offset correction data into the phase-locked loop for frequency synchronization to obtain the fine frequency offset correction data.

[0098] S93. Perform phase ambiguity correction on the fine frequency offset correction data to generate a corrected optimal interpolation signal.

[0099] In this embodiment, first, digital down-conversion is used to perform coarse compensation on the large frequency offset, reducing the frequency offset pulling-in range of the subsequent phase-locked loop (PLL), thereby improving the frequency tracking accuracy; subsequently, the PLL further completes fine frequency offset correction to achieve high-precision frequency synchronization; finally, phase ambiguity correction is used to eliminate the possible fixed phase uncertainty in the carrier recovery process, ensuring the phase consistency of the received signal, thereby achieving correct demodulation. This hierarchical processing method makes full use of the multi-scale characteristics of frequency offset compensation. Compared with the traditional single-stage PLL method, at the same computational complexity, it can effectively expand the capture range of the initial frequency offset and improve the synchronization performance.

[0100] As Figure 4 shown, the system applying the frequency synchronization method based on time synchronization and phase-locked loop includes:

[0101] A signal receiving and processing module, which is used to receive the intermediate frequency or radio frequency signal transmitted by the transmitting end, perform analog-to-digital conversion to generate a digital baseband signal, and then perform down-conversion processing on the digital baseband signal to generate a digitalized signal.

[0102] A frame synchronization module, which is used to receive the digitalized signal and perform frame synchronization on the digitalized signal by using the frame header of the frame structure to receive the valid digitalized signal.

[0103] A phase-locked loop frequency synchronization module, which is used to receive the valid digitalized signal, input the valid digitalized signal into the phase-locked loop for frequency synchronization, and generate the frequency deviation locked by the phase-locked loop and the first correction data by correcting the data with frequency offset.

[0104] A phase ambiguity correction module, which is used to receive the first correction data and perform phase ambiguity correction on the first correction data based on the pilot of the frame structure to generate the second correction data.

[0105] A time synchronization module, which is used to receive the second correction data and perform time synchronization to generate a number of optimal interpolation signals and interpolation resampling times.

[0106] In this embodiment, the time synchronization module is as Figure 5 shown, and is a closed-loop system including an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator.

[0107] Among them, the interpolation filter uses the polyphase decomposition interpolation method based on the Farrow structure to perform resampling at the fractional interval level on the received second correction data to generate an optimal interpolation signal.

[0108] Among them, the timing error detector uses the Gardner timing error detection method to calculate the timing error signal based on the received optimal interpolation signal according to the error characteristics of the resampled values of the adjacent symbol I / Q two paths.

[0109] Among them, the function of the loop filter is to smooth the timing error signal , reduce noise interference; and in this embodiment, an ideal integral type loop filter is used to effectively track the phase and frequency offsets of the local clock relative to the transmitter symbol clock. The output of the loop filter is the control word for controlling the numerically controlled oscillator (NCO) , and its update relationship can be expressed as: , , represents the filtering coefficient of the loop filter, represents the output term of the proportional path, represents the control word of the numerically controlled oscillator.

[0110] Among them, the function of the numerically controlled oscillator is to generate a clock by overflow, that is, to determine the interpolation base point , and at the same time complete the fractional interval calculation to provide to the interpolation value filter for interpolation. The numerically controlled oscillator is a phase decrementer, and its difference equation is: ; where , , are all positive decimals; in addition, since the working period of the numerically controlled oscillator is , and the period of the interpolator is , is adjusted by the loop filter to make the numerically controlled oscillator overflow at the optimal sampling moment; when the loop reaches equilibrium, is approximately a constant. At this time, on average, every period, the register of the numerically controlled oscillator overflows once. At this time, the interpolation base point and the fractional interval are: , .

[0111] The time offset estimation module is used to receive the interpolation resampling moment and the original clock moment at the receiving end, compare them, and calculate the clock frequency deviation between the transmitting end and the receiving end by obtaining the clock accumulation error sequence.

[0112] The carrier frequency offset estimation module is used to receive the clock frequency deviation between the transmitting end and the receiving end and calculate the carrier frequency deviation.

[0113] The PLL false lock module is used to receive the carrier frequency deviation and the frequency deviation locked by the PLL, calculate the difference between the frequency deviation locked by the PLL and the carrier frequency deviation, and determine whether the difference is much larger than the set threshold. If so, the PLL is falsely locked and the frequency deviation of the optimal interpolation signal is corrected. Otherwise, the optimal interpolation signal is output.

[0114] In summary, for the frequency synchronization method and system based on time synchronization and PLL proposed by the present invention, first, time synchronization calculation is performed in the method, and a time synchronization module is introduced in the system. By obtaining the clock frequency deviation and then calculating the frequency deviation of the signal, a relatively accurate frequency deviation estimation can be obtained without using additional pilots; second, digital down-conversion technology is used to coarsely correct the frequency, so that the frequency offset of the received signal is reduced to a range where the PLL is easy to lock, and the loop noise bandwidth parameter B L of the PLL is optimized. The loop noise bandwidth parameter B L can be set to a smaller value to reduce the influence of noise, thereby improving the frequency synchronization accuracy and robustness in a low signal-to-noise ratio environment.

[0115] In the present invention, specific embodiments are used to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those of ordinary skill in the art, based on the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

[0116] Those of ordinary skill in the art will realize that the embodiments described herein are for helping the reader understand the principles of the present invention, and it should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of the present invention according to these technical revelations disclosed by the present invention, and these deformations and combinations are still within the protection scope of the present invention.

Claims

1. A frequency synchronization method based on time synchronization combined with a phase-locked loop, characterized in that, It includes the following steps: S1. Receive the intermediate frequency or radio frequency signal transmitted by the transmitting end, and perform analog-to-digital conversion and down-conversion processing to generate a digital signal; S2. Based on the frame header of the frame structure, perform frame synchronization on the digital signal to receive the valid digital signal; S3. Input the valid digital signal into the phase-locked loop for frequency synchronization, correct the valid digital signal with frequency offset, and generate the frequency offset locked by the phase-locked loop and the first correction data; S4. Based on the pilot of the frame structure, correct the phase ambiguity of the first correction data to generate the second correction data; S5. Perform time synchronization on the second correction data to generate a number of optimal interpolation signals and interpolation resampling moments; S6. Compare the interpolation resampling moment with the original clock moment of the receiving end to obtain the clock accumulation error sequence, and based on the clock accumulation error sequence, calculate the clock frequency deviation between the transmitting end and the receiving end; S7. Calculate the carrier frequency deviation based on the clock frequency deviation between the transmitting end and the receiving end; S8. Calculate the difference between the frequency deviation locked by the phase-locked loop and the carrier frequency deviation, and determine whether the difference is much larger than the set threshold. If so, the phase-locked loop is mislocked and step S9 is executed. Otherwise, output the optimal interpolation signal; S9. Perform frequency deviation correction on the optimal interpolation signal to generate the corrected optimal interpolation signal.

2. The frequency synchronization method based on time synchronization combined with a phase-locked loop according to claim 1, wherein The frame header is composed of a sequence for frame synchronization, and the sequence length is S symbols.

3. The frequency synchronization method based on time synchronization combined with a phase-locked loop according to claim 2, wherein The frame structure also includes a number of data segments, each data segment has a length of D symbols. When performing frame synchronization, the receiving end uses the frame header to perform matching detection on the received digital signal. If the frame header matches successfully, the current data stream is aligned to the starting position of the frame. At the same time, the receiving end stores the data according to the frame structure to generate a number of valid digital signals.

4. The frequency synchronization method based on time synchronization combined with a phase-locked loop according to claim 1, wherein The length of the pilot is P symbols.

5. The frequency synchronization method based on time synchronization combined with a phase-locked loop according to claim 1, characterized in that Step S5 specifically includes: S51. Perform resampling at the fractional interval level on the second correction data to generate the optimal interpolation signal, that is: Among them, represents the index of the resampled interpolation signal, represents the resampling period after interpolation, represents the index of the fixed sampling signal at the receiving end, represents the fixed sampling period at the receiving end, represents the impulse response of the interpolation filter, represents the optimal interpolation signal, represents the second correction data; S52. Based on the optimal interpolation signal, calculate the timing error signal according to the error characteristics of the resampled values of the adjacent symbol I / Q two paths, that is: Among them, represents the timing error signal of the th resampled interpolation signal, represents the th resampled interpolation signal's channel timing error signal, represents the th resampled interpolation signal's channel timing error signal, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value, represents the th resampled interpolation signal's channel resampled value; S53. Smoothly filter the timing error signal and calculate the control word, that is: Among them, , represent filter coefficients, represents the output term of the proportional path, , respectively represent the control words at the -th and -th moments; S54. Calculate the interpolation base point and the fractional interval according to the control word, that is: Among them, represents the counter value at the moment, represents the counter value at the moment, represents the modulo operation, represents the interpolation base point, represents the fractional interval; S55. Calculate the interpolation resampling moment according to the interpolation base point and the fractional interval, that is: Among them, represents the interpolation resampling moment; S56. Based on the interpolation resampling moment, repeat steps S51 - S55 until the second correction data is completely received, and obtain a number of optimal interpolation signals and interpolation resampling moments.

6. The frequency synchronization method based on time synchronization combined with a phase-locked loop according to claim 5, characterized in that Step S6 specifically includes: S61. Compare the interpolation resampling moment with the original clock moment of the receiving end to obtain the clock accumulation error sequence, that is: Among them, represents the clock accumulation error sequence of the th resampled interpolation signal, represents the original clock moment at the receiving end of the th resampled interpolation signal, represents the interpolation resampling moment of the th resampled interpolation signal; S62. Arbitrarily select two different moment error data points on the clock accumulation error sequence, define them as the first index point and the second index point, and the first index point is greater than the second index point, and calculate the clock accumulation error mean corresponding to the first index point and the second index point, that is: Among them, represents the mean of clock accumulation errors, represents taking the mean, represents the second index point, represents the first index point, represents the index window interval between the first index point and the second index point; S63. Calculate the actual time interval corresponding to the first index point and the second index point, that is: Among them, represents the actual time interval; S64. Calculate the clock drift rate based on the average clock accumulation error corresponding to the first index point and the second index point, and the actual time interval corresponding to the first index point and the second index point, i.e.: wherein, represents the clock drift rate; S65. Calculate the clock frequency deviation between the transmitter and the receiver based on the upsampling multiple and the sampling clock period of the receiver, i.e.: Among them, represents the clock frequency deviation, represents the upsampling multiple.

7. The frequency synchronization method based on time synchronization combined with a phase-locked loop according to claim 6, wherein The calculation formula for the carrier frequency deviation is: Among them, represents the carrier frequency deviation, represents the carrier frequency, represents the clock at the transmitting end.

8. The frequency synchronization method based on time synchronization combined with a phase-locked loop according to claim 1, wherein Step S9 specifically includes: S91. Use the digital down-conversion method to correct the frequency offset of the optimal interpolation signal to obtain the coarse frequency offset correction data; S92. Input the coarse frequency offset correction data into the phase-locked loop for frequency synchronization to obtain the fine frequency offset correction data; S93. Perform phase ambiguity correction on the fine frequency offset correction data to generate the corrected optimal interpolation signal.

9. A frequency synchronization system based on time synchronization combined with a phase-locked loop, characterized in that, Applied to the frequency synchronization method based on time synchronization and phase-locked loop as described in any one of claims 1-8, including: A signal receiving and processing module, configured to receive the intermediate frequency or radio frequency signal transmitted by the transmitter, perform analog-to-digital conversion to generate a digital baseband signal, and then perform down-conversion processing on the digital baseband signal to generate a digitized signal; A frame synchronization module, configured to receive the digitized signal and perform frame synchronization on the digitized signal using the frame header of the frame structure to receive the valid digitized signal; A phase-locked loop frequency synchronization module, configured to receive the valid digitized signal, input the valid digitized signal into the phase-locked loop for frequency synchronization, and correct the data with frequency offset to generate the frequency deviation locked by the phase-locked loop and the first correction data; A phase ambiguity correction module, configured to receive the first correction data and perform phase ambiguity correction on the first correction data based on the pilot of the frame structure to generate the second correction data; A time synchronization module, configured to receive the second correction data and perform time synchronization to generate a plurality of optimal interpolation signals and interpolation resampling times; A time offset estimation module, configured to receive the interpolation resampling time and the original clock time of the receiver, compare them, and calculate the clock frequency deviation between the transmitter and the receiver by obtaining the clock accumulation error sequence; A carrier frequency offset estimation module, configured to receive the clock frequency deviation between the transmitter and the receiver and calculate the carrier frequency deviation; A phase-locked loop false lock module, configured to receive the carrier frequency deviation and the frequency deviation locked by the phase-locked loop, calculate the difference between the frequency deviation locked by the phase-locked loop and the carrier frequency deviation, and determine whether the difference is much larger than the set threshold. If so, the phase-locked loop is falsely locked and the frequency deviation of the optimal interpolation signal is corrected. Otherwise, the optimal interpolation signal is output.

10. The frequency synchronization system based on time synchronization combined with a phase-locked loop according to claim 9, characterized in that, The time synchronization module includes an interpolation filter, a timing error detector, a loop filter, and a numerically controlled oscillator; The interpolation filter is configured to receive the second correction data and perform resampling at the fractional interval level on the second correction data to generate the optimal interpolation signal; The timing error detector is configured to receive the optimal interpolation signal and calculate the timing error signal according to the error characteristics of the resampled values of the adjacent symbol I / Q two paths; The loop filter is configured to receive the timing error signal, perform smoothing filtering on the timing error signal, and calculate the control word at the same time; The numerically controlled oscillator is configured to receive the control word and calculate the interpolation base point and the fractional interval.

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