On-site ring bus debugging message transmission mechanism for ASCII (American Standard Code for Information Interchange) code structure

Abstract

The invention discloses a field ring bus debugging message transmission mechanism aiming at an ASCII code structure, which is characterized in that an FPGA (Field Programmable Gate Array) is used for carrying out data real-time receiving, insertion and CRC (Cyclic Redundancy Check) calculation, firstly, after a slave station receives a data message of an ASCII code command sent by a master station, a data detection insertion module of the slave station uses FIFO (First In First Out) as a cache, analyzes an information starting position of the slave station, finds a corresponding node command, and sends the data message to the master station; performing data detection and replacement, and completing real-time insertion of feedback data; then, performing real-time CRC calculation on the detected and inserted data by using a double-CRC check mode; and the data for updating the CRC result is forwarded to the next slave station. According to the invention, the content-changeable FIFO is used as a cache, so that the data forwarding delay can be reduced while the data replacement is completed; and meanwhile, a double-CRC check mode is used, so that the influence of symbol error detection on CRC calculation can be avoided, and time delay introduced by data cascade processing is avoided.

Description

Technical Field

[0001] The present invention belongs to the fields of control and interface bus, and particularly relates to a field ring bus debugging message transmission mechanism for ASCII code structures. Background Art

[0002] The transmission of field ring bus data messages is mostly used for communication between the controller and the servo driver in a numerical control system. Among them, the ring topology structure is a field bus network with a master-slave structure, which has the characteristics of less wiring and simple structure. As Figure 1 shown, the master station sends data messages to each slave station, packs the data information of each slave station into data packets according to certain rules (as Figure 2 shown), and sends them to the ring transmission path. In the ring network, when the data packet passes by each slave station, each slave station only accepts the data belonging to this station, inserts the data that needs to be fed back into the response position, and then forwards the data to the next station. The data packet passes through each slave station in the ring transmission path and finally returns to the master station, and the master station thus obtains the feedback information of each slave station.

[0003] In the publication number CN 101630997A, the slave station receives the binary frame structure through the FPGA, parses and detects the current slave station information in real time. While reading the corresponding information of this station, the information that needs to be uploaded by this station is inserted and forwarded. While forwarding the data, the slave station calculates the CRC, and replaces the original CRC value with the latest calculated CRC result at the end of the frame, thus completing the information reception and transmission of the slave station.

[0004] As Figure 3 shown, after the 2nd slave station receives the information sent by the previous station, if the information does not belong to this station, it is directly forwarded; if it belongs to this station, the information that needs to be sent by this station is inserted and forwarded while receiving. Since the information of the 2nd slave station in the forwarded information has been updated, the CRC value in the frame information also needs to be updated. The 2nd slave station calculates the local CRC while forwarding the data, and after completing all data forwarding, uses the updated CRC result to replace the original CRC result and places it at the end of the frame for transmission.

[0005] Figure 3 In, the second line is the forwarded data, and the data of the 2nd slave station and the CRC result in the dotted box are the updated data when passing through the 2nd station. In order to calculate the CRC result after forwarding in real time, a CRC calculation module is required to calculate the data in real time during the forwarding process.

[0006] In the master's thesis "Research on Field Bus Technology of Numerical Control System Based on FPGA", a field ring bus frame structure is designed, which is represented in binary form, as shown in Table 1, Table 2, and Table 3. Table 1 is the downlink broadcast frame, Table 2 is the uplink feedback frame, and Table 3 is the frame type definition.

[0007]

[0008] Note: The reserved bytes are initialized as the target site number and are retained during normal operation.

[0009] Table 1

[0010]

[0011] Note: The reserved bytes are initialized as the target site number and are retained during normal operation.

[0012] Table 2

[0013]

[0014] Table 3

[0015] This binary frame structure can be transmitted compactly, improving the bus utilization efficiency and reducing latency. However, during debugging, the binary formats of the transmitted frame and the feedback frame are not convenient for visual inspection and need to be parsed before analysis. Summary of the Invention

[0016] Aiming at the deficiencies in the prior art, the purpose of the present invention is to propose an ASCII code frame structure representation method for the on-site ring bus, so as to more intuitively represent various command and feedback information situations during the debugging stage and achieve low-latency reception and forwarding based on the ASCII frame structure.

[0017] To achieve the above object, the present invention proposes a debugging message transmission mechanism for the on-site ring bus with an ASCII code structure and adopts the following technical solutions:

[0018] A debugging message transmission mechanism for the on-site ring bus with an ASCII code structure, where the slave station uses an FPGA to perform real-time data reception, insertion, and CRC calculation, including the following steps:

[0019] Step 1: The master station sends a data message with an ASCⅡ code structure to the slave station;

[0020] Step 2: After receiving the data message sent by the master station, the slave station parses the starting position of the slave station information, locates the target command, performs data type detection and data information replacement, and replaces the target command sequence with feedback data;

[0021] Step 3: For the replaced data message, perform real-time CRC calculation using the double CRC check method and update the CRC check value;

[0022] Step 4: The current slave station forwards the data message with the updated check value to the next slave station through the on-site ring bus.

[0023] Further, the reception feedback of data is completed by the data reception feedback system, which includes a data detection and insertion module and a dual CRC check module; the data is input into the data detection and insertion module and the dual CRC check module simultaneously; the data detection and insertion module uses a FIFO as a storage register, parses the starting position of the slave information, performs data type detection and data information replacement, and requests the dual CRC check module to synchronously update the check value after the replacement is completed; the dual CRC check module uses the dual CRC check method to perform real-time CRC calculation on the detected and replaced data, and outputs the calculated and updated check value to the data detection and insertion module upon request.

[0024] Further, the data detection and insertion module uses a FIFO as a storage register. The FIFO storage register manages the writing and reading of input data through a write pointer wp and a read pointer rp. The frequencies of the input data and the read-out data are the same; after detecting the target command sequence, it is replaced with feedback data in real time, and at the same time, the position of the write pointer wp is updated to the next position after the end of the inserted feedback data; the FIFO storage register includes an empty signal, a full signal, and a wait signal, and controls the external reading operation through the wait signal;

[0025] The specific process of reading, writing, and caching data in the FIFO storage register is as follows:

[0026] Step 1: Define the depth and bit width of the used FIFO storage register;

[0027] Step 2: Initialize the state of the FIFO storage register. The write pointer wp and the read pointer rp are equal, and the empty signal is pulled high, indicating that the current FIFO is empty;

[0028] Step 3: For each symbol written, store the symbol in the position pointed to by the write pointer wp in the FIFO storage register, and update the write pointer wp == wp + 1, and at the same time pull down the empty signal; the writing of data and the reading of data are synchronized, and the update speeds of the write pointer wp and the read pointer rp are the same;

[0029] Step 4: Determine whether the data in the current FIFO storage register is equal to the predefined command type identifier to determine the command type; further determine whether the data at the current position is equal to the predefined slave identifier to determine the starting position of the current slave information;

[0030] Step 5: After detecting the information header of the current slave station, perform detection and replacement processing. Sequentially detect the sequences that partially match the target command sequence. When the effective data length in the FIFO storage register is less than the length of the target command sequence, raise the wait signal to pause the external reading. If an input that does not match the target command sequence is detected, lower the wait signal to allow continuous reading. If the target command sequence is detected, complete the replacement, and at the same time update the wp position to the next position after the end of the inserted feedback data, and lower the wait signal.

[0031] Furthermore, the dual CRC check module adopts the dual CRC check method and consists of two calculation units, CRC0 and CRC1. The two calculation units work simultaneously and dynamically configure each other's states according to the detection situation. The specific operation process is as follows:

[0032] S1: Initialize the states of CRC0 and CRC1 to 0. CRC0 and CRC1 synchronously receive the input data. CRC0 performs real-time replacement calculation and output, while CRC1 synchronously calculates the input data without updating the external state.

[0033] S2: After detecting the target command sequence, CRC0 performs real-time replacement input calculation and updates the current state of CRC0 according to the calculation result. After CRC1 synchronously completes the calculation of the target command sequence and when the next symbol is input, it updates the current state of CRC1 using the current state of CRC0.

[0034] S3: If an input that does not match the target command sequence is detected, update the current state of CRC0 using the current state of CRC1, and then perform the CRC calculation of the current input.

[0035] S4: Input the CRC check value updated by CRC0 calculation into the data detection and insertion module.

[0036] Furthermore, the depth of the FIFO storage register needs to be determined according to the maximum length of the feedback data replaced and inserted in the system command and the data type length to ensure that the data already read during data detection will not be overwritten by the subsequent written data.

[0037] Furthermore, when the lengths of the target command sequence and the corresponding feedback data replaced and inserted are inconsistent, adjust the write pointer (wp) according to the length of the feedback data replaced and inserted, pointing to the last symbol position after replacement or the next position thereof.

[0038] Furthermore, when the data input to the FIFO storage register ends with a specific symbol such as "#", the subsequent written data is replaced using the output result of the dual CRC check module.

[0039] Furthermore, the working clock frequency of the dual CRC check module is higher than the input data rate. When the length of the replaced and inserted feedback data is longer than the length of the target symbol sequence, the CRC calculation corresponding to the replaced and inserted feedback data needs to be completed within the time corresponding to the length of the target symbol sequence.

[0040] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0041] The present invention uses a FIFO with changeable content as a storage register, which can reduce the delay of data forwarding while completing data replacement; uses a dual CRC check method, which can avoid the influence of symbol error detection on CRC calculation, so there is no special requirement for the command transmission order and the flexibility is higher; and uses a dual CRC check method, which can perform CRC check calculation while receiving data and performing data replacement, avoiding the delay introduced by data cascade processing. Description of the Drawings

[0042] Figure 1 is the on-site ring bus structure in the prior art;

[0043] Figure 2 is a schematic diagram of the data packaging method of each slave station;

[0044] Figure 3 is a schematic diagram of the method for a slave station to receive and insert data processing in the prior art;

[0045] Figure 4 is the structure of the data reception feedback system in the present invention;

[0046] Figure 5 is a schematic diagram of the FIFO read and write process in the present invention;

[0047] Figure 6 is a schematic diagram of the execution process of the FIFO cache to change data in the present invention;

[0048] Figure 7 is the structure of the dual CRC check module in the present invention;

[0049] Figure 8 is a schematic diagram of the calculation input and status update in the dual CRC check process. Detailed Embodiments

[0050] The technical solutions of the present invention will be further described in detail below in conjunction with the drawings and specific embodiments.

[0051] A field ring bus debugging message transmission mechanism for the ASCII code structure, where the slave station uses an FPGA to perform real-time data reception, insertion, and CRC calculation, including the following steps:

[0052] Step 1, the master station sends a data message with an ASCII code structure to the slave station;

[0053] Step 2: After receiving the data packet sent by the master station, the slave station parses the starting position of the slave station information, locates the target command, performs data type detection and data information replacement, and replaces the target command sequence with feedback data;

[0054] Step 3: For the replaced data packet, perform real-time CRC calculation using the double CRC check method and update the CRC check value;

[0055] Step 4: The current slave station forwards the data packet with the updated check value to the next slave station through the field ring bus.

[0056] Embodiment

[0057] The ASCII code structure of the downlink broadcast frame sent by the master station is shown in Table 4, and the ASCII code structure of the broadcast frame feedback information is shown in Table 5.

[0058]

[0059] Table 4

[0060]

[0061] Table 5

[0062] The master station sends the downlink broadcast frame information with the ASCII code structure shown in Table 4, including the start symbol, type, slave node number, control command, and command parameters. After receiving the broadcast information, the slave station SUBS_0 replaces "STATE" with "READY", updates the CRC check value, and forwards it to the next slave station, that is, the master station sends the command:

[0063] $BRD_FRM,SUBS_0,STATE,,SUBS_1,STATE,,SUBS_2,STATE,,#70AE042C;

[0064] Slave station feedback information:

[0065] $BRD_FRM,SUBS_0,READY,,SUBS_1,STATE,,SUBS_2,STATE,,#EC72E568.

[0066] As Figure 4 shown, the reception feedback of the data is completed by the data reception feedback system, and the data reception feedback system includes a data detection and insertion module and a double CRC check module; the data is input into the data detection and insertion module and the double CRC check module simultaneously.

[0067] As Figure 5 and 6As shown, the data detection and insertion module uses a FIFO storage register as a cache to complete input data type detection and data information replacement; the FIFO storage register manages the writing and reading of input data through a write pointer wp and a read pointer rp, and the frequencies of the input data and the read-out data are the same; after detecting the target command sequence, it is replaced with feedback data in real time, and at the same time, the wp position is updated to the next position after the end of the replacement and insertion data; the FIFO storage register includes an empty signal, a full signal, and a wait signal, and controls external reading operations through the wait signal.

[0068] The specific process of reading, writing, and caching data in the FIFO storage register is as follows:

[0069] Step 1: Define reg[7:0] fifo_cell[0:31] as the FIFO storage register, which contains 32 storage units, and the bit width of each unit is 8; initialize the FIFO status, make the write pointer wp and the read pointer rp equal, and raise the empty signal to indicate that the current FIFO is empty.

[0070] Step 2: Store each written symbol into fifo_cell[wp], and update the write pointer wp == wp + 1, while lowering the empty signal; the writing of data and the reading of data are synchronized, and the update speeds of the write pointer wp and the read pointer rp are the same.

[0071] Step 3: Determine the command type by judging whether {fifo_cell[wp - 7], fifo_cell[wp - 6], fifo_cell[wp - 5], fifo_cell[wp - 4], fifo_cell[wp - 3], fifo_cell[wp - 2], fifo_cell[wp - 1]} is equal to the predefined command type identifier "BRD_FRM"; determine the start position of the current slave information by judging whether {fifo_cell[wp - 6], fifo_cell[wp - 5], fifo_cell[wp - 4], fifo_cell[wp - 3], fifo_cell[wp - 2], fifo_cell[wp - 1]} is equal to the predefined slave information identifier "SUBS_0".

[0072] Step 4: After detecting the information header of the current slave station, perform detection and replacement processing. Sequentially detect the sequences that match the "STATE" part of the target command sequence: "S", "ST", "STA", "STAT"; if the valid data in the current FIFO is less than 5, raise the wait signal to pause external reading; if a complete matching sequence "STATE" is detected, replace the data in the FIFO from the starting position of the target command sequence to the current write pointer wp with "READY", update the write pointer wp, and at the same time lower the wait signal to allow external to continue reading data.

[0073] As Figure 7 shown, the dual CRC check module adopts the dual CRC check method and consists of two calculation units, CRC0 and CRC1. The two calculation units work simultaneously and dynamically configure each other's initial states according to the detection situation. The specific operation process is as follows:

[0074] S1: Initialize the states of CRC0 and CRC1 to 0. CRC0 and CRC1 synchronously receive input data; CRC0 replaces and calculates in real time and outputs, while CRC1 synchronously calculates the input data but does not update the external state;

[0075] S2: After entering the command sequence of the current slave station, start to detect the partial matching sequences "S", "ST", "STA", "STAT"; if the current input is detected as "S", replace the current input with "R"; if the current input is detected as "T" and the previous input symbol is "S", replace the current input with "E"; if the current input is detected as "A" and the previous input symbols are "ST", replace the current input with "A"; and so on, until the complete matching target command sequence "STATE" is detected. CRC0 replaces "STATE" with "READY" for calculation and updates the CRC0 state according to the calculation result; after CRC1 synchronously completes the calculation of the target command sequence "STATE" and when the next symbol is input, use the current state of CRC0 to update the current state of CRC1;

[0076] S3: If the input data does not match the target command sequence "STATE", use the current state of CRC1 to update the current state of CRC0, and then perform the CRC calculation of the current input.

[0077] The specific data input and CRC state update process is as Figure 8As shown, CRC0 immediately performs replacement calculation when detecting the first "S". When the subsequent input symbol is not "T", it uses the calculation state of CRC1 to update the calculation state of CRC0 and performs CRC calculation on the input "A". When CRC0 continuously detects "STATE", it performs input replacement calculation. After CRC1 completes the complete calculation of "STATE" synchronously, it uses the calculation state of CRC0 to update the calculation state of CRC1.

[0078] CRC0 and CRC1 alternately correct the state through state update to complete the real-time calculation of CRC. This structure can ignore the out-of-order problem in the command and abnormal input situations with similar symbols.

[0079] Finally, the CRC check value updated by the calculation of CRC0 is input into the data detection and insertion module, placed at the end of the replaced data packet, and forwarded to the next slave station through the field ring bus.

[0080] The above is only a preferred specific embodiment of the present invention and is not used to limit the present invention. Any modification, equivalent replacement, improvement, etc. made by those skilled in the art within the technical scope disclosed by the present invention according to the technical solution and inventive concept of the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A field ring bus debugging message transmission mechanism for an ASCII code structure, in which the slave station uses FPGA to perform real-time data reception, insertion and CRC calculation, including the following steps: Step 1: The master station sends a data message with an ASCII code structure to the slave station; Step 2: After receiving the data message sent by the master station, the slave station parses the starting position of the slave station information, locates the target command, performs data type detection and data information replacement, and replaces the target command sequence with feedback data; Step 3: For the replaced data message, use the double CRC check method to perform real-time CRC calculation and update the CRC check value; Step 4: The current slave station forwards the data message with the updated CRC check value to the next slave station via the field ring bus.

2. A field ring bus debugging message transmission mechanism for an ASCII code structure according to claim 1, characterized in that: The data receiving feedback is completed by the data receiving feedback system, which includes a data detection insertion module and a double CRC check module; the data is simultaneously input into the data detection insertion module and the double CRC check module; The data detection insertion module uses FIFO as a storage register, analyzes the starting position of the slave station information, performs data type detection and data information replacement, and requests the dual CRC check module to synchronously update the check value after the replacement is completed; The double CRC check module uses the double CRC check method to perform real-time CRC calculation on the detected and replaced data, and outputs the calculated updated check value to the data detection insertion module upon request.

3. A field ring bus debugging message transmission mechanism for ASCII code structure according to claim 2, characterized in that: The data detection insertion module uses FIFO as a storage register. The FIFO storage register manages the writing and reading of input data through the write pointer wp and the read pointer rp. The frequency of input data is the same as that of read data. After detecting the target command sequence, it is replaced with feedback data in real time, and the write pointer wp position is updated to the next position at the end of the inserted feedback data. The FIFO storage register contains empty signal, full signal and wait signal, and the external read operation is controlled by the wait signal. The specific process of reading, writing and caching data in the FIFO storage register is as follows: Step 1: Define the depth and bit width of the FIFO storage register used; Step 2: Initialize the state of the FIFO storage register, the write pointer wp and the read pointer rp are equal, and the empty signal is pulled high, indicating that the current FIFO is empty; Step 3: Each time a symbol is written, the symbol is stored in the position pointed to by the write pointer wp in the FIFO storage register, and the write pointer wp==wp+1 is updated, and the empty signal is pulled low at the same time; Writing data is done synchronously with reading data, and the update speed of the write pointer wp and the read pointer rp is consistent; Step 4: determine whether the data in the current FIFO storage register is equal to the predefined command type identifier, and determine the command type; then determine whether the current position data is equal to the predefined slave station identifier, and determine the starting position of the current slave station information; Step 5. After the information header of the current slave station is detected, the detection and replacement processing is performed. The sequences that partially match the target command sequence are detected in turn. When the effective data length in the FIFO storage register is less than the target command sequence length, the wait signal is pulled high to suspend external reading; if an input that does not match the target command sequence is detected, the wait signal is pulled low to allow continued reading; if the target command sequence is detected, the replacement is completed, and the wp position is updated to the next position at the end of the inserted feedback data, and the wait signal is pulled low.

4. A field ring bus debugging message transmission mechanism for ASCII code structure according to claim 3, characterized in that: The dual CRC check module adopts a dual CRC check method, which consists of two calculation units, CRC0 and CRC1. The two calculation units work simultaneously and dynamically configure each other's status according to the detection situation. The specific operation process is as follows: S1. Initialize the states of CRC0 and CRC1 to 0. CRC0 and CRC1 receive input data synchronously. CRC0 replaces calculation and outputs in real time. CRC1 calculates synchronous input data but does not update external state. S2. After detecting the target command sequence, CRC0 performs real-time replacement input calculation and updates the current state of CRC0 according to the calculation result; After CRC1 synchronously completes the target command sequence calculation and the next symbol is input, the current state of CRC0 is used to update the current state of CRC1; S3, when an input that does not match the target command sequence is detected, the current state of CRC0 is updated using the current state of CRC1, and then the CRC calculation of the current input is performed; S4. Input the updated CRC check value calculated by CRC0 into the data detection insertion module.

5. A field ring bus debugging message transmission mechanism for ASCII code structure according to claim 4, characterized in that: The depth of the FIFO storage register is determined by the maximum length of the feedback data replaced and inserted in the system command and the data type length.

6. A field ring bus debugging message transmission mechanism for ASCII code structure according to any one of claims 3 to 5, characterized in that: When the target command sequence is inconsistent with the corresponding replacement inserted feedback data length, the write pointer wp is adjusted according to the replacement inserted feedback data length to point to the last symbol position after replacement or its next position.

7. A field ring bus debugging message transmission mechanism for ASCII code structure according to claim 6, characterized in that: When the data input to the FIFO storage register ends with a specific symbol such as "#", the subsequent written data is replaced with the output result of the double CRC check module.

8. A field ring bus debugging message transmission mechanism for ASCII code structure according to claim 7, characterized in that: The working clock frequency of the dual CRC check module is higher than the input data rate. When the length of the replaced feedback data is longer than the target symbol sequence length, the CRC calculation corresponding to the replaced feedback data must be completed within the time corresponding to the target symbol sequence length.

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