Frequency offset estimation method and apparatus, storage medium, communication device, and chip

Abstract

The application discloses a frequency offset estimation method and device, a storage medium, a communication device and a chip, and relates to the technical field of communication. The method comprises the following steps: firstly, performing differential frequency offset estimation based on a primary synchronization signal and a secondary synchronization signal to obtain a primary-secondary differential frequency offset; then, correcting the primary-secondary differential frequency offset by using a half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value; finally, determining a target frequency offset estimation value according to the target correction value and a frequency correction frequency offset corresponding to the primary synchronization signal. The target frequency offset estimation value is determined based on the frequency correction value and the frequency correction frequency offset, broadcast messages are read by using a single branch, the frequency offset does not need to be determined by using a multi-branch attempt, the complexity of signal processing of a terminal device is reduced, and the influence on the performance of the terminal device is reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of communication, and particularly relates to a frequency offset estimation method and device, a storage medium, a communication device and a chip. BACKGROUND

[0002] Terminal devices generally use a low-cost digitally compensated crystal oscillator (DCXO) to provide a clock source. In order to alleviate the problem of large frequency error of the DCXO, an additional frequency offset estimation is usually introduced in baseband processing. SUMMARY

[0003] The present disclosure provides a frequency offset estimation method and device, a storage medium, a communication device and a chip, and mainly aims to solve the technical problem that the branch trial method requires multiple trials of a terminal device, resulting in large signal processing complexity of the terminal device and affecting the performance of the terminal device.

[0004] According to a first aspect of an embodiment of the present disclosure, a frequency offset estimation method is provided, comprising:

[0005] performing differential frequency offset estimation based on a primary synchronization signal and a secondary synchronization signal to obtain a primary-secondary differential frequency offset;

[0006] correcting the primary-secondary differential frequency offset by using a half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value;

[0007] determining a target frequency offset estimation value according to the target correction value and a frequency correction corresponding to the primary synchronization signal.

[0008] In some embodiments of the present disclosure, the step of correcting the primary-secondary differential frequency offset by using a half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value comprises:

[0009] obtaining a frequency offset correction value according to a frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset;

[0010] correcting the primary-secondary differential frequency offset periodically by using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to determine the target correction value.

[0011] In some embodiments of the present disclosure, the step of correcting the primary-secondary differential frequency offset periodically by using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to determine the target correction value comprises:

[0012] obtaining a frequency offset difference value of the frequency offset correction value and the half-symbol frequency offset, respectively;

[0013] The frequency offset correction value corresponding to the minimum frequency offset difference value is determined as the target correction value after period correction.

[0014] In some embodiments of the present disclosure, before the frequency offset correction value is obtained according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset, the method further comprises:

[0015] The maximum frequency offset estimation value corresponding to the primary synchronization signal and the secondary synchronization signal is determined as the frequency offset estimation range.

[0016] In some embodiments of the present disclosure, the frequency offset correction value is obtained according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset, comprising:

[0017] The primary-secondary differential frequency offset is determined as the frequency offset correction value; and / or,

[0018] The frequency offset obtained by adding the primary-secondary differential frequency offset to the maximum frequency offset estimation value is determined as the frequency offset correction value; and / or;

[0019] The frequency offset obtained by subtracting the primary-secondary differential frequency offset from the maximum frequency offset estimation value is determined as the frequency offset correction value.

[0020] In some embodiments of the present disclosure, the method further comprises:

[0021] The primary synchronization sequence detection is performed on the received primary synchronization signal to obtain the frequency offset for correction;

[0022] The original primary synchronization signal and the original secondary synchronization signal are pre-corrected using the frequency offset for correction to obtain the primary synchronization signal and the secondary synchronization signal after correction.

[0023] In some embodiments of the present disclosure, the primary synchronization sequence detection on the primary synchronization signal comprises:

[0024] The primary synchronization detection branch corresponding to the current residual frequency offset is obtained, and the primary synchronization sequence detection is performed on the primary synchronization signal using the primary synchronization detection branch.

[0025] In some embodiments of the present disclosure, the method further comprises:

[0026] The current residual frequency offset is corrected based on the target frequency offset estimation value to obtain a corrected frequency;

[0027] The broadcast message sent by the network device is received according to the frequency.

[0028] In some embodiments of the present disclosure, the target frequency offset estimation value is determined according to the target correction value and the frequency offset corresponding to the primary synchronization signal.

[0029] The target correction value is added to the frequency offset corresponding to the primary synchronization signal to obtain the target frequency offset estimation value.

[0030] According to a second aspect of an embodiment of the present disclosure, a frequency offset estimation device is provided, comprising:

[0031] The obtaining module is configured to obtain the primary synchronization signal after frequency correction and the secondary synchronization signal after frequency correction.

[0032] The obtaining module is configured to perform differential frequency offset estimation on the primary synchronization signal and the secondary synchronization signal to obtain a primary-secondary differential frequency offset.

[0033] The correction module is configured to correct the primary-secondary differential frequency offset by using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value.

[0034] The determination module is configured to determine a target frequency offset estimation value according to the target correction value and the frequency offset corresponding to the primary synchronization signal.

[0035] According to a third aspect of an embodiment of the present disclosure, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the method according to the first aspect.

[0036] According to a fourth aspect of an embodiment of the present disclosure, a communication device is provided, comprising: a transceiver; a memory; and a processor connected to the transceiver and the memory respectively, configured to control wireless signal transceiving of the transceiver by executing computer executable instructions on the memory, and capable of implementing the method according to the first aspect.

[0037] According to a fifth aspect of an embodiment of the present disclosure, a computer program product is provided, which stores a computer program. The computer program is executed by a processor to implement the method according to the first aspect.

[0038] According to a sixth aspect of an embodiment of the present disclosure, a chip is provided, comprising at least one processor and a communication interface. The communication interface is configured to receive a signal input into the chip or output a signal from the chip. The processor is in communication with the communication interface and implements the method according to the first aspect through a logic circuit or execution of code instructions.

[0039] By the above technical solutions, the present disclosure provides a frequency offset estimation method, device, storage medium, communication device and chip. Specifically, first, differential frequency offset estimation is performed based on a primary synchronization signal and a secondary synchronization signal to obtain a primary-secondary differential frequency offset; then the primary-secondary differential frequency offset is corrected using a half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value; finally, a target frequency offset estimation value is determined based on the target correction value and a frequency correction frequency offset corresponding to the primary synchronization signal. The present application obtains the primary-secondary differential frequency offset after differential frequency offset estimation of the primary synchronization signal and the secondary synchronization signal, and then corrects the primary-secondary differential frequency offset using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain the target correction value, so that the primary-secondary differential frequency offset corrected using the target correction value is close to the half-symbol frequency offset with a larger frequency offset estimation range, reducing the frequency offset estimation error. Finally, the target frequency offset estimation value is determined based on the frequency offset correction value and the frequency correction frequency offset, and the broadcast message is read in a single branch, without the need to determine the frequency offset by trying multiple branches, reducing the complexity of signal processing of the terminal device, and further reducing the impact on the performance of the terminal device.

[0040] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0041] The accompanying drawings, which are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0042] Figure 1 A flowchart of a frequency offset estimation method provided by an embodiment of the present application is shown;

[0043] Figure 2 A flowchart of a frequency offset estimation method provided by an embodiment of the present application is shown;

[0044] Figure 3 A structural diagram of a frequency offset estimation device provided by an embodiment of the present application is shown;

[0045] Figure 4 A structural diagram of a communication device provided by an embodiment of the present disclosure is shown;

[0046] Figure 5 A structural diagram of a chip provided by an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0047] Some embodiments of the present disclosure will be described in detail herein with reference to the drawings, of which examples are shown. The following description is related to the drawings when the drawings are referred to, and the same numerals in different drawings represent the same or similar elements unless otherwise indicated. Various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will become apparent to those skilled in the art after understanding the present disclosure. For example, the order of the operations described herein is merely an example, and is not limited to those set forth herein, but can be changed as apparent after understanding the present disclosure, except for the operations that must be performed in a specific order. In addition, the description of features known in the art can be omitted for the sake of clarity and brevity. It should be noted that the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0048] The following describes some embodiments of the present disclosure. It should be noted that the implementation described in some embodiments of the present disclosure below does not represent all implementations consistent with the present disclosure. Instead, they are only examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0049] In some embodiments, branch and try method is used for frequency offset estimation, and the optimal frequency offset estimation value is found by trying multiple possible frequency offset values. However, the branch and try method requires the terminal device to try multiple times, resulting in a large signal processing complexity of the terminal device and affecting the performance of the terminal device.

[0050] To improve the technical problem that the branch and try method requires the terminal device to try multiple times, resulting in a large signal processing complexity of the terminal device and affecting the performance of the terminal device. Embodiments of the present disclosure provide a frequency offset estimation method, as shown in Figure 1 Figure 1 is a flowchart of a frequency offset estimation method according to some embodiments of the present disclosure, comprising the following steps.

[0051] Step 101, performing differential frequency offset estimation based on the primary synchronization signal and the secondary synchronization signal to obtain the primary-secondary differential frequency offset.

[0052] The execution subject of the present embodiment can be a communication apparatus or a communication device, such as an electronic device or a chip, which can be configured on the terminal side.

[0053] ​In some examples, a terminal can be referred to as a terminal device (terminal), a user equipment (UE), a mobile station (MS), a mobile terminal (MT), or the like. The terminal can also be a vehicle, a smart vehicle, a mobile phone, a wearable device, a tablet computer (Pad), a computer with wireless transceiver function, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal device in industrial control, a wireless terminal device in self-driving, a wireless terminal device in remote medical surgery, a wireless terminal device in smart grid, a wireless terminal device in transportation safety, a wireless terminal device in smart city, a wireless terminal device in smart home, or the like. The embodiments are not limited to a specific technology or a specific device form of the terminal.

[0054] In some examples, a network device can be a base station, a satellite, or the like, and the embodiments are not limited to a specific technology or a specific device form of the network device. The network device can be an entity on the network side for transmitting or receiving signals. For example, the network device can be a communication satellite, an evolved NodeB (eNB), a transmission reception point (TRP), a next generation NodeB (gNB) in an NR system, a base station in other future mobile communication systems, or an access node in a wireless fidelity (WiFi) system, or the like. The embodiments of the present disclosure are not limited to a specific technology or a specific device form of the network device. The network device provided in the embodiments can be composed of a central unit (CU) and a distributed unit (DU), where the CU can also be referred to as a control unit. The CU-DU structure can split the protocol layers of the network device, for example, a base station, and the functions of part of the protocol layers are controlled by the CU, and the functions of the remaining part or all of the protocol layers are distributed in the DU and controlled by the CU.

[0055] The signal obtained after performing frequency correction on the primary synchronization signal (PSS); and the signal obtained after performing frequency correction on the secondary synchronization signal (SSS).

[0056] In some examples, during the cell search of the terminal, the primary synchronization signal and the secondary synchronization signal are generally needed to be acquired, and frequency offset estimation and correction are performed on the primary synchronization signal and the secondary synchronization signal, so that the terminal device can be accurately synchronized with the carrier frequency of the communication device. For example, a coarse estimation of the current residual frequency offset of the terminal is first performed to obtain a frequency correction offset, and then the received primary synchronization signal and secondary synchronization signal are respectively subjected to frequency correction processing by using the frequency correction offset, to obtain the primary synchronization signal and the secondary synchronization signal after frequency correction processing, thereby realizing large-range frequency offset correction.

[0057] In some examples, the communication system corresponding to the terminal can be first determined, such as a 5G NR system, an LTE system, etc., and then a phase difference calculation method corresponding to the differential frequency offset estimation is determined according to the communication system, and then the primary-secondary differential frequency offset is obtained based on the phase difference and the absolute time difference between the primary synchronization signal and the secondary synchronization signal. The primary-secondary differential frequency offset can be a frequency offset estimation value calculated by performing differential frequency offset estimation on the primary synchronization sequence corresponding to the primary synchronization signal and the secondary synchronization sequence corresponding to the secondary synchronization signal, which is helpful to obtain a more accurate frequency offset, improve the accuracy of the frequency offset estimation, and reduce the error of the frequency offset estimation.

[0058] Step 102, correcting the primary-secondary differential frequency offset by using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value.

[0059] The half-symbol frequency offset can be a frequency offset estimation value of a half-symbol (such as an OFDM symbol) period of the primary synchronization signal, which can be used to determine a large estimation range of the frequency offset.

[0060] For example, the half-symbol phase difference of the primary synchronization sequence corresponding to the primary synchronization signal can be calculated, the half-symbol frequency offset estimation value corresponding to the primary synchronization signal can be obtained based on the half-symbol phase difference, the primary-secondary differential frequency offset can be compared with the half-symbol frequency offset, the primary-secondary differential frequency offset can be corrected according to the comparison result, the primary-secondary differential frequency offset after correction is close to the half-symbol frequency offset, the frequency offset correction value closest to the half-symbol frequency offset is taken as the target correction value within the half-symbol frequency offset estimation range, and then more fine-grained frequency offset estimation is realized to obtain a more accurate frequency offset estimation value.

[0061] Step 103, determining a target frequency offset estimation value according to the target correction value and the frequency correction offset corresponding to the primary synchronization signal.

[0062] In the embodiment of the present disclosure, the frequency offset can be used for pre-correction of the primary synchronization signal and the secondary synchronization signal respectively, the frequency offset estimation value obtained by rough estimation with a large frequency offset interval, the target correction value can be a half-symbol frequency offset, the primary-secondary differential frequency offset is corrected, the frequency offset correction value in a smaller frequency offset range is further estimated, and finally the target frequency offset estimation value with a large frequency offset estimation range and small error is obtained by combining the frequency offset correction value and the frequency offset correction value. The frequency offset access condition of the later module (for example, the broadcast module, the system message reading module and the like) can be met, the later module does not need to perform multiple frequency offset attempt branches, and only the single frequency offset attempt branch corresponding to the target frequency offset estimation value is retained to read the broadcast message, thereby reducing the complexity of signal processing of the terminal device.

[0063] Compared with the prior art, the primary-secondary differential frequency offset of the primary synchronization signal and the secondary synchronization signal can be obtained first, the primary-secondary differential frequency offset is corrected by using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain the target correction value, so that the primary-secondary differential frequency offset corrected by using the target correction value is close to the half-symbol frequency offset with a large frequency offset estimation range, the frequency offset estimation error is reduced, and finally the target frequency offset estimation value determined based on the frequency offset correction value and the frequency offset correction value is used to read the broadcast message in a single branch, without determining the frequency offset by multiple branch attempts, thereby reducing the complexity of signal processing of the terminal device and further reducing the influence on the performance of the terminal device.

[0064] Further, in order to illustrate the specific implementation process of the embodiment method, the embodiment provides a specific method as shown in Figure 2 The method comprises the following steps:

[0065] Step 201, performing primary synchronization sequence detection on the received original primary synchronization signal to obtain a frequency offset correction value.

[0066] In a specific application scenario, the original primary synchronization signal can be an unprocessed primary synchronization signal received by the terminal. The original primary synchronization signal can be subjected to frequency offset estimation with a large frequency offset interval through primary synchronization sequence detection of the original primary synchronization signal, and rough estimation is performed to reduce the frequency offset attempt branch of the primary synchronization detection. The pre-correction value obtained by the primary synchronization sequence detection is used as the frequency offset correction value to correct the frequency offset of the original primary synchronization signal and the original secondary synchronization signal, remove the large range of frequency offset, and then perform detailed and small range frequency offset estimation.

[0067] Optionally, the primary synchronization sequence detection on the original primary synchronization signal can specifically include: obtaining a primary synchronization detection branch corresponding to a current residual frequency offset, and performing primary synchronization sequence detection on the original primary synchronization signal by using the primary synchronization detection branch.

[0068] In some embodiments, the terminal can attempt multiple primary synchronization detection branches with larger frequency offset intervals according to the current residual frequency offset. The received original primary synchronization signal can be represented as y(i), i=0, 1, 2, …, len-1; the primary synchronization local sequence can be represented as p(k, i), i=0, 1, …, M-1, k=0, 1, 2, where k represents the kth primary synchronization sequence; each primary synchronization detection branch (frequency offset attempt branch) can be represented as fn(n), n=0, 1, …, N-1. Exemplarily, the frequency offset intervals between the frequency offset attempt branches can be set to 10k, 20k.

[0069] Exemplarily, the specific implementation process of the primary synchronization sequence detection is as follows:

[0070] (1) The primary synchronization sequence of the original primary synchronization signal is pre-corrected by each primary synchronization detection branch respectively to obtain the pre-corrected primary synchronization data pn(k, i)=p(k, i)*exp(j*2*pi*fn(n)*i), where pi=3.14; then, the received primary synchronization sequence is correlated with the pre-corrected primary synchronization data pn(i) to obtain the primary synchronization correlation result yr(k, i). The primary synchronization correlation result operation formula is as follows:

[0071] i=0, 1, 2, …, len-1; k=0, 1, 2

[0072] (2) The modulus square of the primary synchronization correlation result yr(k, i) is calculated to obtain the primary synchronization correlation power corresponding to the received data. The primary synchronization correlation power yp(k, i) calculation formula is as follows:

[0073] yp(k, i)=(yr(k, i)) 2 i=0, 1, 2, …, len-1; k=0, 1, 2

[0074] (3) The peak value of the primary synchronization correlation power is detected to obtain the primary synchronization detection result. The specific detection method can be that the top pre-set number (such as nmax_p) of values and the positions, primary synchronization codes, and pre-corrected values corresponding to the values of the primary synchronization correlation power are selected as the detection result of the primary synchronization sequence.

[0075] Optionally, the secondary synchronization sequence detection can be performed according to the primary synchronization sequence detection result. The secondary synchronization sequence can be obtained through the position output by the primary synchronization detection result. The secondary synchronization sequence can be represented as ys(i), i=0, 1, 2, …, M-1; the secondary synchronization local sequence can be represented as s(k, i), k=0, N-1; i=0, 1, …, M-1, where k represents the kth secondary synchronization sequence.

[0076] Exemplarily, the specific implementation process of the secondary synchronization sequence detection is as follows:

[0077] (1) Pre-correction is performed on the secondary synchronization sequence ys(i) to obtain secondary synchronization pre-correction data ysn(i) = ys(i) * exp(-j * 2 * pi * fn * i), where pi = 3.14, and fn can be a primary synchronization detection result of a primary synchronization frequency offset attempt value; then, correlation operation is performed on the received data secondary synchronization sequence ys(i) and s(k, i) to obtain a secondary synchronization correlation result ysr(k), and the correlation operation is as follows:

[0078]

[0079] (2) The modulus square of ysr(k) is calculated to obtain a received data secondary synchronization correlation power, and the secondary synchronization correlation power ysp(k) is calculated according to the following formula:

[0080] ysp(k) = (ysr(k))2 2 , k = 0, N-1

[0081] (3) Peak value detection is performed on the secondary synchronization correlation power to obtain a secondary synchronization detection result, and the specific detection method can be that a preset number (such as nmax_s) of values at the front of the secondary synchronization correlation power and the secondary synchronization code and pre-correction value thereof are taken as the detection result of the secondary synchronization sequence.

[0082] Step 202, pre-correction is performed on the original primary synchronization signal and the original secondary synchronization signal by using the correction frequency offset to obtain the primary synchronization signal and the secondary synchronization signal after correction.

[0083] The original secondary synchronization signal can be an unprocessed secondary synchronization signal received by the terminal.

[0084] For example, the received data yp(i) of the primary synchronization symbol is obtained according to the primary / secondary synchronization detection result, i = 0, 1, 2, …, M-1, the primary synchronization local sequence can be represented as p(i), i = 0, 1, …, M-1, the received data ys(i) of the secondary synchronization symbol can be represented as s(i), i = 0, 1, 2, …, M-1, and the primary synchronization detection frequency offset attempt value fn of the cell is taken as the correction frequency offset.

[0085] Then, pre-correction is performed on the primary synchronization sequence corresponding to the original primary synchronization signal and the secondary synchronization sequence corresponding to the original secondary synchronization signal by using the correction frequency offset, the primary synchronization signal can be represented as ypn(i) = yp(i) * exp(-j * 2 * pi * fn * i), the secondary synchronization signal can be represented as ysn(i) = ys(i) * exp(-j * 2 * pi * fn * i), i = 0, 1, …, M-1, and pi = 3.14.

[0086] In this way, the original primary synchronization signal and the original secondary synchronization signal are pre-corrected by using the frequency offset, the frequency offset correction in a large estimation range is performed, and accurate estimation of the frequency offset is facilitated.

[0087] Step 203, performing differential frequency offset estimation on the primary synchronization signal and the secondary synchronization signal to obtain the primary-secondary differential frequency offset.

[0088] For example, the specific steps of performing differential frequency offset estimation on the primary synchronization signal and the secondary synchronization signal are as follows:

[0089] (1) The secondary synchronization sequence of the secondary synchronization signal is multiplied by the conjugate of the secondary synchronization local sequence to obtain the secondary synchronization conjugate result, which can be represented as:

[0090] ysn_ls(i)=ysn(i)*conj(s(i),i=0,1,…,M-1

[0091] (2) The correlation value of the primary synchronization sequence of the primary synchronization signal and the secondary synchronization sequence of the secondary synchronization signal is calculated, which is represented as:

[0092]

[0093] (3) The phase difference phase1 of the corrected synchronization sequence is calculated:

[0094] When the terminal is an LTE system: phase1=ysn_cor*conj(ypn_cor)

[0095] When the terminal is an NR system: phase1=ypn_cor*conj(ysn_cor)

[0096] (4) The primary-secondary differential frequency offset (primary-secondary synchronization sequence frequency offset estimation value) f1 is calculated:

[0097] f1=angle(phase1) / deltaT1

[0098] In the formula, angle represents the radian value of phase1, and deltaT1 represents the absolute time difference of the primary-secondary synchronization sequence.

[0099] Step 204, obtaining the frequency offset correction value according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset.

[0100] Optionally, before step 204, the method of the embodiment can further include: determining the frequency offset estimation range according to the maximum frequency offset estimation value corresponding to the primary synchronization signal and the secondary synchronization signal.

[0101] In the embodiments of the present disclosure, first, the absolute value f1_max of the maximum frequency offset value that can be estimated by the primary and secondary synchronization sequence corresponding to the primary and secondary synchronization signals can be obtained according to the communication system and the communication protocol of the terminal, as a maximum frequency offset estimation value, to provide a frequency offset estimation range. For example, if the terminal is LTE TDD, f1_max=2336hz can be calculated based on the absolute time difference of the primary and secondary synchronization sequences; accordingly, if the terminal system is LTE FDD, f1_max=7007hz; when the NR subcarrier spacing is 15khz, f1_max=3504hz; and when the NR subcarrier spacing is 30khz, f1_max=7007hz.

[0102] Optionally, the frequency offset correction value can be obtained according to the frequency offset estimation range corresponding to the primary and secondary synchronization signals and the primary and secondary differential frequency offset, and specifically can include: determining the primary and secondary differential frequency offset as the frequency offset correction value; and / or determining the frequency offset after adding the primary and secondary differential frequency offset to the maximum frequency offset estimation value as the frequency offset correction value; and / or determining the frequency offset after subtracting the primary and secondary differential frequency offset from the maximum frequency offset estimation value as the frequency offset correction value.

[0103] For example, the frequency offset estimation range f_period can be calculated according to the following formula:

[0104] f_period=2*f1_max

[0105] For example, based on the maximum frequency offset estimation value and the primary and secondary differential frequency offset, the following three frequency offset correction values f1_0, f1_1, and f1_2 can be obtained:

[0106] f1_0=f1

[0107] f1_1=f1+f_period

[0108] f1_2=f1-f_period

[0109] In this way, the frequency offset correction value corresponding to different periods is obtained according to the maximum frequency offset estimation value, and the period of the primary and secondary differential frequency offset is adjusted, which helps to obtain a more accurate period of the primary and secondary differential frequency offset and improve the accuracy of frequency offset estimation.

[0110] Step 205, using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value, the period of the primary and secondary differential frequency offset is corrected to determine a target correction value.

[0111] For example, the half-symbol differential frequency offset estimation of the primary synchronization sequence corresponding to the primary synchronization signal can include the following steps:

[0112] (1) The primary synchronization sequence of the primary synchronization signal is multiplied by the primary synchronization local sequence conjugate to obtain the primary synchronization conjugate result, which can be represented as:

[0113] ypn_ls(i) = ypn(i) * conj(p(i)), i = 0, 1, …, M-1

[0114] (2) Calculate the correlation values of the front half symbol of the primary synchronization sequence and the back half symbol of the primary synchronization sequence corresponding to the primary synchronization signal, the correlation value of the front half symbol of the primary synchronization sequence ypn_cor0 and the correlation value of the back half symbol of the primary synchronization sequence ypn_cor1, and the calculation formula is as follows:

[0115]

[0116] (3) Calculate the phase difference phase0 of the front half symbol of the primary synchronization sequence and the back half symbol of the primary synchronization sequence corresponding to the primary synchronization signal:

[0117] phase0 = ypn_cor1 * conj(ypn_cor0)

[0118] (4) Calculate the half symbol frequency offset (half symbol frequency offset estimation value) f0 of the primary synchronization sequence corresponding to the primary synchronization signal:

[0119] f0 = angle(phase0) / deltaT0

[0120] In the formula, angle represents the radian value of phase0, and deltaT0 represents the absolute time difference of the half symbol of the primary synchronization sequence.

[0121] In this way, the half symbol frequency offset corresponding to a larger estimation range is obtained, so as to facilitate the period correction of the frequency offset.

[0122] Optionally, step 205 can specifically include: obtaining the frequency offset difference values of the frequency offset correction values and the half symbol frequency offset respectively; determining the frequency offset correction value corresponding to the minimum frequency offset difference value as the target correction value after the period correction.

[0123] In some embodiments, the obtained multiple (such as 3) frequency offset correction values can be compared with the half symbol frequency offset estimation value respectively, and the frequency offset correction value closest to the half symbol frequency offset estimation value is selected as the final target correction value (joint frequency offset estimation result) output. For example, the difference values of the frequency offset correction values and the half symbol frequency offset can be represented according to the following formula:

[0124] deltaf1_0 = |f1_0-f0|

[0125] deltaf1_1 = |f1_1-f0|

[0126] deltaf1_2 = |f1_2-f0|

[0127] In the formula, deltaf1_0, deltaf1_1, and deltaf1_2 are differences between frequency offset correction values f1_0, f1_1, and f1_2 and a half-symbol frequency offset f0, respectively. The frequency offset correction value f1_x corresponding to the minimum frequency offset difference value can be outputted from among deltaf1_0, deltaf1_1, and deltaf1_2, to obtain a joint frequency offset estimation result f_union=x, x=0, 1, 2. For example, if it is determined through comparison that deltaf1_0 is the minimum, then the joint final joint frequency offset estimation result f_union can be determined as f1_0. If deltaf1_1 is the minimum, then the joint final joint frequency offset estimation result f_union can be determined as f1_1. If deltaf1_2 is the minimum, then the joint final joint frequency offset estimation result f_union can be determined as f1_2.

[0128] In this way, the primary synchronization sequence half-symbol differential frequency offset estimation is used to determine a rough range of the frequency offset, and then the primary-secondary synchronization sequence differential frequency offset estimation is used to ensure the accuracy of the frequency offset, so that the frequency offset estimation result is more accurate, the error is smaller, and the frequency offset access condition of the later module can be better met.

[0129] Step 206: determining a target frequency offset estimation value according to the target correction value and the frequency offset corresponding to the primary synchronization signal.

[0130] Optionally, step 206 can specifically include: adding the target correction value and the frequency offset corresponding to the primary synchronization signal to obtain the target frequency offset estimation value.

[0131] In some embodiments, the target frequency offset estimation value can be obtained according to the primary-secondary synchronization sequence detection result and the joint frequency offset estimation result, and a calculation formula of the target frequency offset estimation value is as follows:

[0132] fn_mib=fn+f_union

[0133] In the formula, fn is a frequency offset, which can be a primary synchronization detection frequency offset attempt value of the cell, and f_union can be a joint frequency offset estimation result estimated by the joint frequency offset estimation unit.

[0134] As a possible implementation, the primary synchronization detection can be first used to perform multi-branch attempts at a large frequency offset interval, then the secondary synchronization signal detection is performed based on the primary synchronization detection result, and the joint frequency offset estimation unit is used to perform primary synchronization half-symbol differential frequency offset estimation and primary synchronization sequence differential frequency offset estimation based on the primary and secondary synchronization detection results to obtain a joint frequency offset estimation result (joint frequency offset estimation value). Finally, the post-stage module can read the broadcast message according to the target frequency offset estimation value corresponding to the joint frequency offset estimation value, without performing multi-branch attempts. In this way, the frequency offset attempt branches of the primary synchronization detection and the broadcast message reading are reduced, the overall complexity of the terminal is reduced, and the problem that the half-symbol differential frequency offset estimation of the primary synchronization sequence cannot meet the frequency offset access condition of the post-stage module is solved.

[0135] Optionally, the method of the embodiment can further include correcting the current residual frequency based on the target frequency offset estimation value to obtain a corrected frequency, and receiving the broadcast message sent by the communication device according to the frequency.

[0136] In some embodiments, the joint frequency offset estimation result fn_mib is used to perform frequency offset soft correction or adjust the crystal oscillator of the received data, and then the data is re-received according to the corrected frequency to read the broadcast message sent by the base station. Since the joint frequency offset estimation has a large frequency offset estimation range and a small frequency offset estimation error, the post-stage module does not need to perform multi-frequency offset attempt branches, but only needs to keep a single frequency offset attempt branch, thereby reducing the signal processing complexity of the post-stage module.

[0137] As a possible implementation, the primary synchronization detection can be first used to perform multi-branch attempts at a large frequency offset interval, then the secondary synchronization signal detection is performed based on the primary synchronization detection result, and the joint frequency offset estimation unit is used to perform primary synchronization half-symbol differential frequency offset estimation and primary synchronization sequence differential frequency offset estimation based on the primary and secondary synchronization detection results to obtain a joint frequency offset estimation result (joint frequency offset estimation value). Finally, the post-stage module can read the broadcast message according to the target frequency offset estimation value corresponding to the joint frequency offset estimation value, without performing multi-branch attempts. In this way, the frequency offset attempt branches of the primary synchronization detection and the broadcast message reading are reduced, the overall complexity of the terminal is reduced, and the problem that the half-symbol differential frequency offset estimation of the primary synchronization sequence cannot meet the frequency offset access condition of the post-stage module is solved.

[0138] As another possible implementation, the primary / secondary synchronization detection can be first used to perform branch attempts at a small frequency offset interval, a plurality of possible frequency offset value branches are found during the primary and secondary synchronization sequence detection, and then the primary and secondary synchronization sequence differential frequency offset estimation is performed. The primary and secondary synchronization sequences are used for differential frequency offset estimation to obtain a more accurate frequency offset to meet the frequency offset access condition of the post-stage module. Finally, the post-stage module can perform single-branch attempts, thereby reducing the signal processing complexity of the post-stage module.

[0139] Compared with the prior art, the embodiment firstly uses frequency offset correction to pre-correct the primary synchronization signal and the secondary synchronization signal, corrects the frequency offset in a large estimation range, then obtains the frequency offset correction value corresponding to different periods based on the frequency offset estimation range, adjusts the period of the primary-secondary differential frequency offset using the half-symbol frequency offset, determines the target correction value, and finally corrects the target frequency offset estimation value based on the target correction value and the target frequency offset estimation value determined by the frequency offset correction, and directly uses the corrected frequency to read the broadcast message, corrects the period of the primary-secondary differential frequency offset, improves the accuracy of the frequency offset estimation, and reduces the frequency offset branch attempts in the message reading process and the complexity of signal processing of the terminal device.

[0140] Figure 3 is a frequency offset estimation device block diagram according to some embodiments of the present disclosure. Referring to Figure 3 , the device comprises an acquisition module 31, a correction module 32, and a determination module 33.

[0141] The acquisition module 31 is configured to perform differential frequency offset estimation based on the primary synchronization signal and the secondary synchronization signal, and acquire the primary-secondary differential frequency offset.

[0142] The correction module 32 is configured to correct the primary-secondary differential frequency offset using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a frequency offset correction value.

[0143] The determination module 33 is configured to determine a target frequency offset estimation value according to the target correction value and the frequency offset correction corresponding to the primary synchronization signal.

[0144] In some examples of the embodiment, the correction module 32 is specifically configured to acquire the frequency offset correction value according to the frequency offset estimation range corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset, and correct the period of the primary-secondary differential frequency offset using the half-symbol frequency offset corresponding to the primary synchronization signal and the frequency offset correction value to determine the target correction value.

[0145] In some examples of the embodiment, the correction module 32 is specifically configured to acquire the frequency offset difference value of the frequency offset correction value and the half-symbol frequency offset, and determine the frequency offset correction value corresponding to the minimum frequency offset difference value as the target correction value after the period correction.

[0146] In some examples of the embodiment, the correction module 32 is specifically configured to determine the frequency offset estimation range according to the maximum frequency offset estimation value corresponding to the primary synchronization signal and the secondary synchronization signal.

[0147] In some examples of the embodiment, the correction module 32 is specifically configured to determine the primary-secondary differential frequency offset as the frequency offset correction value, and / or determine the frequency offset obtained by adding the primary-secondary differential frequency offset and the maximum frequency offset estimation value as the frequency offset correction value, and / or determine the frequency offset obtained by subtracting the primary-secondary differential frequency offset and the maximum frequency offset estimation value as the frequency offset correction value.

[0148] In some examples of the present embodiment, the obtaining module 31 is specifically configured to perform primary synchronization sequence detection on the received original primary synchronization signal to obtain a frequency correction offset; and perform pre-correction on the original primary synchronization signal and the original secondary synchronization signal respectively using the frequency correction offset to obtain the pre-corrected primary synchronization signal and the pre-corrected secondary synchronization signal.

[0149] In some examples of the present embodiment, the obtaining module 31 is specifically configured to obtain a primary synchronization detection branch corresponding to the current residual frequency offset, and perform primary synchronization sequence detection on the original primary synchronization signal using the primary synchronization detection branch.

[0150] In some examples of the present embodiment, the obtaining module 31 is specifically further configured to correct the current residual frequency offset based on the target frequency offset estimate to obtain a corrected frequency; and receive the broadcast message sent by the network device according to the frequency.

[0151] In some examples of the present embodiment, the determining module 33 is specifically configured to add the target correction value to the frequency correction offset corresponding to the primary synchronization signal to obtain the target frequency offset estimate.

[0152] As to the apparatus in the above embodiment, the specific manners in which various modules perform operations have been described in detail in the embodiments of the method, and will not be described in detail here.

[0153] Figure 4 FIG. 18 is a structural schematic diagram of a communication device 1800 provided in the present embodiment. The communication device 1800 can be a terminal device, or a network device, or a chip, chip system, or processor supporting the network device to implement the above method, or a chip, chip system, or processor supporting the user device to implement the above method. The apparatus can be used to implement the method described in the above method embodiments, and specific can be referred to the description in the above method embodiments.

[0154] The communication device 1800 includes a transceiver, a memory, and a processor connected with the transceiver and the memory respectively and configured to control the wireless signal transceiving of the transceiver by executing computer executable instructions on the memory and capable of realizing the functions of any of the above method embodiments.

[0155] The communication device 1800 can include one or more processors 1801. The processor 1801 can be a general purpose processor or a special purpose processor, etc. For example, it can be a baseband processor or a central processing unit. The baseband processor can be used to process communication protocols and communication data, and the central processing unit can be used to control the communication device (such as a base station, a baseband chip, a terminal device, a terminal device chip, a DU or a CU, etc.), execute computer programs, and process data of computer programs.

[0156] Optionally, the communication device 1800 can further include one or more memories 1802, which can store computer programs 1804. The processor 1801 executes the computer programs 1804 to enable the communication device 1800 to perform the methods described in the above method embodiments. Optionally, the memories 1802 can also store data. The communication device 1800 and the memories 1802 can be separately arranged, or integrated together.

[0157] Optionally, the communication device 1800 can further include a transceiver 1805, an antenna 1806. The transceiver 1805 can be referred to as a transceiving unit, a transceiver, or a transceiving circuit, etc., and is used to implement the transceiving function. The transceiver 1805 can include a receiver and a transmitter. The receiver can be referred to as a receiver or a receiving circuit, etc., and is used to implement the receiving function. The transmitter can be referred to as a transmitter or a transmitting circuit, etc., and is used to implement the transmitting function.

[0158] Optionally, the communication device 1800 can further include one or more interface circuits 1807. The interface circuit 1807 is used to receive code instructions and transmit them to the processor 1801. The processor 1801 runs the code instructions to enable the communication device 1800 to perform the methods described in the above method embodiments.

[0159] In an implementation manner, the processor 1801 can include a transceiver for implementing the receiving and transmitting functions. For example, the transceiver can be a transceiving circuit, or an interface, or an interface circuit. The transceiving circuit, the interface, or the interface circuit for implementing the receiving and transmitting functions can be separate, or integrated together. The transceiving circuit, the interface, or the interface circuit described above can be used for reading and writing of codes / data, or the transceiving circuit, the interface, or the interface circuit described above can be used for transmission or transfer of signals.

[0160] In an implementation manner, the processor 1801 can store a computer program 1803. The computer program 1803 runs on the processor 1801, and can enable the communication device 1800 to perform the methods described in the above method embodiments. The computer program 1803 can be fixed in the processor 1801. In this case, the processor 1801 can be implemented by hardware.

[0161] In an implementation, the communication device 1800 can include circuitry that can implement the functions of transmitting or receiving or communicating in the foregoing method embodiments. The processors and transceivers described in the present disclosure can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit (RFIC), a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processors and transceivers can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), positive channel metal oxide semiconductor (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0162] The communication device described in the foregoing embodiments can be a network device or a user device, but the scope of the communication device described in the present disclosure is not limited thereto, and the structure of the communication device can not be limited by Figure 4 The communication device can be a standalone device or can be part of a larger device. For example, the communication device can be:

[0163] (1) a standalone integrated circuit (IC), or a chip, or a chip system or subsystem;

[0164] (2) a set of one or more ICs, optionally the set of ICs can also include storage components for storing data, computer programs;

[0165] (3) an ASIC, such as a Modem;

[0166] (4) a module that can be embedded in other devices;

[0167] (5) a receiver, a terminal device, a smart terminal device, a cellular phone, a wireless device, a handset, a mobile unit, a vehicle-mounted device, a network device, a cloud device, an artificial intelligence device, etc.

[0168] (6) other, etc.

[0169] Based on the above embodiments, the embodiments also provide a chip including at least one processor and a communication interface; the communication interface is configured to receive a signal input into the chip or output a signal from the chip, and the processor is in communication with the communication interface and implements the above-described method through a logic circuit or executes code instructions.

[0170] Figure 5 is a structural diagram of a chip 1000 provided by the embodiments for implementing the above frequency offset estimation method. Referring to Figure 5 , the chip 1000 includes at least one communication interface 1001 and a processor 1002, the communication interface 1001 is configured to receive a signal input into the chip 1000 or output a signal from the chip 1000, and the processor 1002 is in communication with the communication interface 1001 and implements the frequency offset estimation method described in the above embodiments of the present disclosure through a logic circuit or executes code instructions.

[0171] Those skilled in the art can also understand that the various illustrative logical blocks and steps listed in the embodiments of the present disclosure can be implemented by electronic hardware, computer software, or a combination of both. Whether the functions are implemented by hardware or software depends on the specific application and design requirements of the overall system. Those skilled in the art can implement the functions described in various ways for each specific application, but such implementation should not be construed as beyond the scope of protection of the embodiments of the present disclosure.

[0172] The present disclosure also provides a computer-readable storage medium having a computer program stored thereon, and the computer program is executed by a processor of a computer to implement the functions of any of the above method embodiments.

[0173] The present disclosure also provides a computer program product, which is executed by a computer to implement the functions of any of the above method embodiments. Like the computer program stored thereon, the computer program product is executed by a processor of a computer to implement the functions of any of the above method embodiments.

[0174] In the embodiments described above, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer programs. When the computer programs are loaded on a computer and executed, all or part of the processes or functions according to the embodiments of the present disclosure are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer programs can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer programs can be transmitted from one website site, computer, server or data center to another website site, computer, server or data center through wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. containing one or more available media sets. The available media can be magnetic media (for example, floppy disk, hard disk, magnetic tape), optical media (for example, high-density digital video disc (digital video disc, DVD)), or semiconductor media (for example, solid state disk (solid state disk, SSD)) and the like.

[0175] Those of ordinary skill in the art can understand that the first, second, and the like various numerical designations involved in the present disclosure are only for the convenience of description and do not limit the scope of the embodiments of the present disclosure, nor represent the order of precedence.

[0176] At least one of the present disclosure can also be described as one or more, and the plurality can be two, three, four or more, which is not limited by the present disclosure. In the embodiments of the present disclosure, for a technical feature, the technical features in the technical feature are distinguished by "first", "second", "third", "A", "B", "C" and "D", and there is no order or size order between the technical features described by "first", "second", "third", "A", "B", "C" and "D".

[0177] As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, apparatus and / or device (e.g., magnetic discs, optical discs, memory, programmable logic devices (PLDs)) used to provide machine instructions and / or data to a programmable processor, including a machine-readable medium that receives the machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal that provides machine instructions and / or data to a programmable processor.

[0178] The systems and techniques described here can be implemented in a computing system that includes a back end component, e.g., as a data server, or that includes a middleware component, e.g., an application server, or that includes a front end component, e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here, or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication, e.g., a communication network. Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0179] The computer system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0180] It should be understood that the various forms of flow shown in the above figures can be re-ordered, added to, or deleted from, without departing from the scope of the present disclosure. For example, the steps recited in the disclosure can be executed in parallel, executed in sequence, or executed in different orders, as long as the desired results of the technical solutions of the present disclosure are achieved, and the present disclosure is not limited herein.

[0181] In addition, it should be understood that various embodiments described in the present disclosure can be implemented alone or in combination with other embodiments as long as the scheme permits.

[0182] Those of ordinary skill in the art can be aware that, in combination with the examples described in the embodiments of the present application, units and algorithm steps can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solutions. Professionals can use different methods to implement the described functions for each specific application, but it should not be considered that such implementation is beyond the scope of the present disclosure.

[0183] Those of ordinary skill in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0184] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A frequency offset estimation method, characterized in that, include: Differential frequency offset estimation is performed based on the primary synchronization signal and the secondary synchronization signal to obtain the primary and secondary differential frequency offset; The primary and secondary differential frequency offsets are corrected using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value. This includes: obtaining a frequency offset correction value based on the frequency offset estimation ranges corresponding to the primary and secondary synchronization signals and the primary and secondary differential frequency offsets; obtaining the frequency deviation values ​​between the frequency offset correction value and the half-symbol frequency offset, and determining the frequency offset correction value corresponding to the minimum frequency deviation value as the target correction value; the half-symbol frequency offset is the frequency offset estimate of half an OFDM symbol period of the primary synchronization signal. Based on the target correction value and the frequency offset corresponding to the main synchronization signal, the target frequency offset estimate is determined; Specifically, the original master synchronization signal is detected by using the master synchronization detection branch corresponding to the current residual frequency offset to obtain the frequency correction offset.

2. The method according to claim 1, characterized in that, Before obtaining the frequency offset correction value based on the frequency offset estimation ranges corresponding to the primary synchronization signal and the secondary synchronization signal and the primary-secondary differential frequency offset, the method further includes: The frequency offset estimation range is determined based on the maximum frequency offset estimates corresponding to the primary synchronization signal and the secondary synchronization signal.

3. The method according to claim 2, characterized in that, The step of obtaining the frequency offset correction value based on the frequency offset estimation ranges corresponding to the primary synchronization signal and the secondary synchronization signal, and the primary-secondary differential frequency offset, includes: The primary and secondary differential frequency offset is determined as the frequency offset correction value; and / or... The frequency offset obtained by adding the primary and secondary differential frequency offset to the maximum frequency offset estimate is determined as the frequency offset correction value; and / or, The frequency offset obtained by subtracting the estimated maximum frequency offset from the primary and secondary differential frequency offset is determined as the frequency offset correction value.

4. The method according to claim 1, characterized in that, Also includes: The original primary synchronization signal and the original secondary synchronization signal are pre-corrected using the frequency offset correction method to obtain the corrected primary synchronization signal and the secondary synchronization signal.

5. The method according to claim 1, characterized in that, The method further includes: The current residual frequency offset is corrected based on the target frequency offset estimate to obtain the corrected frequency; Receive broadcast messages sent by network devices at the corrected frequency.

6. The method according to claim 1, characterized in that, The step of determining the target frequency offset estimate based on the target correction value and the frequency offset corresponding to the primary synchronization signal includes: The target correction value is added to the frequency offset corresponding to the main synchronization signal to obtain the target frequency offset estimate.

7. A frequency offset estimation device, characterized in that, include: The acquisition module is configured to perform differential frequency offset estimation based on the primary synchronization signal and the secondary synchronization signal, and acquire the primary and secondary differential frequency offsets. The correction module is configured to correct the primary-secondary differential frequency offset using the half-symbol frequency offset corresponding to the primary synchronization signal to obtain a target correction value. This includes: obtaining a frequency offset correction value based on the frequency offset estimation ranges corresponding to the primary and secondary synchronization signals and the primary-secondary differential frequency offset; obtaining the frequency deviation values ​​between the frequency offset correction value and the half-symbol frequency offset, and determining the frequency offset correction value corresponding to the minimum frequency deviation value as the target correction value; the half-symbol frequency offset is the frequency offset estimate of half an OFDM symbol period of the primary synchronization signal. The determination module is configured to determine the target frequency offset estimate based on the target correction value and the frequency offset corresponding to the main synchronization signal; Specifically, the original master synchronization signal is detected by using the master synchronization detection branch corresponding to the current residual frequency offset to obtain the frequency correction offset.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

9. A communication device, wherein, include: transceiver; Memory; The processor, connected to both the transceiver and the memory, is configured to control the wireless signal transmission and reception of the transceiver by executing computer-executable instructions on the memory, and is capable of implementing the method of any one of claims 1 to 6.

10. A chip, characterized in that, It includes at least one processor and a communication interface; the communication interface is used to receive signals input to the chip or signals output from the chip, and the processor communicates with the communication interface and implements the method as described in any one of claims 1 to 6 through logic circuits or executing code instructions.

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