Hybrid ADC structure integrated with CDS function, image sensor reading circuit and image sensor

Abstract

The invention discloses a hybrid ADC structure integrated with a CDS function, an image sensor reading circuit and an image sensor. The voltage signal output end of the CDS circuit of the hybrid ADC structure is connected with the voltage signal input end of the sigma-delta ADC, the digital code output end of the sigma-delta ADC is connected with the digital code input end of the digital low-pass filter, and the digital signal output end of the digital low-pass filter is connected with the digital signal input end of the digital logic correction unit; the residual voltage output end of the sigma-delta ADC is connected with the residual voltage input end of the cyclic ADC, the output end of the cyclic ADC is connected with the input end of the RSD unit, and the cyclic signal output end of the RSD unit is connected with the cyclic signal input end of the digital logic correction unit. According to the invention, the sigma-delta ADC and the cyclic ADC are combined, so that the area and the power consumption are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of CMOS image sensor readout circuits, and in particular, to a hybrid ADC structure integrating a CDS function, an image sensor readout circuit, and an image sensor. Background Art

[0002] Column parallel readout is used to quantify and read out a large amount of data in a large-scale parallel sensing system. The ADC in column parallel readout needs to be placed in a small area within a narrow pitch, with low power consumption, capable of converting a large amount of data in a short time, and high resolution to increase the dynamic range. Cyclic ADC has attracted much attention in the application of CMOS image sensor system readout circuits due to its relatively short conversion time for data.

[0003] Cyclic ADC has the advantage of short conversion time because its conversion time is the same as the number of resolution bits. However, it requires an operational amplifier with high gain and a large sampling capacitor to reduce gain error and sampling noise, which results in that cyclic ADC can only achieve limited accuracy. Therefore, cyclic ADC is usually used in applications that require short conversion time and moderate resolution. And sigma-delta ADC can easily achieve higher resolution due to its noise shaping characteristics. When the required resolution is the same, sigma-delta ADC can use a smaller sampling capacitor than cyclic ADC, and the required DC gain of the operational amplifier is also lower than that of cyclic ADC. However, due to the oversampling operation, sigma-delta ADC requires a relatively long conversion time. Therefore, sigma-delta ADC is usually used in applications that require high resolution and allow a relatively long conversion time.

[0004] Hybrid ADC shares operational amplifiers, comparators, capacitors, and switches among ADCs. By adding switches and capacitors, the CDS function used to eliminate fixed pattern noise is integrated into the hybrid ADC, reducing power consumption and area. The redundant bit correction algorithm is adopted in the design, reducing the requirement of the ADC for the comparator accuracy and further reducing the overall power consumption. This hybrid cyclic / sigma-delta ADC achieves a compromise between speed and accuracy, with high accuracy and fast speed, and is suitable for integration in an imaging array. Summary of the Invention

[0005] The object of the present invention is to overcome the disadvantages of cyclic ADC and sigma-delta ADC, meet the requirements of high speed and high precision, and provide a hybrid ADC structure integrating CDS function, a CMOS image sensor readout circuit, and a CMOS image sensor. The hybrid ADC structure integrating CDS function adopts a hybrid structure of cyclic ADC and sigma-delta ADC, uses the oversampling operation and noise shaping characteristics of sigma-delta ADC for coarse quantization to achieve high resolution, and uses a cyclic ADC for fine quantization to reduce the conversion time.

[0006] An object of the present invention is to provide a hybrid ADC structure integrating CDS function, including a CDS circuit, a sigma-delta ADC, a cyclic ADC, a digital low-pass filter, an RSD unit, and a digital logic correction unit; the voltage signal output terminal of the CDS circuit is connected to the voltage signal input terminal of the sigma-delta ADC, the digital code output terminal of the sigma-delta ADC is connected to the digital code input terminal of the digital low-pass filter, and the digital signal output of the digital low-pass filter is connected to the digital signal input of the digital logic correction unit; the residue voltage output terminal of the sigma-delta ADC is connected to the residue voltage input terminal of the cyclic ADC, the output terminal of the cyclic ADC is connected to the input terminal of the RSD unit, and the cyclic signal output terminal of the RSD unit is connected to the cyclic signal input terminal of the digital logic correction unit.

[0007] Among them, during the working process, first, a correlated double sampling operation is performed through a control switch, sampling the pixel reset signal and the pixel signal simultaneously, and the output voltage is sampled and quantized by the sigma-delta ADC. In subsequent cycles, the sigma-delta ADC samples the voltage difference between the actual voltage value adjusted by the control circuit and the expected value of the output of the previous-stage operational amplifier, and performs high-bit conversion to obtain a string of high-bit digital codes and a residue voltage. The high-bit digital codes are converted into a low-speed low-pass data stream by the digital low-pass filter and then output; the residue voltage is sampled and converted by the cyclic ADC until all low-bit digital codes are obtained, and all the digital codes obtained by cycling are added with dislocation to obtain a low-bit parallel output.

[0008] Among them, the sigma-delta ADC / cyclic ADC includes an operational amplifier, cascaded sub-ADCs and sub-DACs, and switches Φ 1_1 , Φ 1_2 , Φ 2 -Φ 7 , Φ 8_1 , Φ 8_2 , Φ s , Φs1 , Φ h , Φ h1 , capacitor C s , C 1 -C 3 ; The positive output terminal and the negative output terminal of the operational amplifier are each connected to one end of switch Φ h , and the other end of switch Φ h is connected to one end of switch Φ s and one end of switch Φ h1 , capacitor C 3 one end, Φ s the other end and the sub-DAC is connected to the reference voltage V ref- , the other end of switch Φ h1 is connected to the input terminal of the sub-ADC, and the sub-ADC outputs B 1 , B 0 to the sub-DAC, and the sub-DAC outputs the processed signal;

[0009] The positive input terminal and the negative input terminal of the operational amplifier are each connected to switches Φ 6 , Φ 7 , Φ s1 one end and the other end of capacitor C 3 , the other end of switch Φ 6 is connected to one end of switch Φ 2 and one end of capacitor C 1 , the other end of capacitor C 1 is connected to switches Φ 4 , , switch Φ 8_1 , , switch Φ 1_1 one end, the other end of switch Φ 4 , Φ 2 is grounded;

[0010] The other end of switch Φ 7 is connected to one end of switch Φ 3 and one end of capacitor C 2 , the other end of capacitor C 2 is connected to switches Φ 5 , , switch Φ 8_2 , , switch Φ 1_2 one end, , switch Φ 8_2 the other end is connected to the other end of , switch Φ 1_1 and is connected to V out ; The other end of switch Φ s1 is connected to one end of switch Φ h2 and one end of capacitor C s , the other end of switch Φ h2 is grounded; The other end of the capacitor C s connected to the negative input terminal of the operational amplifier is connected to V rst , and the other end of the capacitor Cs The other end is connected to V sig ; the switch Φ connected to the negative input terminal of the operational amplifier 8_1 ,, the switch Φ 1_2 The other end is connected to the input signal V DAC+ , the switch Φ connected to the positive input terminal of the operational amplifier 8_1 ,, the switch Φ 1_2 The other end is connected to the input signal V DAC- .

[0011] Among them, during the operation of the sigma-delta ADC, the switches Φ s and Φ s1 are closed, and two identical sampling capacitors C s respectively complete the sampling of the pixel reset signal V rst1 and the pixel signal V sig1 ; two identical holding capacitors C 3 respectively complete the sampling of the reference voltages V ref- and V ref+ ; then, the switch Φ s is disconnected, and Φ h is closed. The two sampling capacitors C s respectively complete the sampling of the pixel exposure signal V rst3 and the pixel signal V sig3 . The two holding capacitors C 3 are connected across the input and output terminals of the operational amplifier to obtain the output voltage of the operational amplifier after noise cancellation; then, the switch Φ s1 is disconnected, and Φ h2 and Φ h1 are closed, and the sigma-delta ADC starts to work.

[0012] Among them, after the sigma-delta ADC starts to work, it enters the sampling state. The comparator unit quantifies the output voltage of the operational amplifier, and through digital-to-analog conversion, a feedback voltage is obtained. The switches Φ 1-1 , Φ 1-2 , Φ 2 , Φ 3 are closed. The capacitor C 1 samples the output voltage of the operational amplifier after noise cancellation, C 2 samples the feedback voltage, and C 3 is reset; subsequently, the switches Φ 1-1 , Φ 1-2 , Φ 2 , Φ 3 are disconnected, and Φ 4 -Φ 7When closed, the sigma-delta ADC enters the integration state, and the charge accumulated on the sampling capacitor is transferred to the integration capacitor; thereafter, the first-order sigma-delta ADC repeats the sampling and integration processes until oversampling is completed, and the output voltage of the operational amplifier in the last cycle is the residue voltage of the first-order sigma-delta ADC; after the sigma-delta ADC generates a serial digital code, it is converted into a low-speed low-pass data stream by a digital low-pass filter.

[0013] Among them, after the sigma-delta ADC outputs the residue voltage of the last cycle, the cyclic ADC starts to work. In the sampling state, the output voltage of the sampling operational amplifier is sampled through capacitor C 2 In the amplification state, the positions of capacitor C 1 and C 2 are interchanged, and the cyclic ADC enters a cycle of sampling and amplification states until all cycles are completed; by alternately turning on and off the clock-controlled switches, capacitor C 1 and C 2 alternately sample the residue voltage signal generated in the previous clock cycle, thereby realizing the pipelined operation of signal sampling and quantization; after all cycles of quantization are completed, all the digital codes obtained from the cycles are added with dislocation to obtain the low-order parallel output.

[0014] The second object of the present invention is to provide an image sensor readout circuit, including the hybrid ADC structure integrating the CDS function.

[0015] The third object of the present invention is to provide an image sensor, including the image sensor readout circuit described above.

[0016] The present invention adopts a hybrid ADC structure, combines a high-precision sigma-delta ADC and a high-speed cyclic ADC, realizes high-speed and high-precision analog-to-digital conversion, and the two-stage ADC shares the same analog circuit block, reducing the area and power consumption.

[0017] The present invention integrates the correlated double sampling function into the ADC, further reducing the area and power consumption required for noise cancellation. The ADCs of the present invention have the same reference voltage and use a redundant bit correction algorithm to improve the tolerance to the equivalent input offset voltage of the comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a block diagram of the hybrid ADC structure integrating the CDS function of the present invention.

[0019] Figure 2 is a schematic diagram of the sigma-delta / cyclic ADC structure of the present invention.

[0020] Figure 3 It is a structural block diagram of a sub-ADC (analog-to-digital converter) of the present invention.

[0021] Figure 4 It is a schematic diagram of a sub-DAC (digital-to-analog converter) logic unit of the present invention.

[0022] Figure 5 It is a working timing diagram of the sigma-delta / cyclic ADC of the present invention. DETAILED DESCRIPTION

[0023] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0024] The hybrid ADC structure of the present invention shares operational amplifiers, comparators, capacitors and switches between two ADCs. By adding switches and capacitors, the CDS function used to eliminate fixed pattern noise is integrated into the hybrid ADC, reducing power consumption and area. The present invention adopts a redundant bit correction algorithm to reduce the ADC's requirements for comparator accuracy and further reduce overall power consumption. The hybrid cyclic / sigma-delta ADC achieves a compromise between speed and accuracy, has high accuracy and high speed, and is suitable for integration in imaging arrays.

[0025] Figure 1 The overall structural block diagram of the hybrid ADC structure with integrated CDS function of the present invention includes a CDS circuit, a sigma-delta ADC, a cyclic ADC, a digital low-pass filter (Digital Lowpass Filter) and a digital logic correction unit (Error Correction Logic).

[0026] Among them, it is used to receive the pixel reset signal V rst , pixel signal V sig The voltage signal of the CDS circuit (V out ) output and the voltage signal (V out ) input terminal, the digital code output terminal of the sigma-delta ADC is connected to the digital code input terminal of the digital low-pass filter (Digital Lowpass Filter), and the digital signal (D sig ) output terminal is connected to the digital signal input terminal of the digital logic correction unit; the residual voltage (V res) The output terminal is connected to the residue voltage input terminal of the cyclic ADC. The output terminal of the cyclic ADC is connected to the input terminal of the RSD unit. The cyclic digital code signal (D cyc ) output terminal is connected to the cyclic digital code signal (D cyc ) input terminal of the digital logic correction unit. The digital logic correction unit processes the input signal from the digital low-pass filter and the input signal of the RSD unit, performs staggered addition, and obtains the low-order parallel output D out .

[0027] In the embodiment of the present application, during operation, first, a correlated double sampling operation is performed through a control switch, and the pixel reset signal V rst and the pixel signal V sig are sampled simultaneously to eliminate the fixed pattern noise. The output voltage V out is sampled and quantized by the sigma-delta ADC. In subsequent cycles, the sigma-delta ADC samples the voltage difference (referred to as the residue voltage V res ) between the actual voltage value adjusted by the control circuit and the expected value of the output of the previous-stage operational amplifier, converts it until the high-order conversion is completed, obtains a string of digital codes and the residue voltage. The digital codes are input to the digital low-pass filter, and after being converted into a low-speed low-pass data stream by the digital low-pass filter, the high-order digital codes of the analog-to-digital conversion (i.e., D sig ) are obtained and input to the digital logic correction unit for processing; the residue voltage V res is sampled and converted by the cyclic ADC again until all the low-order digital codes are obtained, and the digital logic correction unit adds the digital codes obtained in all cycles in a staggered manner to obtain the low-order parallel output; among them, both stages of the ADC adopt the RSD algorithm to avoid the influence of comparator offset.

[0028] Figure 2 is the structural schematic diagram of the sigma-delta / cyclic ADC. The two stages of the ADC share the analog circuit, including a digital-to-analog converter and an analog-to-digital converter. Figure 3 is the structural block diagram of the sub-ADC (analog-to-digital converter) of the present invention. Figure 4 is the schematic diagram of the sub-DAC (digital-to-analog converter) logic unit of the present invention.

[0029] As Figure 2 shown, V rst is the pixel reset signal, V sig is the pixel signal, and the capacitors C 1 , C 2 , C 3 and C sBoth are 1 pF. The operational amplifier adopts a folded cascode structure, and both the output swing and speed can meet the design requirements. Among them, the sampling capacitor C s 's lower plates are respectively connected to the pixel reset signal V rst1 and the pixel signal V sig1 , and the upper plates are connected to the input end of the operational amplifier. The upper plate of the hold capacitor C 3 is connected to the input end of the operational amplifier, and the lower plates are respectively connected to the reference voltages V ref- and V ref+ ; the hold capacitor C 3 is connected across the input and output ends of the operational amplifier, so as to obtain the output voltage of the operational amplifier after noise elimination. The upper plate of C s is grounded, and C 3 is always connected across both ends of the operational amplifier. The output end of the operational amplifier is simultaneously connected to the input end of the sub-ADC.

[0030] In the embodiment of the present application, the sigma-delta ADC samples the output voltage of the operational amplifier after eliminating the fixed pattern noise, and then repeats the sampling and integration processes until the oversampling is completed; the cyclic ADC samples the residue voltage generated in the last cycle of the sigma-delta ADC. During the cyclic process of the sampling and amplification states, the encoding circuit of the RSD unit adopted is composed of D flip-flops and simple logic gates to achieve the function of staggered addition.

[0031] Among them, the comparator adopted by the sub-ADC of the sigma-delta / cyclic ADC structure of the present invention is a dynamic latch type structure with low power consumption. As Figure 3 shown, the front-stage sub-ADC includes two comparators, and their inputs are respectively V in+ , V in- , V ref+ , V ref- , and the outputs are B 0 , B 1- .

[0032] As Figure 4 shown, in the sub-DAC (digital-to-analog converter) logic unit circuit of the sigma-delta / cyclic ADC structure of the present invention, there are switches Φ 00 , Φ 10 , Φ 01 , each having two. One end of the parallel connection of Φ 00 and Φ 10 is connected to one end of the switch Φ 01 and V DAC+ , V DAC- . The other ends of the two switches Φ 01 are respectively connected, and the other ends of the two switches Φ 01 are connected to each other and connected to VCOM are connected, and the other ends of two switches Φ 00 are respectively connected to the reference voltage V ref- , and the other ends of two switches Φ 10 are respectively connected to the reference voltage V ref+ .

[0033] The timing of the overall operation of the present invention is as Figure 5 shown. Figure 5 Among them, Φ 1 , Φ 8 respectively include Φ 1_1 , Φ 1_2 , Φ 8_1 , Φ 8_2 . First, the switches Φ s , Φ s1 are closed, and the upper and lower identical sampling capacitors C s respectively complete the sampling of the pixel reset signal V rst1 and the pixel signal V sig1 . The upper and lower identical holding capacitors C h respectively complete the sampling of the reference voltages V ref- and V ref+ . Then, the switch Φ s is disconnected, and Φ h is closed. The two sampling capacitors C s respectively complete the sampling of the pixel exposure signal V rst3 and the pixel signal V sig3 . The two holding capacitors C h are connected across the input and output ends of the operational amplifier to obtain the output voltage of the operational amplifier after noise cancellation. Next, the switch Φ s1 is disconnected, and Φ h2 and Φ h1 are closed, and the sigma-delta ADC starts to work.

[0034] First, it enters the sampling state. The comparator unit quantifies the output voltage of the operational amplifier, and through digital-to-analog conversion, a feedback voltage is obtained. The switches Φ 1-1 , Φ 1-2 , Φ 2 , Φ 3 are closed. The capacitor C 1 samples the output voltage of the operational amplifier after noise cancellation, C 2 samples the feedback voltage, and C 3 is reset. Subsequently, the switches Φ 1-1 , Φ 1-2 , Φ 2 , Φ 3 are disconnected, and Φ 4 -Φ 7When it is closed, the sigma-delta ADC enters the integration state. The charge accumulated on the sampling capacitor is transferred to the integration capacitor. After that, the first-order sigma-delta ADC repeats the sampling and integration processes until the oversampling is completed. The output voltage of the operational amplifier in the last cycle is the residue voltage of the first-order sigma-delta ADC. During the entire operation of the sigma-delta ADC, a serial digital code is generated, and after the conversion is completed, it will be converted into a low-speed low-pass data stream by a digital low-pass filter.

[0035] After the sigma-delta ADC outputs the residue voltage of the last cycle, the cyclic ADC starts to work. In the sampling state, the lower plate of capacitor C 1 is connected to the output terminal of the sub-DAC, and C 3 is connected across both ends of the operational amplifier, and C 2 samples the output voltage of the operational amplifier. In the amplification state, the positions of C 1 and C 2 are interchanged, and the cyclic ADC enters the cycle of sampling and amplification states until all cycles are completed.

[0036] By alternately turning on and off the clock-controlled switches, capacitors C 1 and C 2 alternately sample the residue voltage signal generated in the previous clock cycle, thus realizing the pipelined operation of signal sampling and quantization. After all cycles of quantization are completed, all the digital codes obtained from the cycles are added with dislocation to obtain the low-order parallel output.

[0037] The integrator adopted by the hybrid sigma-delta ADC of the present invention is a switch-capacitor type circuit with upper and lower symmetry. Due to the adoption of the redundant bit correction algorithm, the requirement of the ADC for the comparator accuracy is reduced.

[0038] Among them, the operational amplifier adopts a fully differential folded cascode structure. The 1.5-bit ADC consists of two latch comparators with simple structures and low static power consumption. The 1.5-bit DAC consists of a logic control circuit. The two stages share the same analog circuit block, reducing the area and power consumption.

[0039] The above shows and describes the basic principles, main features and advantages of the present invention. For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic features of the present invention, the present invention can be implemented in other specific forms.

[0040] Therefore, in any case, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Thus, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced by the present invention.

[0041] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A hybrid ADC structure with integrated CDS function, characterized in that: The invention comprises a CDS circuit, a sigma-delta ADC, a cyclic ADC, a digital low-pass filter, an RSD unit and a digital logic correction unit; the voltage signal output end of the CDS circuit is connected to the voltage signal input end of the sigma-delta ADC, the digital code output end of the sigma-delta ADC is connected to the digital code input end of the digital low-pass filter, the digital signal output of the digital low-pass filter is connected to the digital signal input of the digital logic correction unit; the residual voltage output end of the sigma-delta ADC is connected to the residual voltage input end of the cyclic ADC, the output end of the cyclic ADC is connected to the input end of the RSD unit, and the cyclic signal output end of the RSD unit is connected to the cyclic signal input end of the digital logic correction unit.

2. The hybrid ADC structure with integrated CDS function according to claim 1, characterized in that: During the working process, the correlated double sampling operation is first performed by controlling the switch to sample the pixel reset signal and the pixel signal at the same time. The output voltage is sampled and quantized by the sigma-delta ADC. In the subsequent cycle, the sigma-delta ADC samples the voltage difference between the actual voltage value obtained by the control circuit and the expected value output by the previous stage op amp, and performs high-bit conversion to obtain a string of high-bit digital codes and residual voltage. The high-bit digital code is converted into a low-speed low-pass data stream by the digital low-pass filter and then output; the residual voltage is sampled and converted by the cyclic ADC until all low-bit digital codes are obtained, and the digital codes obtained in all cycles are staggered and added to obtain the low-bit parallel output.

3. The hybrid ADC structure with integrated CDS function according to claim 1, characterized in that: The sigma-delta ADC / cyclic ADC includes an operational amplifier, cascaded sub-ADCs and sub-DACs, and a switch Φ 1_1 , Φ 1_2 , Φ2-Φ7, Φ 8_1 , Φ 8_2 , Φ s , Φ s1 , Φ h , Φ h1 , capacitor C s , C1-C3; the positive phase output terminal and negative phase output terminal of the operational amplifier are respectively connected to the switch Φ h One end of the switch Φ h The other end of the switch Φ s One end and switch Φ h1 , one end of capacitor C3, Φ s The other end and the sub-DAC are connected to the reference voltage V ref- , switch Φ h1 The other end is connected to the input of the sub-ADC, the sub-ADC outputs B1 and B0 to the sub-DAC, and the sub-DAC outputs the processed signal; The positive input terminal and negative input terminal of the operational amplifier are connected to switches Φ6, Φ7, Φ s1 The other end of switch Φ6 is connected to one end of switch Φ2 and one end of capacitor C1, and the other end of capacitor C1 is connected to switch Φ4, switch Φ 8_1 , switch Φ 1_1 At one end, switches Φ4 and Φ2 are grounded at the other end; The other end of switch Φ7 is connected to one end of switch Φ3 and one end of capacitor C2, and the other end of capacitor C2 is connected to switch Φ5 and switch Φ 8_2 , switch Φ 1_2 One end, switch Φ 8_2 The other end is connected to the switch Φ 1_1 The other end is connected to V out Connected; switch Φ s1 The other end of the switch Φ h2 One end and capacitor C s One end of the switch Φ h2 The other end of the operational amplifier is connected to the negative input terminal of the capacitor C s The other end is connected to V rst , the capacitor C connected to the non-inverting input of the operational amplifier s The other end is connected to V sig ; The negative input terminal of the operational amplifier is connected to Φ 8-1 , Φ 1-2 The other end is connected to the input signal V DAC+ , the operational amplifier non-inverting input terminal is connected to Φ 8-1 , Φ 1-2 The other end is connected to the input signal V DAC- .

4. The hybrid ADC structure with integrated CDS function according to claim 3, characterized in that: During the operation of the sigma-delta ADC, the switch Φ s , Φ s1 Closed, two identical sampling capacitors C s Complete the pixel reset signal V rst1 and pixel signal V sig1 The two identical holding capacitors C3 respectively complete the sampling of the reference voltage V ref- and V ref+ After that, the switch Φ s Disconnect, Φ h Closed, two sampling capacitors C s Complete the pixel exposure signal V rst3 and pixel signal V sig3 The two holding capacitors C3 are connected across the input and output terminals of the operational amplifier to obtain the output voltage of the operational amplifier after noise elimination. After that, switch Φ s1 Disconnect, Φ h2 and Φ h1 Closed, the sigma-delta ADC starts working.

5. The hybrid ADC structure with integrated CDS function according to claim 4, characterized in that: After the sigma-delta ADC starts working, it enters the sampling state. The comparator unit quantizes the output voltage of the operational amplifier and obtains a feedback voltage through digital-to-analog conversion. 1-1 , Φ 1-2 , Φ2, Φ3 are closed, capacitor C1 samples the output voltage of the op amp after noise elimination, C2 samples the feedback voltage, and C3 is reset; then, switch Φ 1-1 , Φ 1-2 , Φ2, Φ3 are disconnected, Φ4-Φ7 are closed, the sigma-deltaADC enters the integration state, and the charge accumulated on the sampling capacitor is transferred to the integration capacitor; after that, the first-order sigma-delta ADC repeats the sampling and integration process until the oversampling is completed. The output voltage of the operational amplifier in the last cycle is the residual voltage of the first-order sigma-delta ADC; the sigma-delta ADC generates a serial digital code, which is converted into a low-speed low-pass data stream by a digital low-pass filter.

6. The hybrid ADC structure with integrated CDS function according to claim 5, characterized in that: After the Sigma-Delta ADC outputs the residual voltage of the last cycle, the cyclic ADC starts to work. In the sampling state, the output voltage of the operational amplifier is sampled through capacitor C2. In the amplification state, the positions of capacitors C1 and C2 are swapped, and the cyclic ADC enters a cycle of sampling and amplification until all cycles are completed. By alternating the on and off of the clock control switch, capacitors C1 and C2 alternately sample the residual voltage signal generated by the previous clock cycle, thereby realizing the pipeline operation of signal sampling and quantization. After the quantization of all cycles is completed, the digital codes obtained in all cycles are staggered and added to obtain the low-bit parallel output.

7. An image sensor readout circuit, characterized in that: A hybrid ADC structure with integrated CDS function comprising any one of claims 1-6.

8. An image sensor, characterized in that Includes the image sensor readout circuit as claimed in claim 7.

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