Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present disclosure relate to a semiconductor structure and a method for manufacturing the same. The semiconductor structure comprises: a substrate, the substrate having a plurality of active regions spaced apart along a first direction; the substrate further having a plurality of contact holes spaced apart along the first direction, the contact holes exposing adjacent active regions; and a contact structure filled in the contact holes, the contact structure comprising: a first contact structure located above an active region; a first sidewall structure covering at least part of a side surface of the first contact structure; and a second contact structure covering at least part of a side surface of the first sidewall structure, the second contact structure being located between two adjacent active regions, wherein the first contact structure is in electrical contact with one of the adjacent active regions, and the second contact structure is in electrical contact with the other of the adjacent active regions. The semiconductor structure provided by the embodiments of the present disclosure can at least improve the reliability of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] DRAM (Dynamic Random Access Memory) is a common semiconductor memory. The memory includes word lines, bit line structures, and capacitors. The bit line structures and the capacitors are usually connected to transistors through different contact structures for signal transmission.

[0003] In the preparation process of the semiconductor memory, two adjacent contact structures are formed in different contact holes, and the two contact structures respectively form electrical connections between the bit line structure and the capacitor and different active regions. However, as the size of the semiconductor memory becomes smaller, the adjacent contact structures formed in the different contact holes are prone to electrical contact problems, which can cause short circuits and thus reduce the reliability of the semiconductor memory. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, which at least facilitate improving the reliability of the semiconductor structure.

[0005] Embodiments of the present disclosure provide a semiconductor structure, which includes: a substrate, the substrate having a plurality of active regions spaced apart along a first direction; the substrate also having a plurality of contact holes spaced apart along the first direction, the contact holes exposing adjacent active regions; a contact structure filled in the contact hole, the contact structure including: a first contact structure located above the active region; a first side wall structure covering at least part of the side surface of the first contact structure; a second contact structure covering at least part of the side surface of the first side wall structure, and the second contact structure being located between two adjacent active regions, wherein the first contact structure is in electrical contact with one of the adjacent active regions, and the second contact structure is in electrical contact with the other of the adjacent active regions.

[0006] In some embodiments, the contact structure includes: two spaced-apart second contact structures, the two second contact structures being respectively in electrical contact with different active regions.

[0007] In some embodiments, the active region extends along a preset direction, and the active region includes a first source / drain region, a channel region, and a second source / drain region spaced apart along the preset direction, the channel region being located on both sides of the first source / drain region, and the second source / drain region being located on a side of the channel region away from the first source / drain region; the plurality of active regions include: first active regions and second active regions alternately arranged along the first direction; wherein the first contact structure is in electrical contact with the first source / drain region of one of the adjacent first active regions or second active regions, and the second contact structure is in electrical contact with the second source / drain region of the other of the adjacent first active regions or second active regions.

[0008] In some embodiments, the semiconductor structure further includes: a plurality of bit line structures spaced along a third direction on the substrate, the bit line structures extending along a second direction, the first direction, the second direction and the third direction being perpendicular to each other, and the third direction being perpendicular to the second direction; and a plurality of capacitor structures, each capacitor structure being on the substrate and coupled with the second contact structure.

[0009] In some embodiments, a shape of a projection of the contact hole along the second direction is an inverted trapezoid or an ellipse, a shape of a projection of the contact hole along the third direction is a rectangle, and the second contact structure is on a sidewall of the contact hole along the third direction.

[0010] Correspondingly, the disclosure also provides a method for manufacturing a semiconductor structure, including: providing a substrate, a plurality of active regions being spaced along a first direction in the substrate; forming a contact hole in the substrate, a bottom of the contact hole exposing one of the active regions, and a sidewall of the contact hole exposing another of the active regions; forming a second contact structure on a part of the sidewall of the contact hole, the second contact structure being in electrical contact with the active region exposed by the sidewall of the contact hole; forming a first sidewall structure in the contact hole, the first sidewall structure covering at least the second contact structure; and forming a first contact structure filling the remaining contact hole, the first contact structure being above the active region exposed by the bottom of the contact hole and being in electrical contact with the active region.

[0011] In some embodiments, the method for forming the contact hole includes: forming a first mask layer on the substrate; patterning the first mask layer to form a first opening in the first mask layer, the first opening being partially opposite to one of the active regions and partially opposite to another of the active regions; and etching the substrate along the first opening to expose the active regions by using a first etching process to form the contact hole.

[0012] In some embodiments, the method for forming the second contact structure includes: forming an initial second contact structure on the sidewall of the contact hole by using a deposition process, wherein the initial second contact structure covering the sidewall of the contact hole along the third direction has a first thickness, the initial second contact structure covering the sidewall of the contact hole along the second direction has a second thickness, the first thickness is greater than the second thickness, the first direction, the second direction and the third direction being perpendicular to each other, and the third direction being perpendicular to the second direction, and the sidewall of the contact hole along the third direction exposing the active region; and etching the initial second contact structure by using a second etching process to remove all of the initial second contact structure covering the sidewall of the contact hole along the second direction, and to remove part of the initial second contact structure covering the sidewall of the contact hole along the third direction, the remaining initial second contact structure being the second contact structure.

[0013] In some embodiments, before forming the contact hole, further comprising: forming an isolation structure between the adjacent active regions, the formed contact hole exposes the active region and a portion of the isolation structure on both sides of the active region, and the second contact structure is located on the exposed surface of the isolation structure.

[0014] In some embodiments, the first side wall structure comprises a first silicon oxide layer and a first silicon nitride layer stacked in sequence in a direction away from the first contact structure.

[0015] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages:

[0016] In the semiconductor structure provided by the embodiments of the present disclosure, the contact structure filled in the contact hole comprises a first contact structure and a second contact structure. The first contact structure is located above the active region, and the second contact structure is located between the adjacent active regions. The first contact structure is in electrical contact with one of the adjacent active regions, and the second contact structure is in electrical contact with the other of the adjacent active regions. That is, the first contact structure and the second contact structure are respectively in electrical contact with different active regions of the adjacent active regions, so that signals of different active regions can be led out, or external signals can be transmitted to different active regions.

[0017] For example, the first contact structure can form signal transmission between the active region and the bit line structure, and the second contact structure can form signal transmission between the active region and the capacitor.

[0018] Since the first contact structure and the second contact structure are located in the same contact hole, in the actual process of preparing the semiconductor structure, it is not necessary to etch different contact holes in the substrate to form the first contact structure and the second contact structure respectively, thereby avoiding process damage caused by etching different contact holes, so that the first contact structure and the second contact structure are electrically connected, and the reliability of the semiconductor structure is improved.

[0019] The first contact structure and the second contact structure are insulated by the first side wall structure, so as to avoid electrical contact between the first contact structure and the second contact structure and cause short circuit, thereby further improving the reliability of the semiconductor structure.

[0020] The gate structure is located on the substrate of the peripheral region, which can ensure that the process of actually preparing the gate structure has a large process window, so that the morphology of the gate structure meets the expectation and maintains good performance of the gate structure. While ensuring good performance of the gate structure, the parasitic capacitance of the array region is reduced, thereby improving the performance of the semiconductor structure as a whole. BRIEF DESCRIPTION OF DRAWINGS

[0021] One or more embodiments are illustrated by way of example in the drawings and are described herein in connection with the appended drawings, which are not necessarily drawn to scale, where like references numerals designate corresponding parts throughout the drawings and specification, and in which: The drawings are intended to facilitate an understanding of the present disclosure, and are not intended to limit the application in any way. Other embodiments can be utilized, and other changes can be made, without departing from the spirit or scope of the application. It will further be recognized that the drawings are not necessarily drawn to scale and that, where appropriate, certain dimensions can have been exaggerated or minimized to better illustrate certain changes or features.

[0022] Figures 1 to 4 A cross-sectional structure schematic diagram corresponding to different steps in a preparation method of a semiconductor structure;

[0023] Figure 5 A top view of a semiconductor structure according to an embodiment of the present disclosure;

[0024] Figure 6 A cross-sectional structure schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0025] Figure 7 A partial structure top view of a semiconductor structure according to an embodiment of the present disclosure;

[0026] Figure 8 A partial structure top view of another semiconductor structure according to an embodiment of the present disclosure;

[0027] Figure 9 A cross-sectional structure schematic diagram of another semiconductor structure according to an embodiment of the present disclosure;

[0028] Figure 10 A top view of another semiconductor structure according to an embodiment of the present disclosure;

[0029] Figure 11 A cross-sectional structure schematic diagram of yet another semiconductor structure according to an embodiment of the present disclosure;

[0030] Figure 12 A cross-sectional structure schematic diagram of still another semiconductor structure according to an embodiment of the present disclosure, along the direction of aa';

[0031] Figure 13 A cross-sectional structure schematic diagram of still another semiconductor structure according to an embodiment of the present disclosure, along the direction of bb';

[0032] Figures 14 to 35 A cross-sectional structure schematic diagram corresponding to different steps in a preparation method of a semiconductor structure according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] As can be seen from the background art, the reliability of the semiconductor structure needs to be further improved. Analysis shows that one of the reasons for the reliability of the semiconductor structure needing to be further improved is that, at present, different contact structures need to be prepared in different contact holes to respectively form electrical connections between the bit line structure and the capacitor and different active regions.

[0034] As shown in Figure 1 , first, a first contact hole 1 is formed in a substrate 10, the first contact hole 1 exposes an active region at the bottom, and an initial first contact structure 12 is formed, the initial first contact structure 12 is filled in a plurality of first contact holes 1 and is in electrical contact with the active region 11 in the substrate 10.

[0035] After the initial first contact structure 12 is formed, different film layers required for forming the bit line structure are deposited on the top surface of the initial first contact structure 12.

[0036] Then, as shown in Figure 2 , in the same process step, the above-mentioned different film layers and the initial first contact structure 12 are subjected to a patterning etching process to form a mutually separate bit line structure 14 and a first contact structure 13, the first contact structure 13 is located in the first contact hole 1, and the bit line structure 14 is located on the top surface of the first contact structure 13.

[0037] It is worth noting that, due to the increasingly small size of the semiconductor structure, the size of the first contact hole 1 is also increasingly small, and the aspect ratio of the first contact hole 1 is increasingly large, making it difficult to completely etch the initial first contact structure 12 located at the bottom of the first contact hole 1, as shown by the dashed box in Figure 2 , the residual part caused by incomplete etching. The bottom of the formed first contact structure 13 is likely to occupy the entire bottom or nearly the entire bottom of the first contact hole 1. Or, due to the incomplete alignment of the overlay mark in the patterning process, an etching deviation is caused, making the space on one side of the first contact structure 13 very narrow, thereby making it more difficult to completely etch the bottom of the first contact structure 13 on the narrow side.

[0038] As shown in Figure 3 , a side wall structure 15 is formed on the side wall of the bit line structure 14 and the first contact structure 13. Since the bottom of the first contact structure 13 occupies the entire bottom or nearly the entire bottom of the first contact hole 1, the side wall structure 15 cannot be in contact with the bottom of the first contact hole 1, that is, the side wall structure 15 is formed on the top surface of the residual part in the dashed box, but cannot be formed on the side surface of the residual part, and thus cannot provide protection for the side surface of the residual part.

[0039] Then, as shown in Figure 4As shown, the partial substrate 10 and the partial sidewall structure 15 in the first contact hole 1 are etched to form a second contact hole 2 adjacent to the first contact hole 1. Since the sidewall structure is formed on the top surface of the residual portion in the dashed box, the sidewall structure cannot protect the side surface of the residual portion. Therefore, during the etching of the sidewall structure 15 in the first contact hole 1, the sidewall structure 15 on the top surface of the residual portion in the dashed box is easily etched through, and the bottom of the first contact structure 13 in the dashed box is exposed. After the second contact structure 16 is formed in the second contact hole 2, the second contact structure 16 will be electrically connected with the exposed bottom of the first contact structure 15, and a short circuit problem will occur, as shown in the dashed box in FIG. 1C. Figure 4 The reliability of the semiconductor structure is reduced.

[0040] The semiconductor structure provided by the embodiment of the present disclosure has the advantages that since the first contact structure and the second contact structure are located in the same contact hole, during the actual preparation of the semiconductor structure, different contact holes do not need to be etched in the substrate to form the first contact structure and the second contact structure, respectively, and the process damage caused by etching different contact holes is avoided, so that the first contact structure and the second contact structure are electrically connected, and the reliability of the semiconductor structure is improved. The first sidewall structure is formed between the first contact structure and the second contact structure to insulate the first contact structure and the second contact structure, so that the first contact structure and the second contact structure are not electrically connected, and the reliability of the semiconductor structure is further improved.

[0041] The embodiments of the present disclosure will be described in detail below with reference to the drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to make the readers better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0042] Figure 5 a top view of a semiconductor structure provided by an embodiment of the present disclosure, Figure 5 the dashed box in FIG. 1A represents a contact hole; Figure 6 a sectional structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure, Figure 6 is a sectional structure schematic diagram in the aa' direction, which can refer to the direction shown in FIG. 1A. Figure 5

[0043] Reference is made to Figure 5 and Figure 6 ​The semiconductor structure comprises: a substrate 100, the substrate 100 having a plurality of active regions 101 arranged at intervals along a first direction X; and a plurality of contact holes 103 arranged at intervals along the first direction X in the substrate 100, the contact holes 103 exposing adjacent active regions 101. The semiconductor structure further comprises: a contact structure filled in the contact hole 103, the contact structure comprising: a first contact structure 104 located above the active region 101; a first side wall structure 105 covering at least part of the side surface of the first contact structure 104; and a second contact structure 106 covering at least part of the side surface of the first side wall structure 105, the second contact structure 106 being located between two adjacent active regions 101, wherein the first contact structure 104 is in electrical contact with one of the adjacent active regions 101, and the second contact structure 106 is in electrical contact with the other of the adjacent active regions 101.

[0044] The first contact structure 104 is located above the active region 101 and is in electrical contact with the top of the active region 101. The second contact structure 106 is located between the adjacent active regions 101 along the first direction X, and the first contact structure 104 is in electrical contact with one of the adjacent active regions 101, and the second contact structure 106 is in electrical contact with the other of the adjacent active regions 101. That is, the first contact structure 104 and the second contact structure 106 are respectively in electrical contact with different active regions 101 of the adjacent active regions 101, so as to be able to lead out the signals of different active regions 101 or transmit external signals to different active regions 101.

[0045] In some embodiments, the first contact structure 104 can form signal transmission between the active region 101 and the bit line structure, and the second contact structure 106 can form signal transmission between the active region 101 and the capacitor.

[0046] The first contact structure 104 and the second contact structure 106 are both located in the same contact hole 103, so that, in the actual process of preparing the semiconductor structure, it is not necessary to etch different contact holes 103 in the substrate 100 to form the first contact structure 104 and the second contact structure 106 respectively, thereby avoiding the process damage caused by etching different contact holes 103 to cause the first contact structure 104 and the second contact structure 106 to be electrically connected, and further improving the reliability of the semiconductor structure.

[0047] In addition, since the first side wall structure 105 covers at least part of the side surface of the first contact structure 104, and the second contact structure 106 covers at least part of the side surface of the first side wall structure 105, insulation is formed between the first contact structure 104 and the second contact structure 106 through the first side wall structure 105, thereby avoiding the problem of short circuit caused by electrical contact between the first contact structure 104 and the second contact structure 106, and further improving the reliability of the semiconductor structure.

[0048] In some embodiments, the material of the substrate 100 can be a semiconductor material. In some embodiments, the material of the substrate 100 can be silicon. In some embodiments, the substrate 100 can also be germanium, silicon germanium, or silicon on insulator.

[0049] Referring to Figure 5 , Figure 7 and Figure 8 , in some embodiments, the active region 101 extends along a preset direction W, the active region 101 includes a first source-drain region 111, a channel region 113, and a second source-drain region 112 arranged at intervals along the preset direction W, the channel region 113 is located on both sides of the first source-drain region 111, and the second source-drain region 112 is located on a side of the channel region 113 away from the first source-drain region 111; a plurality of active regions 101 includes a first active region 1011 and a second active region 1012 arranged alternately along a first direction X; wherein the first contact structure 104 is in electrical contact with the first source-drain region 111 of one of the adjacent first active region 1011 or the second active region 1012, and the second contact structure 106 is in electrical contact with the second source-drain region 112 of the other of the adjacent first active region 1011 or the second active region 1012.

[0050] That is, for an active region 101, the number of first source-drain regions 111 is 1, the number of channel regions 113 is 2, which are respectively located on both sides of the first active region 1011, and the number of second source-drain regions 112 is 2, which are respectively located on both sides of the channel region 113 away from the first source-drain region 111.

[0051] One first source-drain region 111, one channel region 113, and one second source-drain region 112 can form one transistor, and since the number of channel regions 113 and the number of second source-drain regions 112 in one active region 101 are both 2, one active region 101 can form two transistors. The two transistors share the same first source-drain region 111.

[0052] In some embodiments, the first source-drain region 111 can be used as a transistor source, and the second source-drain region 112 can be used as a transistor drain.

[0053] In some embodiments, the first source-drain region 111 and the second source-drain region 112 can be doped with the same type of ion, and the channel region 113 can be doped with a different type of ion than the first source-drain region 111 and the second source-drain region 112. For example, the first source-drain region 111 and the second source-drain region 112 can both be doped with N-type ions, and the channel region 113 can be doped with P-type ions, and the transistor formed by the active region 101 can be an NMOS transistor. For another example, the first source-drain region 111 and the second source-drain region 112 can both be doped with P-type ions, and the channel region 113 can be doped with N-type ions, and the transistor formed by the active region 101 can be a PMOS transistor.

[0054] In some embodiments, the N-type ion can be any one of a phosphorus ion, a bismuth ion, an antimony ion, or an arsenic ion.

[0055] In some embodiments, the P-type ion can be any one of a boron ion, an aluminum ion, a gallium ion, or an indium ion.

[0056] The first active region 1011 and the second active region 1012 are the same active region 101. In order to distinguish the adjacent two active regions 101, the adjacent active regions 101 are respectively named as the first active region 1011 and the second active region 1012 arranged alternately. That is, the active regions 101 arranged at intervals along the first direction X include the first active region 1011, the second active region 1012, the first active region 1011, the second active region 1012, …, the first active region 1011, and the second active region 1012 arranged alternately along the first direction X.

[0057] The first contact structure 104 can be in electrical contact with the first source-drain region 111 of the first active region 1011 of the adjacent two active regions 101, and the second contact structure 106 can be in electrical contact with the second source-drain region 112 of the second active region 1012 of the adjacent two active regions 101. If the first source-drain region 111 is the source of the transistor, and the second source-drain region 112 is the drain of the transistor, then the first contact structure 104 is used to transmit the source signal of the first active region 1011, and the second contact structure 106 is used to transmit the drain signal of the second active region 1012. That is, the first contact structure 104 and the second contact structure 106 respectively transmit different signals of the adjacent two active regions 101.

[0058] In some embodiments, the contact structure includes two spaced-apart second contact structures 106, and the two second contact structures 106 are respectively in electrical contact with different active regions 101.

[0059] In some embodiments, the two second contact structures 106 can be respectively located on two sides of the first contact structure 104.

[0060] In some embodiments, the active regions 101 arranged along the first direction X include: a first active region 1011, a second active region 1012, a first active region 1011, a second active region 1012, …, a first active region 1011, a second active region 1012, which are arranged alternately along the first direction X. The first contact structure 104 is located above and in electrical contact with the first active region 1011. One of the two second contact structures 106 can be in electrical contact with one of the second active regions 1012 adjacent to the first active region 1011, and the other of the two contact structures can be in electrical contact with the other of the second active regions 1012 adjacent to the first active region 1011.

[0061] In a specific example, the first contact structure 104 is in electrical contact with the first source / drain region 111 of the first active region 1011, one of the second contact structures 106 is in electrical contact with the second source / drain region 112 of one of the second active regions 1012 adjacent to the first active region 1011, and the other of the second contact structures 106 is in electrical contact with the second source / drain region 112 of the other of the second active regions 1012 adjacent to the first active region 1011.

[0062] More specifically, the two second source / drain regions 112 in each active region 101 are located at opposite ends of the active region 101, respectively, and are referred to as a head second source / drain region and a tail second source / drain region to distinguish the different end positions of the two second source / drain regions 112. The first contact structure 104 is in electrical contact with the first source / drain region 111 of the first active region 1011, one of the second contact structures 106 is in electrical contact with the head second source / drain region of one of the second active regions 1012 adjacent to the first active region 1011, and the other of the second contact structures 106 is in electrical contact with the tail second source / drain region of the other of the second active regions 1012 adjacent to the first active region 1011.

[0063] In some embodiments, the contact structure can also include only one second contact structure 106. For the same contact structure, if the first contact structure 104 is in electrical contact with the first active region 1011, the second contact structure 106 is only in electrical contact with one of the second active regions 1012 adjacent to the first active region 1011, and is not in electrical contact with the other of the second active regions 1012 adjacent to the first active region 1011.

[0064] It can be understood that, regardless of the number of second contact structures 106, each second contact structure 106 is isolated from the first contact structure 104 by the first side wall structure 105.

[0065] Reference Figure 7In some embodiments, the first sidewall structure 105 can surround the entire side of the first contact structure 104, and the second contact structure 106 only covers part of the side of the first sidewall structure 105.

[0066] Reference is made to Figure 8 In some embodiments, the first sidewall structure 105 can also only cover part of the side of the first contact structure 104, and the second contact structure 106 is only located on the surface of the first sidewall structure 105, so that the first sidewall structure 105 functions to isolate the first contact structure 104 from the second contact structure 106, avoiding the problem of electrical connection between the first contact structure 104 and the second contact structure 106 causing short circuit.

[0067] In some embodiments, the contact hole 103 extends in a direction pointing into the substrate 100 from the surface of the substrate 100. In the extension direction of the contact hole 103, the heights of the first sidewall structure 105, the first contact structure 104, and the second contact structure 106 are the same, and the top surfaces of the first sidewall structure 105, the first contact structure 104, and the second contact structure 106 are flush with the opening of the contact hole 103, and the bottom surfaces of the first sidewall structure 105, the first contact structure 104, and the second contact structure 106 are flush with the bottom of the contact hole 103.

[0068] In some embodiments, the material of the first contact structure 104 can include any one of polysilicon, amorphous silicon, or microcrystalline silicon. The material of the second contact structure 106 can include any one of polysilicon, amorphous silicon, or microcrystalline silicon.

[0069] Figure 9 Another schematic diagram of a cross-sectional structure of a semiconductor structure is provided for an embodiment of the present disclosure, Figure 9 is a schematic diagram of a cross-sectional structure in the aa' direction, which can refer to the direction shown in Figure 5 .

[0070] Reference is made to Figure 9 In some embodiments, the first sidewall structure 105 can be a double-layer structure, including a first silicon oxide layer 1051 and a first silicon nitride layer 1052 stacked in sequence in a direction away from the first contact structure 104. The material of the first silicon oxide layer 1051 includes silicon oxide, and the material of the first silicon nitride layer 1052 includes silicon nitride.

[0071] In some embodiments, the first sidewall structure 105 can also be a triple-layer structure, including a first silicon oxide layer and first silicon nitride layers located on both sides of the first silicon oxide layer. Specifically, the triple-layer structure is a first silicon nitride layer, a first silicon oxide layer, and a first silicon nitride layer stacked in sequence in a direction away from the first contact structure 104. The material of the first silicon nitride layer includes silicon nitride, and the material of the first silicon oxide layer includes silicon oxide.

[0072] It is worth noting that, no matter whether the first side wall structure 105 is a double-layer structure or a three-layer structure, the total thickness is the same or close, so that the overall size of the contact hole 103 can be kept small.

[0073] In some embodiments, the semiconductor structure can further include an isolation structure 102 between the adjacent active regions 101, for isolating the adjacent active regions 101. The first contact structure 104 is on the top surface of the active region 101, and the second contact structure 106 can be on the top surface of the isolation structure 102 between the adjacent active regions 101. In some embodiments, the material of the isolation structure 102 can be silicon oxide.

[0074] Reference Figures 10 to 11 In some embodiments, the semiconductor structure further includes a plurality of bit line structures 107 spaced apart along a third direction Z on the substrate 100, the bit line structure 107 extending along a second direction Y, the first direction X, the second direction Y and the third direction Z intersecting each other, and the third direction Z being perpendicular to the second direction Y; and a plurality of capacitor structures, each capacitor structure being on the substrate 100 and coupled with the second contact structure 106.

[0075] The substrate 100 includes an array of active regions 101, the active regions 101 being spaced apart along a first direction X and a second direction Y, wherein each row of active regions 101 is spaced apart along the first direction X, each column of active regions 101 is spaced apart along the second direction Y, and a plurality of columns of active regions 101 are spaced apart along a third direction Z. A plurality of bit line structures 107 spaced apart along the third direction Z correspond to the plurality of columns of active regions 101 one-to-one, and each bit line structure 107 is coupled with the first source / drain region 111 of each active region 101 in each column of active regions 101 through the first contact structure 104.

[0076] In some embodiments, the bit line structure 107 can include a bit line blocking layer 121, a bit line conductive layer 122 and a bit line cap layer 123 stacked in sequence in a direction away from the surface of the substrate 100.

[0077] The bit line blocking layer 121 covers the top surface of the first contact structure 104 and is between the first contact structure 104 and the bit line conductive layer 122, for preventing the mutual diffusion of ions in the first contact structure 104 and the bit line conductive layer 122. The material of the bit line blocking layer 121 can include any one of titanium nitride, tantalum, tantalum nitride or tungsten nitride.

[0078] The bit line conductive layer 122 mainly serves as a conductive function for transmitting electrical signals, and the material of the bit line conductive layer 122 can include a metal material, for example, at least one of tungsten, titanium or nickel.

[0079] The bit line cap layer 123 is used to protect the bit line conductive layer 122. In some embodiments, the material of the bit line cap layer 123 can include any one of silicon nitride or silicon oxynitride.

[0080] Referring to Figure 11 In some embodiments, the semiconductor structure further includes: a second side wall structure 108, the second side wall structure 108 being located on opposite two sidewalls of the bit line structure 107 in the first direction X, i.e. covering the sidewalls of the bit line blocking layer 121, the bit line conductive layer 122 and the bit line cap layer 123 in the first direction X.

[0081] In some embodiments, the second side wall structure 108 can be a double-layer structure, including: a second silicon oxide layer 1081 and a second silicon nitride layer 1082 stacked in sequence in a direction away from the bit line structure 107.

[0082] In some embodiments, the second side wall structure 108 can also be a triple-layer structure, including: a second silicon oxide layer and two second silicon nitride layers, specifically: a second silicon nitride layer, a second silicon oxide layer and a second silicon nitride layer stacked in sequence in a direction away from the bit line structure 107.

[0083] The material of the second side wall structure 108 can be the same as the material of the first side wall structure 105. In other words, the first side wall structure 105 and the second side wall structure 108 can both be the above-mentioned double-layer structure, or both be the above-mentioned triple-layer structure. The thickness of the first silicon oxide layer 1051 in the first side wall structure 105 can be the same as or close to the thickness of the second silicon oxide layer in the second side wall structure 108. The thickness of the first silicon nitride layer 1052 in the first side wall structure 105 can be the same as or close to the thickness of the second silicon nitride layer in the second side wall structure 108.

[0084] The number of the capacitor structures can be multiple, and each capacitor structure is coupled with the second source / drain region 112 of each active region 101.

[0085] Referring to Figure 11 In some embodiments, the semiconductor structure can further include: a capacitor contact plug 110, the capacitor contact plug 110 being located between two adjacent bit line structures 107 in the first direction X on the substrate 100. The bottom surface of the capacitor contact plug 110 is in contact with the top surface of the second contact structure 106, and the capacitor structure is located on the top surface of the capacitor contact plug 110 and is coupled with the active region 101 through the capacitor contact plug 110 and the second contact structure 106.

[0086] In some embodiments, the material of the capacitor contact plug 110 can be the same as the material of the second contact structure 106, for example, can be polysilicon.

[0087] It can be understood that, since the first contact structure 104 and the second contact structure 106 are located in the same contact hole 103, in an actual manufacturing process, the first contact structure 104 and the second contact structure 106 can be manufactured in the contact hole 103 first, and then the bit line structure 107 and the capacitor contact plug 110 are sequentially formed, so that the bit line structure 107 is in contact with the first contact structure 104, and the capacitor contact plug 110 is in contact with the second contact structure 106. In this way, the first contact structure 104 and the bit line structure 107 are formed in different steps, which can avoid the problem of incomplete etching of the first contact structure 104 due to etching of the bit line structure 107 and the first contact structure 104 at the same time, and further avoid the short circuit problem in the related art.

[0088] Figure 12 Another schematic view of a cross section structure of a semiconductor structure along the aa' direction is provided for an embodiment of the present disclosure, specifically a schematic view of a cross section structure along the aa' direction in Figure 10 Figure 13 Another schematic view of a cross section structure of a semiconductor structure along the bb' direction is provided for an embodiment of the present disclosure, specifically a schematic view of a cross section structure along the bb' direction in Figure 10 The aa' direction shown in the embodiment of the present disclosure is consistent with the extension direction of the third direction, and the bb' direction shown in the embodiment of the present disclosure is consistent with the extension direction of the second direction.

[0089] Referring to Figure 10 and Figure 13 In some embodiments, the semiconductor structure further includes: a plurality of word lines 109, the word lines 109 being located in the substrate 100 and forming a buried word line. The plurality of word lines 109 are arranged at intervals along the second direction Y, each word line 109 extends along the third direction Z, and the word line 109 is electrically connected to the channel region 113 of the active region 101. Among them, the two channel regions 113 of each active region 101 are respectively electrically connected to two word lines 109.

[0090] The word line 109 can include a word line conductive layer 131, a word line barrier layer 132 and a word line cap layer 133 stacked in sequence, the word line barrier layer 132 is located on the top surface of the word line conductive layer 131, and the word line cap layer 133 is located on the top surface of the word line conductive layer 131. The material of the word line barrier layer 132 can include any one of titanium nitride, tantalum, tantalum nitride or tungsten nitride. The material of the word line conductive layer 131 can include a metal material, for example, can be at least one of tungsten, titanium or nickel and the like. The material of the word line cap layer 133 can include any one of silicon nitride or silicon oxynitride.

[0091] Referring to Figure 6 , Figure 9 and Figure 12 Among them, Figure 6 , Figure 9 ​and Figure 12 are schematic diagrams of cross-sectional structures along the aa’ direction. In some embodiments, the contact hole 103 has a shape of an inverted trapezoid or an ellipse in the orthographic projection along the second direction Y.

[0092] Referring to Figure 13 , Figure 13 is a schematic diagram of a cross-sectional structure along the bb’ direction. In some embodiments, the contact hole 103 has a shape of a rectangle in the orthographic projection along the third direction Z, and the second contact structure 106 is located on the sidewall of the contact hole 103 along the third direction Z.

[0093] The contact holes 103 are arranged in an array in the substrate 100, and the contact holes 103 are arranged at intervals along the first direction X and the second direction Y. Each row of the contact holes 103 is arranged at intervals along the first direction X, and each column of the contact holes 103 is arranged at intervals along the second direction Y. Each contact hole 103 corresponds to an active region 101, that is, the contact structure in each contact hole 103 corresponds to an active region 101.

[0094] That is, the contact hole 103 has a shape of an inverted trapezoid or an ellipse in the orthographic projection along the extension direction of the bit line structure 107, and the contact hole 103 has a shape of a rectangle in the orthographic projection along the arrangement direction of the bit line structure 107. That is, the sidewall of the contact hole 103 along the extension direction of the bit line structure 107 is perpendicular to the surface of the substrate 100, the sidewall of the contact hole 103 along the arrangement direction of the bit line structure 107 is inclined to the surface of the substrate 100, and the sidewall of the contact hole 103 along the arrangement direction of the bit line structure 107 exposes the active region 101. Since the second contact structure 106 is formed on the sidewall of the contact hole 103, in the step of actually forming the second contact structure 106, the material layer of the second contact structure 106 is first deposited on the entire sidewall of the contact hole 103. The thickness of the material layer of the second contact structure 106 deposited on the vertical sidewall of the contact hole 103 is smaller than the thickness of the material layer of the second contact structure 106 deposited on the inclined sidewall. In the subsequent step of continuing to etch the material layer of the second contact structure 106 on the sidewall of the contact hole 103, after the material layer on the vertical sidewall of the contact hole 103 is etched completely, the material layer on the inclined sidewall of the contact hole 103 still remains, that is, the material layer on the sidewall of the contact hole 103 along the arrangement direction of the bit line structure 107 which is not etched away can be used as the final second contact structure 106, so that the second contact structures 106 on the opposite two sidewalls of the contact hole 103 along the arrangement direction of the bit line structure 107 are separated from each other and respectively electrically contact two active regions 101.

[0095] It is worth noting that the shape of the orthogonal projection of the contact hole 103 along the extending direction of the bit line structure 107 is an inverted trapezoid or an ellipse, and the shape of the orthogonal projection of the contact hole 103 along the arrangement direction of the bit line structure 107 is a rectangle, both of which refer to the shape of the orthogonal projection of the contact hole 103 in the substrate 100.

[0096] In the semiconductor structure provided by the above embodiment, the first contact structure 104 and the second contact structure 106 are both located in the same contact hole 103, and in the actual process of preparing the semiconductor structure, different contact holes 103 do not need to be etched in the substrate 100 to form the first contact structure 104 and the second contact structure 106, respectively, so as to avoid the process damage caused by etching different contact holes 103, so that the first contact structure 104 and the second contact structure 106 are electrically connected, thereby improving the reliability of the semiconductor structure. The first contact structure 104 and the second contact structure 106 are insulated by the first side wall structure 105, so as to avoid the electrical contact between the first contact structure 104 and the second contact structure 106, thereby avoiding short circuit, and further improving the reliability of the semiconductor structure.

[0097] Correspondingly, the disclosure also provides a preparation method of a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiment. The semiconductor structure provided by an embodiment of the disclosure will be described in detail below with reference to the drawings. It is worth noting that the aa' direction and the bb' direction mentioned below can refer to the aa' direction and the bb' direction shown in FIG. 1. Figure 5 Or Figure 10

[0098] Referring to Figures 14 to 35 , the preparation method of the semiconductor structure comprises:

[0099] Referring to Figure 14 , a substrate 100 is provided, and a plurality of active regions 101 are formed in the substrate 100 and arranged at intervals along a first direction X.

[0100] In some embodiments, the material of the substrate 100 can be a semiconductor material. In some embodiments, the material of the substrate 100 can be silicon. In some embodiments, the substrate 100 can also be germanium, germanium silicon or silicon on insulator.

[0101] In some embodiments, the method of forming the active region 101 comprises:

[0102] ​An initial substrate is provided, which is a substrate without doping and etching. A patterning process is performed on the surface of the initial substrate for the positions of the active regions 101. In some embodiments, either a SADP (Self-aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process can be used to perform the patterning process on the surface of the initial substrate. Then, an etching process is performed on the patterned surface of the initial substrate to etch a partial thickness of the initial substrate to form a plurality of spaced-apart trenches in the substrate 100 and the active regions 101 separated by the trenches. In some embodiments, the etching process can be either a dry etching process or a wet etching process.

[0103] In some embodiments, the active regions 101 extend along a preset direction W (refer to FIG. 1A) and each of the active regions 101 includes a first source-drain region 111 (refer to FIG. 1A), a channel region 113 (refer to FIG. 1A) and a second source-drain region 112 (refer to FIG. 1A) spaced apart along the preset direction W, the channel region 113 is located on both sides of the first source-drain region 111, and the second source-drain region 112 is located on a side of the channel region 113 away from the first source-drain region 111. Figure 7 ) extend along a preset direction W (refer to Figure 7 ) and each of the active regions 101 includes a first source-drain region 111 (refer to Figure 7 ) spaced apart along the preset direction W, the channel region 113 is located on both sides of the first source-drain region 111, and the second source-drain region 112 is located on a side of the channel region 113 away from the first source-drain region 111. Figure 7

[0104] For one active region 101, the number of the first source-drain region 111 is 1, the number of the channel region 113 is 2, which are located on both sides of the first active region 1011, and the number of the second source-drain region 112 is 2, which are located on both sides of the channel region 113 away from the first source-drain region 111.

[0105] 1 first source-drain region 111, 1 channel region 113 and 1 second source-drain region 112 can form 1 transistor, and since the number of the channel region 113 and the number of the second source-drain region 112 in one active region 101 are both 2, one active region 101 can form 2 transistors. The two transistors share the same first source-drain region 111.

[0106] Refer to Figure 14 , Figure 14 is a schematic diagram of a cross-sectional structure along the aa' direction. In some embodiments, the method for manufacturing a semiconductor structure further includes forming an isolation structure 102 between adjacent active regions 101.

[0107] ​In some embodiments, an isolation material can be deposited in the trench to form an isolation structure 102 filling the trench. In some embodiments, the isolation structure 102 can be formed by any of an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the isolation structure 102 can be silicon oxide.

[0108] In some embodiments, after the active region 101 is formed, a doping process can be performed on the active region 101 to form a first source-drain region 111, a channel region 113, and a second source-drain region 112.

[0109] In some embodiments, the first source-drain region 111 and the second source-drain region 112 can have the same type of doping ions, and the channel region 113 can have a different type of doping ions from the first source-drain region 111 and the second source-drain region 112. For example, the first source-drain region 111 and the second source-drain region 112 can both have N-type doping ions, and the N-type doping ions can be any of phosphorus ions, bismuth ions, antimony ions, or arsenic ions. The channel region 113 can have P-type doping ions, and the P-type doping ions can be any of boron ions, aluminum ions, gallium ions, or indium ions.

[0110] In some embodiments, the doping process can be an ion implantation process.

[0111] Reference Figure 15 , Figure 15 FIG. 6 is a schematic view of a cross-sectional structure along the direction of bb’, after the active region 101 is formed, a plurality of buried word lines 109 can be formed in the substrate 100. The plurality of word lines 109 are arranged at intervals along a second direction Y, and each word line 109 extends along a third direction Z. The word line 109 is electrically connected to the channel region 113 of the active region 101. Specifically, the two channel regions 113 of each active region 101 are respectively electrically connected to two word lines 109. The first direction X, the second direction Y, and the third direction Z are perpendicular to each other, and the third direction Z is perpendicular to the second direction Y.

[0112] The word line 109 can include a word line conductive layer 131, a word line barrier layer 132, and a word line cap layer 133 stacked in sequence. The word line barrier layer 132 is located on the top surface of the word line conductive layer 131, and the word line cap layer 133 is located on the top surface of the word line conductive layer 131. The material of the word line barrier layer 132 can include any of titanium nitride, tantalum, tantalum nitride, or tungsten nitride. The material of the word line conductive layer 131 can include a metal material, for example, at least one of tungsten, titanium, or nickel. The material of the word line cap layer 133 can include any of silicon nitride or silicon oxynitride.

[0113] The embodiments of the present disclosure do not excessively describe the method of forming the word line 109, and any method capable of forming a buried word line can be used to form the word line 109 in the embodiments of the present disclosure.

[0114] Reference Figures 16 to 18 , Figure 16 With Figure 17 a cross-sectional structure schematic diagram in the aa' direction, Figure 18 a cross-sectional structure schematic diagram in the bb' direction. After forming the word line 109, the contact hole 103 is formed in the substrate 100, the bottom of the contact hole 103 exposes one of the adjacent active regions 101, and the sidewall of the contact hole 103 exposes another of the adjacent active regions 101.

[0115] In some embodiments, the method of forming the contact hole 103 includes:

[0116] First, a first mask layer is formed on the substrate 100. Before forming the first mask layer, a first interlayer dielectric layer 141 and a second interlayer dielectric layer 142 can be formed on the substrate 100, the material of the first interlayer dielectric layer 141 can include silicon nitride, and the material of the second interlayer dielectric layer 142 can include silicon oxide.

[0117] The first mask layer is formed on the top surface of the second interlayer dielectric layer 142, and the material of the second mask layer can be photoresist.

[0118] Then, the first mask layer is patterned to form a first opening in the first mask layer, the first opening is partially opposite to one of the adjacent active regions 101, and the first opening is also partially opposite to another of the adjacent active regions 101.

[0119] Specifically, the active regions 101 arranged at intervals along the first direction X include: first active regions 1011 (reference Figure 7 ) and second active regions 1012 (reference Figure 7 ) arranged alternately along the first direction X, first active regions 1011, second active regions 1012, …, first active regions 1011, second active regions 1012.

[0120] The first opening and the active regions 101 are described by taking three active regions 101 as an example, the three active regions 101 are: a first active region 1011 and two second active regions 1012 adjacent to the first active region 1011. Among them, the first opening is opposite to the first source / drain region 111 of the first active region 1011, and the first opening is opposite to the second source / drain region 112 of the two second active regions 1012, respectively. In this way, after subsequently etching the second interlayer dielectric layer 142, the first interlayer dielectric layer 141 and the substrate 100 along the first opening, the active regions 101 opposite to the first opening can be exposed.

[0121] Referring to Figures 16 to 18 The first etching process is used to etch the substrate 100 along the first opening to expose the active region 101, thereby forming the contact hole 103.

[0122] Specifically, the active regions 101 arranged along the first direction X include: the first active region 1011, the second active region 1012, the first active region 1011, the second active region 1012, …, the first active region 1011, and the second active region 1012, which are arranged alternately along the first direction X.

[0123] The relationship between the first opening and the contact hole 103 is described by taking three active regions 101 as an example, which are: the first active region 1011 and two second active regions 1012 adjacent to the first active region 1011. The bottom of the contact hole 103 exposes the first source / drain region 111 of the first active region 1011, and the opposite two sidewalls of the contact hole 103 respectively expose the second source / drain region 112 of the two second active regions 1012.

[0124] Referring to Figure 18 In some embodiments, the sidewall of the contact hole 103 in the second direction Y can expose the word line cap layer 133 in the word line 109 adjacent along the second direction Y, and the sidewall of the contact hole 103 in the third direction Z can expose the second active region 1012.

[0125] Referring to Figure 16 And Figure 17 In some embodiments, the shape of the contact hole 103 in the second direction Y is an inverted trapezoid or an ellipse; referring to Figure 18 The shape of the contact hole 103 in the third direction Z is a rectangle, and the sidewall of the contact hole 103 in the third direction Z exposes the active region 101.

[0126] It is worth noting that the shape of the contact hole 103 in the direction extending along the bit line structure 107 is an inverted trapezoid or an ellipse, and the shape of the contact hole 103 in the direction along the arrangement of the bit line structure 107 is a rectangle, both of which refer to the shape of the contact hole 103 in the substrate 100.

[0127] In some embodiments, the first etching process can include a dry etching process. Specifically, the etching gas used in the first etching process can include chlorine, tetrafluoromethane, difluoromethane, and argon. The gas flow of chlorine can be 5-30 sccm, the gas flow of tetrafluoromethane can be 20-100 sccm, the gas flow of difluoromethane can be 1-10 sccm, and the gas flow of argon can be 100-300 sccm. The reaction gas pressure of the first etching process can be 5-15 mTorr. The radio frequency power of the first etching process can be 600-1200 W. Under the above process conditions, the first etching process can etch the active region exposed by the first opening, and the active region exposed by the sidewall of the contact hole 103 obtained by etching has an area of a desired size, so that the second contact structure formed on the sidewall of the contact hole 103 in the subsequent process has a larger contact area with the active region, thereby ensuring good electrical contact performance between the second contact structure and the active region.

[0128] Reference Figures 19 to 21 , Figure 19 is a schematic view of a cross-sectional structure in the aa' direction, Figure 20 is a schematic view of a cross-sectional structure in the bb' direction, Figure 21 is a schematic view of a cross-sectional structure in the aa' direction. After the formation of the contact hole 103, a second contact structure 106 is formed on part of the sidewall of the contact hole 103, and the second contact structure 106 is in electrical contact with the active region 101 exposed by the sidewall of the contact hole 103.

[0129] In some embodiments, the method for forming the second contact structure 106 includes:

[0130] Reference Figures 19 to 20 , using a deposition process to form an initial second contact structure 30 on the sidewall of the contact hole 103, wherein the initial second contact structure 30 covering the sidewall of the contact hole 103 in the third direction Z has a first thickness, the initial second contact structure 30 covering the sidewall of the contact hole 103 in the second direction Y has a second thickness, the first thickness is greater than the second thickness, and the sidewall of the contact hole 103 in the third direction Z exposes the active region 101.

[0131] Reference Figure 19 In some embodiments, the shape of the orthographic projection of the contact hole 103 along the second direction Y is an inverted trapezoid or an ellipse. Reference Figure 20 The shape of the orthographic projection of the contact hole 103 along the third direction Z is a rectangle. That is, the sidewall of the contact hole 103 in the second direction Y is perpendicular to the surface of the substrate 100, that is, a vertical surface (reference Figure 20 The sidewall of the contact hole 103 in the third direction Z is inclined to the surface of the substrate 100, that is, an inclined surface (reference Figure 19), and the sidewall of the contact hole 103 in the third direction Z exposes the active region 101. Compared with the vertical surface, the initial second contact structure 30 is easier to be deposited on the inclined surface, and thus, the initial second contact structure 30 is deposited on the sidewall of the contact hole 103 in the third direction Z with a thickness greater than the thickness of the initial second contact structure 30 deposited on the sidewall of the contact hole 103 in the second direction Y.

[0132] The initial second contact structure 30 is not only deposited on the sidewall of the contact hole 103, but also partially above the opening of the contact hole 103, and the initial second contact structure 30 above the opening of the contact hole 103 is deposited on the top surface of the second interlayer dielectric layer 142, and part of the initial second contact structure 30 is also deposited on the bottom surface of the contact hole 103.

[0133] In some embodiments, the initial second contact structure 30 can be formed by an atomic layer deposition process, and the material of the initial second contact structure 30 can be polysilicon.

[0134] In some embodiments, the bottom of the contact hole 103 exposes the active region 101 and part of the isolation structure 102 on both sides of the active region 101, and the initial second contact structure 30 covers the top surface of the active region 101 and part of the isolation structure 102 on both sides of the active region 101.

[0135] Referring to Figure 21 , the initial second contact structure 30 is etched by a second etching process to remove all the initial second contact structure 30 covering the sidewall of the contact hole 103 in the second direction Y, and to remove part of the initial second contact structure 30 covering the sidewall of the contact hole 103 in the third direction Z, and the remaining initial second contact structure 30 serves as the second contact structure 106. Since the first thickness is greater than the second thickness, when the layer of the initial second contact structure 30 on the sidewall of the contact hole 103 in the second direction Y is etched completely, the initial second contact structure 30 on the sidewall of the contact hole 103 in the third direction Z still remains. In this way, the second contact structure 106 is only located on part of the sidewall of the contact hole 103, and the second contact structures 106 on the opposite two sidewalls of the contact hole 103 in the third direction Z are separated from each other. Since the two sidewalls of the contact hole 103 in the third direction Z expose the active region 101, the second contact structures 106 covering the two sidewalls of the contact hole 103 in the third direction Z are respectively in electrical contact with the two active regions 101.

[0136] In some embodiments, the second etching process can include a dry etching process. Specifically, the etching gas used in the second etching process can include chlorine and hydrogen bromide. The flow rate of chlorine can be 5-30 seem, and the flow rate of hydrogen bromide can be 10-100 seem. The reaction pressure of the second etching process can be 10 Torr-30 mTorr. The radio frequency power of the second etching process can be 400-800 W.

[0137] In some embodiments, the contact hole 103 exposes the active region 101 and the partial isolation structure 102 on both sides of the active region 101 at the bottom, and the second contact structure 106 is located on the surface of the exposed isolation structure 102. In this way, the bottom of the second contact structure 106 can be prevented from being in electrical contact with the active region 101 exposed at the bottom of the contact hole 103, and it is ensured that the second contact structure 106 is only in electrical contact with the active region 101 exposed on the sidewall of the contact hole 103.

[0138] Reference Figures 22 to 25 , Figures 22 to 25 are schematic diagrams of cross-sectional structures in the aa' direction. The first sidewall structure 105 is formed in the contact hole 103, and the first sidewall structure 105 covers at least the second contact structure 106.

[0139] In some embodiments, the method of forming the first sidewall structure includes:

[0140] The initial first sidewall structure is formed on the side of the second contact structure 106 in the contact hole 103 and on the sidewall of the remaining portion of the contact hole 103 that is not covered by the second contact structure 106. The initial first sidewall structure is also higher than the opening of the contact hole 103, and the initial first sidewall structure that is higher than the opening of the contact hole 103 covers the top surface of the second interlayer dielectric layer 142. In addition, the initial first sidewall structure also covers the bottom of the contact hole 103.

[0141] In some embodiments, the initial first sidewall structure can be formed by a deposition process, which can include any one of atomic layer deposition, chemical vapor deposition, or other deposition methods.

[0142] The initial first sidewall structure is subjected to a back etching process to remove the initial first sidewall structure on the top surface of the second interlayer dielectric layer 142 and the initial first sidewall structure covering the bottom of the contact hole 103.

[0143] In the above back etching step, the initial first sidewall structure on the side of the second contact structure 106 and the initial first sidewall structure on the sidewall of the contact hole 103 are also etched away by a portion of their thickness.

[0144] It is worth noting that since the sidewall of the contact hole 103 in the second direction Y is perpendicular to the surface of the substrate 100, which is a vertical surface, the sidewall of the contact hole 103 in the third direction Z is inclined to the surface of the substrate 100, which is an inclined surface, therefore, the thickness of the initial first sidewall structure deposited on the side of the second contact structure 106 is greater than the thickness of the initial first sidewall structure deposited on the sidewall of the contact hole 103 in the second direction Y.

[0145] In one specific example, the process parameters of the above-mentioned etch-back process can be adjusted to completely remove the initial first sidewall structure located on the sidewall of the contact hole 103 in the second direction Y, and only retain part of the initial first sidewall structure located on the side of the second contact structure 106.

[0146] In another specific example, the process parameters of the above-mentioned etch-back process can be adjusted to remove part of the thickness of the initial first sidewall structure located on the sidewall of the contact hole 103 in the second direction Y, and remove part of the thickness of the initial first sidewall structure located on the side of the second contact structure 106, to form the first sidewall structure.

[0147] The bottom surface of the first sidewall structure can be in contact with the part of the isolation structure 102 exposed by the bottom of the contact hole 103. Alternatively, part of the bottom surface of the first sidewall structure can be in contact with the part of the isolation structure 102 exposed by the bottom of the contact hole 103, and the remaining part of the bottom surface can be in contact with the part of the active region 101 exposed by the bottom of the contact hole 103.

[0148] In some embodiments, the first sidewall structure 105 includes a first silicon oxide layer 1051 and a first silicon nitride layer 1052 stacked in sequence in a direction away from the first contact structure 104.

[0149] The method of forming the first sidewall structure can include:

[0150] Reference Figure 22 First, an initial first silicon nitride layer 31 is formed on the side of the second contact structure 106 in the contact hole 103 and the remaining part of the sidewall of the contact hole 103 not covered by the second contact structure 106, the initial first silicon nitride layer 31 is also higher than the top surface of the contact hole 103 and located on the surface of the second interlayer dielectric layer 142, and the initial first silicon nitride layer 31 is also located at the bottom of the contact hole 103.

[0151] Reference Figure 23 Then, an etch-back process is performed on the initial first silicon nitride layer 31 to remove the initial first silicon nitride layer 31 higher than the top surface of the contact hole 103 and the initial first silicon nitride layer 31 located at the bottom of the contact hole 103, to form the first silicon nitride layer 1052.

[0152] Reference Figure 24The initial first silicon oxide layer 33 is formed, covering the sidewall of the first silicon nitride layer 1052, being higher than the top surface of the contact hole 103, and being located on the surface of the second interlayer dielectric layer 142, and being located at the bottom of the contact hole 103.

[0153] Referring to Figure 25 The initial first silicon oxide layer 33 is etched back to remove the initial first silicon oxide layer 33 higher than the top surface of the contact hole 103 and the initial first silicon oxide layer 33 located at the bottom of the contact hole 103, to form the first silicon oxide layer 1051.

[0154] In some embodiments, the first sidewall structure can also be a three-layer structure including a first silicon oxide layer and first silicon nitride layers located on both sides of the first silicon oxide layer. Specifically, the three-layer structure is sequentially stacked in the direction away from the first contact structure as follows: a first silicon nitride layer, a first silicon oxide layer, and a first silicon nitride layer.

[0155] Referring to Figures 26 to 31 , Figures 26 to 31 are schematic diagrams of cross-sectional structures in the aa' direction. After the first sidewall structure 105 is formed, the first contact structure 104 is formed to fill the remaining contact hole 103, wherein the first contact structure 104 is located above the active region 101 exposed at the bottom of the contact hole 103 and is in electrical contact with the active region 101.

[0156] In the embodiments of the present disclosure, the first contact structure 104, the first sidewall structure 105, and the second contact structure 106 are formed in the contact hole 103 in advance. Since the aspect ratio of the contact hole 103 is small, the morphology of the deposited first contact structure 104, the first sidewall structure 105, and the second contact structure 106 is better, and the uniformity is higher. At the same time, the problem that the first contact structure 104 is not etched completely due to the simultaneous etching of the bit line structure 107 and the first contact structure 104 in the related art, and the subsequent step of forming the second contact structure 106 causes process damage, resulting in electrical connection between the second contact structure 106 and the first contact structure 104, and causing short circuit of the semiconductor structure, can be avoided.

[0157] In the embodiments of the present disclosure, the second contact structure 106, the first sidewall structure 105, and the first contact structure 104 are sequentially formed, and the first sidewall structure 105 covers the surface of the second contact structure 106, and the first contact structure 104 covers the surface of the first sidewall structure 105, which can ensure that the first contact structure 104 and the second contact structure 106 are completely isolated by the first sidewall structure, and short circuit is avoided.

[0158] In some embodiments, the method of forming the first contact structure 104 can include:

[0159] Reference is made to FIG. 1 1, which illustrates a cross-sectional view of the structure of FIG. 10 after a third etching process is performed on the structure of FIG. 10. Figure 6 A fill layer 34 is formed to fill the remaining contact holes 103, the fill layer 34 is higher than the openings of the contact holes 103 and is located on the surface of the second ILD layer 142. In some embodiments, the fill layer 34 can be formed by a deposition process, and the material of the fill layer 34 can be a non-hardmask material, such as SOH.

[0160] Reference is made to FIG. 12, which illustrates a cross-sectional view of the structure of FIG. 1 1 after the fill layer 34 is removed from the contact holes 103. Figure 27 The fill layer 34 higher than the openings of the contact holes 103 is etched away.

[0161] Reference is made to FIG. 13, which illustrates a cross-sectional view of the structure of FIG. 12 after a fourth etching process is performed on the structure of FIG. 12. Figure 28 A third etching process is performed on the second ILD layer 142, the fill layer 34, the first sidewall structure 105 and the second contact structure 106, and the second ILD layer 142 and the fill layer 34 opposite to the second ILD layer 142, the first sidewall structure 105 and the second contact structure 106 are removed, so that the top surfaces of the remaining fill layer 34, the first sidewall structure 105 and the second contact structure 106 are flush with the top surface of the first ILD layer 141.

[0162] Since the fill layer 34 fills the contact holes 103 and is in contact with the first sidewall structure 105, the fill layer 34 can protect the first sidewall structure 105 from being damaged in the third etching process.

[0163] In some embodiments, the etching selectivity ratios of the second ILD layer 142, the first sidewall structure 105 and the second contact structure 106 are the same in the third etching process, so that the first sidewall structure 105 and the second contact structure 106 are flush with the first ILD layer 141 after only one third etching process.

[0164] Reference is made to FIG. 14, which illustrates a cross-sectional view of the structure of FIG. 13 after the fill layer 34 is removed from the contact holes 103. Figure 29 The fill layer 34 in the contact holes 103 is removed. In some embodiments, a wet etching process can be used to remove the fill layer 34.

[0165] Reference is made to FIG. 15, which illustrates a cross-sectional view of the structure of FIG. 14 after a fifth etching process is performed on the structure of FIG. 14. Figure 30 An initial first contact structure 35 is formed to fill the remaining contact holes 103, the initial first contact structure 35 covers the side surface of the first contact structure 104, the initial first contact structure 35 is also higher than the openings of the contact holes 103 and is located on the top surface of the first ILD layer 141, and the initial first contact structure 35 also covers the bottom surface of the contact holes 103 and is in contact with the active region 101 exposed on the bottom surface of the contact holes 103.

[0166] In some embodiments, the initial first contact structure 35 can be formed by a deposition process, such as an atomic layer deposition process. The material of the initial first contact structure 35 can be polysilicon.

[0167] Reference is made to FIG. 16, which illustrates a cross-sectional view of the structure of FIG. 15 after a sixth etching process is performed on the structure of FIG. 15. Figure 31The initial first contact structure 35 is subjected to a back-etching process to remove the initial first contact structure 35 above the top surface of the contact hole 103, and the remaining initial first contact structure 35 serves as the first contact structure 104.

[0168] Referring to Figures 32 to 33 , Figure 32 and Figure 33 are schematic diagrams of cross-sectional structures in the aa’ direction. In some embodiments, the method for manufacturing the semiconductor structure further includes:

[0169] The bit line structure 107 is formed on the top surface of the first contact structure 104, and the bit line structure 107 is in electrical contact with the first contact structure 104.

[0170] In some embodiments, the number of the bit line structures 107 is plural, and the plural bit line structures 107 are arranged at intervals along the third direction Z, and each bit line structure 107 extends along the second direction Y. The plural bit line structures 107 arranged at intervals along the third direction Z correspond to the plural columns of active regions 101 arranged at intervals along the third direction Z, and each bit line structure 107 is coupled to the first source / drain region 111 of each active region 101 in each column of active regions 101 through the first contact structure 104.

[0171] In some embodiments, the bit line structure 107 includes, in sequence from the direction away from the surface of the substrate 100, a bit line barrier layer 121, a bit line conductive layer 122, and a bit line cap layer 123.

[0172] In some embodiments, the method for forming the bit line structure 107 can include:

[0173] Referring to Figure 32 , a deposition process is used to sequentially form an initial bit line barrier layer 41, an initial bit line conductive layer 42, and an initial bit line cap layer 43 on the substrate 100. Then, a patterning process is performed on the initial bit line barrier layer 41, the initial bit line conductive layer 42, and the initial bit line cap layer 43 to form the bit line barrier layer 121, the bit line conductive layer 122, and the bit line cap layer 123. The patterning process can include any one of an SADP process or an SAQP process.

[0174] Specifically, a deposition process can be used to sequentially form the initial bit line barrier layer 41, the initial bit line conductive layer 42, and the initial bit line cap layer 43 on the substrate 100. The material of the initial bit line barrier layer 41 can include any one of titanium nitride, tantalum, tantalum nitride, or tungsten nitride. The material of the initial bit line conductive layer 42 can include a metal material, for example, at least one of tungsten, titanium, or nickel. The material of the initial bit line cap layer 43 can include any one of silicon nitride or silicon oxynitride.

[0175] Thereafter, continuing to refer to Figure 32A hard mask layer is formed on the surface of the initial bit line capping layer 43. The hard mask layer may include a sub-first hard mask layer 51, an etch stop layer 52, and a sub-second hard mask layer 53, which are stacked sequentially in a direction away from the initial bit line capping layer 43. The pattern of the sub-second hard mask layer 53 is the same as the shape of the bit line structure 107, and it is used to define the shape of the bit line structure 107.

[0176] In some embodiments, the material of the first hard mask layer 51 may include APF, the material of the etch barrier layer 52 may include silicon oxynitride, and the material of the second hard mask layer may include spin-coated hard mask.

[0177] Next, refer to Figure 33 Based on the pattern of the second hard mask layer 53, the first hard mask layer and the etch barrier layer 52 are etched until the top surface of the initial bit line capping layer 43 is exposed. The initial bit line capping layer 43, the initial bit line conductive layer 42 and the initial bit line barrier layer 41 are etched until the top surface of the first interlayer dielectric layer 141 is exposed. The remaining initial bit line capping layer 43 forms the bit line capping layer 123, the remaining initial bit line conductive layer 42 forms the bit line conductive layer 122, and the remaining initial bit line barrier layer 41 forms the bit line barrier layer 121.

[0178] It is not difficult to see that in the embodiment of this disclosure, in the step of etching to form the bit line structure 107, it is not necessary to etch and remove the first contact structure 104 in the contact hole 103. This avoids the problem of insufficient etching capability for the first contact structure 104 due to excessive etching depth-to-width ratio, which leads to etching residue of the first contact structure 104. This fundamentally avoids the problem of short circuit in the semiconductor structure caused by electrical contact between the residual first contact structure 104 and the second contact structure 106.

[0179] refer to Figure 34 , Figure 34 The diagram shows a cross-sectional view along the aa' direction. After the bitline structure 107 is formed, a second sidewall structure 108 is formed on the sidewall of the bitline structure 107. The bottom surface of the second sidewall structure 108 contacts the top surface of the first sidewall structure 105. In some embodiments, the second sidewall structure 108 can be formed using a deposition process.

[0180] In some embodiments, the second sidewall structure 108 may be a double-layer structure, including a second silicon oxide layer and a second silicon nitride layer stacked sequentially along the direction of the back-off line structure 107.

[0181] In some embodiments, the second sidewall structure 108 may also be a three-layer structure, including: a second silicon oxide layer and two second silicon nitride layers, specifically: a second silicon nitride layer, a second oxide layer and a second silicon nitride layer stacked sequentially along the direction of the off-center structure 107.

[0182] refer to Figure 11A capacitor contact plug 110 is formed on the substrate 100, the capacitor contact plug 110 is between the adjacent bit line structures 107, and is in electrical contact with the top surface of the second contact structure 106.

[0183] Compared with the capacitor contact plug 110 and the second contact structure 106 being formed in the same capacitor hole, the capacitor contact plug 110 and the second contact structure 106 are formed separately, so that the aspect ratio of forming the capacitor contact plug 110 and the second contact structure 106 is smaller, thereby improving the uniformity of the topography of forming the capacitor contact plug 110 and the second contact structure 106.

[0184] In some embodiments, the method of forming the capacitor contact plug 110 includes:

[0185] Reference Figure 35 , Figure 35 The cross-sectional structure in the aa' direction is shown in the schematic diagram. The SADP process or the SAQP process can be used to remove the second side wall structure 108 on the substrate 100 and form a capacitor hole, and the top surface of the second contact structure 106 is exposed at the bottom of the capacitor hole.

[0186] Reference Figure 11 The deposition process is used to form the capacitor contact plug 110 filled in the capacitor hole. In some embodiments, the atomic layer deposition process can be used to form the capacitor contact plug, and the material of the capacitor contact plug 110 can be polysilicon.

[0187] After the capacitor contact plug 110 is formed, a capacitor structure is formed, each capacitor structure is located on the side of the capacitor contact plug 110 away from the substrate 100, and is in electrical contact with the capacitor contact plug 110.

[0188] The preparation method of the semiconductor structure provided by the above embodiments includes pre-forming the first contact structure 104, the first side wall structure 105 and the second contact structure 106 in the contact hole 103. Because the aspect ratio of the contact hole 103 is small, the topography of the deposited first contact structure 104, the first side wall structure 105 and the second contact structure 106 is better, and the uniformity is higher. At the same time, the problem that the first contact structure 104 is not etched completely due to etching the bit line structure 107 and the first contact structure 104 at the same time in the related art, and then the second contact structure 106 is formed in the subsequent step, and the process damage occurs to cause the second contact structure 106 to be in electrical connection with the first contact structure 104, so that the semiconductor structure is short-circuited, can be avoided.

[0189] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A semiconductor structure, comprising: a substrate having a plurality of active regions spaced along a first direction; and a plurality of contact holes spaced along the first direction, the contact holes exposing adjacent active regions; a contact structure filled in the contact holes, the contact structure comprising: a first contact structure over the active regions; a first sidewall structure covering at least part of a side of the first contact structure; and a second contact structure covering at least part of a side of the first sidewall structure, the second contact structure being between two adjacent active regions, wherein the first contact structure is in electrical contact with one of the adjacent active regions, and the second contact structure is in electrical contact with the other of the adjacent active regions; wherein the active regions extend along a predetermined direction, the active regions comprise a first source / drain region, a channel region and a second source / drain region spaced along the predetermined direction, the channel region is on both sides of the first source / drain region, and the second source / drain region is on a side of the channel region away from the first source / drain region; wherein the plurality of active regions comprise first active regions and second active regions alternately arranged along the first direction, wherein the first contact structure is in electrical contact with a first source / drain region of one of the adjacent first active regions or second active regions, and the second contact structure is in electrical contact with a second source / drain region of the other of the adjacent first active regions or second active regions. 2.The semiconductor structure of claim 1, wherein the contact structure comprises two spaced second contact structures, each of the two second contact structures being in electrical contact with a different active region. 3.The semiconductor structure of claim 1, further comprising: a plurality of bit line structures spaced along a third direction on the substrate, the bit line structures extending along a second direction, the first direction, the second direction and the third direction being perpendicular to each other, and the third direction being perpendicular to the second direction; and a plurality of capacitor structures, each of the capacitor structures being on the substrate and coupled with the second contact structure. 4.The semiconductor structure of claim 3, wherein a shape of a projection of the contact hole along the second direction is an inverted trapezoid or an ellipse, a shape of a projection of the contact hole along the third direction is a rectangle, and the second contact structure is on a sidewall of the contact hole along the third direction. 5.A method for manufacturing a semiconductor structure, comprising: providing a substrate having a plurality of active regions spaced along a first direction; forming a contact hole in the substrate, the contact hole exposing one of adjacent active regions at a bottom of the contact hole and exposing the other of the adjacent active regions at a sidewall of the contact hole; forming a second contact structure on part of the sidewall of the contact hole, the second contact structure being in electrical contact with the active region exposed by the sidewall of the contact hole; and forming a first sidewall structure in the contact hole, the first sidewall structure covering at least the second contact structure. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ forming a first contact structure filling the rest of the contact hole, wherein the first contact structure is above and in electrical contact with the active region exposed at the bottom of the contact hole; wherein the active region extends along a preset direction, the active region comprises a first source / drain region, a channel region and a second source / drain region arranged at intervals along the preset direction, the channel region is located on both sides of the first source / drain region, and the second source / drain region is located on a side of the channel region away from the first source / drain region; a plurality of the active regions comprise first active regions and second active regions arranged alternately along the first direction; wherein the first contact structure is in electrical contact with the first source / drain region of one of the adjacent first active region or the second active region, and the second contact structure is in electrical contact with the second source / drain region of the other of the adjacent first active region or the second active region.

6. The method of claim 5, wherein the method of forming the contact hole comprises: forming a first mask layer on the substrate; patterning the first mask layer to form a first opening in the first mask layer, the first opening is partially opposite to one of the adjacent active regions and partially opposite to the other of the adjacent active regions; and etching the substrate along the first opening by a first etching process to expose the active region and form the contact hole.

7. The method of claim 6, wherein the method of forming the second contact structure comprises: forming an initial second contact structure on the sidewall of the contact hole by a deposition process, wherein the initial second contact structure covering the sidewall of the contact hole in a third direction has a first thickness, the initial second contact structure covering the sidewall of the contact hole in a second direction has a second thickness, the first thickness is greater than the second thickness, the first direction, the second direction and the third direction intersect with each other, and the third direction is perpendicular to the second direction, and the sidewall of the contact hole in the third direction exposes the active region; etching the initial second contact structure by a second etching process to remove all the initial second contact structure covering the sidewall of the contact hole in the second direction and to remove part of the initial second contact structure covering the sidewall of the contact hole in the third direction, and the remaining initial second contact structure is the second contact structure.

8. The method of claim 7, wherein before forming the contact hole, further comprising: forming an isolation structure between the adjacent active regions, the bottom of the formed contact hole exposes the active region and part of the isolation structure on both sides of the active region, and the second contact structure is located on the exposed surface of the isolation structure.

9. The method of claim 5, wherein the first sidewall structure comprises a first silicon oxide layer and a first silicon nitride layer stacked in sequence in a direction away from the first contact structure.

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