Memory and method of manufacturing the same, electronic device

Abstract

The application relates to a memory and a preparation method thereof and an electronic device. The memory comprises a substrate, a plurality of memory cells arranged in a stacking mode along a direction perpendicular to the substrate on the substrate, a read transistor and a write transistor in the memory cell, a first gate, a first semiconductor layer and a storage gate in the read transistor, a second gate and a second semiconductor layer in the write transistor, a read word line on the substrate, the first gate of the read transistor being part of the read word line, a write word line on the substrate, the second gate of the write transistor being part of the write word line, a bit line comprising a first part and a second part connected to each other, the first part of the bit line being arranged on a side of the first gate away from the write transistor and connected to the first semiconductor layer, and the second part of the bit line being arranged on a side of the second semiconductor layer away from the read transistor and connected to the second semiconductor layer. The memory has high storage performance and use reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design and manufacturing, in particular to a memory and a preparation method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] Therefore, the embodiments of the present application provide a memory and a preparation method thereof, and an electronic device, which are beneficial to improve the storage performance and use reliability of the memory.

[0005] In one aspect, the present application provides a memory according to some embodiments, comprising:

[0006] a substrate;

[0007] a plurality of storage units, the plurality of storage units are stacked on the substrate along a direction perpendicular to the substrate, the storage unit comprises a read transistor and a write transistor, the read transistor and the write transistor in the same storage unit are distributed in a direction parallel to the substrate, the read transistor comprises a first gate, a first semiconductor layer and a storage gate, and the write transistor comprises a second gate and a second semiconductor layer;

[0008] a read word line located on the substrate and extending along a direction perpendicular to the substrate, the first gate of the read transistor is part of the read word line;

[0009] a write word line located on the substrate and distributed apart from the read word line, the write word line extending along a direction perpendicular to the substrate, the second gate of the write transistor being part of the write word line;

[0010] a bit line comprising a first part and a second part connected to each other, the first part of the bit line being arranged on a side of the first gate away from the write transistor and connected to the first semiconductor layer, and the second part of the bit line being arranged on a side of the second semiconductor layer away from the read transistor and connected to the second semiconductor layer;

[0011] wherein the storage gate is located on a side of the first semiconductor layer away from the first gate.

[0012] In some embodiments, the first semiconductor layer has a second surface close to the substrate and a first surface away from the substrate in a direction perpendicular to the substrate, the first portion of the bit line is located on the first surface; the second semiconductor layer has a first side and a second side opposite to each other in a direction parallel to the substrate, the second portion of the bit line is located on the second side of the second semiconductor layer.

[0013] In some embodiments, the memory further comprises a connection line;

[0014] The connection line is located on one side of the read transistor and on the first side and the second side of the second semiconductor layer in a direction parallel to the substrate; the connection line is integrally connected with the second portion of the bit line.

[0015] In some embodiments, the read word line surrounds the sidewall of the first semiconductor layer, and the second semiconductor layer surrounds the sidewall of the write word line.

[0016] In some embodiments, the memory further comprises a ground line;

[0017] The ground line is located beside the read word line and parallel to the read word line; the ground line is connected with the first semiconductor layer.

[0018] In some embodiments, the ground line comprises a main body and a plurality of branch parts;

[0019] The branch parts extend from the main body in a direction parallel to the substrate, and the branch parts are connected with the first semiconductor layer close to the surface of the substrate and away from the surface of the substrate.

[0020] In some embodiments, the first semiconductor layer is annular, and the first semiconductor layer surrounds the storage gate.

[0021] In another aspect, the present application also provides a preparation method of a memory according to some embodiments, comprising:

[0022] Providing a substrate;

[0023] Forming a plurality of memory cells stacked in a direction perpendicular to the substrate on the substrate; the memory cells comprise read transistors and write transistors, the read transistors and the write transistors in the same memory cell are distributed in a direction parallel to the substrate; the read transistor comprises a first gate, a first semiconductor layer and a storage gate, the write transistor comprises a second gate and a second semiconductor layer; wherein the storage gate is located on the side of the first semiconductor layer away from the first gate;

[0024] forming a read word line extending along a direction perpendicular to the substrate on the substrate; a portion of the read word line is used as a first gate of the read transistor;

[0025] forming a write word line spaced apart from the read word line on the substrate; the write word line extends along a direction perpendicular to the substrate, and a portion of the write word line is used as a second gate of the write transistor;

[0026] forming a bit line; the bit line includes a first portion and a second portion connected to each other; the first portion of the bit line is formed on a side of the first gate away from the write transistor and connected to the first semiconductor layer; the second portion of the bit line is formed on a side of the second semiconductor layer away from the read transistor and connected to the second semiconductor layer.

[0027] In some embodiments, after the substrate is provided, the method for preparing the memory further includes:

[0028] forming a stack structure on the substrate; the stack structure includes a plurality of layers of insulating material and a plurality of layers of conductive material alternately stacked along a direction perpendicular to the substrate;

[0029] forming the first gate, the first semiconductor layer and the read word line includes:

[0030] etching the insulating material layer to form a read transistor etching groove; the first semiconductor layer is conformally covered on an inner wall of the read transistor etching groove;

[0031] forming a filling medium layer in the read transistor etching groove;

[0032] etching the filling medium layer to form a read word line containing groove; the read word line is formed by filling the read word line containing groove; the first gate is a portion of the read word line corresponding to the first semiconductor layer.

[0033] In some embodiments, after the first gate, the first semiconductor layer and the read word line are formed, the method for preparing the memory further includes:

[0034] etching the stack structure to form a write transistor containing groove and a write word line defining hole; the write transistor containing groove is located in the conductive material layer, surrounds a periphery of the write word line defining hole and is in communication with the write word line defining hole;

[0035] conformally covering the second semiconductor layer on an inner wall of the write transistor containing groove, and filling the second gate in the write transistor containing groove;

[0036] forming the write word line in the write word line defining hole.

[0037] In some embodiments, the second semiconductor layer is formed to have opposite first and second sides in a direction parallel to the substrate, and the second portion of the bit line is formed on the second side of the second semiconductor layer.

[0038] In some embodiments, the bit line is formed by:

[0039] The filling medium layer and part of the first semiconductor layer are etched to expose a second surface of the first semiconductor layer on a side close to the substrate, forming a first bit line accommodating groove; and a first portion of the bit line is formed in the first bit line accommodating groove.

[0040] In another aspect, the application further provides an electronic device according to some embodiments, comprising the memory according to any one of the preceding embodiments.

[0041] The memory and the preparation method thereof and the electronic device provided by the embodiments of the application can have at least the following advantages:

[0042] In the embodiments of the application, two transistors (a read transistor and a write transistor) are used as a storage unit, and a storage gate is used to store electric charges, so that a storage unit of a double-transistor non-capacitive (also referred to as 2T0C) structure is realized. Compared with the related art, the storage capacitor is omitted, so that the structural integration is improved, and the leakage and refresh time are reduced. Since the storage gate is used to replace the storage capacitor, compared with the traditional memory, the electric charges in the storage capacitor are not lost during data reading (also referred to as destructive reading). The embodiments of the application do not cause loss of electric charges during data reading, and non-destructive reading is realized, so that the memory has higher read-write flexibility, the use reliability and access efficiency of the memory are improved, and the storage performance and use reliability of the memory are improved.

[0043] In addition, in the embodiments of the application, the read transistor includes a first gate and a storage gate. The read transistor adopts a double-gate structure, which is beneficial to improving the gate control ability of the read transistor, reducing the subthreshold swing, and thus improving the on-off ratio of the read transistor, so that the electrical performance of the memory is improved. In the embodiments of the application, the bit line is provided to include a first portion and a second portion connected to each other, the first portion of the bit line is connected to the read transistor, and the second portion is connected to the write transistor. Compared with the related art in which a read bit line and a write bit line are respectively arranged, the number of bit lines can be reduced in the embodiments of the application, so that the memory has higher structural density, and the layout design, especially the layout design in a narrow space, is facilitated, so that the practicality of the memory is also improved. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to make the technical solutions in the embodiments of the present application or the prior art clearer, the accompanying drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only aim to some embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative effort based on these drawings.

[0045] Figure 1 A perspective structural schematic diagram of a memory provided by some embodiments of the present application is shown in the figure.

[0046] Figure 2 A perspective structural schematic diagram of a memory provided by some embodiments of the present application is shown in the figure.

[0047] Figure 3 A perspective structural schematic diagram of a memory provided by some embodiments of the present application is shown in the figure. Figure 2 A rear view structural schematic diagram of the structure shown in the figure is shown in the figure.

[0048] Figure 4 A structural schematic diagram of a memory provided by some embodiments of the present application is shown in (a) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the aa' direction is shown in (b) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the bb' direction is shown in (c) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the cc' direction is shown in (d) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the dd' direction is shown in (e) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the dd' direction is shown in (e) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the dd' direction is shown in (e) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the dd' direction is shown in (e) of the figure. Figure 4 A cross-sectional structural schematic diagram of the structure shown in (a) of the figure in the dd' direction is shown in (e) of the figure.

[0049] Figure 5 An equivalent circuit diagram of a memory provided by some embodiments of the present application is shown in the figure.

[0050] Figure 6 A flow schematic diagram of a preparation method of a memory provided by some embodiments of the present application is shown in the figure.

[0051] Figure 7 A flow schematic diagram of forming a first gate, a first semiconductor layer and a read word line in a preparation method of a memory provided by some embodiments of the present application is shown in the figure.

[0052] Figure 8 A flow schematic diagram of forming a second gate, a second semiconductor layer and a write word line in a preparation method of a memory provided by some embodiments of the present application is shown in the figure.

[0053] Figure 9FIG. 1A in the middle is a schematic view of a cross section structure of the structure shown in FIG. 1A in the middle in the direction of aa' after forming the stack structure in the method for manufacturing the memory provided by some embodiments of the present application; Figure 9 FIG. 1B in the middle is a schematic view of a cross section structure of the structure shown in FIG. 1A in the middle in the direction of bb' after forming the stack structure in the method for manufacturing the memory provided by some embodiments of the present application; Figure 9 FIG. 1C in the middle is a schematic view of a cross section structure of the structure shown in FIG. 1A in the middle in the direction of cc' after forming the stack structure in the method for manufacturing the memory provided by some embodiments of the present application; Figure 9 FIG. 1D in the middle is a schematic view of a cross section structure of the structure shown in FIG. 1A in the middle in the direction of dd' after forming the stack structure in the method for manufacturing the memory provided by some embodiments of the present application; Figure 9 FIG. 1E in the middle is a schematic view of a cross section structure of the structure shown in FIG. 1A in the middle in the direction of ee' after forming the stack structure in the method for manufacturing the memory provided by some embodiments of the present application; Figure 9 FIG. 1F in the middle is a schematic view of a cross section structure of the structure shown in FIG. 1A in the middle in the direction of ff' after forming the stack structure in the method for manufacturing the memory provided by some embodiments of the present application; Figure 9 FIG. 1G in the middle is a schematic view of a cross section structure of the structure shown in FIG. 1A in the middle in the direction of gg' after forming the stack structure in the method for manufacturing the memory provided by some embodiments of the present application;

[0054] Figure 10 FIG. 2A in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of aa' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 10 FIG. 2B in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of bb' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 10 FIG. 2C in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of cc' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 10 FIG. 2D in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of dd' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 10 FIG. 2E in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of ee' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 10 FIG. 2F in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of ff' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 10 FIG. 2G in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of gg' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 10 FIG. 2H in the middle is a schematic view of a cross section structure of the structure shown in FIG. 2A in the middle in the direction of hh' after forming the first mask plate in the method for manufacturing the memory provided by some embodiments of the present application; Figure 11 FIG. 2I in the middle is a schematic view of a top structure of the structure shown in FIG. 2A in the middle;

[0055] Figure 11 FIG. 3A in the middle is a schematic view of a cross section structure of the structure shown in FIG. 3A in the middle in the direction of aa' after forming the second storage unit defining groove in the method for manufacturing the memory provided by some embodiments of the present application; Figure 11 FIG. 3B in the middle is a schematic view of a cross section structure of the structure shown in FIG. 3A in the middle in the direction of bb' after forming the second storage unit defining groove in the method for manufacturing the memory provided by some embodiments of the present application; Figure 11 FIG. 3C in the middle is a schematic view of a cross section structure of the structure shown in FIG. 3A in the middle in the direction of cc' after forming the second storage unit defining groove in the method for manufacturing the memory provided by some embodiments of the present application; Figure 11 FIG. 3D in the middle is a schematic view of a cross section structure of the structure shown in FIG. 3A in the middle in the direction of dd' after forming the second storage unit defining groove in the method for manufacturing the memory provided by some embodiments of the present application; Figure 11 FIG. 3E in the middle is a schematic view of a cross section structure of the structure shown in FIG. 3A in the middle in the direction of ee' after forming the second storage unit defining groove in the method for manufacturing the memory provided by some embodiments of the present application; Figure 11 FIG. 3F in the middle is a schematic view of a cross section structure of the structure shown in FIG. 3A in the middle in the direction of ff' after forming the second storage unit defining groove in the method for manufacturing the memory provided by some embodiments of the present application; Figure 12 FIG. 3G in the middle is a schematic view of a cross section structure of the structure shown in FIG. 3A in the middle in the direction of gg' after forming the second storage unit defining groove in the method for manufacturing the memory provided by some embodiments of the present application;

[0056] Figure 12 FIG. 4A in the middle is a schematic view of a cross section structure of the structure shown in FIG. 4A in the middle in the direction of aa' after forming the storage unit isolation layer in the method for manufacturing the memory provided by some embodiments of the present application; Figure 12 FIG. 4B in the middle is a schematic view of a cross section structure of the structure shown in FIG. 4A in the middle in the direction of bb' after forming the storage unit isolation layer in the method for manufacturing the memory provided by some embodiments of the present application; Figure 12 FIG. 4C in the middle is a schematic view of a cross section structure of the structure shown in FIG. 4A in the middle in the direction of cc' after forming the storage unit isolation layer in the method for manufacturing the memory provided by some embodiments of the present application; Figure 12 FIG. 4D in the middle is a schematic view of a cross section structure of the structure shown in FIG. 4A in the middle in the direction of dd' after forming the storage unit isolation layer in the method for manufacturing the memory provided by some embodiments of the present application;Figure 12 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 12 FIG. 1B is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of bb'; Figure 13 FIG. 1C is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of cc';

[0057] Figure 13 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa' after forming a second mask plate in a method for manufacturing a memory provided by some embodiments of the present application; Figure 13 FIG. 2B is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of bb'; Figure 13 FIG. 2C is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of cc'; Figure 13 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 13 FIG. 2E is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of ee'; Figure 13 FIG. 2F is a schematic view of a top structure of the structure shown in FIG. 2; Figure 13 Figure 13 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 3 along the direction of aa' after forming a support etching groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 14 FIG. 3B is a schematic view of a cross-sectional structure of the structure shown in FIG. 3 along the direction of bb'; FIG. 3C is a schematic view of a cross-sectional structure of the structure shown in FIG. 3 along the direction of cc';

[0058] FIG. 3D is a schematic view of a cross-sectional structure of the structure shown in FIG. 3 along the direction of dd'; Figure 14 FIG. 3E is a schematic view of a cross-sectional structure of the structure shown in FIG. 3 along the direction of ee'; Figure 14 Figure 14 FIG. 4A is a schematic view of a cross-sectional structure of the structure shown in FIG. 4 along the direction of aa' after forming a support groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 14 FIG. 4B is a schematic view of a cross-sectional structure of the structure shown in FIG. 4 along the direction of bb'; Figure 14 FIG. 4C is a schematic view of a cross-sectional structure of the structure shown in FIG. 4 along the direction of cc'; Figure 14 FIG. 4D is a schematic view of a cross-sectional structure of the structure shown in FIG. 4 along the direction of dd'; Figure 15 FIG. 4E is a schematic view of a cross-sectional structure of the structure shown in FIG. 4 along the direction of ee';

[0059] Figure 15 FIG. 5A is a schematic view of a cross-sectional structure of the structure shown in FIG. 5 along the direction of aa' after forming a support groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 15 FIG. 5B is a schematic view of a cross-sectional structure of the structure shown in FIG. 5 along the direction of bb'; Figure 15 FIG. 5C is a schematic view of a cross-sectional structure of the structure shown in FIG. 5 along the direction of cc'; Figure 15 FIG. 5D is a schematic view of a cross-sectional structure of the structure shown in FIG. 5 along the direction of dd'; Figure 15 FIG. 5E is a schematic view of a cross-sectional structure of the structure shown in FIG. 5 along the direction of ee'; Figure 15 Figure 16

[0060] Figure 16 ​​FIG. 1A is a schematic view of a cross section of a structure in the aa' direction after forming an initial support layer in a method of manufacturing a memory according to some embodiments of the application; Figure 16 FIG. 1B is a schematic view of a cross section of the structure shown in FIG. 1A in the bb' direction; Figure 16 FIG. 1C is a schematic view of a cross section of the structure shown in FIG. 1A in the cc' direction; Figure 16 FIG. 1D is a schematic view of a cross section of the structure shown in FIG. 1A in the dd' direction; Figure 16 FIG. 1E is a schematic view of a cross section of the structure shown in FIG. 1A in the ee' direction; Figure 16 FIG. 1F is a schematic view of a cross section of the structure shown in FIG. 1A in the ff' direction; Figure 17 FIG. 1G is a schematic view of a cross section of the structure shown in FIG. 1A in the gg' direction;

[0061] Figure 17 FIG. 2A is a schematic view of a cross section of a structure in the aa' direction after forming a third mask in a method of manufacturing a memory according to some embodiments of the application; Figure 17 FIG. 2B is a schematic view of a cross section of the structure shown in FIG. 2A in the bb' direction; Figure 17 FIG. 2C is a schematic view of a cross section of the structure shown in FIG. 2A in the cc' direction; Figure 17 FIG. 2D is a schematic view of a cross section of the structure shown in FIG. 2A in the dd' direction; Figure 17 FIG. 2E is a schematic view of a cross section of the structure shown in FIG. 2A in the ee' direction; Figure 17 FIG. 2F is a schematic view of a cross section of the structure shown in FIG. 2A in the ff' direction; Figure 17 FIG. 2G is a schematic view of a cross section of the structure shown in FIG. 2A in the gg' direction; Figure 17 FIG. 2H is a schematic view of a cross section of the structure shown in FIG. 2A in the hh' direction; Figure 18 FIG. 2I is a schematic view of a top view of the structure shown in FIG. 2A;

[0062] Figure 18 FIG. 3A is a schematic view of a cross section of a structure in the aa' direction after forming an etch trench for a read transistor in a method of manufacturing a memory according to some embodiments of the application; Figure 18 FIG. 3B is a schematic view of a cross section of the structure shown in FIG. 3A in the bb' direction; Figure 18 FIG. 3C is a schematic view of a cross section of the structure shown in FIG. 3A in the cc' direction; Figure 18 FIG. 3D is a schematic view of a cross section of the structure shown in FIG. 3A in the dd' direction; Figure 18 FIG. 3E is a schematic view of a cross section of the structure shown in FIG. 3A in the ee' direction; Figure 18 FIG. 3F is a schematic view of a cross section of the structure shown in FIG. 3A in the ff' direction; Figure 19 FIG. 3G is a schematic view of a cross section of the structure shown in FIG. 3A in the gg' direction; FIG. 3H is a schematic view of a cross section of the structure shown in FIG. 3A in the hh' direction;

[0063] Figure 19 FIG. 4A is a schematic view of a cross section of a structure in the aa' direction after forming a housing trench for a read transistor in a method of manufacturing a memory according to some embodiments of the application; Figure 19 FIG. 4B is a schematic view of a cross section of the structure shown in FIG. 4A in the bb' direction; Figure 19 FIG. 4C is a schematic view of a cross section of the structure shown in FIG. 4A in the cc' direction; Figure 19 FIG. 4D is a schematic view of a cross section of the structure shown in FIG. 4A in the dd' direction;Figure 19 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 19 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 20 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa';

[0064] Figure 20 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 20 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 20 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 20 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 20 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 20 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 21 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa';

[0065] Figure 21 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 21 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 21 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 21 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 21 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 21 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 22 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa';

[0066] Figure 22 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 22 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 22 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 22 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 22 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 22 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 22 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa'; Figure 22 FIG. 2D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of dd'; Figure 23 FIG. 2A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2 along the direction of aa';

[0067] Figure 23Figure (a) is a schematic cross-sectional view of the structure obtained after forming the grounding wire etching groove in the aa' direction in the method for fabricating the memory provided in some embodiments of this application; Figure 23 Figure (b) is Figure 23 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 23 Figure (c) is Figure 23 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 23 Figure (d) in the middle is Figure 24 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0068] Figure 24 Figure (a) is a schematic cross-sectional view of the structure obtained after forming the grounding wire receiving groove in the aa' direction in the method for fabricating the memory provided in some embodiments of this application; Figure 24 Figure (b) is Figure 24 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 24 Figure (c) in the middle is Figure 24 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 24 Figure (d) in the middle is Figure 25 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0069] Figure 25 Figure (a) is a schematic cross-sectional view of the structure obtained after forming a grounding wire in the aa' direction in the method for fabricating a memory provided in some embodiments of this application; Figure 25 Figure (b) is Figure 25 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 25 Figure (c) is Figure 25 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 25 Figure (d) in the middle is Figure 26 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0070] Figure 26 Figure (a) is a schematic cross-sectional view of the structure obtained after forming the fifth photomask in the aa' direction in the method for fabricating the memory provided in some embodiments of this application. Figure 26 Figure (b) is Figure 26 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 26 Figure (c) is Figure 26 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 26 Figure (d) in the middle isFigure 26 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; Figure 26 FIG. 3B is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the bb' direction; Figure 27 FIG. 3C is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the cc' direction;

[0071] Figure 27 FIG. 4A is a schematic view of a cross-sectional structure of the structure shown in FIG. 3A in the aa' direction after forming a read word line isolation groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 27 FIG. 4B is a schematic view of a cross-sectional structure of the structure shown in FIG. 3A in the bb' direction after forming a read word line isolation groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 27 FIG. 4C is a schematic view of a cross-sectional structure of the structure shown in FIG. 3A in the cc' direction after forming a read word line isolation groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 27 FIG. 4D is a schematic view of a cross-sectional structure of the structure shown in FIG. 3A in the dd' direction after forming a read word line isolation groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 27 FIG. 4E is a schematic view of a top structure of the structure shown in FIG. 3A after forming a read word line isolation groove in a method for manufacturing a memory provided by some embodiments of the present application; Figure 27 Figure 28 FIG. 5A is a schematic view of a cross-sectional structure of the structure shown in FIG. 4A in the aa' direction after forming a read word line isolation layer in a method for manufacturing a memory provided by some embodiments of the present application;

[0072] FIG. 5B is a schematic view of a cross-sectional structure of the structure shown in FIG. 4A in the bb' direction after forming a read word line isolation layer in a method for manufacturing a memory provided by some embodiments of the present application; Figure 28 FIG. 5C is a schematic view of a cross-sectional structure of the structure shown in FIG. 4A in the cc' direction after forming a read word line isolation layer in a method for manufacturing a memory provided by some embodiments of the present application; Figure 28 FIG. 5D is a schematic view of a cross-sectional structure of the structure shown in FIG. 4A in the dd' direction after forming a read word line isolation layer in a method for manufacturing a memory provided by some embodiments of the present application; Figure 28 FIG. 5E is a schematic view of a top structure of the structure shown in FIG. 4A after forming a read word line isolation layer in a method for manufacturing a memory provided by some embodiments of the present application; Figure 28 Figure 28 Figure 28 FIG. 6A is a schematic view of a cross-sectional structure of the structure shown in FIG. 5A in the aa' direction after forming a sixth mask plate in a method for manufacturing a memory provided by some embodiments of the present application; Figure 29 FIG. 6B is a schematic view of a cross-sectional structure of the structure shown in FIG. 5A in the bb' direction after forming a sixth mask plate in a method for manufacturing a memory provided by some embodiments of the present application; FIG. 6C is a schematic view of a cross-sectional structure of the structure shown in FIG. 5A in the cc' direction after forming a sixth mask plate in a method for manufacturing a memory provided by some embodiments of the present application;

[0073] FIG. 6D is a schematic view of a cross-sectional structure of the structure shown in FIG. 5A in the dd' direction after forming a sixth mask plate in a method for manufacturing a memory provided by some embodiments of the present application; Figure 29 FIG. 6E is a schematic view of a top structure of the structure shown in FIG. 5A after forming a sixth mask plate in a method for manufacturing a memory provided by some embodiments of the present application; Figure 29 Figure 29 Figure 29 Figure 29 Figure 29 Figure 29 Figure 17 Figure 30

[0074] Figure 30 ​​​​​​​​Figure (a) is a schematic cross-sectional view of the structure obtained after forming the first gate etching trench in the aa' direction in the method for fabricating a memory provided in some embodiments of this application. Figure 30 Figure (b) is Figure 30 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 30 Figure (c) is Figure 30 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 30 Figure (d) in the middle is Figure 31 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0075] Figure 31 Figure (a) is a schematic cross-sectional view of the structure obtained after forming the first gate accommodating trench in the aa' direction in the method for fabricating the memory provided in some embodiments of this application. Figure 31 Figure (b) is Figure 31 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 31 Figure (c) is Figure 31 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 31 Figure (d) in the middle is Figure 32 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0076] Figure 32 Figure (a) is a schematic cross-sectional view of the structure obtained after forming the first gate dielectric layer in the aa' direction in the method for fabricating a memory provided in some embodiments of this application. Figure 32 Figure (b) is Figure 32 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 32 Figure (c) is Figure 32 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 32 Figure (d) in the middle is Figure 33 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0077] Figure 33 Figure (a) is a schematic cross-sectional view of the structure obtained after forming the read word line in the aa' direction in the method for preparing a memory according to some embodiments of this application; Figure 33 Figure (b) is Figure 33 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 33 Figure (c) is Figure 33 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 33 Figure (d) in the middle isFigure 34 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa';

[0078] Figure 34 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 34 FIG. 1(b) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of bb'; Figure 34 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 34 FIG. 1(c) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of cc'; Figure 34 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 34 FIG. 1(d) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of dd'; Figure 34 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 34 FIG. 1(e) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of ee'; Figure 35 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa';

[0079] Figure 35 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 35 FIG. 1(b) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of bb'; Figure 35 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 35 FIG. 1(c) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of cc'; Figure 35 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 35 FIG. 1(d) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of dd'; Figure 36 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa';

[0080] Figure 36 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 36 FIG. 1(b) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of bb'; Figure 36 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 36 FIG. 1(c) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of cc'; Figure 36 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 36 FIG. 1(d) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of dd'; Figure 37 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa';

[0081] Figure 37 FIG. 1(a) is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 along the direction of aa'; Figure 37FIG. 3B is a cross-sectional view of the structure shown in FIG. 3A along the direction of bb'; Figure 37 FIG. 4B is a cross-sectional view of the structure shown in FIG. 4A along the direction of bb'; Figure 37 FIG. 5B is a cross-sectional view of the structure shown in FIG. 5A along the direction of bb'; Figure 37 FIG. 6B is a cross-sectional view of the structure shown in FIG. 6A along the direction of bb'; Figure 37 FIG. 7B is a cross-sectional view of the structure shown in FIG. 7A along the direction of bb'; Figure 37 FIG. 8B is a cross-sectional view of the structure shown in FIG. 8A along the direction of bb'; Figure 37 FIG. 9B is a cross-sectional view of the structure shown in FIG. 9A along the direction of bb'; Figure 38 FIG. 10B is a cross-sectional view of the structure shown in FIG. 10A along the direction of bb';

[0082] Figure 38 FIG. 11B is a cross-sectional view of the structure shown in FIG. 11A along the direction of bb'; Figure 38 FIG. 12B is a cross-sectional view of the structure shown in FIG. 12A along the direction of bb'; Figure 38 FIG. 13B is a cross-sectional view of the structure shown in FIG. 13A along the direction of bb'; Figure 38 FIG. 14B is a cross-sectional view of the structure shown in FIG. 14A along the direction of bb'; Figure 38 FIG. 15B is a cross-sectional view of the structure shown in FIG. 15A along the direction of bb'; Figure 38 FIG. 16B is a cross-sectional view of the structure shown in FIG. 16A along the direction of bb'; Figure 39 FIG. 17B is a cross-sectional view of the structure shown in FIG. 17A along the direction of bb';

[0083] Figure 39 FIG. 18B is a cross-sectional view of the structure shown in FIG. 18A along the direction of bb'; Figure 39 FIG. 19B is a cross-sectional view of the structure shown in FIG. 19A along the direction of bb'; Figure 39 FIG. 20B is a cross-sectional view of the structure shown in FIG. 20A along the direction of bb'; Figure 39 FIG. 21B is a cross-sectional view of the structure shown in FIG. 21A along the direction of bb'; Figure 39 FIG. 22B is a cross-sectional view of the structure shown in FIG. 22A along the direction of bb'; Figure 39 FIG. 23B is a cross-sectional view of the structure shown in FIG. 23A along the direction of bb'; Figure 40 FIG. 24B is a cross-sectional view of the structure shown in FIG. 24A along the direction of bb';

[0084] Figure 40 FIG. 25B is a cross-sectional view of the structure shown in FIG. 25A along the direction of bb'; Figure 40 FIG. 26B is a cross-sectional view of the structure shown in FIG. 26A along the direction of bb'; Figure 40 FIG. 27B is a cross-sectional view of the structure shown in FIG. 27A along the direction of bb'; Figure 40 FIG. 28B is a cross-sectional view of the structure shown in FIG. 28A along the direction of bb'; Figure 40 FIG. 29B is a cross-sectional view of the structure shown in FIG. 29A along the direction of bb'; Figure 40 FIG. 30B is a cross-sectional view of the structure shown in FIG. 30A along the direction of bb'; Figure 41FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction;

[0085] Figure 41 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 41 FIG. 1B is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the bb' direction; Figure 41 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 41 FIG. 1C is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the cc' direction; Figure 41 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 41 FIG. 1D is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the dd' direction; Figure 41 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 41 FIG. 1E is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the ee' direction; Figure 42 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction;

[0086] Figure 42 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 42 FIG. 1B is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the bb' direction; Figure 42 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 42 FIG. 1C is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the cc' direction; Figure 42 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 42 FIG. 1D is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the dd' direction; Figure 43 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction;

[0087] Figure 43 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 43 FIG. 1B is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the bb' direction; Figure 43 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 43 FIG. 1C is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the cc' direction; Figure 43 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction; Figure 43 FIG. 1D is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the dd' direction; Figure 44 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction;

[0088] Figure 44 FIG. 1A is a schematic view of a cross-sectional structure of the structure shown in FIG. 1 in the aa' direction;Figure 44 FIG. 4B is a cross-sectional view of the structure shown in FIG. 4A in the direction of bb'; Figure 44 Figure 44 FIG. 4C is a cross-sectional view of the structure shown in FIG. 4A in the direction of cc'; Figure 44 Figure 44 FIG. 4D is a cross-sectional view of the structure shown in FIG. 4A in the direction of dd'; Figure 45

[0089] Figure 45 FIG. 5A is a cross-sectional view of the structure shown in FIG. 5A in the direction of aa' after forming a second gate in a method of fabricating a memory according to some embodiments of the application; Figure 45 FIG. 5B is a cross-sectional view of the structure shown in FIG. 5A in the direction of bb'; Figure 45 Figure 45 Figure 45 Figure 45 FIG. 5D is a cross-sectional view of the structure shown in FIG. 5A in the direction of dd'; Figure 46

[0090] Figure 46 FIG. 6A is a cross-sectional view of the structure shown in FIG. 6A in the direction of aa' after forming a second semiconductor layer and a second gate dielectric layer in a method of fabricating a memory according to some embodiments of the application; Figure 46 FIG. 6B is a cross-sectional view of the structure shown in FIG. 6A in the direction of bb'; Figure 46 Figure 46 Figure 46 Figure 46 FIG. 6D is a cross-sectional view of the structure shown in FIG. 6A in the direction of dd'; Figure 47

[0091] Figure 47 FIG. 7A is a cross-sectional view of the structure shown in FIG. 7A in the direction of aa' after forming a second spacer layer in a method of fabricating a memory according to some embodiments of the application; Figure 47 FIG. 7B is a cross-sectional view of the structure shown in FIG. 7A in the direction of bb'; Figure 47 Figure 47 Figure 47 Figure 47 FIG. 7D is a cross-sectional view of the structure shown in FIG. 7A in the direction of dd'; Figure 48 ​​​​​​​​​​​​​​​

[0092] Figure 48 Figure (a) is a schematic cross-sectional view of the structure obtained after forming the second partition layer in the fabrication method of the memory provided in some embodiments of this application in the direction of aa'. Figure 48 Figure (b) is Figure 48 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 48 Figure (c) in the middle is Figure 48 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 48 Figure (d) in the middle is Figure 49 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0093] Figure 49 Figure (a) is a schematic cross-sectional view of the structure obtained after forming the tenth mask in the aa' direction in the method for fabricating the memory provided in some embodiments of this application; Figure 49 Figure (b) is Figure 49 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 49 Figure (c) in the middle is Figure 49 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 49 Figure (d) in the middle is Figure 49 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction; Figure 49 Figure (e) in the middle is Figure 50 A top view of the structure shown in Figure (a);

[0094] Figure 50 Figure (a) is a schematic cross-sectional view of the structure obtained after removing the initial support layer formed in the support etching groove in the fabrication method of the memory provided in some embodiments of this application in the direction of aa'. Figure 50 Figure (b) is Figure 50 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the bb' direction; Figure 50 Figure (c) in the middle is Figure 50 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the cc' direction; Figure 50 Figure (d) in the middle is Figure 51 A schematic diagram of the cross-sectional structure of the structure shown in Figure (a) in the dd' direction;

[0095] Figure 51 Figure (a) is a schematic cross-sectional view of the structure obtained after removing the initial support layer in each support groove in the memory fabrication method provided in some embodiments of this application in the direction of aa'. Figure 51 Figure (b) is Figure 51FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; Figure 51 FIG. 3C is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the cc' direction; Figure 51 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; Figure 51 FIG. 3D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the dd' direction; Figure 52 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction;

[0096] Figure 52 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; Figure 52 FIG. 3B is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the bb' direction; ​ FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 52 FIG. 3C is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the cc' direction; FIG. 52 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 52 FIG. 3D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the dd' direction; FIG. 52 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction;

[0097] FIG. 53 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 53 FIG. 3B is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the bb' direction; FIG. 53 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 53 FIG. 3C is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the cc' direction; FIG. 53 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 53 FIG. 3D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the dd' direction; FIG. 53 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction;

[0098] FIG. 54 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 54 FIG. 3B is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the bb' direction; FIG. 54 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 54 FIG. 3C is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the cc' direction; FIG. 54 FIG. 3A is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the aa' direction; FIG. 54 FIG. 3D is a schematic view of a cross-sectional structure of the structure shown in FIG. 2A in the dd' direction. FIG. 1

[0099] Legend of reference signs: ​

[0100] U, memory cell; T1, read transistor; T2, write transistor; RWL, read word line; WWL, write word line; BL, bit line; BL1, first part of bit line; BL1', first bit line material layer; BL2, second part of bit line; CL, connection line; GND, ground line; E1, first memory cell defining groove; E2, second memory cell defining groove; E3, support etching groove; E4, support groove; E5, read transistor etching groove; E6, read transistor accommodating groove; E7, ground line etching groove; E8, ground line accommodating groove; E9, read word line isolation groove; E10, first gate etching groove; E11, first gate accommodating groove; E12, first partition groove; E13, first bit line accommodating groove; E14, write word line defining hole; E15, write transistor accommodating groove; t, recess; 1, substrate; 2, stack structure; 201, insulating material layer; 202, conductive material layer; 203, first etching stop layer; 204a, first hard mask material layer; 204b, second hard mask material layer; 204c, third hard mask material layer; 204d, fourth hard mask material layer; 204e, fifth hard mask material layer; 204f, sixth hard mask material layer; 205a, first anti-reflective layer; 205b, second anti-reflective layer; 205c, third anti-reflective layer; 205d, fourth anti-reflective layer; 205e, fifth anti-reflective layer; 205f, sixth anti-reflective layer; 206a, first mask plate; 206b, second mask plate; 206c, third mask plate; 206d, fourth mask plate; 206e, fifth mask plate; 206f, sixth mask plate; 206g, seventh mask plate; 206h, eighth mask plate; 207, memory cell isolation layer; 208, initial support layer; 209, support layer; 21, first gate; 211, first gate dielectric layer; 212, filled dielectric layer; 213, read word line isolation layer; 214, first partition layer; 22, first semiconductor layer; 23, memory gate; 231, memory gate dielectric layer; 301, second etching stop layer; 302a, ninth hard mask material layer; 302b, tenth hard mask material layer; 303a, ninth anti-reflective layer; 303b, tenth anti-reflective layer; 304a, ninth mask plate; 304b, tenth mask plate; 31, second gate; 31', second gate material layer; 311, second gate dielectric layer; 311', second gate dielectric material layer; 32, second semiconductor layer; 32', second semiconductor material layer; 33, second partition layer; 4, first protection layer; 5, second protection layer. DETAILED DESCRIPTION

[0101] For the purposes of this application, the application will now be described in more detail with reference to the enclosed drawings. In the drawings, preferred embodiments of the application are shown. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0102] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0103] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In addition, it should be understood that, when a term is used in the singular herein, it is also intended that the term be used in the plural, unless specifically stated otherwise. It should also be understood that the terms "first," "second," etc. are used herein to describe various elements, components, regions, layers and / or sections, but are not intended to be limiting. These terms are used only to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first semiconductor layer could be termed a second semiconductor layer, and, similarly, a second semiconductor layer could be termed a first semiconductor layer; a first semiconductor layer and a second semiconductor layer are different semiconductor layers.

[0104] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other directions, and the spatially relative terms used herein can be interpreted according to the other orientations.

[0105] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0106] Need to be explained, the embodiment provided in the figure only in a schematic way illustrates the basic idea of the present application, although the figure shows only the components related to the present application, not according to the actual implementation of the number of components, shape and size drawing, the actual implementation of each component type, quantity and ratio can be a kind of arbitrary change, and its component layout type can be more complex.

[0107] Due to the deficiency of manufacturing process, the traditional 3D memory structure will cause loss of charge in the storage capacitor when reading data (also known as destructive reading), and the read-write flexibility is poor, which leads to the degradation of the use reliability and access efficiency of the memory, thereby affecting the further improvement of the 3D memory structure and performance.

[0108] In view of the deficiencies in the prior art described above, the present application provides a memory and a preparation method thereof, and an electronic device, which is beneficial to improve the storage performance and use reliability of the memory. The detailed content will be described in the subsequent embodiments.

[0109] In one aspect, according to some embodiments, the present application provides a memory.

[0110] Please refer to FIG. 4 In some embodiments, the memory can specifically include a substrate 1, a plurality of storage units U, a read word line RWL, a write word line WWL and a bit line BL.

[0111] As shown in FIG. 4 (a) of FIG. 1, FIG. 4 (b) of FIG. 2, FIG. 4 (c) of FIG. 3, and FIG. 2 (d) of FIG. 4, the plurality of storage units U are stacked on the substrate 1 along the direction perpendicular to the substrate 1. The storage unit U can include a read transistor T1 and a write transistor T2, and the read transistor T1 and the write transistor T2 in the same storage unit U are distributed in the direction parallel to the substrate 1. The read transistor T1 can include a first gate 21, a first semiconductor layer 22 and a storage gate 23, and the storage gate 23 is located on the side of the first semiconductor layer 22 away from the first gate 21. The write transistor T2 can include a second gate 31 and a second semiconductor layer 32.

[0112] The read word line RWL is located on the substrate 1 and extends in a direction perpendicular to the substrate 1; the first gate 21 of the read transistor T1 is part of the read word line RWL.

[0113] The write word line WWL is located on the substrate 1 and is spaced apart from the read word line RWL, and the write word line WWL extends in a direction perpendicular to the substrate 1; the second gate 31 of the write transistor T2 is part of the write word line WWL.

[0114] The bit line BL includes a first part BL1 and a second part BL2 connected together. The first part BL1 of the bit line can be arranged on the side of the first gate 21 away from the write transistor T2 and connected to the first semiconductor layer 22. The second part BL2 of the bit line is arranged on the side of the second semiconductor layer 32 away from the read transistor T1 and connected to the second semiconductor layer 32.

[0115] In the memory provided in the above embodiment, two transistors (the read transistor T1 and the write transistor T2) are used as the storage unit U, and the storage gate 23 is used to store the electric charge, so that the storage unit U of the double-transistor capacitorless (also referred to as 2T0C) structure is realized. Compared with the related art, the storage capacitor is omitted, so that the structural integration is improved, and the leakage and refresh time are reduced. Since the storage gate 23 is used to replace the storage capacitor, compared with the traditional memory, the electric charge in the storage capacitor will not be lost during data reading (also referred to as destructive reading). The above memory does not cause loss of electric charge during data reading, and realizes non-destructive reading, so that the memory has higher read-write flexibility, the use reliability and access efficiency of the memory are improved, and thus the storage performance and use reliability of the memory are improved.

[0116] In addition, in the memory provided in the above embodiment, the read transistor T1 includes the first gate 21 and the storage gate 23. The read transistor T1 adopts a double-gate structure, which is beneficial to improve the gate control ability of the read transistor T1, reduce the subthreshold swing, and thus improve the on-off ratio of the read transistor T1, so that the electrical performance of the memory is improved. In the memory provided in the above embodiment, the bit line BL is arranged to include the first part BL1 and the second part BL2 connected together, the first part BL1 of the bit line is connected to the read transistor T1, and the second part BL2 is connected to the write transistor T2. Compared with the related art in which the read bit line and the write bit line are arranged respectively, the above memory can reduce the number of bit lines, so that the memory has higher structural density, and is beneficial to the layout design, especially the layout design in a narrow space, so that the practicality of the memory is also improved.

[0117] As an example, as shown in FIGS. 1 and 2, the first part BL1 of the bit line arranged on different layers in a direction perpendicular to the substrate 1 can form a stepped shape. FIG. 3 and FIG. 5 As an example, as shown in FIGS. 1 and 2, the first part BL1 of the bit line arranged on different layers in a direction perpendicular to the substrate 1 can form a stepped shape.

[0118] FIG. 5 Equivalent circuit of the memory with 2T0C structure in the embodiments of the present application. In the embodiments of the present application, the storage gate 23 can be used to store electric charge, corresponding to FIG. 4 the storage node SN in (a).

[0119] In some embodiments, as shown in (a) of FIG. 4 (b) of FIG. 4 (c) of FIG. 4 and (d) of FIG. 1 , the first semiconductor layer 22 has a second surface close to the substrate 1 and a first surface away from the substrate 1 in the direction perpendicular to the substrate 1. The first part BL1 of the bit line is located on the first surface. The second semiconductor layer 32 has opposite first and second sides in the direction parallel to the substrate 1, and the second part BL2 of the bit line is located on the second side of the second semiconductor layer 32.

[0120] Please refer to FIG. 4 and FIG. 1 , in some embodiments, the memory can further include a connection line CL.

[0121] The connection line CL is located on one side of the read transistor T1 in the direction parallel to the substrate 1, and on the first and second sides of the second semiconductor layer 32.

[0122] In some embodiments, the connection line CL can be integrally connected with the second part BL2 of the bit line.

[0123] Please refer to FIG. 1 , in some embodiments, the read word line RWL can surround the sidewall of the first semiconductor layer 22, and the second semiconductor layer 32 can surround the sidewall of the write word line WWL.

[0124] Please refer to FIG. 4 and FIG. 6 , in some embodiments, the memory can further include a ground line GND. The ground line GND can be located beside and parallel to the read word line RWL. The ground line GND is connected with the first semiconductor layer 22.

[0125] In some embodiments, the ground line GND can include a main body and a plurality of branch parts.

[0126] The branch parts extend from the main body in the direction parallel to the substrate 1, and the surfaces close to and away from the substrate 1 of the branch parts are connected with the first semiconductor layer 22.

[0127] As an example, the branch portion is connected to the first semiconductor layer 22 both near the surface of the substrate 1 and away from the surface of the substrate 1. In this way, the contact resistance between the ground line GND and the first semiconductor layer 22 can be reduced.

[0128] In some embodiments, the first semiconductor layer 22 can be annular, and the first semiconductor layer 22 surrounds the storage gate 23. In this way, the gate control capability of the memory can be improved.

[0129] In another aspect, the present application also provides a memory manufacturing method according to some embodiments.

[0130] Please refer to FIG. 7 In some embodiments, the memory manufacturing method can specifically include the following steps:

[0131] S110: providing a substrate.

[0132] S120: forming a plurality of memory cells stacked along a direction perpendicular to the substrate on the substrate; the memory cells include read transistors and write transistors, the read transistors and the write transistors in the same memory cell are distributed in a direction parallel to the substrate; the read transistors include first gates, first semiconductor layers, and storage gates, and the write transistors include second gates and second semiconductor layers; wherein the storage gate is located on a side of the first semiconductor layer away from the first gate.

[0133] S130: forming a read word line extending along a direction perpendicular to the substrate on the substrate; a part of the read word line is used as the first gate of the read transistor.

[0134] S140: forming a write word line distributed apart from the read word line on the substrate; the write word line extends along a direction perpendicular to the substrate, and a part of the write word line is used as the second gate of the write transistor.

[0135] S150: forming a bit line; the bit line includes a first part and a second part connected to each other; the first part of the bit line is formed on a side of the first gate away from the write transistor, and is connected to the first semiconductor layer; the second part of the bit line is formed on a side of the second semiconductor layer away from the read transistor, and is connected to the second semiconductor layer.

[0136] In the preparation method provided in the above embodiment, two transistors (a read transistor and a write transistor) are formed to constitute a storage unit, and a storage gate is used to store electric charges, so that a storage unit of a double-transistor non-capacitor (also referred to as 2T0C) structure is implemented. Compared with the related art, the storage capacitor is omitted, so that the structural integration is improved, and the leakage and refresh time are reduced. Since the storage gate is used to replace the storage capacitor, compared with the traditional memory, the electric charges in the storage capacitor are not lost during data reading (also referred to as destructive reading). The memory prepared in the above embodiment does not cause loss of electric charges during data reading, and non-destructive reading is implemented. The memory has higher read-write flexibility, the use reliability and access efficiency of the memory are improved, and thus the storage performance and use reliability of the memory are improved.

[0137] In addition, in the memory prepared in the above embodiment, the read transistor includes a first gate and a storage gate. The read transistor adopts a double-gate structure, which is beneficial to improve the gate control capability of the read transistor, reduce the subthreshold swing, and thus improve the on-off ratio of the read transistor, so that the electrical performance of the memory is improved. In the above embodiment, the bit line is formed to include a first part and a second part connected to each other. The first part of the bit line is connected to the read transistor, and the second part is connected to the write transistor. Compared with the related art in which a read bit line and a write bit line are respectively arranged, the number of bit lines can be reduced by using the above embodiment, so that the memory has higher structural density, and the layout design, especially the layout design in a narrow space, is facilitated, and thus the practicality of the memory is improved.

[0138] Please refer to FIG. 8 In some embodiments, after the substrate is provided, the preparation method of the memory further includes: forming a stack structure on the substrate. The stack structure includes a plurality of layers of insulating material and a plurality of layers of conductive material which are alternately stacked in a vertical direction of the substrate.

[0139] In some embodiments, the process of forming the first gate, the first semiconductor layer and the read word line can specifically include the following steps:

[0140] S210: etching the insulating material layer to form a read transistor etching groove; and conformally covering the first semiconductor layer on the inner wall of the read transistor etching groove.

[0141] S220: forming a filling medium layer in the read transistor etching groove.

[0142] S230: etching the filling medium layer to form a read word line accommodation groove; filling and forming a read word line in the read word line accommodation groove; and the first gate is a part of the read word line corresponding to the first semiconductor layer.

[0143] Please refer to FIG. 6 to FIG. 8 In some embodiments, after the first gate, the first semiconductor layer and the read word line are formed, the preparation method further includes:

[0144] S310: etching the stack structure to form a write transistor accommodating groove and a write word line defining hole; the write transistor accommodating groove is located in the conductive material layer, surrounds the periphery of the write word line defining hole and is in communication with the write word line defining hole.

[0145] S320: conformally covering the second semiconductor layer on the inner wall of the write transistor accommodating groove and filling the second gate in the write transistor accommodating groove.

[0146] S330: forming a write word line in the write word line defining hole.

[0147] It should be noted that although FIG. 6 to FIG. 8 the steps in the flowchart of the method are displayed in sequence according to the arrows, these steps are not necessarily executed in sequence according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, FIG. 9 to FIG. 54 at least part of the steps in the method can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or steps or stages in other steps.

[0148] In order to more clearly illustrate the preparation method in some embodiments described above, the following FIG. 4 understand some embodiments of the present application. It should be noted that in the embodiments of the present application, the aa' direction, the bb' direction, the cc' direction and the dd' direction refer to FIG. 9 (a) figure in the drawings. It should also be noted that in the embodiments of the present application, the first direction and the second direction are defined to be parallel to the substrate 1 and intersecting.

[0149] In step S110, as shown in FIG. 9 (a) figure, FIG. 9 (b) figure, FIG. 9 (c) figure and FIG. 9 to FIG. 54 (d) figure, a substrate 1 is provided.

[0150] Exemplarily, the substrate 1 can be made of a semiconductor material, an insulating material, a conductor material, or any combination of material categories thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrate or II / VI semiconductor substrate. Alternatively, for example, the substrate 1 can be a layered substrate including a stack of Si and SiGe, a stack of Si and SiC, a silicon-on-insulator (SOI), a silicon-on-silicon germanium, or the like.

[0151] The following will be described in conjunction with FIG. 9 to FIG. 54 It is understood that, in step S120, a plurality of memory cells U are formed on the substrate 1 and stacked along a direction perpendicular to the substrate 1. The memory cell U includes a read transistor T1 and a write transistor T2, and the read transistor T1 and the write transistor T2 in the same memory cell U are distributed in a direction parallel to the substrate 1. Specifically, the read transistor T1 can include a first gate 21, a first semiconductor layer 22, and a storage gate 23, and the storage gate 23 is located on a side of the first semiconductor layer 22 away from the first gate 21. The write transistor T2 can include a second gate 31 and a second semiconductor layer 32.

[0152] In step S130, a read word line RWL is formed on the substrate 1 and extends along a direction perpendicular to the substrate 1, and a portion of the read word line RWL is used as the first gate 21 of the read transistor T1.

[0153] In step S140, a write word line WWL is formed on the substrate 1 and is distributed apart from the read word line RWL. The write word line WWL extends along a direction perpendicular to the substrate 1, and a portion of the write word line WWL is used as the second gate 31 of the write transistor T2.

[0154] In step S150, a bit line BL is formed. The bit line BL includes a first part BL1 and a second part BL2 connected to each other. The first part BL1 of the bit line is formed on a side of the first gate 21 away from the write transistor T2 and is connected to the first semiconductor layer 22. The second part BL2 of the bit line is formed on a side of the second semiconductor layer 32 away from the read transistor T1 and is connected to the second semiconductor layer 32.

[0155] The following will be described in conjunction with FIG. 9 For some embodiments, the processes in steps S120-S150 will be exemplarily described.

[0156] Exemplarily, after the substrate 1 is provided, a stack structure 2 is formed on the substrate 1. Please continue to refer to FIG. 9 (a) of FIG. 1, FIG. 9 (b) of FIG. 1,FIG. 9 Figure (c) in FIG. 10 Figure (d) in The stack structure 2 can specifically include a plurality of layers of insulating material 201 and a plurality of layers of conductive material 202 alternately stacked along the direction of the vertical substrate 1.

[0157] It can be understood that the number of layers of conductive material 202 can be set according to the number of layers of memory cells in the stacked memory cells, and one layer of memory cell can be formed in each layer of conductive material 202. The bottom layer of the stack structure 2 can be a layer of insulating material 201 or a layer of conductive material 202, both of which are allowed. In the embodiments of the present application, the bottom layer of the stack structure 2 is exemplarily illustrated as a layer of insulating material 201.

[0158] The constituting material of the layer of insulating material 201 is not specifically limited in the embodiments of the present application. As an example, the constituting material of the layer of insulating material 201 can include but is not limited to silicon dioxide (SiO2). The forming method of the layer of insulating material 201 is also not specifically limited in the embodiments of the present application. As an example, the layer of insulating material 201 can be formed by but is not limited to a plasma enhanced chemical vapor deposition (PECVD) process. The layer of insulating material 201 can at least be used to provide support and isolation in subsequent processes.

[0159] The constituting material of the layer of conductive material 202 is not specifically limited in the embodiments of the present application. As an example, the constituting material of the layer of conductive material 202 can include but is not limited to titanium nitride (TiN). The forming method of the layer of conductive material 202 is also not specifically limited in the embodiments of the present application. As an example, the layer of conductive material 202 can be formed by but is not limited to a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a chemical vapor deposition (CVD) process.

[0160] Please refer to FIG. 10 Figure (a) in FIG. 10 Figure (b) in FIG. 10 Figure (c) in FIG. 10 Figure (d) in FIG. 11(e) of FIG. 1A, after the formation of the stack structure 2, a first etching stop layer 203, a first hard mask material layer 204a and a first anti-reflective layer 205a are sequentially formed on the stack structure 2 in a direction away from the substrate 1, and a first mask plate (also referred to as a mask) 206a is formed on the surface of the first anti-reflective layer 205a away from the substrate 1. The first mask plate 206a has a first mask pattern therein, which can be used to define the position and shape of the memory cell in a direction parallel to the substrate 1.

[0161] The material of the first etching stop layer 203 is not limited in the embodiments of the present application. For example, the material of the first etching stop layer 203 can include, but is not limited to, silicon nitride (SiN). The method of forming the first etching stop layer 203 is not limited in the embodiments of the present application. For example, the first etching stop layer 203 can be formed by, but is not limited to, atomic layer deposition (ALD) or chemical vapor deposition (CVD). The first etching stop layer 203 can be used as a stop layer when the resulting structure is planarized by a chemical mechanical polishing (CMP) process in a subsequent process.

[0162] The material of the first hard mask material layer 204a is not limited in the embodiments of the present application. For example, the material of the first hard mask material layer 204a can include, but is not limited to, carbon (C). The method of forming the first hard mask material layer 204a is not limited in the embodiments of the present application. For example, the first hard mask material layer 204a can be formed by, but is not limited to, plasma enhanced chemical vapor deposition (PECVD). The first mask pattern of the first mask plate 206a can be transferred to the first hard mask material layer 204a by a lithography process in a subsequent process to form a hard mask layer.

[0163] The material of the first anti-reflective layer 205a is not limited in the embodiments of the present application. For example, the material of the first anti-reflective layer 205a can include, but is not limited to, silicon oxynitride (SiON). The method of forming the first anti-reflective layer 205a is not limited in the embodiments of the present application. For example, the first anti-reflective layer 205a can be formed by, but is not limited to, PECVD.

[0164] Please refer to FIG. 11 (a) of FIG. 1A, FIG. 11 (b) of FIG. 1A, FIG. 11 (c) of FIG. 1A, and FIG. 12Please refer to FIG. 1D, FIG. 1C, FIG. 1B and FIG. 1A, and a first mask plate 206a is used as a mask to etch the first anti-reflective layer 205a and the first hard mask material layer 204a. The first anti-reflective layer 205a and the first hard mask material layer 204a covered by the first mask plate 206a are reserved, and the first anti-reflective layer 205a and the first hard mask material layer 204a not covered by the first mask plate 206a are removed, so that the first mask pattern of the first mask plate 206a is transferred to the first anti-reflective layer 205a and the first hard mask material layer 204a. The reserved first hard mask material layer 204a is used as a first hard mask layer. Then, the first etching stop layer 203 and the stack structure 2 are etched using the first hard mask layer as a mask, so as to form the first memory cell definition groove E1 extending along the second direction (for example, the Y direction) and spaced apart in the first direction (for example, the X direction) and the second memory cell definition groove E2 extending along the first direction (for example, the X direction) and spaced apart in the second direction (for example, the Y direction) in the stack structure 2.

[0165] It can be understood that the first memory cell definition groove E1 and the second memory cell definition groove E2 can define the position and shape of the memory cell in the stack structure 2.

[0166] The embodiment of the present application does not make a specific limitation on the etching method of the first etching stop layer 203 and the stack structure 2. For example, the first etching stop layer 203 and the stack structure 2 can be etched by a dry etching process, but the present application is not limited to this.

[0167] Please refer to FIG. 12 FIG. 1A, FIG. 12 FIG. 1B, FIG. 12 FIG. 1C and FIG. 13 FIG. 1D, and a memory cell isolation layer 207 is formed in the first memory cell definition groove E1 and the second memory cell definition groove E2, so as to isolate adjacent memory cells in subsequent processes.

[0168] The embodiment of the present application does not make a specific limitation on the material of the memory cell isolation layer 207. For example, the material of the memory cell isolation layer 207 can include, but is not limited to, silicon dioxide. The embodiment of the present application does not make a specific limitation on the method of forming the memory cell isolation layer 207. For example, the memory cell isolation layer 207 can be formed by the following steps:

[0169] A storage cell isolation material layer is formed in the first storage cell defining slot E1 and the second storage cell defining slot E2, as well as on the surface of the stacked structure 2, using a deposition process. The deposition process can be, for example, atomic layer deposition (ALD) and / or spin-on dielectric (SOD) coating. Then, an annealing process is performed to densify the storage cell isolation material layer filling the first storage cell defining slot E1 and the second storage cell defining slot E2, thereby achieving better isolation. The storage cell isolation material layer formed on the surface of the stacked structure 2 is then removed, leaving the storage cell isolation material layer filling the first storage cell defining slot E1 and the second storage cell defining slot E2 as the storage cell isolation layer 207. For example, a chemical mechanical polishing (CMP) process can be used to planarize the storage cell isolation layer 207 to improve its surface flatness and thickness uniformity.

[0170] As mentioned above, during the planarization of the storage cell isolation layer 207 using the chemical mechanical polishing process, the first etch stop layer 203 can be used as a stop layer.

[0171] Please see FIG. 13 Figure (a) in the middle FIG. 13 Figure (b) in the middle FIG. 13 Figure (c) in the middle FIG. 13 Figure (d) in the middle and FIG. 14 In Figure (e), a second hard mask material layer 204b and a second anti-reflection layer 205b are formed sequentially from bottom to top along the direction perpendicular to the substrate 1 on the surfaces of the first etch stop layer 203 and the memory cell isolation layer 207 away from the substrate 1. A second mask template 206b is formed on the surface of the second anti-reflection layer 205b away from the substrate 1. The second mask template 206b has a second photomask pattern, which can be used to define the position and shape of the support etching trench in subsequent processes.

[0172] For example, the second hard mask material layer 204b, the second anti-reflection layer 205b and the second mask template 206b can be similar to the aforementioned first hard mask material layer 204a, the first anti-reflection layer 205a and the first mask template 206a, and will not be described in detail here.

[0173] Please see FIG. 14 Figure (a) in the middle FIG. 14 Figure (b) in the middle FIG. 14 Figure (c) in the middle and FIG. 15In Figure (d), the second anti-reflective layer 205b and the second hard mask material layer 204b are etched using the second mask 206b as a mask. The second anti-reflective layer 205b and the second hard mask material layer 204b covered by the second mask 206b are retained, while the second anti-reflective layer 205b and the second hard mask material layer 204b not covered by the second mask 206b are removed, thereby transferring the second photomask pattern of the second mask 206b to the second anti-reflective layer 205b and the second hard mask material layer 204b. The retained second hard mask material layer 204b serves as the second hard mask layer. Subsequently, the first etch stop layer 203 and the stacked structure 2 are etched using the second hard mask layer as a mask to form support etch grooves E3 extending along a second direction (e.g., the Y direction) and spaced apart in a first direction (e.g., the X direction) within the stacked structure 2.

[0174] For example, the etching method for the first etch stop layer 203 and the stacked structure 2 can refer to the etching method for the first etch stop layer 203 and the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0175] Please see FIG. 15 Figure (a) in the middle FIG. 15 Figure (b) in the middle FIG. 15 Figure (c) in the middle and FIG. 16 Figure (d) shows that the corresponding sidewalls of each insulating material layer 201 in the stacked structure 2 are etched in the first direction (e.g., the X direction) based on the support etching trench E3 to form a plurality of support trenches E4 located between adjacent conductive material layers 202 or between conductive material layers 202 and substrate 1.

[0176] This application does not specifically limit the method of etching the insulating material layer 201. As an example, a lateral etching process can be used to remove part of the insulating material layer 201 circumferentially based on the support etching groove E3.

[0177] Please see FIG. 16 Figure (a) in the middle FIG. 16 Figure (b) in the middle FIG. 16 Figure (c) in the middle and FIG. 17 to FIG. 33 As shown in Figure (d), an initial support layer 208 is formed by filling the support etching grooves E3 and E4. The initial support layer 208 can serve as a support in the memory.

[0178] This application does not specifically limit the constituent material of the initial support layer 208. As an example, the constituent material of the initial support layer 208 may include, but is not limited to, high-k dielectric materials (dielectric coefficient greater than 3.9).

[0179] Embodiments of the present application are not limited to the way of forming the initial support layer 208. As an example, the initial support layer 208 can be formed by, but not limited to, filling the support etching trench E3 and the support trench E4 with an atomic layer deposition process. As an example, the initial support layer 208 can be formed by the following steps:

[0180] In the support etching trench E3 and the support trench E4, and on the surface of the stack structure 2, a support material layer is formed by a deposition process, which can be, for example, an atomic layer deposition process. Then, the support material layer formed on the surface of the stack structure 2 is removed, and the support material layer filled in the support etching trench E3 and the support trench E4 is kept as the initial support layer 208. As an example, the initial support layer 208 can be planarized by a chemical mechanical polishing process, so that the surface of the initial support layer 208 away from the surface of the substrate 1 is flush with the first etching stop layer 203, to improve the surface flatness and thickness uniformity of the initial support layer 208.

[0181] The following FIG. 17 can be understood, in some embodiments, the process of forming the first gate 21, the first semiconductor layer 22 and the read word line RWL can be specifically as follows: steps S210-S230.

[0182] In step S210, the insulating material layer 201 is etched to form a read transistor etching trench E5, and the first semiconductor layer 22 is conformally covered on the inner wall of the read transistor etching trench E5.

[0183] As an example, step S210 can specifically include the following steps:

[0184] As shown in (a) of FIG. FIG. 17 , (b) of FIG. FIG. 17 , (c) of FIG. FIG. 17 , (d) of FIG. FIG. 17 and (e) of FIG. FIG. 18 , the third hard mask material layer 204c and the third anti-reflective layer 205c are formed on the first etching stop layer 203, the storage unit isolation layer 207 and the initial support layer 208 away from the surface of the substrate 1, and the third mask plate 206c is formed on the third anti-reflective layer 205c away from the surface of the substrate 1, which are sequentially stacked from bottom to top in the vertical direction of the substrate 1. The third mask plate 206c has a third mask pattern therein, which can be used to define the position and shape of the read transistor etching trench E5 in subsequent processes.

[0185] As an example, the third hard mask material layer 204c, the third anti-reflective layer 205c and the third mask plate 206c can be similar to the first hard mask material layer 204a, the first anti-reflective layer 205a and the first mask plate 206a described above, which will not be described in detail here.

[0186] like FIG. 18 Figure (a) in the middle FIG. 18 Figure (b) in the middle FIG. 18 Figure (c) in the middle and FIG. 19 As shown in Figure (d), the third anti-reflective layer 205c and the third hard mask material layer 204c are etched using the third mask 206c as a mask. The third anti-reflective layer 205c and the third hard mask material layer 204c covered by the third mask 206c are retained, while the parts of the third anti-reflective layer 205c and the third hard mask material layer 204c not covered by the third mask 206c are removed, thereby transferring the third photomask pattern of the third mask 206c to the third anti-reflective layer 205c and the third hard mask material layer 204c. The retained third hard mask material layer 204c serves as the third hard mask layer. Subsequently, the first etch stop layer 203 and the stacked structure 2 are etched using the third hard mask layer as a mask to form read transistor etch trenches E5 spaced apart in the second direction (e.g., the Y direction) within the stacked structure 2.

[0187] For example, the etching method for the first etch stop layer 203 and the stacked structure 2 can refer to the etching method for the first etch stop layer 203 and the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0188] like FIG. 19 Figure (a) in the middle FIG. 19 Figure (b) in the middle FIG. 19 Figure (c) in the middle and FIG. 20 As shown in Figure (d), the corresponding sidewalls of each insulating material layer 201 in the stacked structure 2 are etched in a first direction (e.g., the X direction) based on the read transistor etch trench E5 to form a plurality of read transistor receiving trenches E6 located between adjacent conductive material layers 202 or between the conductive material layer 202 and the substrate 1. The read transistor receiving trenches E6 may expose the sidewall of one side of the initial support layer 208.

[0189] This application does not specifically limit the method of etching the insulating material layer 201. As an example, a lateral etching process can be used, but is not limited to, to remove part of the insulating material layer 201 circumferentially based on the read transistor etching trench E5.

[0190] like FIG. 20 Figure (a) in the middle FIG. 20 Figure (b) in the middle FIG. 20 Figure (c) in the middle and FIG. 21 As shown in Figure (d), the storage gate dielectric layer 231 is conformally covered on the inner wall of the read transistor accommodating trench E6, the exposed surface of the substrate 1, and the sidewall of the read transistor etching trench E5 in the second direction (e.g., the Y direction), and then the first semiconductor layer 22 is conformally covered on the surface of the storage gate dielectric layer 231.

[0191] This application does not specifically limit the constituent material of the storage gate dielectric layer 231. As an example, the constituent material of the storage gate dielectric layer 231 may include, but is not limited to, high-k dielectric materials. Exemplarily, high-k dielectric materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). This application also does not specifically limit the method of forming the storage gate dielectric layer 231. As an example, the storage gate dielectric layer 231 may be conformally covered on the inner wall of the read transistor accommodating trench E6, the exposed surface of the substrate 1, and the sidewalls of the read transistor etching trench E5 in the second direction (e.g., the Y direction) using atomic layer deposition processes, but not limited to these.

[0192] This application does not specifically limit the constituent material of the first semiconductor layer 22. As an example, the constituent material of the first semiconductor layer 22 may include at least one of polycrystalline silicon, amorphous silicon, oxide materials, and two-dimensional materials; the oxide material may be, for example, indium gallium zinc oxide (IGZO). This application also does not specifically limit the method of forming the first semiconductor layer 22. As an example, the first semiconductor layer 22 may be conformally covered on the surface of the storage gate dielectric layer 231 using, but is not limited to, atomic layer deposition processes.

[0193] In some embodiments, a planarization process may be used to process the storage gate dielectric layer 231 and the first semiconductor layer 22 so that the end faces of the storage gate dielectric layer 231 and the first semiconductor layer 22 that are parallel to the substrate 1 and away from the substrate 1 are flush with the surface of the stacked structure 2 away from the substrate 1.

[0194] In step S220, a filling dielectric layer 212 is formed within the read transistor etching trench E5. For example... FIG. 21 Figure (a) in the middle FIG. 21 Figure (b) in the middle FIG. 21 Figure (c) in the middle and FIG. 22 As shown in Figure (d), a filling dielectric layer 212 is formed in the read transistor accommodating trench E6; at the same time, the filling dielectric layer 212 also fills the read transistor etching trench E5.

[0195] This application does not specifically limit the constituent material of the filling dielectric layer 212. As an example, the constituent material of the filling dielectric layer 212 may include, but is not limited to, oxide materials. This application also does not specifically limit the method of forming the filling dielectric layer 212. As an example, the filling dielectric layer 212 may be formed in the read transistor etching trench E5 and the read transistor receiving trench E6 using, but is not limited to, atomic layer deposition processes.

[0196] like FIG. 22 Figure (a) in the middle FIG. 22 Figure (b) in the middle FIG. 22 Figure (c) in the middle FIG. 22 Figure (d) in the middle and FIG. 23 As shown in Figure (e), a fourth hard mask material layer 204d and a fourth anti-reflection layer 205d are formed sequentially from bottom to top along the direction perpendicular to the substrate 1 on the surfaces of the first etch stop layer 203, the memory cell isolation layer 207, and the initial support layer 208 away from the substrate 1. A fourth mask template 206d is formed on the surface of the fourth anti-reflection layer 205d away from the substrate 1. The fourth mask template 206d has a fourth photomask pattern, which can be used to define the position and shape of the grounding line etching trench in subsequent processes.

[0197] For example, the fourth hard mask material layer 204d, the fourth anti-reflection layer 205d and the fourth mask template 206d can be similar to the aforementioned first hard mask material layer 204a, first anti-reflection layer 205a and first mask template 206a, and will not be described in detail here.

[0198] like FIG. 23 Figure (a) in the middle FIG. 23 Figure (b) in the middle FIG. 23 Figure (c) in the middle and FIG. 24 As shown in Figure (d), the fourth anti-reflective layer 205d and the fourth hard mask material layer 204d are etched using the fourth photomask 206d as a mask. The fourth anti-reflective layer 205d and the fourth hard mask material layer 204d covered by the fourth photomask 206d are retained, while the parts of the fourth anti-reflective layer 205d and the fourth hard mask material layer 204d not covered by the fourth photomask 206d are removed, thereby transferring the fourth photomask pattern of the fourth photomask 206d to the fourth anti-reflective layer 205d and the fourth hard mask material layer 204d. The retained fourth hard mask material layer 204d serves as the fourth hard mask layer. Subsequently, the first etch stop layer 203 and the stacked structure 2 are etched using the fourth hard mask layer as a mask to form a grounding line etch groove E7 extending along a second direction (e.g., the Y direction) within the stacked structure 2.

[0199] For example, the etching method for the first etch stop layer 203 and the stacked structure 2 can refer to the etching method for the first etch stop layer 203 and the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0200] like FIG. 24 Figure (a) in the middle FIG. 24 Figure (b) in the middle FIG. 24 Figure (c) in the middle and FIG. 25 As shown in Figure (d), the corresponding sidewalls of the filling dielectric layer 212 in each read transistor accommodating trench E6 are etched in the grounding trench E7 in the first direction (e.g., the X direction) to form a grounding trench E8 within each read transistor accommodating trench E6. The grounding trench E8 exposes at least a portion of the sidewalls of the filling dielectric layer 212 in the second direction (e.g., the Y direction), and the grounding trench E8 can be used to define the position and shape of the grounding wire in subsequent processes.

[0201] This application does not specifically limit the method of etching the filling dielectric layer 212. As an example, a lateral etching process can be used, but is not limited to, to remove part of the filling dielectric layer 212 circumferentially based on the ground wire etching groove E7.

[0202] like FIG. 25 Figure (a) in the middle FIG. 25 Figure (b) in the middle FIG. 25 Figure (c) in the middle and FIG. 26 As shown in Figure (d), the grounding wire GND is formed by filling the grounding wire receiving groove E8 and the grounding wire etching groove E7.

[0203] This application does not specifically limit the constituent materials of the grounding wire GND. As an example, the constituent materials of the grounding wire GND may include at least one of metallic materials, alloy materials, metal nitride materials, and metal oxide materials. Among them, the metallic material may be, for example, tungsten (W); the metal oxide material may be, for example, indium tin oxide (ITO). This application does not specifically limit the method of forming the grounding wire GND. As an example, the grounding wire GND can be formed in the grounding wire receiving groove E8 and the grounding wire etching groove E7 using an atomic layer deposition process.

[0204] like FIG. 26 Figure (a) in the middle FIG. 26 Figure (b) in the middle FIG. 26 Figure (c) in the middle FIG. 26 Figure (d) in the middle and FIG. 27As shown in Figure (e), a fifth hard mask material layer 204e and a fifth anti-reflection layer 205e are formed sequentially from bottom to top along the direction perpendicular to the substrate 1 on the surfaces of the first etch stop layer 203, the memory cell isolation layer 207, the initial support layer 208, the filling dielectric layer 212, and the ground line GND away from the substrate 1. A fifth mask template 206e is formed on the surface of the fifth anti-reflection layer 205e away from the substrate 1. The fifth mask template 206e has a fifth photomask pattern, which can be used to define the position and shape of the read line isolation groove in subsequent processes.

[0205] For example, the fifth hard mask material layer 204e, the fifth anti-reflection layer 205e and the fifth mask template 206e can be similar to the aforementioned first hard mask material layer 204a, first anti-reflection layer 205a and first mask template 206a, and will not be described in detail here.

[0206] like FIG. 27 Figure (a) in the middle FIG. 27 Figure (b) in the middle FIG. 27 Figure (c) in the middle and FIG. 28 As shown in Figure (d), the fifth anti-reflective layer 205e and the fifth hard mask material layer 204e are etched using the fifth mask template 206e as a mask. The fifth anti-reflective layer 205e and the fifth hard mask material layer 204e covered by the fifth mask template 206e are retained, while the parts of the fifth anti-reflective layer 205e and the fifth hard mask material layer 204e not covered by the fifth mask template 206e are removed, thereby transferring the fifth photomask pattern of the fifth mask template 206e to the fifth anti-reflective layer 205e and the fifth hard mask material layer 204e. The retained fifth hard mask material layer 204e serves as the fifth hard mask layer. Subsequently, the stacked structure 2 is etched using the fifth hard mask layer as a mask to form readout line isolation grooves E9 spaced apart in the second direction (e.g., the Y direction) within the stacked structure 2.

[0207] For example, the etching method for the stacked structure 2 can refer to the etching method for the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0208] like FIG. 28 Figure (a) in the middle FIG. 28 Figure (b) in the middle FIG. 28 Figure (c) in the middle and FIG. 29 As shown in Figure (d), a reading line isolation layer 213 is formed by filling the reading line isolation groove E9.

[0209] This application does not specifically limit the constituent material of the read line isolation layer 213. As an example, the constituent material of the read line isolation layer 213 may include, but is not limited to, silicon nitride. This application also does not specifically limit the method of forming the read line isolation layer 213. As an example, atomic layer deposition (ALD) can be used to fill the read line isolation trench E9 with the read line isolation layer 213.

[0210] In step S230, the filling dielectric layer 212 is etched to form a read word line receiving trench. Read word lines RWL are formed by filling the read word line receiving trench. The first gate 21 can be the portion of the read word line RWL corresponding to the first semiconductor layer 22.

[0211] As an example, step S230 may specifically include the following steps:

[0212] like FIG. 29 Figure (a) in the middle FIG. 29 Figure (b) in the middle FIG. 29 Figure (c) in the middle FIG. 29 Figure (d) in the middle and FIG. 30 As shown in Figure (e), a sixth hard mask material layer 204f and a sixth anti-reflection layer 205f are formed sequentially from bottom to top along the direction perpendicular to the substrate 1 on the surfaces of the first etch stop layer 203, the memory cell isolation layer 207, the initial support layer 208, the ground line GND, the filling dielectric layer 212, and the read line isolation layer 213 away from the substrate 1. A sixth mask template 206f is formed on the surface of the sixth anti-reflection layer 205f away from the substrate 1. The sixth mask template 206f contains a sixth photomask pattern, which can be used to define the position and shape of the first gate 21 in subsequent processes.

[0213] For example, the sixth hard mask material layer 204f, the sixth anti-reflection layer 205f and the sixth mask template 206f can be similar to the aforementioned first hard mask material layer 204a, first anti-reflection layer 205a and first mask template 206a, and will not be described in detail here.

[0214] like FIG. 30 Figure (a) in the middle FIG. 30 Figure (b) in the middle FIG. 30 Figure (c) in the middle and FIG. 31As shown in Figure (d), the sixth anti-reflective layer 205f and the sixth hard mask material layer 204f are etched using the sixth photomask 206f as a mask. The sixth anti-reflective layer 205f and the sixth hard mask material layer 204f covered by the sixth photomask 206f are retained, while the parts of the sixth anti-reflective layer 205f and the sixth hard mask material layer 204f not covered by the sixth photomask 206f are removed, thereby transferring the sixth photomask pattern of the sixth photomask 206f to the sixth anti-reflective layer 205f and the sixth hard mask material layer 204f. The retained sixth hard mask material layer 204f serves as the sixth hard mask layer. Subsequently, the stacked structure 2 is etched using the sixth hard mask layer as a mask to form first gate etching trenches E10 spaced apart in a second direction (e.g., the Y direction) within the stacked structure 2.

[0215] For example, the etching method for the stacked structure 2 can refer to the etching method for the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0216] like FIG. 31 Figure (a) in the middle FIG. 31 Figure (b) in the middle FIG. 31 Figure (c) in the middle and FIG. 32 As shown in Figure (d), the first gate etch trench E10 etches the corresponding sidewalls of the filling dielectric layer 212 in each read transistor accommodating trench E6 in a first direction (e.g., the X direction) to form a first gate accommodating trench E11 within each read transistor accommodating trench E6. The first gate accommodating trench E11 exposes at least a portion of the sidewalls of the filling dielectric layer 212 in a second direction (e.g., the Y direction). The first gate accommodating trench E11 can be used to define the position and shape of the first gate in subsequent processes. In this embodiment, the first gate etch trench E10 and the first gate accommodating trench E11 together constitute a read word line accommodating trench.

[0217] This application does not specifically limit the method of etching the filling dielectric layer 212. As an example, a lateral etching process can be used, but is not limited to, to remove part of the filling dielectric layer 212 circumferentially based on the first gate etching trench E10.

[0218] like FIG. 32 Figure (a) in the middle FIG. 32 Figure (b) in the middle FIG. 32 Figure (c) in the middle and FIG. 33 As shown in Figure (d), the first gate dielectric layer 211 conformally covers the inner wall of the first gate accommodating trench E11. It can be understood that the first gate dielectric layer 211 surrounds the sidewall of the first semiconductor layer 22 in a second direction (e.g., the Y direction).

[0219] This application does not specifically limit the material of the first gate dielectric layer 211. As an example, the material of the first gate dielectric layer 211 may include, but is not limited to, high-k dielectric materials. The material of the first gate dielectric layer 211 may be the same as or different from the material of the storage gate dielectric layer 231. This application also does not specifically limit the method of forming the first gate dielectric layer 211. As an example, the first gate dielectric layer 211 may be conformally covered on the inner wall of the first gate receiving trench E11 using, but is not limited to, atomic layer deposition processes.

[0220] like FIG. 33 Figure (a) in the middle FIG. 33 Figure (b) in the middle FIG. 33 Figure (c) in the middle and FIG. 34 As shown in Figure (d), read word lines RWL are formed by filling the first gate receiving trench E11 and the first gate etching trench E10. Among them, the portion of the read word lines RWL filled in the first gate receiving trench E11 serves as the first gate 21.

[0221] This application does not specifically limit the material of the read line RWL in its embodiments. As an example, the material of the read line RWL may include, but is not limited to, tungsten, indium tin oxide, etc. The material of the read line RWL may be the same as or different from the material of the ground line GND. This application does not specifically limit the method of forming the read line RWL in its embodiments. As an example, the read line RWL can be formed by filling the first gate accommodating trench E11 and the first gate etching trench E10 using atomic layer deposition.

[0222] like FIG. 34 Figure (a) in the middle FIG. 34 Figure (b) in the middle FIG. 34 Figure (c) in the middle FIG. 34 Figure (d) in the middle and FIG. 35 As shown in Figure (e), a seventh hard mask material layer and a seventh anti-reflection layer (not shown in the figure for ease of understanding) are formed sequentially from bottom to top along the direction perpendicular to the substrate 1 on the surfaces of the first etch stop layer 203, the memory cell isolation layer 207, the initial support layer 208, the ground line GND, the filling dielectric layer 212, and the read line isolation layer 213 away from the substrate 1. A seventh mask template 206g is formed on the surface of the seventh anti-reflection layer away from the substrate 1. The seventh mask template 206g has a seventh photomask pattern, which can be used to define the position and shape of the first isolation groove in subsequent processes.

[0223] For example, the seventh hard mask material layer, the seventh anti-reflection layer and the seventh mask template 206g can be similar to the aforementioned first hard mask material layer 204a, first anti-reflection layer 205a and first mask template 206a, and will not be described in detail here.

[0224] like FIG. 35 Figure (a) in the middle FIG. 35 Figure (b) in the middle FIG. 35 Figure (c) in the middle and FIG. 36 As shown in Figure (d), the seventh anti-reflective layer 205 and the seventh hard mask material layer 204 are etched using the seventh mask template 206g as a mask. The seventh anti-reflective layer and the seventh hard mask material layer covered by the seventh mask template 206g are retained, while the seventh anti-reflective layer and the seventh hard mask material layer not covered by the seventh mask template 206g are removed, thereby transferring the seventh photomask pattern of the seventh mask template 206g to the seventh anti-reflective layer and the seventh hard mask material layer. The retained seventh hard mask material layer serves as the seventh hard mask layer. Subsequently, the stacked structure 2, the storage gate dielectric layer 231, and the first semiconductor layer 22 are etched using the seventh hard mask layer as a mask to form a first isolation trench E12 extending along a second direction (e.g., the Y direction) within the stacked structure 2. The first isolation trench E12 can disconnect the side of the first semiconductor layer 22 away from the write transistor, thereby effectively eliminating the parasitic channel effect in the read transistor T1, saving the process steps of removing parasitic channels, and making the process simple and easy to implement.

[0225] For example, the etching method for the stacked structure 2, the storage gate dielectric layer 231 and the first semiconductor layer 22 can refer to the etching method for the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0226] like FIG. 36 Figure (a) in the middle FIG. 36 Figure (b) in the middle FIG. 36 Figure (c) in the middle and FIG. 37 to FIG. 54 As shown in Figure (d), a first partition layer 214 is formed by filling the first partition groove E12.

[0227] This application does not specifically limit the constituent material of the first partition layer 214. As an example, the constituent material of the first partition layer 214 may include, but is not limited to, oxide materials. The constituent material of the first partition layer 214 may be the same as or different from the constituent material of the filling medium layer 212. This application also does not specifically limit the method of forming the first partition layer 214. As an example, the first partition layer 214 may be filled in the first partition trench E12 using, but is not limited to, atomic layer deposition processes.

[0228] It should be noted that, for ease of understanding, the following... FIG. 37 The first partition layer 214 is not marked.

[0229] In some embodiments, the process of forming the first portion BL1 of the bit line can specifically be manifested as the following steps: etching the filling dielectric layer 212 and a portion of the first semiconductor layer 22 to expose the second surface of the first semiconductor layer 22 near the substrate 1 to form the first bit line receiving trench E13; then, forming the first portion BL1 of the bit line in the first bit line receiving trench E13.

[0230] like FIG. 37 Figure (a) in the middle FIG. 37 Figure (b) in the middle FIG. 37 Figure (c) in the middle FIG. 37 Figure (d) in the middle and FIG. 37 As shown in Figure (e), an eighth hard mask material layer and an eighth anti-reflection layer are formed on the surfaces of the first etch stop layer 203, the memory cell isolation layer 207, the initial support layer 208, the ground line HND, the filling dielectric layer 212, and the read line isolation layer 213 away from the substrate 1. These layers are stacked sequentially from bottom to top along the direction perpendicular to the substrate 1. (For ease of understanding,) FIG. 37 Figure (a) in the middle FIG. 37 Figure (b) in the middle FIG. 37 Figure (c) in the middle and FIG. 38 (The eighth hard mask material layer and the eighth anti-reflection layer are not shown in Figure (d)). An eighth mask template 206h is formed on the surface of the eighth anti-reflection layer away from the substrate 1. The eighth mask template 206h has an eighth photomask pattern, which can be used to define the position and shape of the first part BL1 of the bit line in subsequent processes.

[0231] For example, the eighth hard mask material layer, the eighth anti-reflection layer and the eighth mask template 206h can be similar to the aforementioned first hard mask material layer 204a, first anti-reflection layer 205a and first mask template 206a, and will not be described in detail here.

[0232] In some embodiments, the first portion of the bit line is arranged in a stepped manner in a first direction (e.g., the X direction). The following example illustrates the formation of the first portion of the topmost bit line.

[0233] FIG. 38 Figure (a) in the middle FIG. 38 Figure (b) in the middle FIG. 38 Figure (c) in the middle and FIG. 39In Figure (d), the eighth anti-reflective layer 205 and the eighth hard mask material layer 204 are etched using the eighth photomask 206h as a mask. The eighth anti-reflective layer and the eighth hard mask material layer covered by the eighth photomask 206h are retained, while the eighth anti-reflective layer and the eighth hard mask material layer not covered by the eighth photomask 206h are removed, thereby transferring the eighth photomask pattern of the eighth photomask 206h to the eighth anti-reflective layer and the eighth hard mask material layer. The retained eighth hard mask material layer serves as the eighth hard mask layer. Subsequently, the topmost filling dielectric layer 212, the first semiconductor layer 22, and the memory gate dielectric layer 231 in the stacked structure 2 are etched using the eighth hard mask layer as a mask to form the first line receiving trench E13. The first line receiving trench E13 exposes the sidewall of the top layer filling dielectric layer 212 away from the initial support layer 208, and aligns the first semiconductor layer 22 and the storage gate dielectric layer 231 away from the substrate 1 in a second direction (e.g., the Y direction).

[0234] For example, the etching method for the topmost filling dielectric layer 212, the first semiconductor layer 22 and the storage gate dielectric layer 231 of the stacked structure 2 can refer to the etching method for the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0235] like FIG. 39 Figure (a) in the middle FIG. 39 Figure (b) in the middle FIG. 39 Figure (c) in the middle and FIG. 40 As shown in Figure (d), a first line material layer BL1' is formed in the first line receiving groove E13 and on the surface away from the substrate 1 of the first etch stop layer 203, the memory cell isolation layer 207, the initial support layer 208, the ground line HND, the filling dielectric layer 212 and the read line isolation layer 213.

[0236] This application does not specifically limit the method of forming the first line material layer BL1'. As an example, the first line material layer BL1' can be formed in the first line receiving trench E13 and on the surface of the first etch stop layer 203, memory cell isolation layer 207, initial support layer 208, ground line HND, filling dielectric layer 212 and read line isolation layer 213 away from the substrate 1 using a chemical vapor deposition process, but not limited to it.

[0237] like FIG. 40 Figure (a) in the middle FIG. 40 Figure (b) in the middle FIG. 40 Figure (c) in the middle and FIG. 41As shown in (d) of FIG. 1, the first bit line material layer BL1' formed away from the surface of the substrate 1 is removed, and the first bit line material layer BL1' filled in the first bit line accommodation groove E13 is reserved as the first part BL1 of the bit line. For example, the first part BL1 of the bit line can be planarized by using a chemical mechanical polishing process, so that the surface of the first part BL1 of the bit line is flush with the first etching stop layer 203 away from the surface of the substrate 1, to improve the surface flatness and thickness uniformity of the first part BL1 of the bit line.

[0238] The material of the first part BL1 of the bit line is not limited in the embodiments of the present application. For example, the material of the first part BL1 of the bit line can include but is not limited to a metal material. The metal material can be tungsten, for example. For example, when tungsten is used to prepare the first part BL1 of the bit line, the above-mentioned method of forming the first bit line material layer BL1' can use a tungsten chemical vapor deposition (WCVD) process.

[0239] For example, after the first part BL1 of the bit line is formed, a first protective layer 4 can be formed away from the surface of the substrate 1 on the first part BL1 of the bit line, the first etching stop layer 203, the storage unit isolation layer 207, the initial support layer 208, the ground line HND, the filling medium layer 212, and the read word line isolation layer 213. The first protective layer 4 can at least be used to protect the first part BL1 of the bit line from damage caused by subsequent processes.

[0240] The material of the first protective layer 4 is not limited in the embodiments of the present application. For example, the material of the first protective layer 4 can include but is not limited to an oxide material. The method of forming the first protective layer 4 is not limited in the embodiments of the present application. For example, a plasma enhanced chemical vapor deposition process can be used to deposit and form the first protective layer 4 away from the surface of the substrate 1 on the first part BL1 of the bit line, the first etching stop layer 203, the storage unit isolation layer 207, the initial support layer 208, the ground line HND, the filling medium layer 212, and the read word line isolation layer 213.

[0241] In some embodiments, after the first gate 21, the first semiconductor layer 22, and the read word line RWL are formed, the preparation method can further include steps S310-S330 as follows:

[0242] S310: Etch stacked structure 2 to form write line definition hole E14 and write transistor receiving groove E15. The write transistor receiving groove E15 is located within conductive material layer 202, surrounds the periphery of write line definition hole E14, and is connected to write line definition hole E14.

[0243] As an example, the process of forming the write line definition hole E14 and the write transistor receiving slot E15 can be specifically represented by the following steps:

[0244] like FIG. 41 Figure (a) in the middle FIG. 41 Figure (b) in the middle FIG. 41 Figure (c) in the middle FIG. 41 Figure (d) in the middle and FIG. 42 As shown in Figure (e), a second etch stop layer 301, a ninth hard mask material layer 302a, and a ninth anti-reflection layer 303a are formed sequentially from bottom to top along the direction perpendicular to the substrate 1 on the surface of the first protective layer 4 away from the substrate 1. A ninth mask 204a is formed on the surface of the ninth anti-reflection layer 303a away from the substrate 1. The ninth mask 204a contains a ninth photomask pattern, which can be used to define the position and shape of the WWL (Write Line) in subsequent processes.

[0245] For example, the ninth hard mask material layer 302a, the ninth anti-reflection layer 303a and the ninth mask template 304a can be similar to the aforementioned first hard mask material layer 204a, first anti-reflection layer 205a and first mask template 206a, and will not be described in detail here.

[0246] like FIG. 42 Figure (a) in the middle FIG. 42 Figure (b) in the middle FIG. 42 Figure (c) in the middle and FIG. 43 As shown in Figure (d), the ninth anti-reflective layer 303a and the ninth hard mask material layer 302a are etched using the ninth mask template 304a as a mask. The ninth anti-reflective layer 303a and the ninth hard mask material layer 302a covered by the ninth mask template 304a are retained, while the parts of the ninth anti-reflective layer 303a and the ninth hard mask material layer 302a not covered by the ninth mask template 304a are removed, thereby transferring the ninth photomask pattern of the ninth mask template 304a to the ninth anti-reflective layer 303a and the ninth hard mask material layer 302a. The retained ninth hard mask material layer 302a serves as the ninth hard mask layer. Subsequently, the stacked structure 2 is etched using the ninth hard mask layer as a mask to form the writing line definition hole E14.

[0247] For example, the etching method for the stacked structure 2 can refer to the etching method for the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0248] likeFIG. 43 Figure (a) in the middle FIG. 43 Figure (b) in the middle FIG. 43 Figure (c) in the middle and FIG. 44 As shown in Figure (d), the corresponding sidewalls of each conductive material layer 202 are etched based on the write line definition hole E14 to form a plurality of write transistor accommodating trenches E15 located between adjacent insulating material layers 201.

[0249] This application does not specifically limit the method of etching each conductive material layer 202. As an example, the corresponding sidewalls of each conductive material layer 202 can be etched based on the write line definition hole E14 using a back etching process, but not limited to that used in the previous application.

[0250] In step S320, a second semiconductor layer 32 is conformally covered on the inner wall of the write transistor receiving trench E15, and a second gate 31 is filled in the write transistor receiving trench E15.

[0251] As an example, step S320 may specifically include the following steps:

[0252] like FIG. 44 Figure (a) in the middle FIG. 44 Figure (b) in the middle FIG. 44 Figure (c) in the middle and FIG. 45 As shown in Figure (d), a second semiconductor material layer 32', a second gate dielectric material layer 311', and a second gate material layer 31' are sequentially formed on the inner wall of the write transistor accommodating trench E15 and the inner wall of the write word line defining hole E14. The second semiconductor material layer 32' may also cover the surface of the second etch stop layer 301 away from the substrate 1, and the second gate dielectric material layer 311' may also cover the surface of the second etch stop layer 301 away from the second etch stop layer 301. The second gate material layer 31' fills the write word line defining hole E14 and the write transistor accommodating trench E15, and may also cover the surface of the second gate dielectric material layer 311' away from the second semiconductor material layer 32'.

[0253] This application does not specifically limit the method of forming the second semiconductor material layer 32', the second gate dielectric material layer 311', and the second gate material layer 31'. As an example, atomic layer deposition (ALD) processes can be used, but are not limited to, to sequentially form the second semiconductor material layer 32', the second gate dielectric material layer 311', and the second gate material layer 31' on the inner wall of the write transistor accommodating trench E15 and the inner wall of the write word line defining via E14. It is understood that it is permissible for the methods of forming the second semiconductor material layer 32', the second gate dielectric material layer 311', and the second gate material layer 31' to be the same or different.

[0254] like FIG. 45 Figure (a) in the middle FIG. 45 Figure (b) in the middle FIG. 45Figure (c) in the middle and FIG. 46 As shown in Figure (d), the second gate material layer 31' formed in the write word line definition hole E14 is removed, and the second gate material layer 31' formed in the write transistor accommodating groove E15 is retained as the second gate 31.

[0255] This application does not specifically limit the material of the second gate 31. As an example, the material of the second gate 31 may include, but is not limited to, indium tin oxide. The material of the second gate 31 may be the same as or different from the material of the read word line (RWL). This application does not specifically limit the method of removing the second gate material layer 31' formed in the write word line definition hole E14. As an example, the second gate material layer 31' formed in the write word line definition hole E14 may be removed using, but is not limited to, a wet etching process.

[0256] like FIG. 46 Figure (a) in the middle FIG. 46 Figure (b) in the middle FIG. 46 Figure (c) in the middle and FIG. 47 As shown in Figure (d), the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the write line definition hole E14 are removed, and the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the inner wall of the write transistor receiving groove E15 are retained and used as the second semiconductor layer 32 and the second gate dielectric layer 311, respectively.

[0257] This application does not specifically limit the constituent material of the second semiconductor layer 32. As an example, the constituent material of the second semiconductor layer 32 may include, but is not limited to, indium gallium zinc oxide. The constituent material of the second semiconductor layer 32 may be the same as or different from the constituent material of the first semiconductor layer 22. This application also does not specifically limit the constituent material of the second gate dielectric layer 311. As an example, the constituent material of the second gate dielectric layer 311 may include, but is not limited to, high-k dielectric materials. The constituent material of the second gate dielectric layer 311 may be the same as or different from the constituent material of the first gate dielectric layer 211.

[0258] Furthermore, this application does not specifically limit the method for removing the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the write line definition hole E14. As an example, a wet etching process can be used, but is not limited to, to remove the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the write line definition hole E14.

[0259] It is understood that the second gate material layer 31' formed in the write line definition hole E14, the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the write line definition hole E14 can be removed simultaneously. For example, the second gate material layer 31' formed in the write line definition hole E14, the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the write line definition hole E14 can be removed using the same wet etching process. Alternatively, the second gate material layer 31' formed in the write line definition hole E14, the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the write line definition hole E14 can also be removed separately. For example, the second gate material layer 31' formed in the write line definition hole E14, the second semiconductor material layer 32' and the second gate dielectric material layer 311' formed on the sidewall and bottom of the write line definition hole E14 can be formed using multiple wet etching processes.

[0260] As an example, after forming the second semiconductor layer 32 and the second gate dielectric layer 311, a plurality of grooves t can also be formed on the end face of the second semiconductor layer 32 and the second gate dielectric layer 311 perpendicular to the substrate 1.

[0261] like FIG. 47 Figure (a) in the middle FIG. 47 Figure (b) in the middle FIG. 47 Figure (c) in the middle and FIG. 48 As shown in Figure (d), a second partition layer 33 is formed in each groove t. Exemplarily, the end face of each second partition layer 33 in the direction perpendicular to the substrate 1 may be flush with the end face of the second gate 31 in the direction perpendicular to the substrate 1.

[0262] This application does not specifically limit the constituent material of the second isolation layer 33. As an example, the constituent material of the second isolation layer 33 may include, but is not limited to, silicon dioxide. As an example, the second isolation layer 33 may be formed by, but is not limited to, the following steps: forming a second isolation material layer in each groove t and on the end face of the second gate 31 perpendicular to the direction of the substrate 1; then removing the second isolation material layer formed on the end face of the second gate 31 perpendicular to the direction of the substrate 1, and retaining the second isolation material layer formed in each groove t as the second isolation layer 33.

[0263] Exemplarily, the second barrier material layer can be formed using, but is not limited to, atomic layer deposition. Exemplarily, the second barrier material layer formed on the end face of the second gate 31 in the direction perpendicular to the substrate 1 can be removed using, but is not limited to, dry etching.

[0264] In step S330, please refer to FIG. 48 Figure (a) in the middle FIG. 48the (b) figure in FIG. 1, FIG. 48 the (c) figure in FIG. 1, and FIG. 49 the (d) figure in FIG. 1, the write word line WWL is formed in the write word line defining hole E14.

[0265] The material of the write word line WWL is not particularly limited in the embodiments of the present application. For example, the material of the write word line WWL can include, but is not limited to, indium tin oxide. The material of the write word line WWL can be the same as or different from the material of the read word line RWL. The method of forming the write word line WWL is not particularly limited in the embodiments of the present application. For example, the write word line WWL can be formed by the following steps: forming a write word line material layer on the surface of the second etching stop layer 301 away from the first protective layer 4 and in the write word line defining hole E14; and then removing the write word line material layer formed on the surface of the second etching stop layer 301 away from the first protective layer 4, and retaining the write word line material layer filled in the write word line defining hole E14 as the write word line WWL.

[0266] For example, the write word line material layer can be formed on the surface of the second etching stop layer 301 away from the first protective layer 4 and in the write word line defining hole E14 by, but not limited to, an atomic layer deposition process. For example, after the write word line material layer formed on the surface of the second etching stop layer 301 away from the first protective layer 4 is removed, the surface of the write word line WWL away from the substrate 1 can be planarized by a chemical mechanical polishing process to improve the surface flatness and thickness uniformity of the write word line WWL. As described above, the second etching stop layer 301 can be used as a stop layer in the process of planarizing the write word line WWL by the chemical mechanical polishing process.

[0267] It can be understood that, in some embodiments, the material of the write word line WWL can be the same as the material of the second gate 31. In this way, the write word line WWL and the second gate 31 can actually be formed as an integral structure.

[0268] For example, the second semiconductor layer 32 is formed to have opposite first and second sides in a direction parallel to the substrate 1, wherein the first side is closer to the read transistor T1 and the second side is farther away from the read transistor T1. In the example, the second part BL2 of the bit line can be formed on the second side of the second semiconductor layer 32.

[0269] For example, the part of the connection line CL corresponding to the first gate 21 can be used as the storage gate 23, the part of the connection line CL corresponding to the first part BL1 of the bit line can be used as the drain of the read transistor T1, and the part of the connection line CL corresponding to the second side of the second semiconductor layer 32 can be used as the drain of the write transistor T2.

[0270] As an example, the second portion BL2 of the bit line can be part of the connection line CL; for example, the end of the connection line CL furthest from the write transistor T2 can be used as the second portion BL2 of the bit line. The first portion BL1 and the second portion BL2 can together constitute the bit line BL.

[0271] like FIG. 49 Figure (a) in the middle FIG. 49 Figure (b) in the middle FIG. 49 Figure (c) in the middle FIG. 49 Figure (d) in the middle and FIG. 50 As shown in Figure (e), a tenth hard mask material layer 302b and a tenth anti-reflection layer 303b are formed sequentially from bottom to top along the direction perpendicular to the substrate 1 on the surface of the second etch stop layer 301 away from the substrate 1, and a tenth mask template 304b is formed on the surface of the tenth anti-reflection layer 303b away from the substrate 1. The tenth mask template 206b contains a tenth photomask pattern, which can be used to define the position and shape of the second partition groove in subsequent processes.

[0272] For example, the tenth hard mask material layer 302b, the tenth anti-reflection layer and the tenth mask template 206h can be similar to the aforementioned ninth hard mask material layer 302a, the ninth anti-reflection layer 303a and the ninth mask template 304a, and will not be described in detail here.

[0273] like FIG. 50 Figure (a) in the middle FIG. 50 Figure (b) in the middle FIG. 50 Figure (c) in the middle and FIG. 51 Figure (d) shows the etching of the tenth antireflective layer 303b and the tenth hard mask material layer 302b using the tenth mask template 304b as a mask. The tenth antireflective layer 303b and the tenth hard mask material layer 302b covered by the tenth mask template 304b are retained, while the parts of the tenth antireflective layer 303b and the tenth hard mask material layer 302b not covered by the tenth mask template 304b are removed, thereby transferring the tenth photomask pattern of the tenth mask template 304b to the tenth antireflective layer 303b and the tenth hard mask material layer 302b. The retained tenth hard mask material layer 302b serves as the tenth hard mask layer. Subsequently, the stacked structure 2 is etched using the tenth hard mask layer as a mask to remove the initial support layer 208 formed in the support etching groove E3.

[0274] For example, the etching method for the stacked structure 2 can refer to the etching method for the stacked structure 2 in the aforementioned steps, and will not be described in detail here.

[0275] like FIG. 51 Figure (a) in the middle FIG. 51 Figure (b) in the middle FIG. 51 Figure (c) in the middle and FIG. 52Figure (d) shows the removal of the initial support layer 208 in each support groove E4 of the stacked structure 2 based on the support etching groove E3.

[0276] This application does not specifically limit the method of removing the initial support layer 208. As an example, the initial support layer 208 in each support groove E4 of the stacked structure 2 can be removed using a lateral etching process based on the support etching groove E3.

[0277] like FIG. 52 Figure (a) in the middle FIG. 52 Figure (b) in the middle FIG. 52 Figure (c) in the middle and FIG. 53 Figure (d) shows that the first semiconductor layer 22 is partially removed based on the support etching trench E3 and support trench E4, so that the side of the first semiconductor layer 22 near the write transistor is disconnected, thereby effectively eliminating the parasitic channel effect in the read transistor T1, saving the process steps of removing parasitic channels, and the process flow is simple and easy to implement.

[0278] This application does not specifically limit the method of removing part of the first semiconductor layer 22. As an example, a wet etching process can be used, but is not limited to, to remove the part of the first semiconductor layer 22 as described above.

[0279] like FIG. 53 Figure (a) in the middle FIG. 53 Figure (b) in the middle FIG. 53 Figure (c) in the middle and FIG. 54 As shown in Figure (d), a support layer 209 is formed by filling the support etching grooves E3 and E4. The support layer 209 can serve as a support in the memory.

[0280] This application does not specifically limit the constituent material of the support layer 209. As an example, the constituent material of the support layer 209 may include, but is not limited to, high-k dielectric materials. Using a high-k dielectric material to fabricate the support layer 209 is beneficial for increasing the capacitance of the memory node in subsequent processes. The constituent material of the support layer 209 may be the same as or different from the constituent material of the initial support layer 208.

[0281] The embodiments of this application do not specifically limit the method of forming the support layer 209. As an example, the support layer 209 can be filled in the support etching trench E3 and the support trench E4 using an atomic layer deposition process, but not limited to that used.

[0282] As an example, such as FIG. 54 Figure (a) in the middle FIG. 54 Figure (b) in the middle FIG. 54 Figure (c) in the middle and ​In the (d) view in FIG. 1, after the support layer 209 is formed, a second protective layer 5 can also be formed away from the surface of the substrate 1 on the second etching stop layer 301, the write word line WWL, and the support layer 209.

[0283] The material of the second protective layer 5 is not limited in the embodiments of the present application. For example, the material of the second protective layer 5 can include, but is not limited to, an oxide material. The material of the second protective layer 5 can be the same as or different from the material of the first protective layer 4. The method of forming the second protective layer 5 is not limited in the embodiments of the present application. For example, the second protective layer 5 can be formed away from the surface of the substrate 1 on the second etching stop layer 301, the write word line WWL, and the support layer 209 by using, but not limited to, a plasma enhanced chemical vapor deposition process.

[0284] It should be noted that the method of manufacturing the memory in the embodiments of the present application can be used to manufacture the corresponding memory, and thus the technical features of the method of manufacturing the memory and the memory can be replaced and supplemented with each other without conflict, so that those skilled in the art can understand the technical content of the present application.

[0285] In another aspect, the present application also provides an electronic device according to some embodiments. The electronic device can be, for example, a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, or any device with a data storage function. The electronic device can include the memory described in some of the foregoing embodiments. Therefore, the electronic device also has the technical advantages of the memory, which will not be described in detail here.

[0286] In some embodiments, the electronic device includes a housing, a circuit board arranged in the housing, and a memory integrated on the circuit board. The structure of the memory can refer to the related description in some of the foregoing embodiments. The electronic device can also include other necessary elements or components, which are not limited in the embodiments of the present application.

[0287] In some embodiments, the external control device such as a processor or an actuator coupled with the memory can also be integrated on the circuit board. For example, the electronic device also includes a processor integrated on the circuit board. The processor is coupled with the memory, and the processor can control the read and write operations of the memory.

[0288] The technical features of the above-described embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described, and as long as the combinations of the technical features do not conflict, they should be considered as the scope of the present application.

[0289] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A memory, characterized in that, include: Substrate; Multiple storage units; A plurality of the memory cells are stacked on the substrate in a direction perpendicular to the substrate; each memory cell includes a read transistor and a write transistor, and the read transistor and the write transistor in the same memory cell are spaced apart in a direction parallel to the substrate; each read transistor includes a first gate, a first semiconductor layer and a memory gate, and each write transistor includes a second gate and a second semiconductor layer; A read word line is located on the substrate and extends in a direction perpendicular to the substrate; the first gate of the read transistor is a part of the read word line; A write line is located on the substrate and is spaced apart from the read line, the write line extending in a direction perpendicular to the substrate; the second gate of the write transistor is a part of the write line; The bit line includes a first portion and a second portion connected together; the first portion of the bit line is disposed on the side of the first gate away from the write transistor and is connected to the first semiconductor layer; the second portion of the bit line is disposed on the side of the second semiconductor layer away from the read transistor and is connected to the second semiconductor layer. The storage gate is located on the side of the first semiconductor layer opposite to the first gate.

2. The memory according to claim 1, characterized in that, The first semiconductor layer has a second surface close to the substrate and a first surface away from the substrate in a direction perpendicular to the substrate, and the first portion of the bit line is located on the first surface; the second semiconductor layer has opposing first and second sides in a direction parallel to the substrate, and the second portion of the bit line is located on the second side of the second semiconductor layer.

3. The memory according to claim 2, characterized in that, The memory also includes: connecting wires; The connection line is located on one side of the read transistor in a direction parallel to the substrate, and is located on the first side and the second side of the second semiconductor layer; the connection line is integrally connected to the second portion of the bit line.

4. The memory according to claim 2, characterized in that, The reading line surrounds the sidewall of the first semiconductor layer, and the second semiconductor layer surrounds the sidewall of the writing line.

5. The memory according to claim 1, characterized in that, Also includes: Grounding wire; The grounding wire is located beside the reading line and is parallel to the reading line; the grounding wire is connected to the first semiconductor layer.

6. The memory according to claim 5, characterized in that, The grounding wire includes a main body and multiple branch sections; The branch extends from the main body in a direction parallel to the substrate, and both the surface of the branch near the substrate and the surface away from the substrate are connected to the first semiconductor layer.

7. The memory according to claim 1, characterized in that, The first semiconductor layer is ring-shaped and surrounds the memory gate.

8. A method for fabricating a memory, characterized in that, include: Provide substrate; A plurality of memory cells are formed on the substrate and stacked in a direction perpendicular to the substrate; The memory cell includes a read transistor and a write transistor, and the read transistor and the write transistor in the same memory cell are spaced apart in a direction parallel to the substrate; the read transistor includes a first gate, a first semiconductor layer and a memory gate, and the write transistor includes a second gate and a second semiconductor layer; wherein, the memory gate is located on the side of the first semiconductor layer opposite to the first gate; A read word line is formed on the substrate, extending in a direction perpendicular to the substrate; a portion of the read word line is used as the first gate of the read transistor; Write lines are formed on the substrate at intervals from the read lines; the write lines extend in a direction perpendicular to the substrate, and a portion of the write lines serves as the second gate of the write transistor; A bit line is formed; the bit line includes a first portion and a second portion connected to each other; the first portion of the bit line is formed on the side of the first gate away from the write transistor and is connected to the first semiconductor layer; the second portion of the bit line is formed on the side of the second semiconductor layer away from the read transistor and is connected to the second semiconductor layer.

9. The method for fabricating a memory according to claim 8, characterized in that, After providing the substrate, the method for fabricating the memory further includes: A stacked structure is formed on the substrate; the stacked structure includes multiple layers of insulating material and multiple layers of conductive material alternately stacked along a direction perpendicular to the substrate; Forming the first gate, the first semiconductor layer, and the read word line includes: The insulating material layer is etched to form a read transistor etching trench; the first semiconductor layer is conformally covered on the inner wall of the read transistor etching trench; A filling dielectric layer is formed within the etching trench of the read transistor; The filling dielectric layer is etched to form a read line receiving groove; the read line is formed by filling the read line receiving groove; the first gate is the portion of the read line corresponding to the first semiconductor layer.

10. The method for fabricating a memory according to claim 9, characterized in that, After forming the first gate, the first semiconductor layer, and the read word line, the fabrication method further includes: The stacked structure is etched to form a write transistor receiving groove and a write word line defining hole; the write transistor receiving groove is located within the conductive material layer, surrounds the periphery of the write word line defining hole, and is connected to the write word line defining hole; The second semiconductor layer is conformally covered on the inner wall of the write transistor receiving trench, and the second gate is filled in the write transistor receiving trench; The writing line is formed within the defined hole for the writing line.

11. The method for fabricating a memory according to claim 10, characterized in that, The second semiconductor layer is formed in a direction parallel to the substrate, having opposing first and second sides, and a second portion of the bit line is formed on the second side of the second semiconductor layer.

12. The method for fabricating a memory according to claim 11, characterized in that, Forming the bit line includes: The filling dielectric layer and a portion of the first semiconductor layer are etched to expose a second surface of the first semiconductor layer near the substrate, forming a first bit line receiving trench; a first portion of the bit line is formed within the first bit line receiving trench.

13. An electronic device, characterized in that, include: The memory as described in any one of claims 1 to 7.

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