Semiconductor structure, method for manufacturing a semiconductor structure, and electronic device

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: forming a stack structure on a substrate, the stack structure comprising a plurality of layers of sacrificial layers and a plurality of layers of interlayer dielectric layers which are alternately stacked along a direction perpendicular to the substrate; wherein the sacrificial layers comprise non-metallic materials; etching the stack structure to form an etching groove and a first word line definition hole; the etching groove extends through the stack structure along the direction perpendicular to the substrate and along a first direction; and the first word line definition hole is located on the side of the etching groove in a second direction and has a spacing between the etching groove. In the preparation method of the semiconductor structure, the sacrificial layers in the stack structure comprise non-metallic sacrificial layers, the etching groove and the first word line definition hole formed by etching the stack structure have side walls with high steepness, and the side wall surfaces are smooth and flat, which is beneficial to improving the production yield and use reliability of the semiconductor structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure, a preparation method of the semiconductor structure and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that any slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] Based on this, the present application provides a semiconductor structure, a preparation method of the semiconductor structure and an electronic device, which is beneficial to improve the production yield and use reliability of the semiconductor structure.

[0005] In order to achieve the above-mentioned purpose, in one aspect, the present application provides, according to some embodiments, a preparation method of a semiconductor structure, the semiconductor structure comprising a first transistor and a second transistor, a first gate of the first transistor being connected with a first word line, a first source / drain of the first transistor being connected with a first bit line, and a second source / drain of the first transistor being connected with a storage gate; the storage gate simultaneously serving as a back gate of the second transistor;

[0006] The preparation method comprises:

[0007] providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of layers of sacrificial layers and a plurality of layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein the sacrificial layers comprise a non-metallic material;

[0008] etching the stack structure to form an etching groove and a first word line defining hole; the etching groove penetrates through the stack structure in the direction perpendicular to the substrate and extends in a first direction; the first word line defining hole is located on the side of the etching groove in a second direction and has a spacing between the etching groove; the first direction and the second direction intersect and are both parallel to the substrate;

[0009] lateral etching each of the sacrificial layers based on the etching groove and the first word line definition hole to form a first transistor accommodating groove and a first bit line accommodating groove; the first transistor accommodating groove is located in a first etching region of the sacrificial layer and surrounds a side of the first word line definition hole; the first bit line accommodating groove is located in a second etching region of the sacrificial layer and is between the first transistor accommodating groove and the etching groove; the second etching region and the first etching region are in communication;

[0010] forming a storage gate on a side of the first transistor accommodating groove away from the first bit line accommodating groove.

[0011] In some embodiments, the forming a storage gate on a side of the first transistor accommodating groove away from the first bit line accommodating groove includes:

[0012] forming a conductive material layer filling the etching groove, the first word line definition hole, the first transistor accommodating groove and the first bit line accommodating groove;

[0013] removing part of the conductive material layer to retain the conductive material layer formed on the side of the first transistor accommodating groove away from the first bit line accommodating groove; the retained conductive material layer serves as the storage gate.

[0014] In some embodiments, the conductive material layer filling the etching groove, the first word line definition hole, the first transistor accommodating groove and the first bit line accommodating groove is formed by an atomic layer deposition process.

[0015] In some embodiments, the interlayer dielectric layer is formed at least by an oxide material, and the sacrificial layer is formed at least by one of a nitride material and a polysilicon material.

[0016] In some embodiments, the method for manufacturing the semiconductor structure further includes:

[0017] forming a gate dielectric layer and a first word line in the first word line definition hole in sequence;

[0018] filling a first semiconductor layer in the first transistor accommodating groove; the first semiconductor layer surrounds a sidewall of the gate dielectric layer and covers an inner wall of the first bit line accommodating groove;

[0019] forming a first bit line covering the first semiconductor layer and filling the first bit line accommodating groove in the first bit line accommodating groove.

[0020] In some embodiments, before the etching the stacked structure to form an etching groove and a first word line definition hole, the method for manufacturing the semiconductor structure further includes:

[0021] etching the stack structure to form a first via and an isolation groove which are arranged in intervals and penetrate the stack structure; based on the first via and the isolation groove, laterally etching each of the sacrificial layers to form a second transistor accommodating groove and a second bit line accommodating groove;

[0022] forming an insulating medium layer and a second semiconductor layer on the sidewall of the second transistor accommodating groove and the sidewall of the second bit line accommodating groove in sequence; wherein the insulating medium layer also covers the sidewall of the first via and the sidewall of the isolation groove;

[0023] forming a second bit line in the second bit line accommodating groove, which covers the second semiconductor layer and fills the second bit line accommodating groove; filling the isolation groove to form a second bit line isolation structure; filling the first via to form a second word line;

[0024] the storage gate is formed on the side of the second semiconductor layer away from the second bit line, and the insulating medium layer is located between the second semiconductor layer and the storage gate.

[0025] In another aspect, the present application also provides a semiconductor structure according to some embodiments, comprising:

[0026] a substrate;

[0027] a plurality of memory cells; the memory cells comprise a first transistor and a second transistor; the first transistor and the second transistor in the same memory cell are arranged and connected along a second direction; the second direction is parallel to the substrate; the second transistor comprises a second semiconductor layer, a second word line medium layer, a storage gate and a second gate; the second semiconductor layer at least partially surrounds the second gate, the storage gate and the second gate have the second semiconductor layer and the second word line medium layer therebetween, and the storage gate at least partially surrounds the second semiconductor layer.

[0028] In some embodiments, the semiconductor structure further comprises a second bit line; the second bit line extends along a first direction; the first direction is parallel to the substrate and intersects with the second direction;

[0029] the second semiconductor layer at least partially surrounds the second bit line, and the second semiconductor layer is in contact with the second bit line.

[0030] In some embodiments, the semiconductor structure further comprises a second word line;

[0031] The second word line extends in a direction perpendicular to the substrate; the second gate is a part of the second word line; the second word line comprises a first main body part perpendicular to the substrate, and a first extension part extending from the first main body part to the second direction; the first extension part is connected to the second semiconductor layer through the second word line dielectric layer both away from a top surface of the substrate and close to a bottom surface of the substrate.

[0032] In some embodiments, the semiconductor structure further comprises a ground line;

[0033] The ground line comprises a second main body part perpendicular to the substrate, and a second extension part extending from the second main body part to the second direction; the second extension part is at least partially surrounded and contacted by the second semiconductor layer.

[0034] In some embodiments, the semiconductor structure further comprises a first via hole;

[0035] The first via hole is provided with the first main body part and the second main body part parallel to each other, and the second word line dielectric layer between the first main body part and the second main body part.

[0036] In some embodiments, the semiconductor structure further comprises:

[0037] A first word line definition hole perpendicular to the substrate; the first word line definition hole has a first word line and a gate dielectric layer between the first word line and a sidewall of the first word line definition hole;

[0038] A first transistor accommodation groove surrounding a circumferential side of the first word line definition hole; the first transistor accommodation groove is filled with a first semiconductor layer.

[0039] In some embodiments, the first word line definition hole and the first transistor accommodation groove are in communication.

[0040] In some embodiments, the first semiconductor layer is arranged to surround the sidewall of the gate dielectric layer.

[0041] In some embodiments, the semiconductor structure further comprises:

[0042] A first bit line extending in the first direction;

[0043] A first bit line accommodation groove, in which the first bit line is arranged; the first bit line accommodation groove and the first transistor accommodation groove are in communication.

[0044] In another aspect, the application further provides an electronic device comprising some of the semiconductor structures described above according to some embodiments.

[0045] The semiconductor structure, the preparation method of the semiconductor structure and the electronic device provided in the application can / has at least the following advantages:

[0046] In the embodiment of the application, the stack structure formed on the substrate includes a plurality of layers of sacrificial layers and a plurality of layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein the sacrificial layers include a non-metallic material. The chemical properties of the non-metallic sacrificial layers and the interlayer dielectric layers have no significant difference, so that the etching groove and the first word line definition hole formed by etching the above stack structure have a sidewall with high steepness, and the sidewall surface is smooth and flat, which is beneficial to improve the production yield and use reliability of the semiconductor structure. The sidewall of the etching groove and the first word line definition hole is formed to have a profile with high steepness and smooth and flat surface, which is also beneficial to the adhesion of the subsequent filling material, improves the filling quality, and further improves the production yield and use reliability of the semiconductor structure.

[0047] In the semiconductor structure provided in the embodiment of the application, by making the second semiconductor layer at least partially surround the second gate, the structure of CAA can be formed, and the gate control ability of the main gate is increased; and by making the storage gate at least partially surround the second semiconductor layer, the structure of GAA can be formed, the control ability of the storage gate is improved, and the voltage retention ability of the storage gate is increased, and the data storage ability of the semiconductor structure is increased. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0049] Figure 1 The flowchart of the preparation method of the semiconductor structure provided in some embodiments of the application is shown in the following figure:

[0050] Figure 2 The flowchart of step S500 in the preparation method of the semiconductor structure provided in some embodiments of the application is shown in the following figure:

[0051] Figure 3 The flowchart of the preparation method of the semiconductor structure provided in some embodiments of the application is shown in the following figure:

[0052] Figure 4 The flowchart of the preparation method of the semiconductor structure provided in some embodiments of the application is shown in the following figure:

[0053] Figure 5 The (a) figure in the above is a top view structural schematic diagram of the structure obtained after forming the stack structure in some embodiments of the application;Figure 5 Figure (a) is also a top view of the semiconductor structure provided in some embodiments of this application; Figure 5 Figure (b) is Figure 5 The cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a) is shown in the middle.

[0054] Figure 6 Figure (a) is a top view of the structure obtained after forming the partition structure in some embodiments of this application; Figure 6 Figure (b) is Figure 6 The cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a) is shown in the middle. Figure 6 Figure (c) in the middle is Figure 6 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0055] Figure 7 Figure (a) is a top view of the structure obtained after forming the first through hole, the isolation trench, the second transistor accommodating trench and the second bit line accommodating trench in some embodiments of this application; Figure 7 Figure (b) is Figure 7 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 7 Figure (c) in the middle is Figure 7 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0056] Figure 8 Figure (a) is a top view of the structure obtained after forming the sacrificial dielectric layer in some embodiments of this application; Figure 8 Figure (b) is Figure 8 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 8 Figure (c) in the middle is Figure 8 The cross-sectional view of the structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0057] Figure 9 Figure (a) is a top view of the structure obtained after forming the second semiconductor layer in some embodiments of this application; Figure 9 Figure (b) is Figure 9 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 9 Figure (c) in the middle is Figure 9 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0058] Figure 10Figure 2(a) is a top view schematic diagram of a structure after forming a second bit line material layer in some embodiments of the present application; Figure 10 Figure 2(b) is a cross-sectional view schematic diagram of the structure shown in Figure 2(a) along the direction of AA' perpendicular to the substrate; Figure 10 Figure 2(c) is a cross-sectional view schematic diagram of the structure shown in Figure 2(a) along the direction of BB' perpendicular to the substrate; Figure 10 Figure 2(d) is a top view schematic diagram of a structure after forming a second bit line in some embodiments of the present application; Figure 10 Figure 2(e) is a cross-sectional view schematic diagram of the structure shown in Figure 2(d) along the direction of AA' perpendicular to the substrate; Figure 2(f) is a cross-sectional view schematic diagram of the structure shown in Figure 2(d) along the direction of BB' perpendicular to the substrate;

[0059] Figure 11 Figure 3(a) is a top view schematic diagram of a structure after forming a ground line in some embodiments of the present application; Figure 11 Figure 3(b) is a cross-sectional view schematic diagram of the structure shown in Figure 3(a) along the direction of AA' perpendicular to the substrate; Figure 11 Figure 3(c) is a cross-sectional view schematic diagram of the structure shown in Figure 3(a) along the direction of BB' perpendicular to the substrate; Figure 11 Figure 3(d) is a top view schematic diagram of a structure after forming a second word line defining hole in some embodiments of the present application; Figure 11 Figure 3(e) is a cross-sectional view schematic diagram of the structure shown in Figure 3(d) along the direction of AA' perpendicular to the substrate; Figure 3(f) is a cross-sectional view schematic diagram of the structure shown in Figure 3(d) along the direction of BB' perpendicular to the substrate;

[0060] Figure 12 Figure 4(a) is a top view schematic diagram of a structure after forming a second word line in some embodiments of the present application; Figure 12 Figure 4(b) is a cross-sectional view schematic diagram of the structure shown in Figure 4(a) along the direction of AA' perpendicular to the substrate; Figure 12 Figure 4(c) is a cross-sectional view schematic diagram of the structure shown in Figure 4(a) along the direction of BB' perpendicular to the substrate; Figure 12 Figure 12 Figure 5(a) is a top view schematic diagram of a structure after forming a third word line in some embodiments of the present application; Figure 5(b) is a cross-sectional view schematic diagram of the structure shown in Figure 5(a) along the direction of AA' perpendicular to the substrate;

[0061] Figure 5(c) is a cross-sectional view schematic diagram of the structure shown in Figure 5(a) along the direction of BB' perpendicular to the substrate; Figure 13 Figure 13 Figure 13 Figure 6(a) is a top view schematic diagram of a structure after forming a fourth word line in some embodiments of the present application; Figure 13 Figure 6(b) is a cross-sectional view schematic diagram of the structure shown in Figure 6(a) along the direction of AA' perpendicular to the substrate; Figure 13 Figure 6(c) is a cross-sectional view schematic diagram of the structure shown in Figure 6(a) along the direction of BB' perpendicular to the substrate;

[0062] Figure 14 Figure 7(a) is a top view schematic diagram of a structure after forming a fifth word line in some embodiments of the present application; Figure 14 Figure 7(b) is a cross-sectional view schematic diagram of the structure shown in Figure 7(a) along the direction of AA' perpendicular to the substrate; Figure 14 Figure 7(c) is a cross-sectional view schematic diagram of the structure shown in Figure 7(a) along the direction of BB' perpendicular to the substrate; Figure 14 Figure 14 Figure 8(a) is a top view schematic diagram of a structure after forming a sixth word line in some embodiments of the present application; Figure 8(b) is a cross-sectional view schematic diagram of the structure shown in Figure 8(a) along the direction of AA' perpendicular to the substrate;

[0063] Figure 15 Figure (a) is a top view of the structure obtained after forming the etching groove and the first word line definition hole in some embodiments of this application; Figure 15 Figure (b) is Figure 15 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 15 Figure (c) is Figure 15 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0064] Figure 16 Figure (a) is a top view of the structure obtained after forming a conductive material layer in some embodiments of this application; Figure 16 Figure (b) is Figure 16 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 16 Figure (c) is Figure 16 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0065] Figure 17 Figure (a) is a top view of the structure obtained after forming the memory gate in some embodiments of this application; Figure 17 Figure (b) is Figure 17 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 17 Figure (c) is Figure 17 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0066] Figure 18 Figure (a) is a top view of the structure obtained after forming the sacrificial material layer in some embodiments of this application; Figure 18 Figure (b) is Figure 18 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 18 Figure (c) is Figure 18 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0067] Figure 19 Figure (a) is a top view of the structure obtained after forming the gate dielectric layer and the first word line in some embodiments of this application; Figure 19 Figure (b) is Figure 19 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 19 Figure (c) is Figure 19 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0068] Figure 20 Figure (a) is a top view of the structure obtained after exposing part of the sidewall of the gate dielectric layer in some embodiments of this application; Figure 20 Figure (b) is Figure 20 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 20 Figure (c) in the middle is Figure 20 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0069] Figure 21 Figure (a) is a top view of the structure obtained after forming the first line material layer in some embodiments of this application; Figure 21 Figure (b) is Figure 21 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 21 Figure (c) in the middle is Figure 21 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0070] Figure 22 Figure (a) is a top view of the structure obtained after forming the first semiconductor layer and the first bit line in some embodiments of this application; Figure 22 Figure (b) is Figure 22 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 22 Figure (c) in the middle is Figure 22 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle.

[0071] Figure 23 Figure (a) is a top view of the structure obtained after forming the first line isolation structure in some embodiments of this application. Figure 23 Figure (a) is also a top view of the semiconductor structure provided in some other embodiments of this application; Figure 23 Figure (b) is Figure 23 A schematic diagram of the cross-sectional structure perpendicular to the substrate along the AA' direction shown in Figure (a); Figure 23 Figure (c) in the middle is Figure 23 The cross-sectional structure perpendicular to the substrate along the BB' direction shown in Figure (a) is shown in the middle. Figure 23 Figure (d) in the middle is Figure 23 Figure (b) shows a schematic diagram of the cross-sectional structure of the structure parallel to the substrate along the CC' direction;

[0072] Figure 24A perspective view of a semiconductor structure provided in some embodiments of the present application;

[0073] Figure 25 A perspective view of a semiconductor structure provided in some embodiments of the present application; Figure 24 A perspective view of a semiconductor structure provided in some embodiments of the present application;

[0074] Figure 26 A perspective view of a semiconductor structure provided in some embodiments of the present application; Figure 24 A perspective view of a semiconductor structure provided in some embodiments of the present application;

[0075] Figure 27 A perspective view of a semiconductor structure provided in some embodiments of the present application; Figure 23 A perspective view of a semiconductor structure provided in some embodiments of the present application;

[0076] Figure 28 A perspective view of a semiconductor structure provided in some embodiments of the present application; Figure 26 A perspective view of a semiconductor structure provided in some embodiments of the present application.

[0077] BRIEF DESCRIPTION OF DRAWINGS

[0078] 1, substrate; 11, separation groove; 12, separation structure; 13, ground layer; 2, stack structure; 21, sacrificial layer; 22, interlayer dielectric layer; 23, cap layer; 31, gate dielectric layer; 32, first bit line isolation structure; 320, first bit line material layer; 33, second word line dielectric layer; 331, first main body portion; 332, first extension portion; 34, second bit line isolation structure; 340, second bit line material layer; 35, first word line dielectric layer; 371, second main body portion; 372, second extension portion; 41, first semiconductor layer; 411, first semiconductor material layer; 42, second semiconductor layer; 421, second semiconductor material layer; 43, storage gate; 431, conductive material layer; 51, sacrificial dielectric layer; 52, insulating dielectric layer; 53, filling dielectric layer; 54, sacrificial material layer; U, storage cell; T1, second transistor; T2, first transistor; SN, storage node; WWL, first word line; WBL, first bit line; RWL, second word line; RBL, second bit line; GND, ground line; E1, isolation groove; E2, etching groove; H1, first via; H2, first word line defining hole; H3, second word line defining hole; H4, second via; G1, second transistor accommodating groove; G2, second bit line accommodating groove; G3, first transistor accommodating groove; G4, first bit line accommodating groove; G5, capacitor accommodating groove. DETAILED DESCRIPTION

[0079] For the purpose of promoting an understanding of the principles of the application, reference will now be made to the embodiments illustrated in the drawings. There is shown in the drawings, preferred embodiments of the application. It should be noted, however, that the application can be practiced in many different forms and should not be considered limited to the embodiments set forth in the following description. Rather, these embodiments are provided so that this disclosure will be thorough and complete. It is therefore contemplated that working the application in other forms can fall within the scope of the application.

[0080] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0081] It will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or layer or intervening elements or layers can also be present. In addition, it will be understood that, when a term is used in the singular, it is also intended to include the plural, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0082] Spatially relative terms, such as "on", "under", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "on" or "under" other elements or features would then be oriented "on" or "under" the other elements or features. Thus, the exemplary term "on" can encompass both an orientation of above and below. The device can also be oriented in the other directions, and the spatially relative terms used herein are intended to encompass such additional

[0083] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0084] It should be noted that the diagrams provided in the embodiments are only schematic and that for purposes of explanation of the basic idea of the present application, only components related to the present application are shown, rather than being drawn in accordance with the number, shape and size of components in actual implementation, and the form, number and proportion of each component in actual implementation can be arbitrarily changed, and the component layout form can also be more complex.

[0085] The present application provides a semiconductor structure, a preparation method of a semiconductor structure and an electronic device, which are beneficial to improving the production yield and use reliability of the semiconductor structure. The detailed content will be described in subsequent embodiments.

[0086] In one aspect, the present application provides, according to some embodiments, a preparation method of a semiconductor structure. The semiconductor structure includes a first transistor and a second transistor. A first gate of the first transistor is connected with a first word line. A first source / drain of the first transistor is connected with a first bit line. A second source / drain of the first transistor is connected with a storage gate. The storage gate simultaneously serves as a back gate of the second transistor.

[0087] Please refer to Figure 1 In some embodiments, the preparation method of the semiconductor structure can specifically include the following steps:

[0088] S100: providing a substrate; forming a stack structure on the substrate, the stack structure including a plurality of layers of sacrificial layers and a plurality of layers of interlayer dielectric layers alternately stacked along a direction perpendicular to the substrate; wherein the sacrificial layers include a non-metallic material.

[0089] S300: etching the stack structure to form an etching groove and a first word line definition hole; the etching groove penetrates through the stack structure along a direction perpendicular to the substrate and extends along a first direction; the first word line definition hole is located on a side of the etching groove in a second direction and has a spacing between the etching groove; the first direction and the second direction intersect and are both parallel to the substrate.

[0090] S400: based on the etching groove and the first word line definition hole, laterally etching each sacrificial layer to form a first transistor accommodation groove and a first bit line accommodation groove; the first transistor accommodation groove is located in a first etching region of the sacrificial layer and surrounds a circumferential side of the first word line definition hole; the first bit line accommodation groove is located in a second etching region of the sacrificial layer and is located between the first transistor accommodation groove and the etching groove; the second etching region and the first etching region are connected in communication.

[0091] S500: forming a storage gate on a side of the first transistor accommodation groove away from the first bit line accommodation groove.

[0092] In the method for manufacturing the semiconductor structure provided in the above embodiment, the stack structure formed on the substrate comprises a plurality of layers of sacrificial layers and a plurality of layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein the sacrificial layers comprise non-metallic materials. The non-metallic sacrificial layers have no significant difference in chemical properties from the interlayer dielectric layers, so that the etching groove and the first word line defining hole formed by etching the stack structure have sidewalls with high steepness and smooth surfaces, which is conducive to improving the production yield and use reliability of the semiconductor structure. The sidewalls of the etching groove and the first word line defining hole are formed to have a profile with high steepness and smooth surfaces, which is also conducive to the adhesion of the subsequent filling material, improves the filling quality, and further improves the production yield and use reliability of the semiconductor structure.

[0093] Referring to Figure 2 In some embodiments, step S500 forms the storage gate on the side of the first transistor accommodation groove away from the first bit line accommodation groove, which can specifically include the following steps:

[0094] S510: forming a conductive material layer to fill the etching groove, the first word line defining hole, the first transistor accommodation groove and the first bit line accommodation groove.

[0095] S520: removing part of the conductive material layer to retain the conductive material layer formed on the side of the first transistor accommodation groove away from the first bit line accommodation groove; the retained conductive material layer serves as the storage gate.

[0096] Referring to Figure 3 In some embodiments, the method for manufacturing the semiconductor structure can further include the following steps:

[0097] S610: sequentially forming a gate dielectric layer and a first word line in the first word line defining hole.

[0098] S620: filling a first semiconductor layer in the first transistor accommodation groove; the first semiconductor layer surrounds the sidewall of the gate dielectric layer and covers the inner wall of the first bit line accommodation groove.

[0099] S630: forming a first bit line in the first bit line accommodation groove, which covers the first semiconductor layer and fills the first bit line accommodation groove.

[0100] It can be understood that, in the method for manufacturing the semiconductor structure provided in the above embodiment, the gate dielectric layer and the first word line are sequentially formed in the first word line defining hole, and the first semiconductor layer is formed to surround the sidewall of the gate dielectric layer, so that the first semiconductor layer surrounds the first word line, and the first transistor has a Channel-All-Around (CAA) structure, which is conducive to saving the structure size. Therefore, when the above semiconductor structure is applied to the manufacturing process of a memory, the storage density of the memory can be improved.

[0101] Please refer to Figure 4 In some embodiments, before the step S300 etching the stack structure to form the etching groove and the first word line defining hole, the method for manufacturing the semiconductor structure can further comprise the following steps:

[0102] S210: etching the stack structure to form the first via and the isolation groove which are arranged in a spaced manner and penetrate through the stack structure; based on the first via and the isolation groove, etching each of the sacrificial layers laterally to form the second transistor accommodating groove and the second bit line accommodating groove.

[0103] S220: sequentially forming the insulating medium layer and the second semiconductor layer on the sidewall of the second transistor accommodating groove and the sidewall of the second bit line accommodating groove; wherein the insulating medium layer also covers the sidewall of the first via and the sidewall of the isolation groove.

[0104] S230: forming the second bit line which covers the second semiconductor layer and fills the second bit line accommodating groove in the second bit line accommodating groove; filling the second bit line isolation structure in the isolation groove; and filling the second word line in the first via.

[0105] It should be understood that, although Figures 1 to 4 the steps in the flowchart of FIG. 1 are shown in sequence according to the direction of the arrows, these steps are not necessarily executed in sequence according to the direction of the arrows. Unless otherwise specified herein, the execution of these steps is not limited in sequence, and these steps can be executed in other sequences. Moreover, Figures 1 to 4 at least part of the steps in the flowchart of FIG. 1 can comprise multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with other steps or steps or stages in other steps.

[0106] In order to more clearly illustrate the method for manufacturing the semiconductor structure provided by some embodiments described above, the following please combine Figures 5 to 23 understand some embodiments of the present application.

[0107] It should be noted that the first direction and the second direction intersect in the embodiments of the present application. In order to facilitate understanding, the first direction is taken as the Y direction and the second direction is taken as the X direction for exemplary illustration in the embodiments of the present application.

[0108] It should be further noted that, as an example, the first transistor can be a write transistor, and the second transistor can be a read transistor; or, the first transistor can be a read transistor, and the second transistor can be a write transistor. The first transistor is taken as the write transistor and the second transistor is taken as the read transistor for exemplary illustration in the embodiments of the present application.

[0109] In step S100, as Figure 5 Figure (a) and Figure 5 As shown in Figure (b), a substrate 1 is provided, and a stacked structure 2 is formed on the substrate 1. The stacked structure 2 may include multiple sacrificial layers 21 and multiple interlayer dielectric layers 22 alternately stacked along a direction perpendicular to the substrate 1. The sacrificial layers 21 comprise a non-metallic material. This application embodiment is illustrated with the direction perpendicular to the substrate 1 as the Z-direction.

[0110] This application does not specifically limit the constituent material of substrate 1. As an example, substrate 1 can be composed of semiconductor material, insulating material, conductive material, or any combination thereof. Substrate 1 can be a single-layer structure or a multi-layer structure. For example, substrate 1 can be such as silicon (Si) substrate 1, silicon germanium (SiGe) substrate, silicon germanium carbon (SiGeC) substrate, silicon carbide (SiC) substrate, gallium arsenide (GaAs) substrate, indium arsenide (InAs) substrate, indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, substrate 1 can be a layered substrate 1 including, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0111] As an example, the bottom layer of stacked structure 2 can be a sacrificial layer 21, and the top layer of stacked structure 2 can be an interlayer dielectric layer 22; or, the bottom layer of stacked structure 2 can be an interlayer dielectric layer 22, and the top layer of stacked structure 2 can be a sacrificial layer 21. Please refer to [link to relevant documentation]. Figure 5 In Figure (b) of this application embodiment, the bottom layer of the stacked structure 2 is the sacrificial layer 21 and the top layer of the stacked structure 2 is the interlayer dielectric layer 22 for illustrative purposes.

[0112] This application does not specifically limit the materials of the sacrificial layer 21 and the interlayer dielectric layer 22. In some embodiments, the sacrificial layer 21 and the interlayer dielectric layer 22 may be formed of materials with the same or similar chemical properties.

[0113] As an example, the interlayer dielectric layer 22 can be formed of at least an oxide material; correspondingly, the sacrificial layer 21 can be formed of at least one of a nitride material and a polycrystalline silicon material, that is, the non-metallic sacrificial layer can be formed of a nitride material, or a polycrystalline silicon material, or a combination of a nitride material and a polycrystalline silicon material.

[0114] Furthermore, in some embodiments, such as Figure 5 As shown in Figure (b), in step S100, a capping layer 23 may also be formed on the stacked structure 2 to provide electrical protection for the semiconductor structure.

[0115] In some embodiments, such asFigure 6 the (a) figure in FIG. 1A, Figure 6 the (b) figure in FIG. 1B, and Figure 6 the (c) figure in FIG. 1C, the method for manufacturing the semiconductor structure can further include the following steps:

[0116] The patterned stack structure 2 to form a plurality of separation grooves 11 arranged in columns along the first direction. Then, the separation structure 12 is formed in the separation grooves 11.

[0117] As an example, the separation structure 12 obtained in the above steps can be used to define the setting position of the memory cell. Specifically, the separation structures 12 adjacent in the first direction can be used to define the setting position of the corresponding memory cell.

[0118] The material of the separation structure 12 is not limited in the embodiments of the present application. As an example, the material of the separation structure 12 includes but is not limited to one or more of oxide, nitride, oxynitride, and carbide. For example, the oxide includes silicon dioxide (SiO2); the nitride includes silicon nitride (SiN); the oxynitride includes silicon oxynitride (SiON); and the carbide includes silicon carbide.

[0119] In some embodiments, as shown in Figure 7 the (a) figure in FIG. 1A, Figure 7 the (b) figure in FIG. 1B, and Figure 7 the (c) figure in FIG. 1C, before the step S300, the method for manufacturing the semiconductor structure can further include the following steps S210-S230:

[0120] In the step S210, the stack structure 2 is etched to form the first through holes H1 and the isolation grooves E1 which are spaced apart and penetrate through the stack structure 2; and then, based on the first through holes H1 and the isolation grooves E1, each of the sacrificial layers 21 is laterally etched to form the second transistor accommodating groove G1 and the second bit line accommodating groove G2.

[0121] It can be understood that the sacrificial layer 21 located between the first through hole H1 and the isolation groove E1 in the step S210 can be completely removed.

[0122] The present embodiments are not limited in the order of the process of forming the first through hole H1 and the isolation groove E1 in the above step S210. The isolation groove E1 can be formed at the same time as the first through hole H1, i.e., the isolation groove E1 and the first through hole H1 can be formed based on the same mask layer by using a one-time etching process, which is beneficial to simplify the process flow of the manufacturing method and improve the production efficiency of the manufacturing method; or, the isolation groove E1 can be formed separately from the first through hole H1, i.e., the isolation groove E1 and the first through hole H1 can be formed based on different mask layers by using a multi-time etching process. The present embodiments are exemplarily described by taking the isolation groove E1 and the first through hole H1 as being formed at the same time.

[0123] Specifically, such as Figure 7 Figure (a) in the middle Figure 7 Figure (b) in the middle and Figure 7 As shown in Figure (c), when the bottom layer of the stacked structure 2 is the sacrificial layer 21, the second transistor receiving trench G1 near the substrate 1 is located between the substrate 1 and the bottom interlayer dielectric layer 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the second transistor receiving trench G1 exposes the lower surface of the interlayer dielectric layer 22 near the substrate 1, and the lower sidewall of the second transistor receiving trench G1 exposes the surface of the substrate 1. The remaining second transistor receiving trenches G1 are located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the second transistor receiving trench G1 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the second transistor receiving trench G1 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0124] Accordingly, when the bottom layer of the stacked structure 2 is an interlayer dielectric layer 22, the second transistor receiving trenches G1 are all located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the second transistor receiving trench G1 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the second transistor receiving trench G1 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0125] In step S220, please refer to Figures 8 to 9 An insulating dielectric layer 52 and a second semiconductor layer 42 are sequentially formed on the sidewall of the second transistor accommodating trench G1 and the sidewall of the second bit line accommodating trench G2; wherein, the insulating dielectric layer 52 also covers the sidewall of the first through hole H1 and the sidewall of the isolation trench E1.

[0126] The process of forming the insulating dielectric layer 52 and the second semiconductor layer 42 in step S220 can be specifically represented by the following steps, for example:

[0127] like Figure 8 Figure (a) in the middle Figure 8 Figure (b) in the middle and Figure 8 As shown in Figure (c), an insulating dielectric layer 52 and a second semiconductor material layer 421 are sequentially formed on the sidewall of the second transistor accommodating trench G1, the sidewall of the first through hole H1, and the sidewall of the isolation trench E1, and a sacrificial dielectric layer 51 is formed to fill the second transistor accommodating trench G1, the first through hole H1, and the isolation trench E1.

[0128] like Figure 9 Figure (a) in the middle Figure 9 Figure (b) in the middle and Figure 9As shown in Figure (c), the sacrificial dielectric layer 51 located in the first via H1 and the isolation trench E1, as well as the second semiconductor material layer 421 on the sidewall of the first via H1 and the sidewall of the isolation trench E1, are removed to form the second semiconductor layer 42.

[0129] In step S230, please refer to Figures 9 to 11 A second bit line RBL (e.g., a read bit line) is formed in the second bit line receiving groove G2, covering the second semiconductor layer 42 and filling the second bit line receiving groove G2; a second bit line isolation structure 34 is formed in the isolation groove E1; and a second word line RWL (e.g., a read word line) is formed in the first through hole H1.

[0130] Step S230, which forms the second bit line RBL, can be specifically represented by the following steps, for example:

[0131] like Figure 9 Figure (a) in the middle Figure 9 Figure (b) in the middle and Figure 9 As shown in Figure (c), a filling medium layer 53 is formed to fill the exposed first through-hole H1 and the isolation groove E1.

[0132] like Figure 10 Figure (a) in the middle Figure 10 Figure (b) in the middle and Figure 10 As shown in Figure (c), the filling dielectric layer 53 located in the first trench E1 is removed to expose the first trench E1; then, based on the first trench E1, the sacrificial dielectric layer 51 located in the second transistor accommodating trench G1 located on both sides of the first trench E1 is removed to expose the second bit line accommodating trench G2, and a second bit line material layer 340 covering the second semiconductor layer 42 and filling the second bit line accommodating trench G2 is formed in the second bit line accommodating trench G2.

[0133] like Figure 11 Figure (a) in the middle Figure 11 Figure (b) in the middle and Figure 11 As shown in Figure (c), the second bit line material layer 340 located within the first trench E1 is removed to expose the first trench E1, and the remaining second bit line material layer 340 serves as the second bit line RBL. Subsequently, a second bit line isolation structure 34 may also be formed within the first trench E1, by way of example. The second bit line isolation structure 34 can be used to achieve isolation between adjacent second bit lines RBL.

[0134] In step S230, the second word line RWL can be formed after the second bit line RBL and the second bit line isolation structure 32 are formed. In some embodiments, a ground line GND can also be formed in the first via H1 and the second transistor receiving slot G1. The following is in conjunction with... Figures 12 to 14For example, the formation of the ground line GND and the second word line RWL in the first via hole H1 and the second transistor accommodating groove G1 can be implemented as follows:

[0135] As shown in Figure 12 (a) of FIG. 1, Figure 12 (b) of FIG. 2, and Figure 12 (c) of FIG. 3, the portion of the filling dielectric layer 53 located in the first via hole H1 is removed, and the sacrificial dielectric layer 51 located outside the first via hole H1 is further removed; the ground line GND is formed in the exposed gap.

[0136] As shown in Figure 13 (a) of FIG. 4, Figure 13 (b) of FIG. 5, and Figure 13 (c) of FIG. 6, the remaining filling dielectric layer 53 is removed, and the sacrificial dielectric layer 51 located outside the first via hole H1 is further removed to form the second word line definition hole H3.

[0137] As shown in Figure 14 (a) of FIG. 7, Figure 14 (b) of FIG. 8, and Figure 14 (c) of FIG. 9, the second word line dielectric layer 33 covering the inner wall of the second word line definition hole H3 is formed, and the second word line RWL covering the second word line dielectric layer 33 and filling the second word line definition hole H3 is formed.

[0138] In step S300, as shown in Figure 15 (a) of FIG. 10, Figure 15 (b) of FIG. 11, and Figure 15 (c) of FIG. 12, the stack structure 2 is etched to form the etching groove E2 and the first word line definition hole H2. The etching groove E2 penetrates the stack structure 2 in a direction perpendicular to the substrate 1 and extends in the first direction, and the first word line definition hole H2 is located beside the etching groove E2 in the second direction and has a spacing between the etching groove E2.

[0139] As an example, the stack structure 2 can be etched by a dry etching process to form the etching groove E2 and the first word line definition hole H2, but not limited to this. It can be understood that the etching groove E2 and the plurality of first word line definition holes H2 can be formed at the same time, that is, the etching groove E2 and the plurality of first word line definition holes H2 can be formed by one etching process based on the same mask layer; or, the etching groove E2 and the plurality of first word line definition holes H2 can be formed separately, that is, the etching groove E2 and the plurality of first word line definition holes H2 can be formed by multiple etching processes based on different mask layers.

[0140] In step S400, please continue to refer to Figure 15 (a) of FIG. 13, Figure 15 (b) of FIG. 14, and Figure 15In Figure (c), each sacrificial layer 21 is laterally etched based on the etching trench E2 and the first word line definition hole H2 to form the first transistor accommodating trench G3 and the first word line accommodating trench G4.

[0141] The first transistor receiving trench G3 is located in the first etched region of the sacrificial layer 21 and surrounds the periphery of the first word line defining hole H2. The first word line receiving trench G4 is located in the second etched region of the sacrificial layer 21 and is located between the first transistor receiving trenches G3. It should be noted that the second etched region and the first etched region are connected.

[0142] Specifically, such as Figure 15 Figure (a) in the middle Figure 15 Figure (b) in the middle and Figure 15 As shown in Figure (c), when the bottom layer of the stacked structure 2 is the sacrificial layer 21, the first transistor receiving trench G3 near the substrate 1 is located between the substrate 1 and the bottom interlayer dielectric layer 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the first transistor receiving trench G3 exposes the lower surface of the interlayer dielectric layer 22 near the substrate 1, and the lower sidewall of the first transistor receiving trench G3 exposes the surface of the substrate 1. The remaining first transistor receiving trenches G3 are located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the first transistor receiving trench G3 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the first transistor receiving trench G3 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0143] Correspondingly, when the bottom layer of the stacked structure 2 is an interlayer dielectric layer 22, the first transistor receiving trenches G3 are all located between adjacent interlayer dielectric layers 22; that is, in the direction perpendicular to the substrate 1, the upper sidewall of the first transistor receiving trench G3 exposes the lower surface of the upper adjacent interlayer dielectric layer 22, and the lower sidewall of the first transistor receiving trench G3 exposes the upper surface of the lower adjacent interlayer dielectric layer 22.

[0144] As an example, step S400 can employ anisotropic etching to perform lateral etching on each sacrificial layer 21. Anisotropic etching selectively etches the material in a preset crystal orientation or crystal plane, leaving little or no etching traces in other directions. Therefore, using anisotropic etching for back etching in the above steps can make the morphology of the resulting structure more precise and controllable.

[0145] like Figure 15 Figure (a) in the middle Figure 15 Figure (b) in the middle and Figure 15As shown in FIG. 3(c), the sacrificial layer 21 between the first transistor accommodation groove G3 and the first bit line accommodation groove G4 is completely removed, so that the first transistor accommodation groove G3 and the first bit line accommodation groove G4 are communicated. Specifically, the plurality of first transistor accommodation grooves G3 are communicated with the first word line defining holes H2, and the plurality of first bit line accommodation grooves G4 are communicated with the etching groove E2. Since the etching groove E2 and the plurality of first word line defining holes H2 both penetrate the stack structure 2 and extend into the substrate 1, in some embodiments, the plurality of first transistor accommodation grooves G3 and the plurality of first bit line accommodation grooves G4 can be directly formed by one etching process, so as to further simplify the process flow of the preparation method and improve the production efficiency.

[0146] In step S500, referring to Figures 16 to 17 , the storage gate 43 is formed on the side of the first transistor accommodation groove G3 away from the first bit line accommodation groove G4. It can be understood that the storage gate 43 can be jointly formed with the second semiconductor layer 42 to form the second transistor T2.

[0147] It should be noted that the storage gate 43 is formed on the side of the second semiconductor layer 42 away from the second bit line RBL, and the insulating medium layer 52 is located between the second semiconductor layer 42 and the storage gate 43.

[0148] In some embodiments, step S500 forms the storage gate 43 on the side of the first transistor accommodation groove G3 away from the first bit line accommodation groove G4, which can be specifically performed as steps S510-S520.

[0149] In step S510, as shown in Figure 16 FIG. 2(a), Figure 16 FIG. 2(b), and Figure 16 FIG. 2(c), the conductive material layer 431 filling the etching groove E2, the first word line defining hole H2, the first transistor accommodation groove G3, and the first bit line accommodation groove G4 is formed.

[0150] In step S520, as shown in Figure 17 FIG. 2(a), Figure 17 FIG. 2(b), and Figure 17 FIG. 2(c), part of the conductive material layer 431 is removed to reserve the conductive material layer 431 formed on the side of the first transistor accommodation groove G3 away from the first bit line accommodation groove G4; the reserved conductive material layer 431 serves as the storage gate 43.

[0151] The present embodiment does not make specific limitation on the way of forming the conductive material layer 431 in step S510. In some embodiments, the atomic layer deposition process can be used to form the conductive material layer 431 filling the etching groove E2, the first word line defining hole H2, the first transistor accommodation groove G3, and the first bit line accommodation groove G4.

[0152] In some embodiments, the method for preparing the semiconductor structure may further include the following steps S610 to S630.

[0153] In step S610, please refer to Figures 18 to 19 A gate dielectric layer 31 and a first word line WWL (e.g., a write line) are sequentially formed within the first word line definition hole H2.

[0154] The process of forming the gate dielectric layer 31 and the first word line WWL in step S610 can be specifically represented by the following steps:

[0155] like Figure 18 Figure (a) in the middle Figure 18 Figure (b) in the middle and Figure 18 As shown in Figure (c), a sacrificial material layer 54 is formed to fill the first transistor accommodating trench G3, the first word line defining via H2, the first bit line accommodating trench G4, and the etching trench E2. For example, the sacrificial material layer 54 can be formed using a deposition process, which may include, but is not limited to, atomic layer deposition, chemical vapor deposition, and molecular layer deposition.

[0156] like Figure 19 Figure (a) in the middle Figure 19 Figure (b) in the middle and Figure 19 As shown in Figure (c), the sacrificial material layer 54 within the first word line defining hole H2 is removed. Then, the gate dielectric layer 31 and the first word line WWL are sequentially formed within the first word line defining hole H2.

[0157] It is understood that in the embodiments of this application, the sacrificial material layer 54, the sacrificial layer 21, the interlayer dielectric layer 22, and the substrate 1 all have a certain etching selectivity ratio, so as to better remove the sacrificial material layer 54 in subsequent processes.

[0158] For example, the constituent materials of the first word line WWL include, but are not limited to, one or more of conductive polycrystalline silicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. For example, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0159] For example, the material of the gate dielectric layer 31 may include, but is not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric coefficient greater than 3.9), low-k dielectric material (dielectric coefficient greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric coefficient less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (silicon carbide), or combinations thereof. Exemplarily, high-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). The material of the first word line dielectric layer 35 may be the same as or different from the material of the gate dielectric layer 31.

[0160] Please refer to the following: Figures 20 to 22 Understandably, in step S620, a first semiconductor layer 41 is filled into the first transistor receiving trench G3. Specifically, the first semiconductor layer 41 may surround the sidewall of the gate dielectric layer 31 and cover the inner wall of the first bit line receiving trench G4. Understandably, the first semiconductor layer 41 may be used to form the first transistor T1. In step S630, a first bit line WBL (e.g., a write bit line) is formed in the first bit line receiving trench G4, covering the first semiconductor layer 41 and filling the first bit line receiving trench G4.

[0161] As an example, the above steps S620~S630 can be specifically represented as follows:

[0162] like Figure 20 Figure (a) in the middle Figure 20 Figure (b) in the middle and Figure 20 As shown in Figure (c), the remaining sacrificial material layer 54 is removed to expose a portion of the sidewalls of the gate dielectric layer 31. As an example, the remaining sacrificial material layer 54 can be removed using, but is not limited to, wet etching processes.

[0163] like Figure 21 Figure (a) in the middle Figure 21 Figure (b) in the middle and Figure 21 As shown in Figure (c), a first semiconductor material layer 411 is deposited in the removal region of the remaining sacrificial material layer 54, such that the first semiconductor material layer 411 fills the first transistor accommodating trench G3 and covers the inner wall of the first line accommodating trench G4 and the sidewall of the interlayer dielectric layer 22 exposed in the etching trench E2. Subsequently, a first line material layer 320 is formed, covering the first semiconductor material layer 411 and filling the first line accommodating trench G4 and the etching trench E2.

[0164] likeFigure 22 Figure (a) in the middle Figure 22 Figure (b) in the middle and Figure 22 As shown in Figure (c), the first semiconductor material layer 411 and the first first line material layer 320 in the etch trench E2 are removed to form the first semiconductor layer 41 and the first first line WBL.

[0165] As an example, the material of the first semiconductor layer 41 may include at least one of polycrystalline silicon, amorphous silicon, oxide materials (e.g., IGZO, IZO, ITO, zinc oxide) and two-dimensional materials (e.g., graphene, molybdenum disulfide, etc.).

[0166] In some embodiments, the first semiconductor material layer 411 is formed of a metal oxide semiconductor material. For example, the material of the first semiconductor material layer 411 includes at least one of indium, gallium, zinc or tin, such as indium gallium zinc oxide (IGZO), to help reduce the leakage current of the first transistor T1, thereby ensuring the reliability of the first transistor T1 and reducing the refresh time of the first transistor T1.

[0167] Accordingly, the second semiconductor layer 42 can also be formed using a metal oxide semiconductor material, and the material of the second semiconductor layer 42 can be the same as or different from the material of the first semiconductor layer 41. For example, the material of the second semiconductor layer 42 can also be IGZO material, which helps to reduce the leakage current of the second transistor T2, thereby ensuring the reliability of the second transistor T2 and reducing the refresh time of the second transistor T2.

[0168] Furthermore, as an example, the first semiconductor material layer 411 and the first line material layer 320 can be formed using atomic layer deposition processes to form a first semiconductor material layer 411 and a first line material layer 320 with better morphology.

[0169] For example, the material of the first line WBL can be, but is not limited to, metallic materials, such as tungsten, nickel, or titanium.

[0170] In some embodiments, the first semiconductor material layer 411 and the first line material layer 320 in the etching tank E2 can be removed by a dry etching process.

[0171] In some embodiments, such as Figure 23 Figure (a) in the middle Figure 23 Figure (b) in the middle and Figure 23 As shown in Figure (c), the method for fabricating the semiconductor structure may further include the following step: forming a first line isolation structure 32 in the etching trench E2.

[0172] In another aspect, the present application provides, according to some embodiments, a semiconductor structure.

[0173] It can be understood that the semiconductor structure provided by the embodiments of the present application can be used as at least part of a memory. In some embodiments, the semiconductor structure can be a memory. The following will be described in combination with Figures 23 to 26 The semiconductor structure is taken as a 2T0C structure memory for example.

[0174] In some embodiments, the semiconductor structure can include a substrate 1 and a plurality of memory cells U.

[0175] The memory cell U is arranged on the substrate 1, and the memory cell U can include a first transistor T1 and a second transistor T2.

[0176] The first transistor T1 and the second transistor T2 in the same memory cell U are arranged and connected along a second direction, and the second direction is parallel to the substrate 1; the second transistor T1 includes a second semiconductor layer 42, a second word line RWL dielectric layer 33, a storage gate 43, and a second gate; the second semiconductor layer 42 at least partially surrounds the second gate, the storage gate 43 and the second gate have the second semiconductor layer 42 and the second word line RWL dielectric layer 33 therebetween, and the storage gate 43 at least partially surrounds the second semiconductor layer 42.

[0177] In the semiconductor structure provided by the above embodiments, by making the second semiconductor layer 42 at least partially surround the second gate, a CAA structure can be formed to increase the gate control ability of the main gate; and by making the storage gate 43 at least partially surround the second semiconductor layer 42, a GAA structure can be formed to improve the control ability of the storage gate 43, while increasing the voltage holding ability of the storage gate 43 and the data storage ability of the semiconductor structure.

[0178] For example, the second transistor T2 can be a single-gate structure or a double-gate structure. Please refer to Figures 23 to 26 It can be understood that the following embodiments in which the second transistor T2 is a double-gate structure.

[0179] In some embodiments, the semiconductor structure can further include a second bit line RBL, and the second bit line RBL can extend along a first direction parallel to the substrate 1; the first direction is parallel to the substrate and intersects the second direction.

[0180] In some embodiments, the semiconductor structure can further include a second word line RWL, and the second word line RWL extends along a direction perpendicular to the substrate 1.

[0181] The second gate is part of a second word line RWL; the second word line RWL includes a first main portion perpendicular to the substrate 1, and a first extending portion 332 extending from the first main portion 331 in a second direction; the first extending portion is connected to the second semiconductor layer 42 through the second word line RWL dielectric layer 33 both away from the top surface of the substrate 1 and close to the bottom surface of the substrate 1.

[0182] In some embodiments, the semiconductor structure can further include a first bit line WBL extending along a first direction parallel to the substrate 1.

[0183] In some embodiments, the semiconductor structure can further include a first word line WWL extending along a direction perpendicular to the substrate 1, and a second word line RWL extending along a direction perpendicular to the substrate 1; the sidewall of the first word line WWL is provided with a gate dielectric layer 31, and the sidewall of the second word line RWL is provided with a second word line dielectric layer 33.

[0184] Here, the second bit line RBL and the second word line RWL are insulated. The second word line RWL, when used as a read word line of the semiconductor structure, can also be used as a gate of the second transistor T2 in each memory cell U, for controlling the on-off of the second transistor T2.

[0185] In some embodiments, the semiconductor structure can further include a ground line GND. Specifically, the ground line GND is located beside the second word line RWL and parallel to the second word line RWL.

[0186] In some embodiments, the first transistor T1 can include a first semiconductor layer 41. The first semiconductor layer 41 is arranged to surround the sidewall of the gate dielectric layer 31, and cover the upper and lower surfaces of the first bit line WBL and the sidewall of the first bit line WBL close to the first word line WWL.

[0187] In some embodiments, the second transistor T2 can include a second semiconductor layer 42 and a storage gate 43. The second semiconductor layer 42 at least partially surrounds the second bit line RBL, and the second semiconductor layer 42 is in contact with the second bit line RBL.

[0188] For example, the second semiconductor layer 42 is arranged to surround the sidewall of the insulating dielectric layer 52 along the first direction, and arranged to surround the side of the ground line GND away from the second word line RWL, and cover the upper and lower surfaces of the corresponding second bit line RBL; the storage gate 43 is arranged to the side of the second semiconductor layer 42 away from the second bit line RBL.

[0189] In the semiconductor structure provided by the above embodiments, the second transistor T2 adopts a double-gate structure, so that the gate control capability of the second transistor T2 is enhanced, thereby reducing the subthreshold swing, improving the on-off ratio of the second transistor T2, and enhancing the electrical performance of the semiconductor structure in the above embodiments.

[0190] In some embodiments, the second word line RWL can include a first body portion 331 and a first protruding portion 332. The first body portion 331 extends along the direction of the vertical substrate 1, and the first protruding portion 332 is disposed on the side of the second bit line RBL close to the first body portion 331. The second semiconductor layer 42 also surrounds the sidewall of the first word line dielectric layer 33 disposed to cover the first protruding portion 332.

[0191] In some embodiments, the ground line GND includes a second body portion 371 and a second protruding portion 372. The second body portion 371 extends along the direction of the vertical substrate 1, and the second protruding portion 372 is disposed on the side of the corresponding storage gate 43 close to the second body portion 371, and the second protruding portion 372 protrudes from the second body portion 371 to the second direction.

[0192] For example, the second protruding portion 372 is at least partially surrounded and contacted by the second semiconductor layer 42.

[0193] For example, the first body portion 331 and the first protruding portion 332 can be an integrally formed structure; the second body portion 371 and the second protruding portion 372 can also be an integrally formed structure.

[0194] In some embodiments, the semiconductor structure can further include a first via H1. The first via H1 can be provided with a first body portion 331 and a second body portion 371 parallel to each other, and the first body portion 331 and the second body portion 371 have a second word line dielectric layer 33 therebetween.

[0195] In some embodiments, the semiconductor structure can further include a first bit line isolation structure 32 and a second bit line isolation structure 34. The first bit line isolation structure 32 is located on the side of the first bit line WBL away from the first word line WWL and extends along the first direction; the second bit line isolation structure 34 is located on the side of the second bit line RBL away from the second word line RWL and extends along the first direction.

[0196] In some embodiments, the semiconductor structure can further include an interlayer dielectric layer 22 located on the upper and lower surfaces of the memory cell U. The interlayer dielectric layer 22 can be used to separate the memory cells U adjacent in the first direction.

[0197] In some embodiments, the semiconductor structure can further include a plurality of separation structures 12 arranged in columns in the first direction. The separation structure 12 can be used to separate the memory cells U adjacent in the first direction.

[0198] In some embodiments, an insulating dielectric layer 52 is further provided between each conductive structure of the semiconductor structure, which can avoid charge leakage and effectively reduce the leakage current.

[0199] As an example, the insulating medium layer 52 can cover the outer surface of the second semiconductor layer 42, and be located between the ground line GND and the interlayer dielectric layer 22, between the ground line GND and the substrate 1, between the second word line RWL and the interlayer dielectric layer 22, between the second word line dielectric layer 33 and the substrate 1, and between the second bit line isolation structure 34 and the substrate 1. For example, the insulating medium layer 52 located to cover the outer surface of the second semiconductor layer 42 and between the second semiconductor layer 42 and the storage gate 43 can also serve as a gate dielectric layer of the storage gate 43.

[0200] In some embodiments, the semiconductor structure can further include a ground layer 13 located in the substrate 1. The second main body portion 371 of the ground line GND penetrates the insulating medium layer 52 in the vertical direction of the substrate 1 and extends to the ground layer 13.

[0201] In some embodiments, the semiconductor structure can further include a first word line defining hole H2. The first word line defining hole H2 is perpendicular to the substrate 1.

[0202] The first word line WWL and the gate dielectric layer 31 are located in the first word line defining hole H2, and the gate dielectric layer 31 is located between the first word line WWL and the sidewall of the first word line defining hole H2.

[0203] In some embodiments, the semiconductor structure can further include a first transistor accommodating groove G3. The first transistor accommodating groove G3 surrounds the circumferential side of the first word line defining hole H2.

[0204] As an example, the first transistor accommodating groove G3 can be filled with the first semiconductor layer 41.

[0205] In some embodiments, the first word line defining hole H2 and the first transistor accommodating groove G3 can be in communication.

[0206] In some embodiments, the semiconductor structure can further include a first bit line accommodating groove G4. The first bit line WBL can be arranged in the first bit line accommodating groove G4. As an example, the first bit line accommodating groove G4 and the first transistor accommodating groove G3 can be in communication.

[0207] Figure 27 For the semiconductor structure of the memory of the 2T0C structure in the present embodiment, an equivalent circuit thereof is shown as an example, Figure 28 wherein an equivalent circuit of a memory cell U is shown as an example. Please understand in combination with Figures 23 to 26 The storage gate 43 can be used to store charges, for example, the storage gate 43, the second semiconductor layer 42, and the insulating medium layer 52 therebetween can be equivalent to a capacitor, corresponding to Figure 27 the storage node SN in Figure 28 The ground line GND can be used to connect the ground voltage G.

[0208] It should be noted that the semiconductor structures in the embodiments of the present application can be prepared by using the corresponding preparation methods of the semiconductor structures, and thus the technical features of the structure embodiments and the method embodiments can be replaced and supplemented with each other without conflicts, so as to enable the person skilled in the art to understand the technical content of the present application.

[0209] In another aspect, the present application also provides an electronic device according to some embodiments, which can include some of the above semiconductor structures. The electronic device can include but is not limited to mobile phones, televisions, displays, tablets, computers and the like. Since the semiconductor structure with better performance and reliability is used, the electronic device of the embodiments of the present application has more beneficial performance and higher reliability.

[0210] The technical features of the above embodiments can be combined arbitrarily, and in order to make the description simple, not all possible combinations of the technical features of the above embodiments are described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0211] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for those skilled in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The semiconductor structure comprises a first transistor and a second transistor, a first gate of the first transistor is connected with a first word line, a first source / drain of the first transistor is connected with a first bit line, and a second source / drain of the first transistor is connected with a storage gate; The storage gate simultaneously serves as a back gate of the second transistor; The preparation method comprises: providing a substrate; forming a stack structure on the substrate, the stack structure comprising a plurality of layers of sacrificial layers and a plurality of layers of interlayer dielectric layers alternately stacked in a direction perpendicular to the substrate; wherein the sacrificial layers comprise non-metallic materials; etching the stack structure to form an etching groove and a first word line defining hole; the etching groove extends through the stack structure in a direction perpendicular to the substrate and extends in a first direction; the first word line defining hole is located on a side of the etching groove in a second direction and has a spacing between the etching groove; the first direction and the second direction intersect and are both parallel to the substrate; laterally etching each of the sacrificial layers based on the etching groove and the first word line defining hole to form a first transistor accommodating groove and a first bit line accommodating groove; the first transistor accommodating groove is located in a first etching region of the sacrificial layer and surrounds a periphery of the first word line defining hole; the first bit line accommodating groove is located in a second etching region of the sacrificial layer and is located between the first transistor accommodating groove and the etching groove; the second etching region and the first etching region are connected in communication; forming a storage gate on a side of the first transistor accommodating groove away from the first bit line accommodating groove, comprising: forming a layer of conductive material filling the etching groove, the first word line defining hole, the first transistor accommodating groove and the first bit line accommodating groove; removing part of the layer of conductive material to retain the layer of conductive material formed on the side of the first transistor accommodating groove away from the first bit line accommodating groove; the retained layer of conductive material serves as the storage gate.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The layer of conductive material filling the etching groove, the first word line defining hole, the first transistor accommodating groove and the first bit line accommodating groove is formed by an atomic layer deposition process.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The interlayer dielectric layers are formed at least by using oxide materials, and the sacrificial layers are formed at least by using one of nitride materials and polysilicon materials.

4. The method of producing a semiconductor structure according to any one of claims 1 to 3, wherein The preparation method of the semiconductor structure further comprises: forming a gate dielectric layer and a first word line in the first word line defining hole in sequence; filling a first semiconductor layer in the first transistor accommodating groove; the first semiconductor layer surrounds a sidewall of the gate dielectric layer and covers an inner wall of the first bit line accommodating groove; forming a first bit line covering the first semiconductor layer and filling the first bit line accommodating groove in the first bit line accommodating groove.

5. The method of producing a semiconductor structure according to any one of claims 1 to 3, wherein Before the etching the stack structure to form the etching groove and the first word line defining hole, the preparation method of the semiconductor structure further comprises: etching the stack structure to form a first via and an isolation groove arranged in a spaced manner and penetrating through the stack structure; laterally etching each of the sacrificial layers based on the first via and the isolation groove to form a second transistor accommodating groove and a second bit line accommodating groove; An insulating medium layer and a second semiconductor layer are sequentially formed on the sidewall of the second transistor accommodating groove and the sidewall of the second bit line accommodating groove, wherein the insulating medium layer also covers the sidewall of the first via and the sidewall of the isolation groove; A second bit line is formed in the second bit line accommodating groove to cover the second semiconductor layer and fill the second bit line accommodating groove; a second bit line isolation structure is formed by filling the isolation groove; and a second word line is formed by filling the first via; The storage gate is formed on the side of the second semiconductor layer away from the second bit line, and the insulating medium layer is located between the second semiconductor layer and the storage gate.

Images