Semiconductor device and method of manufacturing a semiconductor device
By designing a metal dopant concentration gradient and support pattern structure for the lower electrode in a semiconductor device, the problem of insufficient capacitance in semiconductor devices is solved, and the effect of improving capacitance efficiency in miniaturized designs is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-06-17
- Publication Date
- 2026-04-07
AI Technical Summary
To support high-capacity and highly integrated semiconductor devices, especially DRAM, each cell needs to have a capacitance exceeding a predetermined level, a requirement that is difficult to achieve effectively with existing technologies.
By designing a metal dopant concentration gradient in the lower electrode of a semiconductor device, and utilizing the difference between the outer and inner parts of the metal dopant in the lower electrode, combined with the structure of the support pattern and the dielectric film, a capacitor structure is formed, thereby improving the capacitance efficiency of the capacitor.
This approach improves the capacitance performance of semiconductor devices while reducing design rules and feature sizes, thus meeting the demands for high capacity and high integration.
Smart Images
Figure CN120076323B_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese Invention Patent Application No. 202010552109.1, filed on June 17, 2020, entitled “Semiconductor Device and Method of Manufacturing Semiconductor Device”. TECHNICAL FIELD
[0002] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device using a capacitor as a data storage element and a method of manufacturing the same. BACKGROUND
[0003] In order to support the recent trend toward large capacity and highly integrated semiconductor devices, design rules and minimum feature sizes of semiconductor devices are being continuously reduced. Such a trend is particularly applicable to semiconductor memory devices, such as dynamic random access memory (DRAM). For example, in order for a DRAM to function properly, each cell can need to have a capacitance exceeding a predetermined level. SUMMARY
[0004] According to an embodiment of the present disclosure, there is provided a semiconductor device including: a landing pad on a substrate; a lower electrode on the landing pad and connected to the landing pad, the lower electrode including an outer portion and an inner portion inside the outer portion, the outer portion including a first region and a second region; a dielectric film on the lower electrode extending along the first region of the outer portion; and an upper electrode on the dielectric film, wherein the outer portion of the lower electrode includes a metal dopant, a concentration of the metal dopant in the first region of the outer portion is different from a concentration of the metal dopant in the second region of the outer portion.
[0005] According to another embodiment of the present disclosure, there is provided a semiconductor device including: a landing pad disposed on a substrate; a lower electrode disposed on the landing pad and connected to the landing pad and extending in a thickness direction of the substrate; at least one support pattern in contact with a portion of the lower electrode; a dielectric film extending along an outer surface of the lower electrode and an outer surface of the at least one support pattern; and an upper electrode disposed on the dielectric film, wherein the lower electrode includes a metal dopant, the outer surface of the lower electrode is at least partially doped with the metal dopant, and a concentration of the metal dopant in a portion of the outer surface of the lower electrode between the lower electrode and the dielectric film is higher than a concentration of the metal dopant in a portion of the outer surface of the lower electrode between the lower electrode and the at least one support pattern.
[0006] According to another embodiment of this disclosure, a semiconductor device is provided, comprising: a landing pad disposed on a substrate; an etch stop film disposed on the landing pad to expose a portion of the landing pad; a first support pattern disposed on the etch stop film and spaced apart from the etch stop film, and having a first thickness; a second support pattern disposed on the first support pattern and spaced apart from the first support pattern, and having a second thickness greater than the first thickness; a lower electrode disposed on the landing pad to contact the etch stop film, the first support pattern, and the second support pattern; a dielectric film extending along the contours of the lower electrode, the first support pattern, and the second support pattern; and an upper electrode disposed on the dielectric film, wherein the lower electrode includes a metal dopant, the sidewalls of the lower electrode are at least partially doped with a metal dopant, and the portion of the sidewalls of the lower electrode between the lower electrode and the second support pattern includes a portion not containing a metal dopant.
[0007] According to another embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: forming a lower electrode on a landing pad; forming a support pattern to partially contact the sidewall of the lower electrode; forming an interface layer comprising a metal dopant along the contour of the lower electrode and the support pattern; diffusing the metal dopant into the lower electrode by a heat treatment process; removing the interface layer after the heat treatment process; forming a dielectric film along the contour of the lower electrode and the support pattern; and forming an upper electrode on the dielectric film. Attached Figure Description
[0008] Features will become apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:
[0009] Figure 1 A cross-sectional view of a semiconductor device according to some embodiments of the present disclosure is shown;
[0010] Figure 2 It shows Figure 1 Enlarged cross-sectional view of the lower electrode, support pattern, and etch stop film;
[0011] Figure 3 It shows Figure 1 An enlarged sectional view of part P in the diagram;
[0012] Figure 4 The concentration of metal dopant is shown along... Figure 2 A curve showing the change of line A;
[0013] Figure 5 The concentration of metal dopant is shown along... Figure 2 A graph showing the change of line B;
[0014] Figure 6 The diagram shows the concentration of the metal dopant along... Figure 2A curve showing the change of line C;
[0015] Figure 7 Semiconductor devices according to some embodiments of the present disclosure are shown;
[0016] Figure 8 Semiconductor devices according to some embodiments of the present disclosure are shown;
[0017] Figure 9 Semiconductor devices according to some embodiments of the present disclosure are shown;
[0018] Figure 10 Semiconductor devices according to some embodiments of the present disclosure are shown;
[0019] Figure 11 Semiconductor devices according to some embodiments of the present disclosure are shown;
[0020] Figure 12 Semiconductor devices according to some embodiments of the present disclosure are shown;
[0021] Figure 13 The concentration of metal dopant at... Figure 12 A graph showing the changes near the outer surface of the lower electrode of a semiconductor device;
[0022] Figure 14 Semiconductor devices according to some embodiments of the present disclosure are shown;
[0023] Figure 15 Semiconductor devices according to some embodiments of the present disclosure are shown; and
[0024] Figures 16 to 21 A cross-sectional view is shown of a stage in a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation
[0025] Figure 1 This is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure. Figure 2 It is shown Figure 1 A cross-sectional view of the lower electrode, support pattern, and etch stop film. Figure 3 yes Figure 1 An enlarged sectional view of part P. Figure 4 This shows the concentration of the metal dopant along... Figure 2 The curve showing the change of line A. Figure 5 This shows the concentration of the metal dopant along... Figure 2 The curve showing the change of line B. Figure 6 This shows the concentration of the metal dopant along... Figure 2 The curve showing the change of line C.
[0026] Reference Figures 1 to 3 Semiconductor devices according to some embodiments of the present disclosure may include a landing pad 120, an etch stop film 130, a lower support pattern 140, an upper support pattern 150, a lower electrode 200, a capacitor dielectric film 250, and an upper electrode 260.
[0027] The landing pad 120 may be disposed on the substrate 100. The landing pad 120 may be connected to the substrate 100. The landing pad 120 may be electrically connected to a conductive area formed on or in the substrate 100.
[0028] The landing pad 120 can be connected to the substrate 100 via the storage contact 115. The landing pad 120 can be disposed on the storage contact 115.
[0029] Interlayer insulating film 110 may be disposed on substrate 100. Storage contact 115 and landing pad 120 may be disposed in interlayer insulating film 110 on substrate 100.
[0030] For example, substrate 100 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In another example, substrate 100 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited thereto. Substrate 100 will be described below as a silicon substrate.
[0031] The interlayer insulating film 110 may include at least one of, for example, silicon oxide, silicon nitride, silicon oxide nitride (SiON), silicon oxycarbon nitride (SiOCN), and combinations thereof.
[0032] Storage contact 115 may include at least one of, for example, a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. Landing pad 120 may include at least one of, for example, a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, and a metal. For example, landing pad 120 may include tungsten (W).
[0033] An etch stop film 130 may be disposed on the interlayer insulating film 110. The etch stop film 130 may at least partially expose the landing pads 120.
[0034] For example, an etch stop film 130 may be disposed on the landing pad 120. The etch stop film 130 may include a lower electrode hole 130h. The lower electrode hole 130h may at least partially expose the landing pad 120.
[0035] The etch stop film 130 may include, for example, one of silicon nitride, silicon carbonate (SiCO), silicon oxide, silicon carbonitride (SiCN), silicon oxide nitride, and combinations thereof. The etch stop film 130 may include silicon carbonitride or silicon nitride.
[0036] The lower electrode 200 can be disposed on the landing pad 120. The lower electrode 200 can be connected to the landing pad 120.
[0037] The lower electrode 200 may extend in the thickness direction of the substrate 100, i.e., in the second direction DR2. The length of the lower electrode 200 extending in the second direction DR2 may be greater than the length of the lower electrode 200 extending in the first direction DR1. Alternatively, the length of the lower electrode 200 extending in the second direction DR2 may be greater than the width of the lower electrode 200 in the first direction DR1. The lower electrode 200 may be, for example, in the shape of a pillar or cylinder.
[0038] Here, the second direction DR2 can be a direction parallel to the thickness direction of the substrate 100. For example, the second direction DR2 can extend along the normal relative to the upper surface of the substrate 100. The first direction DR1 can intersect the second direction DR2 and can be a direction parallel to the top surface of the substrate 100 or the top surface of the interlayer insulating film 110.
[0039] The lower electrode 200 may include an outer surface 200s defining the shape of the lower electrode 200. The outer surface 200s may include a bottom surface 200bs facing the top surface of the landing pad 120, a sidewall 200ss extending in the second direction DR2, and a top surface 200us facing, for example, parallel to the bottom surface 200bs. The sidewall 200ss may connect the bottom surface 200bs and the top surface 200us. For example, as... Figure 1 As shown, the two lower electrodes 200 can be adjacent to each other along the first direction DR1, such that each of the two lower electrodes 200 can be connected to a corresponding landing pad 120. For example, as Figure 1 As further shown, the two lower electrodes 200 can be connected to each other via the lower support pattern 140 and the upper support pattern 150.
[0040] A portion of the lower electrode 200 can be disposed within the lower electrode hole 130h. The lower electrode 200 can pass through the lower electrode hole 130h to connect to the landing pad 120. For example, the lower portion of the lower electrode 200 can fill the lower electrode hole 130h and directly contact the landing pad 120. For example, a portion of the sidewall 200ss of the lower electrode 200 can directly contact the etch stop film 130, for example.
[0041] The lower electrode 200 may include, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), or a conductive metal oxide (e.g., iridium oxide), but this disclosure is not limited thereto. The lower electrode 200 will be described below as including titanium nitride (TiN).
[0042] The lower electrode 200 may include a metal dopant. The interior and / or exterior of the lower electrode 200 may be doped with a metal dopant.
[0043] The metal dopant may include at least one of, for example, tin (Sn), molybdenum (Mo), niobium (Nb), tantalum (Ta), indium (In), nickel (Ni), cobalt (Co), tungsten (W), titanium (Ti), vanadium (V), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and ruthenium (Ru). The metal dopant may be different from the metal included in the lower electrode 200. For example, when the lower electrode 200 comprises titanium nitride, the lower electrode 200 may be doped with any of the aforementioned metal dopants other than titanium. The lower electrode 200 and the metal dopant will be described in more detail below.
[0044] The lower support pattern 140 may be disposed on the etch stop film 130. The lower support pattern 140 may be spaced apart from the etch stop film 130 in the second direction DR2. The lower support pattern 140 may be in direct contact with the lower electrode 200, for example. The lower support pattern 140 may be in direct contact with a portion of the sidewall 200ss of the lower electrode 200, for example. The lower support pattern 140 may include an outer surface 140s extending in the first direction DR1. The outer surface 140s of the lower support pattern 140 may include a top surface 140us and a bottom surface 140bs facing each other, for example, the top surface 140us and the bottom surface 140bs may be parallel to each other and parallel to the bottom surface 200bs and the top surface 200us of the lower electrode 200.
[0045] The upper support pattern 150 may be disposed on the lower support pattern 140, for example, the lower support pattern 140 may be between the substrate 100 and the upper support pattern 150. The upper support pattern 150 may be spaced apart from the lower support pattern 140 in the second direction DR2. The upper support pattern 150 may be in direct contact with the lower electrode 200, for example. The upper support pattern 150 may be in direct contact with a portion of the sidewall 200ss of the lower electrode 200, for example. The upper support pattern 150 may include an outer surface 150s extending in the first direction DR1. The outer surface 150s of the upper support pattern 150 may include a top surface 150us and a bottom surface 150bs facing each other, for example, the top surface 150us and the bottom surface 150bs may be parallel to each other and parallel to the top surface 140us and the bottom surface 140bs of the lower support pattern 140.
[0046] For example, the top surface 150us of the upper support pattern 150 may be on the same plane as the top surface 200us of the lower electrode 200. For instance, the top surface 150us and the top surface 200us may be at the same distance from the top surface of the substrate 100 and may be flush with each other. In another example, the top surface 150us of the upper support pattern 150 may protrude beyond the top surface 200us of the lower electrode 200 in a direction away from the orientation of the substrate 100, for example, protruding above the top surface 200us of the lower electrode 200. The top surface 150us of the upper support pattern 150 will be described below as being on the same plane as the top surface 200us of the lower electrode 200.
[0047] The lower support pattern 140 and the upper support pattern 150 may include at least one of, for example, silicon nitride, silicon carbonate, silicon oxide, silicon carbonitride, silicon oxide nitride, and combinations thereof. For example, the lower support pattern 140 and the upper support pattern 150 may include silicon carbonitride or silicon nitride.
[0048] The thickness t11 of the lower support pattern 140 in the second direction DR2 can be different from the thickness t12 of the upper support pattern 150 in the second direction DR2. For example, as Figure 1 As shown, the thickness t11 of the lower support pattern 140 can be less than the thickness t12 of the upper support pattern 150.
[0049] For example, such as Figure 1 As shown, the semiconductor device according to an embodiment may include both a lower support pattern 140 and an upper support pattern 150. In another example, the semiconductor device according to an embodiment may include only one of the lower support pattern 140 and the upper support pattern 150. In yet another example, the semiconductor device according to some embodiments may include a third support pattern in addition to the lower support pattern 140 and the upper support pattern 150.
[0050] A capacitor dielectric film 250 can be disposed on the lower electrode 200. The capacitor dielectric film 250 can be formed, for example, conformally along the outer surface 200s of the lower electrode 200, the outer surface 150s of the upper support pattern 150, the outer surface 140s of the lower support pattern 140, and the top surface of the etch stop film 130. The capacitor dielectric film 250 can extend along the contours of the lower electrode 200, the upper support pattern 150, the lower support pattern 140, and the etch stop film 130. For example, as... Figure 1 As shown, the capacitor dielectric film 250 may be formed, for example, conformally along the outer surfaces 200s of two adjacent lower electrodes 200, rather than on the portions of the surfaces of the two adjacent lower electrodes 200 that face each other.
[0051] Because the lower support pattern 140 and the upper support pattern 150 are in direct contact with the lower electrode 200, for example, the capacitor dielectric film 250 may not extend between the lower support pattern 140 and the lower electrode 200, or between the upper support pattern 150 and the lower electrode 200. Furthermore, the capacitor dielectric film 250 may not extend between the etch stop film 130 and the lower electrode 200.
[0052] The capacitor dielectric film 250 may be in direct contact with the lower electrode 200, for example. The capacitor dielectric film 250 may be in direct contact with the outer surface 150s of the upper support pattern 150, the outer surface 140s of the lower support pattern 140, and the top surface 130s of the etch stop film 130, for example.
[0053] The capacitor dielectric film 250 may include at least one of the following: silicon oxide, silicon nitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and combinations thereof, but this disclosure is not limited thereto.
[0054] The capacitor dielectric film 250 is shown as a single-layer film, but this disclosure is not limited thereto. For example, the capacitor dielectric film 250 may have a stacked structure in which zirconium oxide, aluminum oxide and zirconium oxide are sequentially stacked.
[0055] In another example, the capacitor dielectric film 250 may have a stacked structure in which a ferroelectric material film and a dielectric material film are stacked. The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may have a thickness sufficient to have ferroelectric properties. The thickness of the ferroelectric material film may vary depending on the type of ferroelectric material used to form the ferroelectric material film.
[0056] For example, ferroelectric material films can include single-metal oxide films. Here, the single-metal oxide can be a binary compound comprising a single metal and oxygen, such as a single metal and oxygen.
[0057] For example, the metal included in the single metal oxide film can be hafnium (Hf), and the single metal oxide film can be a hafnium oxide (HfO) film. Here, the hafnium oxide film can have a chemical formula that conforms to or does not conform to stoichiometry.
[0058] In another example, the metal included in the single metal oxide film can be a lanthanide rare earth metal, and the single metal oxide film can be a lanthanide rare earth metal oxide film. Here, the lanthanide rare earth metal oxide film may or may not have a stoichiometric chemical formula.
[0059] Ferroelectric films can also include dopants internally incorporated into single-metal oxide films. The doping concentration of the dopant can vary depending on the type of dopant, but it can be below 10%.
[0060] For example, when the single metal oxide film is a hafnium oxide film, the dopant inside the single metal oxide film may include at least one of gadolinium (Gd), silicon (Si), aluminum (Al), yttrium (Y), lanthanum (La), scandium (Sc), cerium (Ce), dysprosium (Dy), tantalum, strontium (Sr), and niobium (Nb). In another example, when the single metal oxide film is a lanthanide rare earth metal oxide film, the dopant inside the single metal oxide film may include at least one of silicon, aluminum, hafnium, zirconium (Zr), and niobium.
[0061] Alternatively, the ferroelectric material film may not include the dopants present inside the single metal oxide film.
[0062] When the ferroelectric material film comprises a single metal oxide film, the ferroelectric material film can have a thickness of, for example, greater than 1 nm and less than 10 nm. For example, the ferroelectric material film can comprise a bimetallic oxide, such as a bimetallic oxide film.
[0063] Bimetallic oxides can be ternary compounds composed of two metals and oxygen. The metals included in the bimetallic oxide film can be, for example, hafnium and zirconium. The bimetallic oxide film can be hafnium zirconium oxide (Hf... x Zr (1-x) Hafnium zirconium oxide films (where x is greater than 0.2 and less than 0.8) can have chemical formulas that conform to or do not conform to stoichiometry.
[0064] For example, the bimetallic oxide film may also include a dopant internally present in the bimetallic oxide film. This dopant may include at least one of gadolinium, silicon, aluminum, yttrium, lanthanum, scandium, cerium, dysprosium, tantalum, and strontium. In another example, the ferroelectric film may not include the dopant internally present in the bimetallic oxide film.
[0065] When the ferroelectric material film includes a bimetallic oxide film, the ferroelectric material film can have a thickness of, for example, greater than 1 nm and less than 20 nm.
[0066] Dielectric materials have a positive permittivity, while ferroelectric materials have a negative permittivity. That is, dielectric materials have a positive capacitance, and ferroelectric materials have a negative capacitance.
[0067] Generally, if two or more capacitors with positive capacitance are connected in series, the sum of their capacitances decreases. However, if a capacitor with negative capacitance and a capacitor with positive capacitance are connected in series, the sum of their capacitances increases.
[0068] The upper electrode 260 may be disposed on the capacitor dielectric film 250. The upper electrode 260 may include, for example, a first sub-upper electrode 261 and a second sub-upper electrode 262. The first sub-upper electrode 261 may be formed along the contour of the capacitor dielectric film 250. The second sub-upper electrode 262 may be disposed on the first sub-upper electrode 261.
[0069] The first sub-upper electrode 261 and the second sub-upper electrode 262 may include, for example, doped semiconductor materials, conductive metal nitrides (e.g., titanium nitride, tantalum nitride, or tungsten nitride), metals (e.g., ruthenium, iridium, titanium, niobium, nickel, copper (Cu), molybdenum, or tantalum), or conductive metal oxides (e.g., iridium oxide or molybdenum oxide), but this disclosure is not limited thereto. For example, the upper electrode 260 may include only one of the first sub-upper electrode 261 and the second sub-upper electrode 262.
[0070] Reference Figure 1 and Figure 2 The lower electrode 200 may include an outer portion 210 and an inner portion 220 within the outer portion 210. In this respect, note that... Figure 2 It shows Figure 1 The left lower electrode 200, while its portion (at the bottom) is connected to the etch stop film 130 and its portion (above the etch stop film 130) is connected to the lower support pattern 140 and the upper support pattern 150. For example, as Figure 2 As shown, the outer portion 210 and the inner portion 220 can be integrally formed with each other, for example, to form a seamless electrode. Figure 2 The dashed lines in the diagram are imaginary lines between the outer portion 210 and the inner portion 220, shown only for convenience.
[0071] like Figure 2 As shown, the outer portion 210 may surround the inner portion 220. The outer portion 210 may include the outer surface 200s of the lower electrode 200. The outer portion 210 may be defined as the portion of the lower electrode 200 that includes the outer surface 200s and has a thickness. Therefore, the thickness of the outer portion 210 is not particularly limited, and the ratio of the thickness of the outer portion 210 to the width of the lower electrode 200 in the first direction DR1 may be greater than zero and less than 0.5. For example, the ratio of the total width of portion 210sp_1 along the first direction DR1 to the total width of the bottom portion 210bp along the first direction DR1 may be greater than 0 and less than 0.5.
[0072] The outer portion 210 may include a bottom portion 210bp, a top portion 210up, and a side portion 210sp. The side portion 210sp may be a portion of the outer portion 210 extending from the bottom surface 200bs of the lower electrode 200 to the top surface 200us of the lower electrode 200. For example, the side portion 210sp may include two identical portions along two opposing sidewalls 200ss of the lower electrode 200 and separated from each other by the inner portion 220.
[0073] The side portion 210sp may include the sidewall 200ss of the lower electrode 200. Because the side portion 210sp extends to the bottom surface 200bs of the lower electrode 200, the bottom portion 210bp may include a portion of the bottom surface 200bs of the lower electrode 200. Because the side portion 210sp also extends to the top surface 200us of the lower electrode 200, the top portion 210up may include a portion of the top surface 200us of the lower electrode 200.
[0074] The side portion 210sp may be in direct contact with, for example, the etch stop film 130, the lower support pattern 140, and the upper support pattern 150. The portion of the side portion 210sp that is not in contact with any of the etch stop film 130, the lower support pattern 140, and the upper support pattern 150 may be the first portion 210sp_1.
[0075] The portion of side portion 210sp that contacts the upper support pattern 150 can be portion 2_1, 210sp_21. The portion of side portion 210sp that contacts the lower support pattern 140 can be portion 2_2, 210sp_22. The portion of side portion 210sp that contacts the etch stop film 130 can be portion 2_3, 210sp_23. For example, as... Figure 2 As shown, part 210sp_1 can be between parts 210sp_21 and 210sp_22, and between parts 210sp_22 and 210sp_23. For example, as Figure 2 As further shown, portions 210sp_1 and portions 210sp_21 to 210sp_23 may have the same width along the first direction DR1 and may be continuous with each other.
[0076] like Figure 1 and Figure 2As shown, the capacitor dielectric film 250 may extend along the first portion 210sp_1 of the top portion 210up and the side portion 210sp. The capacitor dielectric film 250 does not extend along the bottom portion 210bp, nor along the second_2 portion 210sp_22 and the second_1 portion 210sp_21 of the side portion 210sp; that is, the capacitor dielectric film 250 does not extend between the outer portion 210 and each of the lower support pattern 140 and the upper support pattern 150.
[0077] The region where the capacitor dielectric film 250 is formed may correspond to the first region of the outer portion 210. The region where the capacitor dielectric film 250 is not formed may correspond to the second region of the outer portion 210. The second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 may include the first region and the second region of the outer portion 210. For example, the second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 may include the first region only where it overlaps with the top portion 210up.
[0078] The portion of the sidewall 200ss of the lower electrode 200 that does not contact any of the etch stop film 130, the lower support pattern 140, and the upper support pattern 150 can be the first portion 200ss_1 of the sidewall 200ss of the lower electrode 200. The portion of the sidewall 200ss of the lower electrode 200 that contacts the upper support pattern 150 can be the second portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The portion of the sidewall 200ss of the lower electrode 200 that contacts the lower support pattern 140 can be the second portion 200ss_22 of the sidewall 200ss of the lower electrode 200. The portion of the sidewall 200ss of the lower electrode 200 that contacts the etch stop film 130 can be the second portion 200ss_23 of the sidewall 200ss of the lower electrode 200.
[0079] The second-1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the upper support pattern 150. The second-2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the lower support pattern 140. The second-3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the etch stop film 130.
[0080] The second_1 portion 210sp_21 of the side portion 210sp includes the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The second_2 portion 210sp_22 of the side portion 210sp includes the second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200. The second_3 portion 210sp_23 of the side portion 210sp includes the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200.
[0081] The capacitor dielectric film 250 may extend along the first portion 200ss_1 of the sidewall 200ss of the lower electrode 200 and the top surface 200us of the lower electrode 200. The capacitor dielectric film 250 does not extend along the bottom surface 200bs of the lower electrode 200 and the second_1 portion 200ss_21, the second_2 portion 200ss_22 and the second_3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200.
[0082] The region where the capacitor dielectric film 250 is formed can correspond to the first region of the outer portion 210 of the lower electrode 200. The region where the capacitor dielectric film 250 is not formed can correspond to the second region of the outer portion 210 of the lower electrode 200.
[0083] Figure 4 The variation in the concentration of the metal dopant Md in the side portion 210sp of the outer portion 210 of the lower electrode 200 is shown. For example, as Figure 4 As shown, the concentration change of metal dopant Md can be basically the same as the concentration change of metal dopant Md in the sidewall 200ss of the lower electrode 200. Figure 4 The concentration of metal dopant Md in the side portion 210sp of the outer portion 210 of the lower electrode 200 is shown to vary from the top surface 200us of the lower electrode 200 to the bottom surface 200bs of the lower electrode 200.
[0084] Reference Figure 4 The concentration of metal dopant Md in the second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 decreases as it moves away from the top surface 200µs of the lower electrode 200. The concentration of metal dopant Md can be zero in the second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210. The second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 includes a first sub-region containing metal dopant Md and a second sub-region not containing metal dopant Md.
[0085] Here, a zero metal dopant concentration does not necessarily mean that the metal dopant Md is absent, but can mean that the second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 is doped with the metal dopant Md to an amount less than the predetermined detection limit.
[0086] The concentration of the metal dopant Md can also be zero in the second-2nd portion 210sp_22 and the second-3rd portion 210sp_23 of the side portion 210sp of the outer portion 210. The concentration of the metal dopant Md can also be C0 in the first portion 210sp_1 of the side portion 210sp of the outer portion 210, that is, C0 in the portion of the side portion 210sp facing, for example, the dielectric film 250 of the contact capacitor.
[0087] In other words, the concentration of metal dopant Md in the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 decreases as it moves away from the top surface 200us of the lower electrode 200. The concentration of dopant Md can be zero in the second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200. The second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 can include portions containing metal dopant Md and portions not containing metal dopant Md.
[0088] The concentration of metal dopant Md can also be zero in the second-2 part 200ss_22 and the second-3 part 200ss_23 of the sidewall 200ss of the lower electrode 200. The concentration of metal dopant Md can be C0 in the first part 200ss_1 of the sidewall 200ss of the lower electrode 200.
[0089] The concentration of metal dopant Md in the top portion 210up of the outer portion 210 can be substantially the same as the concentration of metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210. Therefore, the concentration of metal dopant Md can be C0 in the top portion 210up of the outer portion 210 of the lower electrode 200 or at the top surface 200us of the lower electrode 200.
[0090] At least a portion of the outer portion 210 of the lower electrode 200 may include a metal dopant Md. The outer portion 210 of the lower electrode 200 may include regions doped with metal dopant Md and regions not doped with metal dopant Md.
[0091] The capacitor dielectric film 250 may extend along the first portion 210sp_1 of the side portion 210sp of the outer portion 210. However, the capacitor dielectric film 250 does not extend along the second portion 210sp_22 and the second portion 210sp_23 of the side portion 210sp of the outer portion 210.
[0092] The concentration of metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210 can be different from the concentration of metal dopant Md in the second_1 portion 210sp_21, the second_2 portion 210sp_22, and the second_3 portion 210sp_23 of the side portion 210sp of the outer portion 210. For example, the concentration of metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210 can be higher than the concentration of metal dopant Md in the second_1 portion 210sp_21, the second_2 portion 210sp_22, and the second_3 portion 210sp_23 of the side portion 210sp of the outer portion 210.
[0093] The concentration of metal dopant Md compared between different regions can be the average concentration of metal dopant Md. That is, there may be a portion of the second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 where the concentration of metal dopant Md is particularly high, but the average concentration of metal dopant Md may be lower in the second_1 portion 210sp_21 of the side portion 210sp of the outer portion 210 than in the first portion 210sp_1 of the side portion 210sp of the outer portion 210.
[0094] The lower electrode 200 may include a metal dopant Md, and at least some of the outer surfaces 200s of the lower electrode 200 may be doped with the metal dopant Md. The outer surfaces 200s of the lower electrode 200 may include regions doped with the metal dopant Md and regions not doped with the metal dopant Md.
[0095] The concentration of metal dopant Md can be higher in the first part 200ss_1 of the sidewall 200ss of the lower electrode 200 than in the second part 200ss_21, the second part 200ss_22 and the second part 200ss_23 of the sidewall 200ss of the lower electrode 200.
[0096] In other words, the concentration of metal dopant Md, i.e., C0, in the portion of the outer surface 200s of the lower electrode 200 between the lower electrode 200 and the capacitor dielectric film 250 can be higher than the concentration of metal dopant Md in the portions of the outer surface 200s of the lower electrode 200 between the lower electrode 200 and the upper support pattern 150, between the lower electrode 200 and the lower support pattern 140, and between the lower electrode 200 and the etch stop film 130.
[0097] Reference Figure 5The upper support pattern 150 may not contain metal dopant Md. The interior of the upper support pattern 150 may not contain metal dopant Md. Similarly, the lower support pattern 140 and the etch stop film 130 may not contain metal dopant Md.
[0098] Figure 6 The variation in the concentration of metal dopant Md in the first portion 210sp_1 of the side portion 210sp of the outer portion 210, where the capacitor dielectric film 250 is formed, is shown. The concentration of metal dopant Md in the outer portion 210 of the lower electrode 200 decreases away from the outer surface 200s of the lower electrode 200, for example, decreasing in the direction toward the orientation of the inner portion 220.
[0099] Figure 6 The outer portion 210 of the lower electrode 200 is shown to include metal dopant Md, and the inner portion 220 of the lower electrode 200 does not include metal dopant Md, but this disclosure is not limited thereto.
[0100] Figure 7 Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 8 Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 7 and Figure 8 The semiconductor devices discussed below will primarily focus on those related to... Figures 1 to 6 The differences in semiconductor devices are used to describe this.
[0101] In detail, Figure 7 This illustrates the concentration of metal dopant in semiconductor devices according to some embodiments of the present disclosure along... Figure 2 The curve showing the change of line A. Figure 8 This illustrates the concentration of metal dopant in semiconductor devices according to some embodiments of the present disclosure along... Figure 2 The curve showing the change of line A.
[0102] Reference Figure 7 The second-2 portion 210sp_22 and the second-3 portion 210sp_23 of the side portion 210sp of the outer portion 210 of the lower electrode 200 may include a metal dopant Md. The second-2 portion 210sp_22 and the second-3 portion 210sp_23 of the side portion 210sp of the outer portion 210 include regions containing the metal dopant Md and regions not containing the metal dopant Md. The second-2 portion 200ss_22 and the second-3 portion 200ss_23 of the sidewall 200ss of the lower electrode 200 may include a metal dopant Md.
[0103] Reference Figure 8The second 210sp_22 of the side portion 210sp of the outer portion 210 of the lower electrode 200 may generally include the metal dopant Md. The second 200ss_22 of the sidewall 200ss of the lower electrode 200 may generally include the metal dopant Md. The second 200ss_22 of the sidewall 200ss of the lower electrode 200 may generally be doped with the metal dopant Md.
[0104] Figure 9 Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 9 The semiconductor devices discussed below will primarily focus on those related to... Figures 1 to 6 The differences in semiconductor devices are used to describe this.
[0105] Specifically, Figure 9 This illustrates the concentration of metal dopant in semiconductor devices according to some embodiments of the present disclosure along... Figure 2 The curve showing the change of line B.
[0106] Reference Figure 9 The upper support pattern 150 may include a metal dopant Md. The outer surface 150s of the upper support pattern 150 may be doped with the metal dopant Md.
[0107] The concentration of metal dopant Md at the outer surface 150s of the upper support pattern 150 can be lower than the concentration of metal dopant Md (i.e. CO) in the first part 200ss_1 of the sidewall 200ss of the lower electrode 200. The first part 200ss_1 of the sidewall 200ss of the lower electrode 200 is the boundary between the lower electrode 200 and the capacitor dielectric film 250.
[0108] Although not specifically shown, the lower support pattern 140 may include a metal dopant Md, and the outer surface 140s of the lower support pattern 140 may be doped with a metal dopant Md. The etch stop film 130 may include a metal dopant Md, and the top surface 130s of the etch stop film 130 may be doped with a metal dopant Md.
[0109] The concentration of metal dopant Md at the outer surface 140s of the lower support pattern 140 and at the top surface 130s of the etch stop film 130 can be lower than the concentration of metal dopant Md, i.e., C0, in the first part 200ss_1 of the sidewall 200ss of the lower electrode 200.
[0110] The outer surface 150s of the upper support pattern 150, the outer surface 140s of the lower support pattern 140, and / or the top surface 130s of the etch stop film 130 may include a metal dopant Md.
[0111] Figure 10Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 11 Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 10 and Figure 11 The semiconductor devices discussed below will primarily focus on those related to... Figures 1 to 6 The differences in semiconductor devices are used to describe this.
[0112] In detail, Figure 10 and Figure 11 Semiconductor devices according to some embodiments of this disclosure and Figure 1 An enlarged sectional view of the portion corresponding to part P, which is surrounded by dashed lines.
[0113] Reference Figure 10 The semiconductor device according to some embodiments of this disclosure may further include an insertion film 255 disposed between the lower electrode 200 and the upper electrode 260. The insertion film 255 may be disposed inside the capacitor dielectric film 250.
[0114] The insert film 255 can promote the crystallization of the capacitor dielectric film 250. The capacitor dielectric film 250 can be divided into a first portion 250a and a second portion 250b by the insert film 255. The insert film 255 can contact the first portion 250a and the second portion 250b of the capacitor dielectric film 250.
[0115] The intercalation film 255 may include at least one of, for example, titanium (Ti), niobium (Nb), molybdenum (Mo), tin nitride, and tin oxide. Alternatively, the intercalation film 255 may include at least one of ruthenium and ruthenium oxide.
[0116] Reference Figure 11 The semiconductor device according to some embodiments of this disclosure may further include a passivation film 265 disposed between the capacitor dielectric film 250 and the upper electrode 260. The passivation film 265 can prevent oxygen atoms included in the capacitor dielectric film 250 from moving to the upper electrode 260.
[0117] The passivation film 265 may include a metal oxide. The passivation film 265 may include at least one of, for example, titanium oxide, tantalum oxide, molybdenum oxide, tin oxide, and niobium oxide.
[0118] Figure 12 Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 13 This indicates the concentration of the metal dopant at... Figure 12 A graph showing the changes near the outer surface of the lower electrode of a semiconductor device. Figure 12 The semiconductor devices discussed below will primarily focus on those related to... Figures 1 to 6 The differences in semiconductor devices are used to describe this.
[0119] In detail, Figure 13 It is shown in Figure 12 The concentration of metal dopants in semiconductor devices along Figure 2 The curve showing the change of line A.
[0120] Reference Figure 2 , Figure 12 and Figure 13 The second_1 portion 210sp_21 and the second_2 portion 210sp_22 of the side portion 210sp of the outer portion 210 of the lower electrode 200 may generally include the metal dopant Md. The second_1 portion 200ss_21 and the second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200 may generally include the metal dopant Md. The second_1 portion 200ss_21 of the sidewall 200ss of the lower electrode 200 may generally be doped with the metal dopant Md. The second_2 portion 200ss_22 of the sidewall 200ss of the lower electrode 200 may generally be doped with the metal dopant Md.
[0121] Figure 14 Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 14 The semiconductor devices discussed below will primarily focus on those related to... Figures 1 to 6 The differences in semiconductor devices are used to describe this.
[0122] Reference Figure 14 The lower electrode 200 may include a bottom portion 202 extending along the top surface of the landing pad 120 and a sidewall portion 201 protruding from the bottom portion 202. The sidewall portion 201 of the lower electrode 200 may extend in a second direction DR2.
[0123] The outer surface 200s of the lower electrode 200 may include a first sidewall 200ss1 and a second sidewall 200ss2. The outer surface 200s of the lower electrode 200 may also include a top surface 200us connecting the first sidewall 200ss1 and the second sidewall 200ss2. The outer surface 200s of the lower electrode 200 may also include a first bottom surface 200bs_1 connected to the first sidewall 200ss1 and a second bottom surface 200bs_2 connected to the second sidewall 200ss2. The lower electrode 200 may be in the shape of a container.
[0124] The etching stop film 130, the lower support pattern 140 and the upper support pattern 150 can contact the first sidewall 200ss1 of the lower electrode 200.
[0125] The capacitor dielectric film 250 may extend along the first sidewall 200ss1 and the second sidewall 200s2 of the lower electrode 200. The bottom portion 202 of the lower electrode 200 may include an outer portion 210 and an inner portion 220. The sidewall portion 201 of the lower electrode 200 may also include an outer portion 210 and an inner portion 220.
[0126] For example, the ratio of the thickness of the outer portion 210 of the lower electrode 200 to the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be greater than 0 and less than 0.5. The width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be the distance between the first sidewall 200ss1 and the second sidewall 200ss2 of the lower electrode 200 that face each other.
[0127] Figure 15 Semiconductor devices according to some embodiments of the present disclosure are shown. Figure 15 The semiconductor devices discussed below will primarily focus on those related to... Figures 1 to 6 The differences in semiconductor devices are used to describe this.
[0128] Reference Figure 15 The semiconductor device according to some embodiments of this disclosure may further include an insulating pattern 160 that contacts the lower electrode 200 and extends in the second direction DR2. The insulating pattern 160 may be disposed on the etch stop film 130. The insulating pattern 160 may include sidewalls 160s and a top surface 160u.
[0129] The landing pad 120 can be disposed in the etch stop film 130. The lower electrode 200 can be disposed on the etch stop film 130.
[0130] The lower electrode 200 may include a bottom portion 202 extending along the top surface of the landing pad 120 and a sidewall portion 201 protruding from the bottom portion 202. The sidewall portion 201 of the lower electrode 200 may extend in a second direction DR2. The sidewall portion 201 of the lower electrode 200 may extend along the sidewall 160s of the insulating pattern 160.
[0131] The outer surface 200s of the lower electrode 200 may include a first sidewall 200ss1 and a second sidewall 200ss2. The second sidewall 200ss2 may face the sidewall 160s of the insulating pattern 160. The outer surface 200s of the lower electrode 200 may also include a top surface 200us connecting the first sidewall 200ss1 and the second sidewall 200ss2. The outer surface 200s of the lower electrode 200 may also include a bottom surface 200bs, which is connected to the second sidewall 200ss2 and faces the top surface 130s of the etch stop film 130 and the top surface of the landing pad 120.
[0132] The capacitor dielectric film 250 may extend along the first sidewall 200ss1 of the lower electrode 200, but not along the second sidewall 200ss2 of the lower electrode 200. The capacitor dielectric film 250 is not disposed between the second sidewall 200ss2 of the lower electrode 200 and the sidewall 160s of the insulating pattern 160. The capacitor dielectric film 250 may extend along the top surface 160u of the insulating pattern 160.
[0133] For example, the ratio of the thickness of the outer portion 210 of the lower electrode 200 to the width of the sidewall portion 201 of the lower electrode 200 in the first direction DR1 can be greater than zero and less than 0.5.
[0134] The concentration of the metal dopant can be higher at the first sidewall 200ss1 of the lower electrode 200 than at the second sidewall 200ss2 of the lower electrode 200. The second sidewall 200ss2 of the lower electrode 200 may include regions doped with metal dopant and regions not doped with metal dopant.
[0135] Figures 16 to 21 This is a cross-sectional view showing stages in a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.
[0136] Reference Figure 16 Storage contacts 115 and landing pads 120 can be formed in the interlayer insulating film 110 on the substrate 100. Etch stop film 130, lower molding film 111, lower support film 140p, upper molding film 112 and upper support film 150p can be formed sequentially on the interlayer insulating film 110.
[0137] Reference Figure 17 The lower electrode 200 can be formed on the landing pad 120 to penetrate the etch stop film 130, the lower molding film 111, the lower support film 140p, the upper molding film 112, and the upper support film 150p. A portion of the lower electrode 200 can be disposed in the lower electrode hole 130h included in the etch stop film 130.
[0138] Reference Figure 18 The upper support pattern 150 and the lower support pattern 140 can be formed to connect the lower electrodes 200 that are adjacent to each other along the first direction DR1. The upper support pattern 150 and the lower support pattern 140 can be in direct contact with portions of the sidewalls of the lower electrode 200, for example.
[0139] The upper support pattern 150 can be formed by removing a portion of the upper support film 150p. For example, the portion of the upper support film 150p on the outer sidewall of the lower electrode 200 can be removed to retain only the upper support pattern 150 on the sidewalls facing each other that connect adjacent lower electrodes 200. The upper molded film 112 can be formed by, for example, completely removing the area in which the upper support pattern 150 is not formed.
[0140] Subsequently, the lower support pattern 140 can be formed by removing a portion of the lower support film 140p. For example, the portion of the lower support film 140p on the outer sidewall of the lower electrode 200 can be removed to retain only the lower support pattern 140 of the sidewalls facing each other connecting adjacent lower electrodes 200. The lower molded film 111 can be formed by, for example, completely removing the area in which the lower support pattern 140 is not formed.
[0141] As a result, gaps S, such as empty spaces, can be formed between the upper support pattern 150 and the lower support pattern 140, and between the lower support pattern 140 and the etch stop film 130.
[0142] Reference Figure 19 The interface layer 225 may be formed along the contours of the lower electrode 200, the upper support pattern 150, and the lower support pattern 140, and along the top surface of the etch stop film 130. The interface layer 225 may include a metal dopant. The interface layer 225 may include at least one of, for example, tin, molybdenum, niobium, tantalum, indium, nickel, cobalt, tungsten, titanium, vanadium, phosphorus, arsenic, antimony, bismuth, and ruthenium.
[0143] Reference Figure 20 The metal dopant included in the interface layer 225 can be diffused into the lower electrode 200 through a heat treatment process 230. As a result, the lower electrode 200 can be doped with a metal dopant. For example, the concentration of the metal dopant can be determined according to the portion of the lower electrode 200 in direct contact with the interface layer 225 containing the metal dopant. Figure 4 The curve in the graph varies within the lower electrode 200. For example, the concentration of the metal dopant can be determined according to the diffusion distance of the metal dopant within the lower electrode 200. Figure 6 The curves in the figure vary within the lower electrode 200. For example, the concentration of the metal dopant within the lower electrode 200 decreases as the distance from the outer wall 200ss increases.
[0144] Reference Figure 20 and Figure 21 After heat treatment process 230, the interface layer 225 can be removed. Thereafter, the capacitor dielectric film 250 can be formed along the contours of the lower electrode 200, the upper support pattern 150 and the lower support pattern 140 and along the top surface of the etch stop film 130.
[0145] Refer again Figure 1 The upper electrode 260 can be formed on the capacitor dielectric film 250. For example, as... Figure 1 As shown, a single upper electrode 260 can continuously cover two adjacent lower electrodes 200.
[0146] In summary, increasing capacitance increases the amount of charge that can be stored in the capacitor, thereby improving the refresh characteristics of semiconductor devices. Improved refresh characteristics in semiconductor devices can increase yield. To increase capacitance, a dielectric film with a high dielectric constant is used in the capacitor, or the contact area between the lower electrode and the dielectric film is increased.
[0147] Embodiments of this disclosure provide a semiconductor device having a designed interface between a lower electrode and a capacitor dielectric film to improve the performance and reliability of the capacitor. Embodiments of this disclosure also provide a method for manufacturing a semiconductor device including the aforementioned capacitor.
[0148] Example embodiments have been disclosed herein, and although specific terminology has been used, they will be used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some cases, it will be apparent to those skilled in the art at the time of filing of this application that features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.
[0149] Korean Patent Application No. 10-2019-0071903, entitled "Semiconductor Device and Method of Manufacturing Semiconductor Device", filed with the Korean Intellectual Property Office on June 18, 2019, is incorporated herein by reference in its entirety.
Claims
1. A semiconductor device, comprising: Substrate; A first insulating layer on the substrate; Contact structure in the first insulating layer; A second insulating layer on top of the first insulating layer; A lower electrode on the second insulating layer, the lower electrode passing through the second insulating layer and contacting the contact structure, and the lower electrode having a side portion including a metal dopant; A first support pattern above the substrate; Dielectric layer on the lower electrode; and The upper electrode on the dielectric layer, The side portion of the lower electrode includes a first side portion, a second side portion, and a third side portion between the first side portion and the second side portion. The second insulating layer contacts the first side portion of the lower electrode. The first support pattern contacts the second side portion of the lower electrode. The dielectric layer contacts the third side portion of the lower electrode. The metal dopant includes a material different from that of the lower electrode, and The concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in at least one of the first side portion and the second side portion of the lower electrode.
2. The semiconductor device according to claim 1, wherein: Each of the lower electrode and the upper electrode comprises a titanium nitride. The metal dopants include niobium, and The dielectric layer comprises hafnium oxide, aluminum oxide, and zirconium oxide.
3. The semiconductor device of claim 1, wherein the dielectric layer is spaced apart from the first side portion and the second side portion of the lower electrode.
4. The semiconductor device of claim 1, further comprising a second support pattern below the first support pattern, the second support pattern contacting a fourth side portion of the side portion of the lower electrode, the third side portion being between the second side portion and the fourth side portion and between the fourth side portion and the first side portion.
5. The semiconductor device according to claim 4, wherein, The concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in the fourth side portion of the lower electrode.
6. The semiconductor device according to claim 4, wherein, The dielectric layer is spaced apart from the fourth side portion of the lower electrode.
7. The semiconductor device according to claim 1, wherein, The lower electrode is a cylindrical shape with an internal filling.
8. The semiconductor device according to claim 1, wherein, The lower electrode is cylindrical in shape with an open upper end.
9. The semiconductor device of claim 4, wherein the thickness of the first support pattern is greater than the thickness of the second support pattern.
10. The semiconductor device of claim 1, wherein the lower electrode comprises at least one of a doped semiconductor material, titanium nitride, tantalum nitride, tungsten nitride, ruthenium, iridium, titanium, tantalum, or iridium oxide.
11. The semiconductor device of claim 1, wherein the metal dopant comprises at least one selected from tin, molybdenum, niobium, tantalum, indium, nickel, cobalt, tungsten, titanium, vanadium, phosphorus, arsenic, antimony, bismuth, or ruthenium.
12. The semiconductor device of claim 1, wherein the upper electrode comprises at least one selected from doped semiconductor material, titanium nitride, tantalum nitride, tungsten nitride, ruthenium, iridium, titanium, niobium, nickel, copper, molybdenum, tantalum, iridium oxide, or molybdenum oxide.
13. The semiconductor device according to claim 1, wherein the dielectric layer comprises at least one selected from silicon oxide, silicon nitride, silicon nitride, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.
14. A semiconductor device, comprising: Substrate; A first insulating layer on the substrate; Contact structure in the first insulating layer; A second insulating layer on top of the first insulating layer; A lower electrode on the second insulating layer, the lower electrode passing through the second insulating layer and contacting the contact structure, and the lower electrode having a side portion including a metal dopant; A first support pattern above the substrate; A second support pattern above the first support pattern; Dielectric layer on the lower electrode; and The upper electrode on the dielectric layer, The side portion of the lower electrode includes a first side portion, a second side portion, and a third side portion between the first side portion and the second side portion. The first support pattern contacts the first side portion of the lower electrode. The second support pattern contacts the second side portion of the lower electrode. The dielectric layer contacts the third side portion of the lower electrode. The lower electrode comprises titanium nitride. The metal dopant mentioned above includes niobium, and The concentration of the metal dopant in the third side portion of the lower electrode is different from the concentration of the metal dopant in at least one of the first side portion and the second side portion of the lower electrode.
15. The semiconductor device of claim 14, wherein the concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in at least one of the first side portion and the second side portion of the lower electrode.
16. The semiconductor device of claim 14, wherein the side portion of the lower electrode includes a fourth side portion below the first side portion of the lower electrode, and the second insulating layer contacts the fourth side portion of the lower electrode.
17. The semiconductor device of claim 16, wherein the concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in the fourth side portion of the lower electrode.
18. A semiconductor device, comprising: Substrate; A first insulating layer on the substrate; Contact structure in the first insulating layer; A second insulating layer on top of the first insulating layer; A lower electrode on the second insulating layer, the lower electrode passing through the second insulating layer and contacting the contact structure, and the lower electrode having a side portion including a metal dopant; A first support pattern above the substrate; A second support pattern above the first support pattern; Dielectric layer on the lower electrode; and The upper electrode on the dielectric layer, The side portion of the lower electrode includes a first side portion, a second side portion, a third side portion between the first side portion and the second side portion, and a fourth side portion below the first side portion. The first support pattern contacts the first side portion of the lower electrode. The second support pattern contacts the second side portion of the lower electrode. The dielectric layer contacts the third side portion of the lower electrode. The second insulating layer contacts the fourth side portion of the lower electrode. The metal dopant includes a material different from that of the lower electrode, and The concentration of the metal dopant in the third side portion of the lower electrode is higher than the concentration of the metal dopant in at least one of the first side portion, the second side portion, and the fourth side portion of the lower electrode.
19. The semiconductor device according to claim 18, wherein: Each of the lower electrode and the upper electrode comprises a titanium nitride. The metal dopants include niobium, and The dielectric layer comprises hafnium oxide, aluminum oxide, and zirconium oxide.
Citation Information
Patent Citations
Bag for seeding planting
KR1020190071903A
Deep trench varactors
CN102257622A
Semiconductor memory device with increased capacitance and reduced preformance fluctuation
US20030155601A1