Memory chip and method of manufacturing the same

Abstract

A memory chip and a method of manufacturing the same are provided. The memory chip includes: a memory region including a cell plug in which data is stored; and a guard ring surrounding the memory region. The guard ring includes sub-layers of the same material arranged in the same order as the layer forming the cell plug.

Description

Technical Field

[0001] Various embodiments of the present disclosure generally relate to a memory chip and a method of manufacturing the memory chip, and more particularly, to a memory chip including a guard-ring and a method of manufacturing the memory chip including the guard-ring. Background Art

[0002] Multiple memory chips can be manufactured on a wafer simultaneously.

[0003] When the manufacturing of the memory chips is completed, a dicing process of cutting the wafer along a scribe lane between the memory chips can be performed. The memory chips separated from each other by the dicing process can be used to manufacture various electronic products through different packaging processes.

[0004] Each memory chip may include a memory region for storing data and a guard-ring for protecting the memory region. The memory region may include memory blocks and peripheral circuits. The devices in the memory region are manufactured by a microfabrication process. Therefore, during the manufacturing process, the devices in the memory region may be vulnerable to physical shocks or chemical penetrations from outside the memory chip. The guard-ring may be configured to protect the memory region from external physical shocks or chemical penetrations.

[0005] As the integration density of the memory chip increases, the size of the guard-ring decreases, which may reduce the function of the guard-ring. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a memory chip may include: a memory region including cell plugs storing data; and a guard-ring surrounding the memory region, wherein the guard-ring includes sub-layers having the same material arranged in the same order as the layer forming the cell plugs.

[0007] According to an embodiment of the present disclosure, a memory chip may include: cell plugs and a guard-ring. The cell plugs may include a first layer penetrating a stacked structure in the memory region, a second layer surrounded by the first layer, a third layer surrounded by the second layer, a fourth layer surrounded by the third layer, and a fifth layer surrounded by the fourth layer. The guard-ring may be located around the memory region and may include a first sub-layer corresponding to the first layer, a second sub-layer surrounded by the first sub-layer and corresponding to the second layer, a third sub-layer surrounded by the second sub-layer and corresponding to the third layer, a fourth sub-layer surrounded by the third sub-layer and corresponding to the fourth layer, and a fifth sub-layer surrounded by the fourth sub-layer and corresponding to the fifth layer.

[0008] According to an embodiment of the present disclosure, a method of manufacturing a memory chip may include: forming a stacked structure defining a memory region and a guard region surrounding the memory region over a lower structure; forming a first opening in the memory region of the stacked structure; forming a second opening in the guard region of the stacked structure; increasing a width of the second opening to change the second opening into a guard opening; and simultaneously forming different layers along surfaces of the first opening and the guard opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a view showing a wafer on which a memory chip is manufactured;

[0010] Figure 2 is a view showing a memory chip according to an embodiment of the present disclosure;

[0011] Figure 3 is a view showing a memory region of the memory chip;

[0012] Figure 4 is a view showing a memory cell array;

[0013] Figure 5 is a view showing a structure of a cell plug included in a memory block;

[0014] Figure 6 is a view showing a structure of a guard ring according to an embodiment of the present disclosure;

[0015] Figures 7A to 7K is a cross-sectional view showing a method of manufacturing a memory chip;

[0016] Figures 8A to 8D is a plan view showing a method of manufacturing a memory chip;

[0017] Figure 9 is a plan view showing a part of the guard ring;

[0018] Figure 10 is a view showing an effect of the guard ring according to the present disclosure; and

[0019] Figure 11 is a view showing a structure of a guard ring according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] The specific structures and functional descriptions disclosed herein are illustrative for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure should not be construed as limited to the specific embodiments set forth herein and may be implemented in various forms.

[0021] In the following, it should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. The above terms are only used to distinguish one component from another and do not imply the number or order of components.

[0022] Some embodiments of the present disclosure relate to a memory chip capable of improving the protection function of a guard ring and a method of manufacturing the memory chip.

[0023] Figure 1 is a view showing a wafer on which a plurality of memory chips MC are manufactured.

[0024] Referring to Figure 1 , a plurality of memory chips MC may be formed on a wafer WF. The wafer WF may be a substrate on which a plurality of memory chips MC can be formed. The wafer WF is shown as a circular substrate formed by cutting a single crystal ingot obtained by growing silicon (Si) or gallium arsenide (GaAs) into a small thickness.

[0025] After the manufacturing process of the plurality of memory chips MC on the wafer WF is completed, a dicing process of cutting the wafer WF along the dicing street SCL may be performed. The plurality of memory chips MC may be separated from each other by the dicing process.

[0026] The plurality of memory chips MC may be manufactured as various types of memory devices, and the memory chips MC manufactured on the same wafer WF may be manufactured as the same type of memory device. For example, the memory chips MC may be classified as volatile memory devices or non-volatile memory devices. Volatile memory devices may lose stored data when not powered. Non-volatile memory devices can retain stored data even when not powered. Volatile memory devices may be random access memory (RAM) devices, and the RAM devices may be classified as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices. Examples of non-volatile memory devices may include NAND flash memory devices, NOR flash memory devices, resistive random access memory (ReRAM) devices, phase change random access memory (PRAM) devices, magnetoresistive random access memory (MRAM) devices, ferroelectric random access memory (FRAM) devices, or spin transfer torque random access memory (STT-RAM) devices. However, the present disclosure should not be limited to the types of memory devices described above.

[0027] Figure 2 is a view showing a memory chip according to an embodiment of the present disclosure.

[0028] Referring to Figure 2 showsFigure 1 One of a plurality of memory chips MC. The memory chip MC may include a memory region MR and a guard ring GR surrounding the memory region MR.

[0029] Devices configured to store, output, or erase data may be included in the memory region MR. For example, memory cells and peripheral circuits may be included in the memory region MR. The memory cells may be configured to store data, and the peripheral circuits may be configured to perform programming operations, read operations, and erase operations. The memory cells may be formed in a cell plug CP. The cell plug CP may extend in a vertical direction with respect to the substrate. For example, assuming the substrate defines an XY plane, and the cell plug CP may extend in a Z direction perpendicular to the XY plane. The cell plug CP may include a core pillar CR, a channel layer CH, a tunnel isolation layer TX, a charge trapping layer CTL, and a blocking layer BX. The core pillar CR may have a cylindrical shape or a rectangular pillar shape, and may include an insulating material or a conductive material. Insulating or conductive means electrically insulating or electrically conductive. The channel layer CH may surround the core pillar CR and may include polysilicon. The tunnel isolation layer TX may surround the channel layer CH and may include an oxide layer. The charge trapping layer CTL may surround the tunnel isolation layer TX, and may include a nitride layer. The blocking layer BX may surround the charge trapping layer CTL and may include an oxide layer.

[0030] The guard ring GR may include a plurality of sub-layers surrounding the memory region MR. Referring to the enlarged view of region A1 of the guard ring GR, the guard ring GR may include a first sub-layer S1 to a fifth sub-layer S5 forming a symmetric structure with respect to a central axis Ax. For example, the guard ring GR may include a first sub-layer S1 facing each other with respect to the central axis Ax, a second sub-layer S2 facing each other with respect to the central axis Ax and respectively contacting the first sub-layer S1, a third sub-layer S3 facing each other with respect to the central axis Ax and respectively contacting the second sub-layer S2, a fourth sub-layer S4 facing each other with respect to the central axis Ax and respectively contacting the third sub-layer S3, and a fifth sub-layer S5 extending along the central axis Ax and located between the fourth sub-layers S4.

[0031] The guard ring GR may include a layer forming the cell plug CP. The first sub-layer S1 of the guard ring GR may be the same as the blocking layer BX of the cell plug CP, the second sub-layer S2 of the guard ring GR may be the same as the charge trapping layer CTL of the cell plug CP, the third sub-layer S3 of the guard ring GR may be the same as the tunnel isolation layer TX of the cell plug CP, the fourth sub-layer S4 of the guard ring GR may be the same as the channel layer CH of the cell plug CP, and the fifth sub-layer S5 of the guard ring GR may be the same as the core pillar CR of the cell plug CP.

[0032] The cell plug CP of the guard ring GR and the memory region MR can be formed simultaneously. For example, the first sub-layer S1 of the guard ring GR can be formed simultaneously with the barrier layer BX of the cell plug CP, the second sub-layer S2 of the guard ring GR can be formed simultaneously with the charge trapping layer CTL of the cell plug CP, the third sub-layer S3 of the guard ring GR can be formed simultaneously with the tunnel isolation layer TX of the cell plug CP, the fourth sub-layer S4 of the guard ring GR can be formed simultaneously with the channel layer CH of the cell plug CP, and the fifth sub-layer S5 of the guard ring GR can be formed simultaneously with the core column CR of the cell plug CP. The materials of the first sub-layer S1 to the fifth sub-layer S5 included in the guard ring GR can be changed according to the materials of the barrier layer BX, the charge trapping layer CTL, the tunnel isolation layer TX, the channel layer CH, and the core column CR included in the cell plug CP.

[0033] Therefore, in the embodiments to be described below, a guard ring GR including five sub-layers (for example, the first sub-layer S1 to the fifth sub-layer S5) is described. However, the number and materials of the sub-layers forming the guard ring GR can be changed according to the cell plug CP.

[0034] When the guard ring GR includes the first sub-layer S1 to the fifth sub-layer S5 in contact with each other, an interface IT can exist between each pair of adjacent sub-layers among the first sub-layer S1 to the fifth sub-layer S5 that include different materials from each other. Therefore, the first sub-layer S1 to the fifth sub-layer S5 and the different interfaces can prevent or mitigate the inflow of impurities.

[0035] Figure 3 is a schematic diagram showing the memory region MR of the memory chip MC.

[0036] Referring to Figure 3 , the memory region MR can include a memory cell array 110 and a peripheral circuit 180. The memory cell array 110 can include a first memory block BLK1 to a j-th memory block BLKj. Each of the first memory block BLK1 to the j-th memory block BLKj can include memory cells capable of storing data. The drain select line DSL, the word line WL, the source select line SSL, and the source line SL can be connected to each of the first memory block BLK1 to the j-th memory block BLKj, and the bit line BL can be commonly connected to the first memory block BLK1 to the j-th memory block BLKj.

[0037] The first storage block BLK1 to the j-th storage block BLKj may be formed in a three-dimensional structure. The storage block having a three-dimensional structure may include cell plugs extending in a vertical direction with respect to a substrate. Each of the cell plugs may include a plurality of memory cells and select transistors. The memory cells may store one-bit data or two or more bits of data according to a programming method. For example, a method of storing one-bit data in one memory cell is referred to as a single-level cell (SLC) method, and a method of storing two-bit data in one memory cell is referred to as a multi-level cell (MLC) method. A method of storing three-bit data in one memory cell is referred to as a triple-level cell (TLC) method, and a method of storing four-bit data in one memory cell is referred to as a quad-level cell (QLC) method. In addition, five or more bits of data may be stored in one memory cell.

[0038] The peripheral circuit 180 may be configured to perform a programming operation for storing data in the memory cell array 110, a read operation for outputting the data stored in the memory cell array 110, and an erase operation for erasing the data stored in the memory cell array 110. For example, the peripheral circuit 180 may include a voltage generator 120, a row decoder 130, a page buffer bank 140, a column decoder 150, an input / output circuit 160, and a control circuit 170.

[0039] The voltage generator 120 may generate various operation voltages Vop for a programming operation, a read operation, or an erase operation in response to an operation code OPCD. For example, the voltage generator 120 may be configured to generate a programming voltage, a turn-on voltage, a turn-off voltage, a negative voltage, a precharge voltage, a verify voltage, a read voltage, a pass voltage, or an erase voltage in response to the operation code OPCD. The operation voltage Vop generated by the voltage generator 120 may be applied to a drain select line DSL, a word line WL, a source select line SSL, and a source line SL of a selected storage block through the row decoder 130.

[0040] A programming voltage can be applied to a selected word line among word lines WL during a programming operation, and can be used to increase a threshold voltage of a memory cell coupled to the selected word line. A conduction voltage can be applied to a drain select line DSL or a source select line SSL, and can be used to conduct a drain select transistor or a source select transistor. A cutoff voltage can be applied to the drain select line DSL or the source select line SSL, and can be used to cutoff the drain select transistor or the source select transistor. For example, the cutoff voltage can be set to 0V. A precharge voltage can be higher than 0V, and can be applied to a bit line BL during a read operation. A verify voltage can be used during a verify operation to determine whether the threshold voltage of a selected memory cell has been increased to a target level. The verify voltage can be set to various levels according to the target level, and can be applied to the selected word line. During a read operation of a selected memory cell, a read voltage can be applied to the selected word line. For example, the read voltage can be set to various levels according to a programming method of the selected memory cell. A pass voltage can be applied to an unselected word line among word lines WL during a programming operation or a read operation, and can be used to conduct a memory cell coupled to the unselected word line. An erase voltage can be used during an erase operation for erasing memory cells included in a selected memory block, and can be applied to a source line SL.

[0041] The row decoder 130 can be configured to transfer an operation voltage Vop to the drain select line DSL, the word line WL, the source select line SSL, and the source line SL coupled to a selected memory block according to a row address RADD. For example, the row decoder 130 can be coupled to the voltage generator 120 through a global line, and can be coupled to the first memory block BLK1 to the j-th memory block BLKj through the drain select line DSL, the word line WL, the source select line SSL, and the source line SL.

[0042] The page buffer group 140 can include page buffers (not shown) respectively coupled to the first memory block BLK1 to the j-th memory block BLKj. Each of the page buffers (not shown) can be coupled to the first memory block BLK1 to the j-th memory block BLKj through a bit line BL.

[0043] The column decoder 150 can be configured to transfer data between the page buffer group 140 and the input / output circuit 160 in response to a column address CADD. For example, the column decoder 150 can be coupled to the page buffer group 140 through a column line CL, and can transfer an enable signal through the column line CL. The page buffers (not shown) included in the page buffer group 140 can receive or output data through a data line DL in response to the enable signal.

[0044] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data through the input / output line I / O. For example, the input / output circuit 160 may transfer the command CMD and the address ADD received from an external controller through the input / output line I / O to the control circuit 170, and may transfer the data received from the external controller through the input / output line I / O to the page buffer group 140. Alternatively, the input / output circuit 160 may output the data transferred from the page buffer group 140 to an external controller through the input / output line I / O.

[0045] The control circuit 170 may output an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, and a column address CADD in response to the command CMD and the address ADD. For example, when the command CMD input to the control circuit 170 corresponds to a programming operation, the control circuit 170 may control the peripheral circuit 180 to perform a programming operation on the memory block selected by the address ADD. When the command CMD input to the control circuit 170 corresponds to a read operation, the control circuit 170 may control the peripheral circuit 180 to perform a read operation on the memory block selected by the address ADD and output read data. When the command CMD input to the control circuit 170 corresponds to an erase operation, the control circuit 170 may control the peripheral circuit 180 to perform an erase operation on the selected memory block.

[0046] Figure 4 is a diagram showing a memory cell array.

[0047] Referring to Figure 4 , the memory cell array 110 may be located above the peripheral circuit 180, but the positions of the memory cell array 110 and the peripheral circuit 180 are not limited to Figure 4 the positions shown. For example, the memory cell array 110 may be located on the same plane as the peripheral circuit 180. Alternatively, after the memory cell array 110 and the peripheral circuit 180 are formed on different substrates, the memory cell array 110 and the peripheral circuit 180 may be brought into contact with each other.

[0048] The memory cell array 110 may include a first memory block BLK1 to a j-th memory block BLKj. The first memory block BLK1 to the j-th memory block BLKj may be spaced apart from each other in the Y direction. The first memory block BLK1 to the j-th memory block BLKj may be configured in the same manner as each other, and may be separated from each other by slit regions 1SR, 2SR, etc. Each of the slit regions 1SR, 2SR, etc. may extend in the X direction. For example, the first memory block BLK1 and the second memory block BLK2 may be separated from each other by the first slit region 1SR.

[0049] Each of the first storage block BLK1 to the j-th storage block BLKj may include a cell plug CP. For example, assuming that the substrate defines an XY plane, the cell plug CP may extend in the Z direction perpendicular to the XY plane, or may be arranged to be spaced apart from each other.

[0050] Figure 5 is a diagram showing the structure of the cell plug included in the storage block, and shows a cross-section of one cell plug CP of the cell plugs CP shown in the XZ direction Figure 4 of the cell plug CP shown.

[0051] Referring to Figure 5 , the cell plug CP may include a core pillar CR, a channel layer CH, a tunnel isolation layer TX, a charge trapping layer CTL, and a blocking layer BX. The core pillar CR may have a cylindrical shape or a rectangular pillar shape, and may include an insulating material or a conductive material. The channel layer CH may surround the side surface and the lower surface of the core pillar CR, and may include polysilicon. The tunnel isolation layer TX may surround the side surface and the lower surface of the channel layer CH, and may include an oxide layer. The charge trapping layer CTL may surround the side surface and the lower surface of the tunnel isolation layer TX, and may include a nitride layer. The blocking layer BX may surround the side surface and the lower surface of the charge trapping layer CTL, and may include an oxide layer.

[0052] Figure 6 is a diagram showing the structure of a guard ring according to an embodiment of the present disclosure.

[0053] Figure 6 shows a part of the guard ring GR extending in the Y direction included in the memory chip MC. The guard ring GR may include a first sub-layer S1 to a fifth sub-layer S5. The fifth sub-layer S5 may have a linear shape extending in the Y direction. The height of the fifth sub-layer S5 in the Z direction may vary according to the depth of the trench in which the guard ring GR is formed. The fifth sub-layer S5 may correspond to the core pillar CR of the cell plug CP. The fourth sub-layer S4 may surround the side surface and the lower surface of the fifth sub-layer S5, and may correspond to the channel layer CH of the cell plug CP. The third sub-layer S3 may surround the side surface and the lower surface of the fourth sub-layer S4, and may correspond to the tunnel isolation layer TX of the cell plug CP. The second sub-layer S2 may surround the side surface and the lower surface of the third sub-layer S3, and may correspond to the charge trapping layer CTL of the cell plug CP. The first sub-layer S1 may surround the side surface and the lower surface of the second sub-layer S2, and may correspond to the blocking layer BX of the cell plug CP.

[0054] The cross-section of the first sub-layer S1 may have a tubular shape surrounding the second sub-layer S2. The cross-section of the second sub-layer S2 may have a tubular shape surrounding the third sub-layer S3. The cross-section of the third sub-layer S3 may have a tubular shape surrounding the fourth sub-layer S4. The cross-section of the fourth sub-layer S4 may have a tubular shape surrounding the fifth sub-layer S5. For some embodiments, the tubular shape may have a variable diameter along the longitudinal axis of the tube. The fifth sub-layer S5 may have a linear shape along the longitudinal axis of the tube.

[0055] According to one embodiment of the present application, the guard ring GR may be formed simultaneously with the cell plug CP in the memory region MR. A method of manufacturing a memory chip including the cell plug CP and the guard ring GR is described below.

[0056] Figures 7A to 7K is a cross-sectional view showing a method of manufacturing a memory chip, and Figures 8A to 8D is a plan view showing a method of manufacturing a memory chip.

[0057] Referring to Figure 7A and Figure 8A , a first stacked structure 1STK defining a memory region MR and a guard region GD may be formed on the lower structure UST. For example, the first stacked structure 1STK may be formed above the lower structure UST in the Z direction. The lower structure UST may be a substrate or a peripheral circuit structure. The first stacked structure 1STK may include a first material layer MT1 and a second material layer MT2 that are different from each other. The first material layer MT1 and the second material layer MT2 may be alternately stacked. For example, the first material layer MT1 may be an oxide layer, and the second material layer MT2 may be a nitride layer.

[0058] The first opening OP1 and the second opening OP2 may be formed simultaneously. The first opening OP1 penetrates the first stacked structure 1STK in the memory region MR to expose a part of the lower structure UST, and the second opening OP2 penetrates the first stacked structure 1STK in the guard region GD to expose a part of the lower structure UST. Each of the first opening OP1 and the second opening OP2 may be formed to have a hole shape. For example, each of the first opening OP1 and the second opening OP2 may be formed to have a hole shape including an elliptical cross-section, a circular cross-section, or a rectangular cross-section. The first opening OP1 may be formed in the memory region MR, and the second opening OP2 may be formed in the guard region GD. An anisotropic dry etching method may be used to perform the etching process for forming the first opening OP1 and the second opening OP2. The etching process may be performed to expose a part of the lower structure UST. In one embodiment, it is assumed that the width of each of the second openings OP2 formed by the anisotropic dry etching process is a first width W1.

[0059] When forming the first opening OP1 and the second opening OP2, holes can be formed simultaneously in other regions in the memory region MR. For example, the memory region MR may include a cell region CE, a peripheral region PR, and a slit region SR. In subsequent processes, a memory block including memory cells can be formed in the cell region CE, peripheral circuits can be formed in the peripheral region PR, and slits for partitioning the memory blocks can be formed in the slit region SR.

[0060] The first opening OP1 can be formed in the cell region CE. The third opening OP3 can be formed in a region in the peripheral region PR where a contact portion for electrically connecting a device in the cell region CE and the peripheral circuits in the peripheral region PR is to be formed. Fourth openings OP4 spaced apart from each other in the X direction can be formed in the slit region SR.

[0061] Referring to Figure 7B and Figure 8B , a first mask pattern 1MS in which a guard region GD and a slit region SR are open can be formed on the first stacked structure 1STK. For example, the second opening OP2 formed in the guard region GD and the fourth opening OP4 formed in the slit region SR can be exposed through the openings in the first mask pattern 1MS.

[0062] Referring to Figure 7C and Figure 8C , an etching process can be performed to increase the size of each of the second opening OP2 and the fourth opening OP4 exposed through the openings in the first mask pattern 1MS. Here, the size of each of the second opening OP2 and the fourth opening OP4 refers to the diameter or width of each of the second opening OP2 and the fourth opening OP4. The etching process can be performed so that the second openings OP2 arranged in the X direction overlap each other and the second openings OP2 arranged in the Y direction overlap each other. The etching process can be performed by a wet etching process or an isotropic dry etching process. When performing the wet etching process or the isotropic dry etching process, a part of the side surface and the bottom surface of each of the second opening OP2 and the fourth opening OP4 can be removed. Therefore, the diameter or width of each of the second opening OP2 and the fourth opening OP4 can be increased. For example, by the wet etching process or the isotropic dry etching process, the width of each of the second openings OP2 can be increased to a second width W2 greater than the first width W1. When the diameter or width of each of the second openings OP2 increases and adjacent second openings OP2 overlap and merge with each other, the second openings OP2 can become a continuous guard opening gOP extending around the cell region CE, the peripheral region PR, and the slit region SR.

[0063] Referring to Figure 7D and Figure 8D, after removing the first mask pattern 1MS, a second mask pattern 2MS can be formed in which the guard region GD, the cell region CE, and the peripheral region PR are open. For example, the second mask pattern 2MS can block the slit region SR and the dicing street region. The dicing street region can surround the guard region GD. The guard opening gOP and the first opening OP1 can be exposed by the second mask pattern 2MS. In Figure 8D , it is shown that the holes formed in the peripheral region PR are also exposed. However, the embodiments are not limited thereto, and the second mask pattern 2MS can be formed to block the holes formed in the peripheral region PR.

[0064] Referring to Figure 7E , a first layer C1 can be formed along the surface of each of the first opening OP1 and the guard opening gOP. For example, the first layer C1 can be formed along the side surface and the bottom surface of each of the first opening OP1 and the guard opening gOP. The first layer C1 can be an insulating layer. For example, the first layer C1 can be an oxide layer.

[0065] Referring to Figure 7F , a second layer C2 can be formed along the surface of the first layer C1. For example, the second layer C2 can be formed along the side surface and the bottom surface of each of the first opening OP1 and the guard opening gOP that are covered by the first layer C1. The second layer C2 can be a nitride layer.

[0066] Referring to Figure 7G , a third layer C3 can be formed along the surface of the second layer C2. For example, the third layer C3 can be formed along the side surface and the bottom surface of each of the first opening OP1 and the guard opening gOP that are covered by the second layer C2. The third layer C3 can be an insulating layer. For example, the third layer C3 can be an oxide layer.

[0067] Referring to Figure 7H , a fourth layer C4 can be formed along the surface of the third layer C3. For example, the fourth layer C4 can be formed along the side surface and the bottom surface of each of the first opening OP1 and the guard opening gOP that are covered by the third layer C3. The fourth layer C4 can be polysilicon.

[0068] Referring to Figure 7I , the region surrounded by the fourth layer C4 can be filled with a fifth layer C5. The fifth layer C5 can be an insulating layer or a conductive layer. Thus, the first layer C1 to the fifth layer C5 formed in the memory region MR can be cell plugs CP, and the first layer C1 to the fifth layer C5 formed in the guard region GD can be guard rings GR.

[0069] The first layer C1 of the cell plug CP may correspond to the blocking layer BX, the second layer C2 of the cell plug CP may correspond to the charge trapping layer CTL, the third layer C3 of the cell plug CP may correspond to the tunnel isolation layer TX, the fourth layer C4 of the cell plug CP may correspond to the channel layer CH, and the fifth layer C5 of the cell plug CP may correspond to the core column CR.

[0070] The first layer C1 of the guard ring GR may correspond to the first sub-layer S1, the second layer C2 of the guard ring GR may correspond to the second sub-layer S2, the third layer C3 of the guard ring GR may correspond to the third sub-layer S3, the fourth layer C4 of the guard ring GR may correspond to the fourth sub-layer S4, and the fifth layer C5 of the guard ring GR may correspond to the fifth sub-layer S5.

[0071] Referring to Figure 7J , an etching process may be performed to remove the second material layer MT2 from the first stack structure 1STK in the memory region MR. For example, an isotropic dry etching process or a wet etching process may be performed. The etching process may be performed using a gas or an etchant having a higher etching selectivity for the second material layer MT2 than for the first material layer MT1. Although not shown in the figure, an isolation structure (not shown) separating the first stack structure 1STK may be formed between the memory region MR and the guard region GD, and due to the isolation structure (not shown), the first stack structure 1STK in the guard region GD may be retained.

[0072] Referring to Figure 7K , a third material layer M3 may be formed between the first material layers M1. The third material layer M3 may serve as a gate line of the memory block. Therefore, the third material layer M3 may include a conductive layer. For example, the third material layer M3 may include a metal material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or may include a semiconductor material such as silicon (Si) or polysilicon (Poly-Si). However, the material for the third material layer M3 is not necessarily limited to the materials specifically indicated above.

[0073] As referred to Figures 7A to 7K and Figures 8A to 8D described, the guard ring GR according to an embodiment of the present disclosure is formed simultaneously with the cell plug CP in the memory region MR. Therefore, the manufacturing time can be reduced compared to a process in which the guard ring GR and the cell plug CP are formed separately.

[0074] Figure 9 is a plan view showing a part of the guard ring.

[0075] Referring to Figure 9, showing a part of a memory chip. The guard ring GR of the memory chip is located in the guard region GD of the memory chip and can extend in the orthogonal direction from the corner. The guard region GD can be surrounded by the scribe lane SCL. In a plan view, the first sub-layer S1 to the fifth sub-layer S5 forming the guard ring GR can have a layout with multiple ovals or circles overlapping.

[0076] Figure 10 is a diagram showing the effect of the guard ring according to the present disclosure.

[0077] Referring to Figure 10 , the guard ring GR can have a linear shape extending in each of the X direction and the Y direction. The guard ring GR of the memory chip can extend to form a right angle at the corner of the memory chip. The memory chip can be surrounded by the scribe lane SCL. Since the first sub-layer S1 to the fifth sub-layer S5 in contact with each other form the guard ring GR, an interface IT can be formed between the first sub-layer S1 to the fifth sub-layer S5 in contact with each other.

[0078] When impurities DP are introduced into the memory chip from the outside of the memory chip during the manufacturing process of the memory chip, the impurities DP may first contact the first sub-layer S1. When the film quality of the part of the first sub-layer S1 in contact with the impurities DP is sturdy, the impurities DP may not be able to penetrate the first sub-layer S1 and may move along the interface IT between the outer layer surrounding the first sub-layer S1 and the first sub-layer S1. When a pinhole is formed in a part of the first sub-layer S1, the impurities DP may penetrate the first sub-layer S1 along the pinhole and may reach the second sub-layer S2. The pinhole can be a defect that may occur during the manufacturing process of the memory chip and can be a hole-type defect that may occur in the heat treatment process, the etching process, or the cleaning process. During the manufacturing process of the memory chip, the pinhole may appear in an unexpected area. Even when a pinhole is formed in a part of the first sub-layer S1, a pinhole may not be formed in the second sub-layer S2. When a pinhole is formed in the first sub-layer S1 and no pinhole is formed in the second sub-layer S2, the impurities DP may reach the interface IT between the first sub-layer S1 and the second sub-layer S2, but may not be able to penetrate the second sub-layer S2. Even when a pinhole is formed in a part of the second sub-layer S2, a pinhole may not be formed in the third sub-layer S3. When a pinhole is formed in the second sub-layer S2 and no pinhole is formed in the third sub-layer S3, the impurities DP may reach the interface IT between the second sub-layer S2 and the third sub-layer S3, but may not be able to penetrate the third sub-layer S3. Therefore, the introduction of impurities into the memory region MR and the oxidation of the memory region MR can be suppressed.

[0079] Since the type of the impurity DP can vary according to the manufacturing process of the memory chip, the materials through which the impurity DP can penetrate may be different. In the guard ring GR according to an embodiment of the present disclosure, the first sub-layer S1 to the fifth sub-layer S5 including different materials from each other may be in contact with each other. Therefore, even when different types of impurities DP are introduced, the regions into which the impurity DP may penetrate or diffuse can be restricted.

[0080] Therefore, it may be difficult for the impurity DP to penetrate all of the first sub-layer S1 to the fifth sub-layer S5 included in the guard ring GR and reach the memory region MR. As a result, the reliability of the memory region MR can be enhanced.

[0081] According to an embodiment, the first sub-layer S1 to the fourth sub-layer S4 of the guard ring GR (more specifically, each pair of sub-layers among a pair of first sub-layers S1, a pair of second sub-layers S2, a pair of third sub-layers S3, and a pair of fourth sub-layers S4) may have a symmetric structure with respect to the fifth sub-layer S5. Therefore, even when the impurity DP penetrates a specific sub-layer among the first sub-layer S1 to the fourth sub-layer S4, in order to reach the memory region MR, the impurity DP also needs to penetrate the paired sub-layer of the specific sub-layer in the corresponding pair of sub-layers. As a result, the probability of the impurity DP penetrating the guard ring GR can be reduced, and thus the reliability of the memory region MR can be improved.

[0082] According to an embodiment, the guard ring GR includes a plurality of different sub-layers (e.g., the first sub-layer S1 to the fifth sub-layer S5) extending in the X direction and the Y direction in the memory chip, so that the stress applied to the wafer in the X direction or the Y direction can be reduced. Therefore, the phenomenon of wafer bending can be reduced.

[0083] Figure 11 is a diagram showing a guard ring structure according to another embodiment of the present disclosure.

[0084] Referring to Figure 11 , the first sub-layer S1 to the fifth sub-layer S5 may form an arc surface instead of a right angle at the corner region 111 of the guard ring GR. In this type of layout, even when impurities are introduced into the guard ring GR from the outside, the phenomenon of impurities concentrating at the corner region 111 can be reduced.

[0085] According to the embodiment of the present disclosure, the protection function of the guard ring can be improved, and defects in the memory region surrounded by the guard ring can be prevented or alleviated. Therefore, the yield of the memory chip can be improved.

[0086] Cross-reference to related applications

[0087] This application claims the priority of Korean Patent Application No. 10-2023-0167849, filed with the Korean Intellectual Property Office on November 28, 2023, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory chip, comprising: a memory area, the memory area including cell plugs storing data; as well as a guard ring surrounding the memory area, The guard ring includes sub-layers having the same material as the layers forming the cell plug and arranged in the same order as the layers forming the cell plug.

2. The memory chip according to claim 1, wherein: The sub-layer has a symmetrical structure with respect to a layer located in the center of the guard ring.

3. The memory chip according to claim 1, wherein: Sub-layers in contact with each other among the sub-layers include different materials from each other.

4. The memory chip according to claim 1, wherein: The sublayers include: a first sub-layer, the first sub-layers being located at the outermost sides of the guard rings and facing each other; second sub-layers, the second sub-layers respectively contact inner surfaces of the first sub-layers and face each other; third sub-layers, the third sub-layers respectively contacting inner surfaces of the second sub-layers and facing each other; fourth sub-layers, the fourth sub-layers respectively contacting inner surfaces of the third sub-layers and facing each other; and The fifth sublayer is located between the fourth sublayers.

5. The memory chip according to claim 4, wherein: The fifth sub-layer contacts an inner surface of the fourth sub-layer.

6. The memory chip according to claim 4, wherein: Each of the first sublayer, the third sublayer, and the fifth sublayer is an insulating layer.

7. The memory chip according to claim 6, wherein: The insulating layer is an oxide layer.

8. The memory chip according to claim 4, wherein: Each of the second sub-layers is a nitride layer.

9. The memory chip according to claim 4, wherein: Each of the fourth sub-layers is a polysilicon layer.

10. The memory chip according to claim 1, wherein: One side of the guard ring has an arc shape.

11. A memory chip, comprising: a cell plug including a first layer penetrating a stacked structure in a memory region, a second layer surrounded by the first layer, a third layer surrounded by the second layer, a fourth layer surrounded by the third layer, and a fifth layer surrounded by the fourth layer; as well as a guard ring disposed around the memory region, Wherein, the protective ring comprises: a first sublayer, the first sublayer corresponding to the first layer; a second sublayer, the second sublayer being surrounded by the first sublayer and corresponding to the second layer; a third sublayer, the third sublayer being surrounded by the second sublayer and corresponding to the third layer; a fourth sublayer, the fourth sublayer being surrounded by the third sublayer and corresponding to the fourth layer; and A fifth sublayer is surrounded by the fourth sublayer and corresponds to the fifth layer.

12. The memory chip according to claim 11, wherein: In a cross section of the guard ring taken in a direction orthogonal to a direction in which the guard ring extends, each of the first to fourth sub-layers has a tubular shape, and the fifth sub-layer has a linear shape.

13. The memory chip according to claim 11, wherein: Each of the first layer, the third layer, the fifth layer, the first sub-layer, the third sub-layer, and the fifth sub-layer is an insulating layer.

14. The memory chip according to claim 13, wherein: The insulating layer is an oxide layer.

15. The memory chip according to claim 11, wherein: Each of the second layer and the second sub-layer is a nitride layer.

16. The memory chip according to claim 11, wherein: Each of the fourth layer and the fourth sub-layer is a polysilicon layer.

17. A method for manufacturing a memory chip, the method comprising the following steps: forming a stacked structure defining a memory area and a protection area surrounding the memory area over the lower structure; forming a first opening in the memory region of the stacked structure; forming a second opening in the guard region of the stacked structure; increasing the width of the second opening and changing the second opening into a protective opening; as well as Different layers are simultaneously formed along surfaces of the first opening and the protection opening.

18. The method according to claim 17, wherein: The first opening and the second opening are formed by a same etching process.

19. The method according to claim 18, wherein: The first opening and the second opening are formed simultaneously.

20. The method according to claim 17, wherein: An etching process for forming the first opening and the second opening is performed until a portion of the lower structure is exposed.

21. The method according to claim 17, wherein: The step of simultaneously forming different layers comprises the following steps: forming a first layer along each of surfaces of the first opening and the guard opening; forming a second layer along a surface of the first layer formed in each of the first opening and the protection opening; forming a third layer along a surface of the second layer formed in each of the first opening and the protection opening; forming a fourth layer along a surface of the third layer formed in each of the first opening and the protection opening; and A fifth layer is formed along a surface of the fourth layer formed in each of the first opening and the protection opening.

22. The method according to claim 21, wherein: Each of the first layer, the third layer, and the fifth layer includes an insulating layer.

23. The method according to claim 21, wherein: The second layer includes a nitride layer.

24. The method according to claim 21, wherein: The fourth layer includes polysilicon.

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