Word line partitioning in stacked memory arrays

Abstract

The invention relates to word line partitioning in a stacked memory array. An example memory device includes a first active region of a memory array, the memory array having a pillar lattice structure; a second active region of the array; and a third region electrically separating the first active region from the second active region, where the pillar lattice structure is not interrupted in the third region.

Description

Technical Field

[0001] The present disclosure generally relates to memory arrays and their formation, and more particularly, to word line partitioning in stacked memory arrays. Background Art

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in a computer or other electronic device. There are many different types of memory, including random access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), resistive memory (such as RRAM), and flash memory, among others.

[0003] Memory can be used as volatile and non-volatile data storage devices for a wide range of electronic applications. Volatile memory may require power to maintain its data, while non-volatile memory can provide persistent data by retaining the stored data when not powered. Flash memory, only as one type of non-volatile memory, can use single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. Non-volatile memory can be used in, for example, personal computers, portable memory sticks, solid state drives (SSDs), digital cameras, cellular phones, portable music players (such as MP3 players), movie players, and other electronic devices. Memory cells can be arranged in an array, where the array is used in a memory device.

[0004] A memory device may have an array of memory cells. The memory array may include groups of memory cells, such as blocks, sub-blocks, strings, etc. In some instances, the memory array may be a stacked memory array, which can be referred to as a three-dimensional (3D) memory array. Memory cells at a common location (e.g., at a common vertical level) in the stacked memory array can form a level of memory cells, for example. Memory cells in each level can be commonly coupled to a common access line, such as a word line. In some instances, a group of memory cells can include memory cells from different levels, which are serially coupled to form a serially coupled memory cell string (such as a NAND string) between a select transistor coupled to a source and a select transistor coupled to a data line (such as a bit line).

[0005] In some instances, formation of a stacked memory array can include a replacement gate process. When a semiconductor structure (e.g., a semiconductor pillar) is formed through an alternating dielectric stack, the replacement gate process can be used to remove dielectric from a tier of the stack at which memory cells will be formed adjacent to the semiconductor structure and form a conductive access line (e.g., a metal access line) in place of the removed dielectric. In various instances, openings (e.g., trenches or slits) can be formed through the stack to provide access to various tiers in the stack to remove selected dielectric material layers (e.g., via an etchant) and replace them with tiers of conductive material (e.g., metal) that can serve as access lines. SUMMARY OF THE INVENTION

[0006] According to one aspect of the present disclosure, a memory device having a word line partition is provided. The memory device includes: a first active region of a memory array, wherein the array includes a pillar lattice structure; a second active region of the array; and a third region that electrically separates the first active region from the second active region, wherein the pillar lattice structure is uninterrupted in the third region.

[0007] According to another aspect of the present disclosure, a method of forming a stacked memory array having a word line partition is provided. The method includes: forming a stack of alternating first and second dielectrics; forming a dielectric extension through the stack such that: a first portion of the dielectric extension is in a first region of the stack; a second portion of the dielectric extension is in a second region of the stack; and a third portion of the dielectric extension is in a third region of the stack that separates the first region from the second region; removing the first portion of the dielectric extension, the second portion of the dielectric extension, and the first dielectric from the first region and the second region; and forming a conductive material in a space of the first region and the second region formed by removing the first portion of the dielectric extension, the second portion of the dielectric extension, and the first dielectric.

[0008] According to yet another aspect of the present disclosure, a method of forming a stacked memory array having a word line partition is provided. The method includes: forming a stack of alternating first and second dielectrics; forming an opening through the stack such that the opening extends through a first region of a semiconductor structure, a second region of the semiconductor structure, and a third region of the semiconductor structure, wherein the third region separates the first region from the second region; lining the opening with a dielectric liner; forming a sacrificial material adjacent to the dielectric liner; removing the first dielectric, the sacrificial material, and the dielectric liner formed in a first group and a second group; and forming a conductive material in a space of the first region and the second region formed by removing the first dielectric, the sacrificial material, and the dielectric liner.

[0009] According to another aspect of the present disclosure, a stacked memory array with word line division is provided. The stacked memory array includes: an intermediate region including a pillar lattice structure; a first lateral memory cell region including the pillar lattice structure; and a second lateral memory cell region including the pillar lattice structure and electrically separated from the first lateral memory cell region by the intermediate region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a top view of a stacked memory array with divided word lines according to the background art.

[0011] Figure 2A is a top view of processing stages associated with forming a stacked memory array according to several embodiments of the present disclosure.

[0012] Figure 2B is during the processing stage according to several embodiments of the present disclosure in Figure 2A and is a cross-section observed along line A-A in Figure 2A during the processing stage.

[0013] Figure 3A is a top view of a processing stage corresponding to after the processing stage of FIG. 2 according to several embodiments of the present disclosure.

[0014] Figure 3B is during the processing stage according to several embodiments of the present disclosure in Figure 3A and is a cross-section observed along line B-B in Figure 3A during the processing stage.

[0015] Figure 3C is during the processing stage according to several embodiments of the present disclosure in Figure 3A and is a cross-section observed along line C-C in Figure 3A during the processing stage.

[0016] Figures 3D to 3F are various views corresponding to a specific processing stage associated with forming a stacked memory array according to several embodiments of the present disclosure.

[0017] Figure 4A is a top view of a processing stage corresponding to after the processing stage of FIG. 3 according to several embodiments of the present disclosure.

[0018] Figure 4B is during the processing stage according to several embodiments of the present disclosure in Figure 4A and is a cross-section observed along line F-F in Figure 4A during the processing stage.

[0019] Figure 4C is during the processing stage according to several embodiments of the present disclosure in Figure 4Aobserved along line G-G in during the processing stage in Figure 4A Cross-section observed in the cross-section along line G-G in

[0020] Figure 5A is a top view corresponding to a specific processing stage associated with forming a stacked memory array according to several embodiments of the present disclosure.

[0021] Figure 5B is in according to several embodiments of the present disclosure Figure 5A observed along line H-H in during the processing stage in Figure 5A Cross-section observed in the cross-section along line H-H in

[0022] Figure 5C is a cross-section observed along line I-I in according to several embodiments of the present disclosure Figure 5A Cross-section observed in the cross-section along line I-I in

[0023] Figure 5D is corresponding to according to several embodiments of the present disclosure Figures 5A to 5C Top view of the processing stage after the processing stage of

[0024] Figure 5E is in according to several embodiments of the present disclosure Figure 5D observed along line J-J in during the processing steps of the processing stage in Figure 5D Cross-section observed in the cross-section along line J-J in

[0025] Figure 5F is in according to several embodiments of the present disclosure Figure 5D observed along line K-K in during the processing steps of the processing stage in Figure 5D Cross-section observed in the cross-section along line K-K in

[0026] Figure 6A is a top view of the processing stage after the processing stage corresponding to FIG. 5 according to several embodiments of the present disclosure.

[0027] Figure 6B is in according to several embodiments of the present disclosure Figure 6A observed along line N-N in during the processing stage in Figure 6A Cross-section observed in the cross-section along line N-N in

[0028] Figure 6C is in according to several embodiments of the present disclosure Figure 6A observed along line O-O in during the processing stage in Figure 6A Cross-section observed in the cross-section along line O-O in

[0029] Figure 7A is a top view corresponding to the processing stage associated with forming a stacked memory array according to several embodiments of the present disclosure.

[0030] Figure 7Bis a cross-section observed along line P-P in Figure 7A during a processing stage according to several embodiments of the present disclosure. Figure 7A is a cross-section observed along line Q-Q in

[0031] Figure 7C during a processing stage according to several embodiments of the present disclosure. Figure 7A is a cross-section observed along line Q-Q in Figure 7A during a processing stage according to several embodiments of the present disclosure.

[0032] Figure 7D is a top view corresponding to a processing stage after the stage corresponding to Figures 7A to 7C according to several embodiments of the present disclosure.

[0033] Figure 7E is a cross-section observed along line R-R in Figure 7D during a processing stage according to several embodiments of the present disclosure. Figure 7D is a cross-section observed along line R-R in

[0034] Figure 7F is a cross-section observed along line S-S in Figure 7D during a processing stage according to several embodiments of the present disclosure. Figure 7D is a cross-section observed along line S-S in

[0035] Figure 7G is a top view corresponding to a processing stage after the stage corresponding to Figures 7D to 7F according to several embodiments of the present disclosure.

[0036] Figure 7H is a cross-section observed along line T-T in Figure 7G during a processing stage according to several embodiments of the present disclosure. Figure 7G is a cross-section observed along line T-T in

[0037] Figure 7I is a cross-section observed along line U-U in Figure 7G during a processing stage according to several embodiments of the present disclosure. Figure 7G is a cross-section observed along line U-U in

[0038] Figure 8A is a top view corresponding to a processing stage after the processing stage of FIG. 7 according to several embodiments of the present disclosure.

[0039] Figure 8B is a cross-section observed along line V-V in Figure 8A during a processing stage according to several embodiments of the present disclosure. Figure 8A is a cross-section observed along line V-V in

[0040] Figure 8C is a cross-section observed along line V-V in Figure 8A during a processing stage according to several embodiments of the present disclosure.Figure 8A The cross-section observed along line W-W in

[0041] Figure 9 Illustrates a stacked memory array in accordance with several embodiments of the present disclosure.

[0042] Figure 10 Is a block diagram of an apparatus in accordance with several embodiments of the present disclosure. DETAILED DESCRIPTION

[0043] Disclosed herein is word line partitioning and its formation in a stacked memory array. Some memory arrays may include architectures in which word lines are partitioned into two segments. For example, some memory arrays are wide enough such that their relatively long word lines can be split to maintain RC and random read performance. In many cases, the two segments are of equal or substantially equal size. Two string drivers each serving a half-page segment (e.g., 8KB) can be placed at the center or the edge of the plane. In the latter case, the continuous word line electrodes are cut at the center of the plane with minimal space loss and minimal symmetric perturbation.

[0044] Previous methods for performing half-plane word line splitting may involve forming a gap in a pillar structure to electrically isolate the two resulting half-word lines. Due to the overly long half-plane interruption, such methods increase the loss of word line length. In some methods, for example, the interruption can be about 20 microns. It should be understood that the longer the interruption, the greater the reduction in the number of memory cells available for storing data.

[0045] Embodiments of the present disclosure can electrically isolate two half-word lines by forming a dielectric extension between the two half-word lines without interrupting the pillar structure of the array. Thus, compared to previous methods, the half-plane interruption is reduced in embodiments of the present disclosure. In some embodiments, the half-plane interruption is less than half of the interruption seen in previous methods. For example, the half-plane interruption can be about 8 microns. The two resulting half-word lines may be referred to herein as a "first active region" and a "second active region", and the portion of the array associated with the dielectric extension between them may be referred to herein as a "partition wall" and / or a "third region". The dielectric extension can be formed through a stack of alternating first and second dielectrics. For example, the first dielectric can be at a tier in the stack where memory cells will be formed adjacent to a semiconductor structure.

[0046] The dielectric extension can extend from between a group of semiconductor structures in the first active region through the third region and to the second active region. The dielectric extension can couple the alternating dielectrics in both the first and second active regions to the alternating dielectrics in the third region.

[0047] When a dielectric extension couples alternating dielectrics in first and second active regions to alternating dielectrics in a third region, an opening may be formed between groups of semiconductor structures. For example, the opening may provide access to a first dielectric to enable its removal (e.g., as part of a replacement gate process). The coupling may limit movement that may occur to the semiconductor structures when forming the opening. For example, excessive movement of the semiconductor structures may make it difficult to align data line contacts to the semiconductor structures during subsequent processing.

[0048] When a dielectric extension couples a second dielectric in first and second active regions to alternating dielectrics in a third region, a first dielectric in the first and second active regions may be removed. The coupling is used to limit movement that may occur to the semiconductor structures when the first dielectric is removed. In a subsequent process, metal may be formed by supplying metal through the opening in a space corresponding to the first dielectric to form an access line when the dielectric extension couples the second dielectric in the first and second active regions to alternating dielectrics in the third region. The coupling is used to limit movement that may occur to the semiconductor structures when forming the metal.

[0049] FIG. 1 is a top view of a stacked memory array with divided word lines according to the background art. The array shown in FIG. 1 includes a full plane (e.g., 16 KB) that has been divided into two half planes - a first half plane 104-1 and a second half plane 104-2. As shown in FIG. 1, a prior method for performing half plane word line division may involve forming a gap 103 in a pillar structure to electrically isolate two resulting half word lines. Such methods increase the loss of word line length due to the overly long half plane break 106. In some methods, for example, the break 106 may be about 20 microns.

[0050] In FIG. 1, an alternating dielectric stack 101 is shown, such as alternating nitride and oxide. Semiconductor structures may be included in groups 118-1 and 118-2. In some instances, memory cells may be partially formed adjacent to semiconductor structure 105, for example, at a tier of the stack 101 having nitride.

[0051] An opening 108 including sections 110-1, 110-2, 110-3, and 112 is formed through the stack 101. For example, a removal material selective to nitride may be supplied through the opening 108 to remove the nitride while leaving the oxide. In some instances, a partially formed memory cell may be completed by accessing the memory cell through the opening 108. Metal (e.g., tungsten) may be supplied through the opening 108 to form an access line that may be coupled to the memory cell. In some instances, the formation of the opening 108, the removal of the nitride, the completion of the memory cell, and the formation of the access line may be formed as part of a replacement gate process.

[0052] A dielectric may be formed in the opening 108 to electrically isolate the access lines corresponding to group 118-1 from the access lines corresponding to group 118-2. A section 112 of the opening 108 crosses over to sections 110-1 to 110-3. For example, sections 110-1 to 110-3 and 112 form respective "T intersections". In some instances, the opening 108 may be formed during a single processing step in which sections 110-1 to 110-3 and 112 may be concurrently formed (e.g., during a single etch). However, as an example, the "T intersection" may be formed by performing a first etch through the stack 101 to form sections 110-1 to 110-3 and performing a second etch through the stack 101 to form section 112.

[0053] Figures 2A to 2B are various views corresponding to specific processing stages associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. Figure 2A is a top view of a processing stage associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. Figure 2B is during the processing stage in accordance with several embodiments of the present disclosure in Figure 2A and is a cross-section taken along line A-A in Figure 2A as observed. Figure 2A and 2B may be collectively referred to herein as "Figure 2". As shown in Figure 2, the pillars 220 may be formed in three zones: a first zone 207-1, a second zone 207-2, and a third zone 209. The dielectric material 221 may be formed in the openings of the stack.

[0054] Figures 3A to 3C are various views corresponding to specific processing stages associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. Figure 3A is a top view corresponding to a processing stage after the processing stage of Figure 2 in accordance with several embodiments of the present disclosure. Figure 3B is during the processing stage in accordance with several embodiments of the present disclosure in Figure 3A and is a cross-section taken along line B-B in Figure 3A as observed. Figure 3C is during the processing stage in accordance with several embodiments of the present disclosure in Figure 3A and is a cross-section taken along line C-C in Figure 3A as observed. Figure 3A and 3B 3C may be collectively referred to herein as "Figure 3".

[0055] A mask may be formed over a portion of the stack. For example, the mask may be formed over the zone 309 to cover a portion of the dielectric 321 in the zone 309. The portion of the dielectric 321 is removed, as Figure 3AShown in []. For example, the dielectric 321 formed in regions 307-1 and 307-2 is removed, leaving the dielectric 321 in region 309. In some instances, the portions of the dielectric 321 not covered by the mask are removed, for example, by wet etching or by reactive ion etching (RIE), leaving the portions of the dielectric 321 covered by the mask.

[0056] Figures 3D to 3F are various views corresponding to specific processing stages associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. Figure 3D is in accordance with several embodiments of the present disclosure corresponding to Figure 3C is a top view of the processing stage after the processing stage of []. Metal 319 can be supplied through a section (discussed further below) to form metal in the space. For example, metal 319 can form an access line that may include a control gate of a memory cell and a control line that may include a gate of a select transistor. For example, metal 319 can be formed in the space as part of a replacement gate process.

[0057] In some instances, after the formation of metal 319, a dielectric structure can pass through a stack of dielectrics not removed by the removal material alternating with the metal. Figure 3E is in accordance with several embodiments of the present disclosure corresponding to Figure 3D is a top view of the processing stage after the processing stage of []. As Figure 3D shown in [], after the formation of metal 319, dielectric 326 can be formed in the first and second regions.

[0058] Figure 4A is a top view of the processing stage after the processing stage of Figure 3 in accordance with several embodiments of the present disclosure. Figure 4B is in accordance with several embodiments of the present disclosure during Figure 4A is a cross-section observed along line F-F in [] during the processing stage of []. Figure 4A during the processing stage of []. Figure 4C is in accordance with several embodiments of the present disclosure during Figure 4A is a cross-section observed along line G-G in [] during the processing stage of []. Figure 4A during the processing stage of []. Figure 4A , 4B and 4C may be collectively referred to herein as "Figure 4".

[0059] The example array illustrated in Figure 4 includes a plurality of metal entry points 413 in the third region 409. Depending on the number of metal entry points, for example, the width of the guard band 410 can be increased relative to the array illustrated in Figure 2.

[0060] Figure 5Ais a top view corresponding to a particular processing stage associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. In some instances, the array can be a three-dimensional NAND memory array. Figure 5B is during the processing stage in accordance with several embodiments of the present disclosure in Figure 5A during the processing stage in Figure 5A a cross-section observed along line H-H in Figure 5C is a cross-section observed along line I-I in accordance with several embodiments of the present disclosure in Figure 5A in Figures 5A to 5C can correspond to a processing stage that can occur after several processing stages have taken place. In some instances, the processing stage can include several steps that can have several sub-steps.

[0061] As shown in FIG. 5, a group of semiconductor structures 520 passes through a region of a stack of alternating dielectrics 523 and 525 formed on (e.g., over) a semiconductor. The semiconductor structures 520 and the semiconductor can be polysilicon, silicon doped conductively to have p-type conductivity (e.g., single crystal p - -type silicon), or the like. Dielectric 525 can be an oxide, and dielectric 523 can be a nitride. For example, dielectric 523 can be a sacrificial dielectric that can be removed during a subsequent processing stage.

[0062] In the processing stage corresponding to Figures 5A to 5C , an opening is formed through the stack. For example, a mask (e.g., an imaging resist) is formed over the uppermost dielectric 525 and patterned to define the regions of the stack to be removed. The defined regions to be removed are then removed (e.g., by etching) to form an opening.

[0063] The opening extends from region 509 into regions 507-1 and 507-2. During the processing stage in Figures 5A to 5C , a dielectric extension 528, which can be an oxide, is formed in the opening. Note that dielectric extension 528 can couple the alternating dielectrics 523 and 525 to the alternating dielectrics 525 and 523, as shown in Figure 5B .

[0064] Figure 5D is a top view corresponding to a processing stage after the processing stage in accordance with several embodiments of the present disclosure in Figures 5A to 5C . Figure 5E is a cross-section observed along line J-J during the processing steps of the processing stage in accordance with several embodiments of the present disclosure in Figure 5D in Figure 5D in Figure 5F is a cross-section observed along line K-K during the processing steps of the processing stage in accordance with several embodiments of the present disclosure in Figure 5D in Figure 5D in

[0065] During Figures 5D to 5F the processing steps, an opening 530 is formed through the stack and through a portion of the dielectric extension 528, stopping at or in the upper surface of the semiconductor. For example, the opening 530 through the dielectric extension 528 can be preformed as part of a replacement gate process. The dielectric extension 528 and the corresponding opening 530 can overlap in region 509 and in portions of regions 507-1 and 507-2. The opening 530 can provide access to the alternating dielectrics 523 and 525.

[0066] The opening 530 passes through a central portion of the dielectric extension 528, where the opening 530 overlaps the dielectric extension 528. For example, where any of the openings 530 overlap the dielectric extension 528, the dielectric extension 528 can be lined in the opening 530, as Figure 5E shown. For example, as Figure 5E shown, a portion of the dielectric extension 528 is between the opening 530 and the alternating dielectrics 523 and 525.

[0067] Note that when the opening 530 is formed, the dielectric extension 528 couples the alternating dielectrics 523 and 525 in region 509 to the alternating dielectrics 525 and 523. This coupling limits the movement that can occur in the semiconductor structure when the opening 530 is formed.

[0068] The opening 530 can provide access to the dielectric 523 to effect removal of the dielectric 523. For example, the dielectric 523 can be removed as part of a replacement gate process. A removal material (e.g., a wet etchant) can be supplied through the opening 530 to remove the dielectric 523 to form a stack with alternating dielectrics 525 and spaces. Note that the uppermost and lowermost spaces expose the gate dielectric, and the space between the uppermost and lowermost spaces exposes the barrier dielectric.

[0069] When the dielectric 523 is removed, the dielectric extension 528 couples the alternating dielectrics 523 and 525 to the alternating dielectrics 525 and 523. This coupling limits the movement that can occur in the semiconductor structure when the dielectric 523 is removed.

[0070] The removal material can flow from the opening 530 into regions 507-1 and 507-2. However, the removal material may not flow into region 509 (e.g., the portion of the opening 530 that overlaps with the dielectric extension 528). The distance that the dielectric extension 528 extends into regions 507-1 and 507-2 can be selected to limit the penetration of the removal material into region 509. For example, if the distance is too large, the removal material may not be able to completely remove the dielectric 523 from regions 507-1 and 507-2. If the distance is too small, the removal material may remove too much of the dielectric 523 from region 509. Metal 519 (e.g., tungsten) can be supplied through the opening 530 to form metal 519 in the space. For example, metal 519 can be formed in the space as part of a replacement gate process. As Figure 3D shown, after the formation of the metal 319, a dielectric 526 can be formed in the opening 530.

[0071] Figures 6A to 6C are various views corresponding to specific processing stages associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. Figure 6A is a top view corresponding to a processing stage after the processing stage of FIG. 5 in accordance with several embodiments of the present disclosure. Figure 6B is in accordance with several embodiments of the present disclosure during Figure 6A the processing stage along Figure 6A the line N-N in Figure 6C is a cross-section observed in accordance with several embodiments of the present disclosure during Figure 6A the processing stage along Figure 6A the line O-O in Figure 6A 、 6B and 6C may be collectively referred to herein as "FIG. 6".

[0072] The example array illustrated in FIG. 6 includes a plurality of metal entry points 613 in a third region 609. Depending on the number of metal entry points, for example, the width of the guard band 610 can be increased relative to the array illustrated in FIG. 2.

[0073] Figures 7A to 7I are various views corresponding to specific processing stages associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. Figure 7A is a top view corresponding to a processing stage associated with forming a stacked memory array in accordance with several embodiments of the present disclosure. Figure 7B is in accordance with several embodiments of the present disclosure during Figure 7A the processing stage along Figure 7A the line P-P in Figure 7C is in accordance with several embodiments of the present disclosure during Figure 7A the processing stage along Figure 7AThe cross-section observed along line Q-Q in Figure 7A , 7B , 7C, 7D, 7E, 7F, 7G, 7H, 7I may be collectively referred to herein as "Figure 7".

[0074] During the processing stage corresponding to Figures 7A to 7C , an opening is formed through the stack. For example, a mask (such as an imaging resist) is formed over the uppermost dielectric 725 and patterned to define the regions of the stack to be removed. The defined regions to be removed are then removed (e.g., by etching) to form an opening.

[0075] The opening extends from region 709 into regions 707-1 and 707-2. During the processing stage of Figures 7A to 7C , a dielectric extension 732, which may be an oxide, is formed in the opening. Note that the dielectric extension 732 may couple the alternating dielectrics 723 and 725 to the alternating dielectrics 725 and 723, as shown in Figure 7B .

[0076] Figures 7D to 7F are various views corresponding to specific processing stages associated with forming a stacked memory array according to several embodiments of the present disclosure. Figure 7D is a top view corresponding to a processing stage after the stage corresponding to Figures 7A to 7C according to several embodiments of the present disclosure. Figure 7E is a cross-section observed along line R-R in Figure 7D during the processing stage of Figure 7D according to several embodiments of the present disclosure. Figure 7F is a cross-section observed along line S-S in Figure 7D during the processing stage of Figure 7D according to several embodiments of the present disclosure.

[0077] During the processing stage corresponding to Figures 7D to 7F , an opening 734 is formed through the stack and adjacent to a portion of the dielectric extension 732, stopping at or in the upper surface of the semiconductor. For example, the opening 734 may be pre-formed as part of a replacement gate process. The dielectric extension 732 and the opening 734 may be adjacent in regions 707-1 and 707-2. The opening 734 may provide access to the alternating dielectrics 723 and 725.

[0078] Figures 7G to 7I are various views corresponding to specific processing stages associated with forming a stacked memory array according to several embodiments of the present disclosure. Figure 7G is a top view corresponding to a processing stage after the stage corresponding to Figures 7D to 7F according to several embodiments of the present disclosure. Figure 7His a cross-section observed along line T-T in Figure 7G during a processing stage according to several embodiments of the present disclosure. Figure 7G is a cross-section observed along line U-U in Figure 7I during a processing stage according to several embodiments of the present disclosure. Figure 7G during a processing stage according to several embodiments of the present disclosure. Figure 7G is a cross-section observed along line U-U in

[0079] As Figures 7G to 7I shown, metal 719 (e.g., tungsten) can be supplied through opening 734 to form metal 719 in the space. For example, metal 719 can be formed in the space as part of a replacement gate process. As Figure 7G shown, after the formation of metal 719, dielectric 736 can be formed in opening 734.

[0080] Figure 8A is a top view corresponding to a processing stage after the processing stage of FIG. 7 according to several embodiments of the present disclosure. Figure 8B is a cross-section observed along line V-V in Figure 8A during a processing stage according to several embodiments of the present disclosure. Figure 8A is a cross-section observed along line V-V in Figure 8C is a cross-section observed along line W-W in Figure 8A during a processing stage according to several embodiments of the present disclosure. Figure 8A is a cross-section observed along line W-W in Figure 8A , 8B and 8C may be collectively referred to as "FIG. 8" herein.

[0081] The example array illustrated in FIG. 8 includes a plurality of metal entry points 813 in the third region 809. Depending on the number of metal entry points, for example, the width of the guard band 810 can be increased with respect to the array illustrated in FIG. 2.

[0082] Figure 9 illustrates a stacked memory array 960 according to several embodiments of the present disclosure. For example, the array 960 may include a region 902 (e.g., a memory cell region). The array 960 includes a stepped structure 975 adjacent to the region 902.

[0083] The array 960 may include a stack alternating between a dielectric 925 and a metal layer tier 919. The semiconductor structure 905 passes through the stack in the region 902 and terminates at or in the upper surface of the semiconductor 925. The select transistor 932 may be adjacent to each semiconductor structure 905 at the tier corresponding to the uppermost metal layer tier 919, and the select transistor 934 may be adjacent to each semiconductor structure 905 at the tier corresponding to the lowermost metal layer tier 919. The memory cell 926 may be adjacent to each semiconductor structure 905 at the tier corresponding to the metal layer tier 919 between the uppermost and lowermost metal layer tiers 919.

[0084] The uppermost and lowermost metal layer tiers 919 may be control lines forming or coupled to the control gates of the select transistors 932 and 934, respectively. The metal layer tiers 919 between the uppermost and lowermost metal layer tiers 919 may be access lines forming or coupled to the control gates of the memory cells 926.

[0085] The stepped structure 975 includes steps 976 that may each include a respective metal layer tier 919 above the adjacent dielectric 925. The respective contacts 978 are coupled to the metal layer tiers 919 of each respective step 976. The respective contacts 978 may be coupled to an activation (e.g., access) circuitry via respective lines 979. The data line 980 is coupled to the semiconductor structure 905 via a data line contact 982.

[0086] An opening 950 is formed through the stack. The opening 950 may terminate at a dielectric extension in a manner similar to that previously described herein. For example, a dielectric extension (e.g., dielectric liner 947) may line a section of the opening 950.

[0087] Compared to previous methods, the dielectric extension may provide more compact isolation between adjacent blocks on either side of the Figure 9 opening 950. For example, some previous methods may add another stepped structure opposite the Figure 9 stepped structure 975 in the to isolate adjacent blocks on either side of the opening 950. However, the added stepped structure may occupy additional space compared to the dielectric extension.

[0088] Figure 10FIG. 0 is a block diagram of a device in accordance with several embodiments of the present disclosure. For example, the device can be an electronic system such as computing system 1090. Computing system 1090 can include a memory system 1092, which can be, for example, a solid state drive (SSD). Memory system 1092 can include a host interface 1094, a controller 1095 (such as a processor and / or other control circuitry), and several memory devices 1096 (such as NAND flash devices) that provide storage capacity for memory system 1092. Memory devices 1096 can have several memory arrays 1060, such as the memory arrays described herein.

[0089] Controller 1095 can be coupled to host interface 1094 and several memory devices 1096 via one or more channels and can be used to transfer data between memory system 1092 and host 1091. Host 1091 can be coupled to host interface 1094 through communication channel 1093. Host 1091 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a smart phone, or a memory card reader, as well as various other types of hosts.

[0090] The term semiconductor can refer to, for example, a material layer, a wafer, or a substrate and includes any underlying semiconductor structure. The term "semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, an epitaxial layer of silicon supported by an underlying semiconductor structure, and other semiconductor structures well known to those skilled in the art. Further, when a semiconductor is mentioned in the following description, previous process steps may have been used to form regions / junctions in the underlying semiconductor structure, and the term semiconductor can include the underlying layer containing such regions / junctions.

[0091] As used herein, "a" can refer to one or more of something, and "several" of something can refer to one or more of such things. For example, several memory cells can refer to one or more memory cells. "A plurality of" something is intended to be two or more. As used herein, the term "coupled" can include electrical coupling, direct coupling, and / or a direct connection without an intervening element (e.g., by direct physical contact) or an indirect coupling and / or connection using an intervening element. The term coupled can further include two or more than two elements that cooperate or interact with each other (e.g., in a causal relationship). As used herein, multiple actions that are executed concurrently refer to actions that at least partially overlap within a particular time period.

[0092] The figures in this document follow a numbering convention where the first or first few digits correspond to the figure number and the remaining digits identify the elements or components within the figure. Similar elements or components between different figures may be identified by using similar numbers. As should be understood, the elements shown in the various embodiments herein may be added, exchanged, and / or eliminated to provide several additional embodiments of the present disclosure. Additionally, the proportions and relative scales of the elements provided in the figures are intended to illustrate the various embodiments of the present disclosure and are not to be used in a limiting sense.

[0093] Although specific embodiments have been illustrated and described herein, those of ordinary skill in the art will appreciate that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. The present disclosure is intended to cover adaptations or variations of the various embodiments of the present disclosure. It should be understood that the foregoing description has been presented in an illustrative manner and not a limiting manner. Those skilled in the art will appreciate combinations of the above-described embodiments and other embodiments not specifically described herein after reviewing the foregoing description. The scope of the various embodiments of the present disclosure includes other applications in which the above structures and methods are used. Accordingly, the scope of the various embodiments of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A memory device (1096) having word line partitioning, comprising: a first active region (207-1, 307-1, 407-1, 507-1, 707-1) of a memory array (960), wherein the array comprises a pillar lattice structure (220); a second active region (207-2, 307-2, 407-2, 507-2, 707-2) of the array; and A third region (209, 309, 409, 509, 609, 709, 809) electrically separates the first active region from the second active region, wherein the pillar lattice structure is uninterrupted in the third region.

2. The memory device of claim 1, wherein the first active area corresponds to a first half-plane of the memory array, and wherein the second active area corresponds to a second half-plane of the memory array.

3. The memory device of claim 1, wherein the first active area and the second active area are substantially the same size.

4. The memory device of claim 1, wherein the first active area comprises a first portion of a word line and the second active area comprises a second portion of the word line.

5. The memory device of claim 4, wherein the word line comprises memory cells corresponding to a 16 kilobyte page size.

6. The memory device of claim 1, further comprising: a first set of string drivers at a first end of the array and associated with the first active region; and A second set of string drivers is at a second end of the array and associated with the second active region.

7. The memory device of any one of claims 1 to 6, further comprising a plurality of metal access points (413, 613, 813) in the third region.

8. The memory device of any one of claims 1-6, further comprising a plurality of metal contacts (978) in the third region.

9. A method of forming a stacked memory array with word line partitioning, comprising: forming a stack of alternating first dielectrics (523, 723) and second dielectrics (525, 725); A dielectric extension (528, 732) is formed through the stack such that: A first portion of the dielectric extension is in a first region (207-1, 307-1, 407-1, 507-1, 707-1) of the stack; A second portion of the dielectric extension is in a second region (207-2, 307-2, 407-2, 507-2, 707-2) of the stack; and a third portion of the dielectric extension is in a third region (209, 309, 409, 509, 609, 709, 809) of the stack separating the first region from the second region; removing the first portion of the dielectric extension, the second portion of the dielectric extension, and the first dielectric from the first region and the second region; and Conductive material (319, 719, 919) is formed in spaces of the first and second regions formed by removing the first portion of the dielectric extension, the second portion of the dielectric extension, and the first dielectric.

10. The method of claim 9, wherein forming the conductive material comprises forming a metal.

11. The method of claim 9, wherein the method includes forming a plurality of metal contacts (978) in the third region after forming the conductive material.

12. The method of any one of claims 9-11, wherein removing the first dielectric from the first region and the second region is performed as part of a replacement gate process.

13. A method of forming a stacked memory array with word line partitioning, comprising: forming a stack of alternating first dielectrics (523, 723) and second dielectrics (525, 725); forming an opening (530) through the stack such that the opening extends through a first region of the semiconductor structure, a second region of the semiconductor structure, and a third region of the semiconductor structure, wherein the third region separates the first region from the second region; lining the opening with a dielectric liner (947); forming a sacrificial material adjacent to the dielectric liner; removing the first dielectric, the sacrificial material, and the dielectric liner formed in the first group and the second group; A conductive material is formed in spaces of the first and second regions formed by removing the first dielectric, the sacrificial material, and the dielectric liner. The method of claim 13 , wherein the conductive material comprises tungsten.

15. A stacked memory array with word line partitioning, comprising: an intermediate region (209, 309, 409, 509, 609, 709, 809) comprising a pillar lattice structure; a first lateral memory cell region (207-1, 307-1, 407-1, 507-1, 707-1) comprising the pillar lattice structure; and A second lateral memory cell region (207-2, 307-2, 407-2, 507-2, 707-2) includes the pillar lattice structure and is electrically separated from the first lateral memory cell region by the middle region.

16. The array of claim 15, wherein: The first lateral memory cell region includes first and second groups of memory cells and a first dielectric between the first and second groups; and The second lateral memory cell region includes third and fourth groups of memory cells and the first dielectric between the third and fourth groups.

17. The array of claim 15, wherein the width of the intermediate region is less than 10 microns.

18. The array of claim 15, wherein the pillar lattice structure is uninterrupted across the array.

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