Semiconductor device and memory device including the same

Abstract

A semiconductor device and a memory device including the semiconductor device are provided. The semiconductor device includes a channel layer, a ferroelectric layer on the channel layer, a charge trapping layer on the ferroelectric layer, a barrier modulation layer on the charge trapping layer, a tunnel barrier layer on the barrier modulation layer, and a gate electrode on the tunnel barrier layer. The barrier modulation layer is configured to have a higher electron affinity than the tunnel barrier layer and the charge trapping layer, and a lower band gap than the tunnel barrier layer and the charge trapping layer.

Description

Technical Field

[0001] Various example embodiments relate to semiconductor devices and storage devices including semiconductor devices. Background Art

[0002] As storage devices have become smaller and highly integrated, vertical NAND flash devices have been developed, which include a plurality of memory cells stacked in a direction perpendicular to a substrate. In recent years, research has been conducted to apply ferroelectric field effect transistors (FeFETs) having a low operating voltage and a fast programming speed to vertical NAND flash devices. An FeFET is a semiconductor device in which storage characteristics are implemented by adjusting a threshold voltage according to a polarization direction of a ferroelectric material. An FeFET device is manufactured by forming a gate insulating film including a ferroelectric material. Summary of the Invention

[0003] Various example embodiments include semiconductor devices and / or storage devices including semiconductor devices.

[0004] Additional aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the presented example embodiments.

[0005] According to one or more example embodiments, a semiconductor device includes a channel layer, a ferroelectric layer on the channel layer, a charge trapping layer on the ferroelectric layer, a barrier modulation layer on the charge trapping layer, a tunnel barrier layer on the barrier modulation layer, and a gate electrode on the tunnel barrier layer. The barrier modulation layer is configured to have a high electron affinity compared to the tunnel barrier layer and the charge trapping layer and is configured to have a low bandgap compared to the tunnel barrier layer and the charge trapping layer.

[0006] Alternatively or additionally, according to one or more example embodiments, a semiconductor device includes a channel layer, a ferroelectric layer on the channel layer, a barrier modulation layer on the ferroelectric layer, a tunnel barrier layer on the barrier modulation layer and including at least one of silicon oxide or aluminum oxide, and a gate electrode on the tunnel barrier layer. The barrier modulation layer is configured to have a high electron affinity compared to the tunnel barrier layer and the ferroelectric layer and have a low bandgap compared to the tunnel barrier layer and the ferroelectric layer.

[0007] Alternatively or additionally, according to one or more example embodiments, a storage device includes a plurality of cell columns, where each of the plurality of cell columns includes a channel layer extending perpendicular to a substrate, a ferroelectric layer on the channel layer, a charge trapping layer on the ferroelectric layer, a barrier modulation layer on the charge trapping layer, a tunnel barrier layer on the barrier modulation layer, and a plurality of gate electrodes on the tunnel barrier layer. The barrier modulation layer is configured to have a high electron affinity compared to the tunnel barrier layer and the charge trapping layer and have a low bandgap compared to the tunnel barrier layer and the charge trapping layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features, and advantages of certain example embodiments will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a cross-sectional view schematically showing a semiconductor device according to some example embodiments;

[0010] Figure 2 shows Figure 1 the energy band diagram of the semiconductor device shown;

[0011] Figure 3A and Figure 3B shows the result of the amount of charge tunneling toward the gate electrode in accordance with the measurement of the potential barrier of electrons;

[0012] Figures 4A to 4C shows a semiconductor device including a SiO 2 tunnel barrier layer and a SiN charge trapping layer;

[0013] Figure 5 is a cross-sectional view schematically showing a semiconductor device according to some example embodiments;

[0014] Figures 6A to 6C shows a semiconductor device including a SiO 2 tunnel barrier layer and a HZO ferroelectric layer;

[0015] Figure 7 is a cross-sectional view schematically showing a semiconductor device according to some example embodiments;

[0016] Figure 8 shows Figure 7 the energy band diagram of the semiconductor device shown;

[0017] Figure 9 is a perspective view schematically showing a memory device according to some example embodiments;

[0018] Figure 10 shows Figure 9 the cross-section of the cell column shown;

[0019] Figure 11 is Figure 10 an enlarged view of part B of;

[0020] Figure 12 is a cross-sectional view of a memory device according to some example embodiments;

[0021] Figure 13 is a cross-sectional view of a memory device according to some example embodiments;

[0022] Figure 14 is a conceptual diagram schematically showing a device architecture that can be applied to an electronic device;

[0023] Figure 15 is a block diagram showing a storage system according to some example embodiments; and

[0024] Figure 16 is a block diagram showing a neuromorphic apparatus according to some example embodiments and an external device connected to the neuromorphic apparatus. Detailed Embodiments

[0025] Now, various embodiments will be described in detail, examples of which are shown in the accompanying drawings, where the same reference numerals always denote the same elements. In this regard, these embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, only the provided example embodiments are described below by referring to the accompanying drawings to explain various aspects. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. Expressions such as "at least one of..." modify the entire list of elements when located after a list of elements, rather than modifying individual elements in the list.

[0026] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same components, and for clarity and convenience of explanation, the dimensions of each component in the drawings may be exaggerated. On the other hand, the embodiments to be described below are merely examples, and various modifications are possible with respect to these embodiments.

[0027] Hereinafter, when a part is described as being "above" or "on" another part, it may include cases where the part is non - contactingly above, below, to the left, and to the right, in addition to being in contact with the top, bottom, left, and right. Unless the context is clearly different, singular expressions include plural expressions. Further, when a part "includes" a component, it means that it may further include other components without excluding other components, unless otherwise specifically stated to the contrary.

[0028] The use of the term "above" and the use of similar indicative words may correspond to both singular and plural forms. If the order for steps used to configure a method is clearly described or there is no contrary description, these steps can be executed in a suitable order, not necessarily limited to the described order.

[0029] In addition, terms such as "..." and "module" described in the specification are units that process at least one function or operation, which can be implemented by hardware or software or by combining hardware and software.

[0030] The connections of lines between components shown in the drawings or connection members show functional connections and / or physical or circuit connections, which are shown as replaceable or additional functional connections, physical connections or circuit connections in an actual device.

[0031] The use of all examples or exemplary terms is only intended to describe the technical idea in detail, and the scope is not limited by these examples or exemplary terms unless restricted by the claims.

[0032] A ferroelectric field-effect transistor (FeFET) is or includes a memory device that utilizes the property of changing the threshold voltage of a transistor by switching spontaneous polarization. The FeFET can have two or more threshold voltages, such as a minimum threshold voltage and a maximum threshold voltage determined by the polarization state of the ferroelectric, and various threshold voltages between the minimum and maximum threshold voltages. These threshold voltages can be non-volatile and insensitive to the application of an external power supply, and multiple information can be stored through these threshold voltages, enabling a multi-level memory to be realized. Here, a memory window (MW) can be configured in which the difference between the minimum threshold voltage and the maximum threshold voltage corresponds to the sensing margin. It is desirable to ensure as much MW as possible so that a sufficient number of multiple levels can be realized in the FeFET-based memory device.

[0033] Figure 1 is a cross-sectional view schematically showing a semiconductor device 100 according to some example embodiments. Figure 1 The semiconductor device 100 shown can be an FeFET. The semiconductor device 100 can constitute a memory cell of a memory device to be described later.

[0034] Referring Figure 1 , the semiconductor device 100 can include a semiconductor substrate 110, a ferroelectric layer 130, a charge trapping layer 140, a barrier modulation layer 150, a tunnel barrier layer 160, and a gate electrode 170. A channel element 115 can be formed in an upper region of the semiconductor substrate 110 to correspond to the gate electrode 170, and a first region (e.g., a source region S) and a second region (e.g., a drain region D) can be formed on both sides of the channel element 115. The semiconductor substrate 110 can include a halo or pocket implant region adjacent to the source region S and / or the drain region D; the example embodiments are not limited thereto.

[0035] The semiconductor substrate 110 may include, for example, a Group IV semiconductor (such as one or more of silicon (Si), germanium (Ge), silicon-germanium (SiGe)) and / or a Group III-V semiconductor compound. The semiconductor substrate 110 may include, for example, one or more of an oxide semiconductor, a nitride semiconductor, a oxynitride semiconductor, a two-dimensional (2D) semiconductor material, quantum dots, or an organic semiconductor. Here, the oxide semiconductor may include, for example, InGaZnO, etc., the 2D semiconductor material may include, for example, transition metal dichalcogenides (TMDs) and / or graphene, and the quantum dots may include one or more of colloidal QDs, nanocrystal structures, etc. However, this is merely an example, and the embodiments are not limited thereto.

[0036] The semiconductor substrate 110 may further include a dopant. The dopant may include a p-type dopant and / or an n-type dopant. The p-type dopant may include, for example, one or more of Group III elements (such as boron (B), aluminum (Al), gallium (Ga), indium (In), etc.), and the n-type dopant may include, for example, one or more of Group V elements (such as phosphorus (P), arsenic (As), antimony (Sb), etc.). For example, the semiconductor substrate 110 may be a p-Si substrate doped with a p-type dopant on Si, or an n-Si substrate doped with an n-type dopant on Si. However, this is only an example. In some additional examples, the semiconductor substrate may include both a p-type dopant and an n-type dopant at very different concentrations; the exemplary embodiments are not limited thereto.

[0037] The interface layer 120 may be formed on the surface of the semiconductor substrate 110. The interface layer 120 may be or may include an oxide and / or a nitride of the semiconductor substrate 110, but the embodiments are not limited thereto. For example, when the semiconductor substrate 110 includes silicon, the interface layer 120 may include silicon oxide.

[0038] The gate electrode 170 may be disposed above the semiconductor substrate 110. The gate electrode 170 may include, for example, a metal and / or a metal nitride. The metal may include, for example, one or more of Al, tungsten (W), molybdenum (Mo), titanium (Ti), or tantalum (Ta), and the metal nitride may include, for example, titanium nitride (TiN) and / or tantalum nitride (TaN).

[0039] The gate electrode 170 may include one or more of a metal carbide, polysilicon (such as doped polysilicon), or a 2D conductive material. The metal carbide may be a metal carbide doped with Al and / or Si. As a specific example, the metal carbide may include one or more of TiAlC, TaAlC, TiSiC, or TaSiC. The gate electrode 170 may also have a structure in which a plurality of materials are stacked. For example, the gate electrode 170 may have a stacked structure of a metal nitride layer / metal layer (such as TiN / Al), or a stacked structure of a metal nitride layer / metal carbide layer / metal layer (such as TiN / TiAlC / W).

[0040] The ferroelectric layer 130 may be between the semiconductor substrate 110 and the gate electrode 170. A ferroelectric is or includes a material having ferroelectricity, which maintains a spontaneous polarization with the alignment of internal electric dipole moments. Even in a state where no external electric field is applied, the ferroelectric material has a remanent polarization of dipoles. Further, in a ferroelectric, the direction of polarization can be switched by an external electric field in units of domains.

[0041] The ferroelectric layer 130 may include, for example, at least one of a fluorite-based material, a perovskite, or a nitride-based material. Here, "fluorite" and "perovskite" refer to specific configurations / motifs of materials. The fluorite-based material may include, for example, at least one oxide selected from the group consisting of or including hafnium (Hf), Si, Al, zirconium (Zr), yttrium (Y), lanthanum (La), gadolinium (Gd), or strontium (Sr), and may or may not include fluorine. As a specific example, the fluorite-based material may include at least one of hafnium oxide (HfO), zirconium oxide (ZrO), or hafnium zirconium oxide (HfZrO). The perovskite may include, for example, PZT, BaTiO 3 、PbTiO 3 or the like, and the embodiments are not limited thereto. The nitride-based material may include, for example, AlScN, but the embodiments are not limited thereto.

[0042] The ferroelectric layer 130 may further include a certain dopant. For example, the ferroelectric layer 130 may include a material in which a certain dopant is inserted into at least one of HfO, ZrO, or HfZrO. Here, the certain dopant may include, for example, at least one of Zr, La, Al, Si, or Y at the same concentration or at different concentrations. However, the exemplary embodiments are not limited thereto.

[0043] The tunnel barrier layer 160 may be between the ferroelectric layer 130 and the gate electrode 170. The tunnel barrier layer 160 may be configured to shield the polarization at the upper interface of the ferroelectric layer 130 by means of charges introduced through tunneling. Accordingly, the MW may increase due to the effect that the capacitance decreases as the space between the ferroelectric layer 130 and the gate electrode 170 increases.

[0044] In the tunnel barrier layer 160, tunneling should occur rapidly at a high voltage, and at the standby voltage, the charges introduced into the tunnel barrier layer 160 need not be released. The tunnel barrier layer 160 may include, for example, silicon oxide (SiO 2 ). However, this is merely an example, and the tunnel barrier layer 160 may include various other materials. For example, the tunnel barrier layer 160 may include aluminum oxide (Al 2 O 3 ).

[0045] The charge trapping layer 140 may be between the tunnel barrier layer 160 and the ferroelectric layer 130. The charge trapping layer 140 may be or may correspond to a layer for trapping charges between the tunnel barrier layer 160 and the ferroelectric layer 130, and the charges trapped by the charge trapping layer 140 are added to the charges tunneling through the tunnel barrier layer 160, so that the increasing effect of the MW may be increased or maximized. The charge trapping layer 140 may include, for example, silicon nitride (SiN). However, the embodiments are not limited thereto.

[0046] The barrier modulation layer 150 may be between the tunnel barrier layer 160 and the charge trapping layer 140. The barrier modulation layer 150 may be configured to increase the barrier of electrons. The barrier modulation layer 150 may include a material having a high electron affinity and a low bandgap compared with the tunnel barrier layer 160 and also compared with the charge trapping layer 140.

[0047] In a general semiconductor device, the tunnel barrier layer may mainly include silicon oxide (SiO 2 ), and the charge trapping layer may mainly include silicon nitride (SiN). In a state where no external voltage is applied to the semiconductor device including the tunnel barrier layer and the charge trapping layer, the charges trapped on the charge trapping layer may be released to the gate electrode. In this case, since the barrier of electrons is very low compared with the barrier of holes, electrons may be more easily released to the gate electrode than holes. This may result in a worse result in the retention characteristics in the erase operation state compared with the programming operation state.

[0048] Figure 2 Schematically shows Figure 1 The energy band diagram (or Fermi diagram) of the semiconductor device 100 shown. Refer to Figure 2, a barrier modulation layer 150 including a material having a high electron affinity and a low bandgap compared to the tunnel barrier layer 160 and the charge trapping layer 140 may be inserted between the tunnel barrier layer 160 and the charge trapping layer 140, such that the barrier Ep for electrons may be increased compared to the case where there is no barrier modulation layer 150.

[0049] Figure 3A and Figure 3B show results of the amount of charge tunneling toward the gate electrode in accordance with the measurement of the barrier for electrons. In Figure 3A and Figure 3B , the tunnel barrier layer includes silicon oxide having a thickness of 2 nm.

[0050] Figure 3A shows the amount of charge tunneling toward the gate electrode for 1 ms in accordance with the intensity of the electric field applied to the tunnel barrier layer when the barrier for electrons is 2 eV. Figure 3B shows the amount of charge tunneling toward the gate electrode for 1 ms in accordance with the intensity of the electric field applied to the tunnel barrier layer when the barrier for electrons is 3 eV. Referring to Figure 3A and Figure 3B , when an electric field of about 2 MV / cm is applied to the tunnel barrier layer, the amount of charge tunneling toward the gate electrode can be further reduced in the case where the barrier for electrons is 3 eV compared to the case where the barrier for electrons is 2 eV, which indicates that the tunneling current flowing through the gate electrode is greatly reduced. Thus, as the barrier for electrons increases, the retention characteristics in the erase operation state can be improved.

[0051] According to various exemplary embodiments, a barrier modulation layer 150 that can be configured to increase the barrier Ep for electrons compared to the barrier Eh for holes may be inserted between the tunnel barrier layer 160 and the charge trapping layer 140, such that the amount of electrons released to the gate electrode 170 is reduced. Accordingly, the retention characteristics in the erase operation state can be improved or enhanced. The barrier modulation layer 150 may include a material having a high electron affinity and a low bandgap compared to both the tunnel barrier layer 160 and the charge trapping layer 140. The barrier modulation layer 150 may include a material having a sum of electron affinity and bandgap of 8 eV or less. However, the exemplary embodiments are not limited thereto. The barrier modulation layer 150 may include, for example, TiO 2 , Ta 2 O 5 , SrTiO 3 or one or more of ZnO. The barrier modulation layer 150 may have a thickness of about 0.1 nm to about 5 nm, but the embodiments are not limited thereto.

[0052] Figures 4A to 4C shows the energy band diagram of a semiconductor device including a SiO 2 tunnel barrier layer and a SiN charge trapping layer.

[0053] Figure 4A Show SiO 2 Energy band diagram of a semiconductor device without a barrier modulation layer between the tunnel barrier layer and the SiN charge trapping layer. Refer to Figure 4A SiO 2 The electron affinity and bandgap of the tunnel barrier layer are 0.95 eV and 8.9 eV, respectively. The electron affinity and bandgap of the SiN charge trapping layer are 2.15 eV and 5.1 eV, respectively. SiO 2 The barrier for electrons between the tunnel barrier layer and the SiN charge trapping layer is 1.1 eV, and the barrier for holes is 2.7 eV.

[0054] Figure 4B Show the energy band diagram of a semiconductor device with the first barrier modulation layer BML1 between the SiO 2 tunnel barrier layer and the SiN charge trapping layer. Refer to Figure 4B Compared with the SiO 2 tunnel barrier layer and the SiN charge trapping layer, the first barrier modulation layer BML1 can have a high electron affinity and a low bandgap. Specifically, the electron affinity and bandgap of the first barrier modulation layer BML1 are 2.95 eV and 4.9 eV, respectively. Thus, the sum of the electron affinity and the bandgap of the first barrier modulation layer BML1 is 7.85 eV. SiO 2 The barrier for electrons between the tunnel barrier layer and the first barrier modulation layer BML1 is 2.0 eV, which is increased compared with the case of Figure 4A .

[0055] Figure 4C Show the energy band diagram of a semiconductor device with the second barrier modulation layer BML2 between the SiO 2 tunnel barrier layer and the SiN charge trapping layer. Refer to Figure 4C Compared with the SiO 2 tunnel barrier layer and the SiN charge trapping layer, the second barrier modulation layer BML2 has a high electron affinity and a low bandgap. Specifically, the electron affinity and bandgap of the second barrier modulation layer BML2 are 5.4 eV and 3.5 eV, respectively. Thus, the sum of the electron affinity and the bandgap of the second barrier modulation layer BML2 is 8.9 eV. SiO 2 The barrier for electrons between the tunnel barrier layer and the second barrier modulation layer BML2 is 4.45 eV, which is greatly increased compared with the case of Figure 4A , but the barrier for holes is greatly reduced compared with the case of Figure 4A .

[0056] As described above, compared with the SiO 2The first barrier modulation layer BML1, which has a higher electron affinity and a lower bandgap compared to the tunnel barrier layer and the SiN charge trapping layer and has a sum of electron affinity and bandgap of 8 eV or less, can be SiO 2 between the tunnel barrier layer and the SiN charge trapping layer, so that the barrier for electrons can be effectively increased, and similarly, the retention characteristics in the erase operation state can be improved.

[0057] The following [Table 1] shows the electron affinity and bandgap of exemplary materials.

[0058] [Table 1]

[0059]

[0060] Referring to [Table 1], materials that have a higher electron affinity and a lower bandgap compared to the tunnel barrier layer and the SiN charge trapping layer and have a sum of electron affinity and bandgap of 8 eV or less can be, for example, TiO 2 、Ta 2 、Ta 2 O 5 、SrTiO 3 or ZnO.

[0061] Figure 5 is a cross-sectional view schematically showing a semiconductor device 200 according to some example embodiments. Hereinafter, the differences between the present embodiment and the above-described embodiment will be described.

[0062] Referring to Figure 5 , the semiconductor device 200 may include a semiconductor substrate 110, a ferroelectric layer 130, a barrier modulation layer 150, a tunnel barrier layer 160, and a gate electrode 170. An interface layer 120 may be formed on the surface of the semiconductor substrate 110.

[0063] The ferroelectric layer 130 may be between the semiconductor substrate 110 and the gate electrode 170. The ferroelectric layer 130 may include at least one of, for example, a fluorite-based material, a perovskite, or a nitride-based material. For example, the ferroelectric layer may include at least one of HfO, ZrO, or HfZrO. The tunnel barrier layer 160 may be between the ferroelectric layer 130 and the gate electrode 170. The tunnel barrier layer 160 may include, for example, silicon oxide (SiO 2 ) and / or aluminum oxide (Al 2 O 3 ).

[0064] The barrier modulation layer 150 may be between the tunnel barrier layer 160 and the ferroelectric layer 130. The barrier modulation layer 150 may include a material having a high electron affinity and a low bandgap compared to both the tunnel barrier layer 160 and the ferroelectric layer 130 to increase the barrier for electrons. The barrier modulation layer 150 may include a material having a sum of electron affinity and bandgap of 8 eV or less. However, embodiments are not limited thereto. The barrier modulation layer 150 may include, for example, TiO 2 、Ta 2 O 5 、SrTiO 3 or at least one of ZnO. The barrier modulation layer 150 may have a thickness of about 0.1 nm to about 5 nm, but embodiments are not limited thereto.

[0065] Figures 6A to 6C Shows the energy band diagram of a semiconductor device including a SiO 2 tunnel barrier layer and a HZO ferroelectric layer. "HZO" represents hafnium-zirconium oxide.

[0066] Figure 6A Shows the energy band diagram or Fermi level diagram of a semiconductor device without a barrier modulation layer between the SiO 2 tunnel barrier layer and the HZO ferroelectric layer. Refer to Figure 6A ,the electron affinity and bandgap of the SiO 2 tunnel barrier layer are 0.95 eV and 8.9 eV, respectively. The electron affinity and bandgap of the HZO ferroelectric layer are 2.65 eV and 5.7 eV, respectively. The barrier for electrons between the SiO 2 tunnel barrier layer and the HZO ferroelectric is 1.7 eV, and the barrier for holes is 1.5 eV.

[0067] Figure 6B Shows the energy band diagram of a semiconductor device with a first barrier modulation layer BML1 between the SiO 2 tunnel barrier layer and the HZO ferroelectric layer. Refer to Figure 6B ,compared to the SiO 2 tunnel barrier layer and the HZO ferroelectric layer, the first barrier modulation layer BML1 may have a high electron affinity and a low bandgap. Specifically, the electron affinity and bandgap of the first barrier modulation layer BML1 are 2.95 eV and 4.9 eV, respectively. Therefore, the sum of the electron affinity and bandgap of the first barrier modulation layer BML1 is 7.85 eV. The barrier for electrons between the SiO 2 tunnel barrier layer and the first barrier modulation layer BML1 is 2.0 eV, which is increased compared to the case of Figure 6A .

[0068] Figure 6C Shows the second barrier modulation layer BML2 in the SiO 2Energy band diagram of a semiconductor device between a tunnel barrier layer and an HZO ferroelectric layer. Refer to Figure 6C , compared with the SiO 2 tunnel barrier layer and the HZO ferroelectric layer, the second barrier modulation layer BML2 has a high electron affinity and a low bandgap. Specifically, the electron affinity and the bandgap of the second barrier modulation layer BML2 are 5.4 eV and 3.5 eV, respectively. Therefore, the sum of the electron affinity and the bandgap of the second barrier modulation layer BML2 is 8.9 eV. SiO 2 The potential barrier for electrons between the tunnel barrier layer and the second barrier modulation layer BML2 is 4.45 eV, which is greatly increased compared with the case of Figure 6A , but the potential barrier for holes is 0.95 eV, which is greatly reduced compared with the case of Figure 6A .

[0069] As described above, the first barrier modulation layer BML1 having a high electron affinity and a low bandgap compared with the SiO 2 tunnel barrier layer and the HZO ferroelectric layer and a sum of electron affinity and bandgap of 8 eV or less is between the SiO 2 tunnel barrier layer and the HZO ferroelectric charge trapping layer, so that the potential barrier for electrons can be effectively increased, and similarly, the retention characteristics in the erase operation state can be improved.

[0070] Figure 7 is a cross-sectional view schematically showing a semiconductor device 300 according to some example embodiments. Hereinafter, the differences between the example embodiments shown in Figure 7 and the above-described embodiments will be described.

[0071] Refer to Figure 7 , the semiconductor device 300 may include a semiconductor substrate 110, a ferroelectric layer 130, a charge trapping layer 140, a barrier modulation layer 350, a tunnel barrier layer 160, and a gate electrode 170. An interface layer 120 may be formed on the surface of the semiconductor substrate 110.

[0072] The ferroelectric layer 130 may be between the semiconductor substrate 110 and the gate electrode 170. The tunnel barrier layer 160 may be between the ferroelectric layer 130 and the gate electrode 170, and the charge trapping layer 140 may be between the tunnel barrier layer 160 and the ferroelectric layer 130. The tunnel barrier layer 160 may include, for example, silicon oxide (SiO 2 ) and / or aluminum oxide (Al 2 O 3 ). The charge trapping layer 140 may include, for example, silicon nitride (SiN). However, the embodiments are not limited thereto.

[0073] The barrier modulation layer 350 may be between the tunnel barrier layer 160 and the charge trapping layer 140. The barrier modulation layer 350 may include a matrix 351 and metal nanocrystals 352 dispersed (e.g., uniformly dispersed) in the matrix 351. The matrix 351 may be used to increase the barrier for electrons, and the matrix 351 and the barrier modulation layer in the above exemplary embodiment (see Figure 1 150) may have the same material. For example, the matrix 351 may include a material having a high electron affinity and a low bandgap compared to the tunnel barrier layer 160 and the charge trapping layer 140. The matrix 351 may include a material having the sum of the electron affinity and the bandgap of 8 eV or less. The matrix 351 may include, for example, TiO 2 , Ta 2 O 5 , SrTiO 3 or one or more of ZnO.

[0074] The metal nanocrystals 352 may be used to further increase the barrier for electrons by confining the electrons inside. Figure 8 Shows Figure 7 the energy band diagram of the semiconductor device 300 shown. As Figure 8 shown, in the region where the metal nanocrystals 352 are present, the barrier for electrons can be increased more effectively. The barrier modulation layer 350 may have a thickness of about 0.1 nm to about 5 nm, but the embodiments are not limited thereto.

[0075] As described above, the case where the semiconductor device 300 includes the charge trapping layer 140 has been described. However, the semiconductor device may not include the charge trapping layer. In this case, the barrier modulation layer 350 including the matrix 351 and the metal nanocrystals 352 may be between the tunnel barrier layer 160 and the ferroelectric layer 130. Here, the matrix 351 may include a material having a high electron affinity and a low bandgap compared to the tunnel barrier layer 160 and the ferroelectric layer 130.

[0076] Figure 9 is a cross-sectional view schematically showing a storage device 700 according to some exemplary embodiments. Figure 9 The storage device 700 shown in

[0077] Referring to Figure 9 , the storage device 700 may include a plurality of cell columns CS arranged on a substrate 701. Here, each of the plurality of cell columns CS may be arranged to extend in a direction perpendicular to the substrate 701 (or perpendicular to the upper surface of the substrate 701) ( Figure 9 the z-axis direction in

[0078] The interlayer insulating layer 775 and the gate electrode 770 may be alternately stacked on the substrate 701 in a direction perpendicular to the substrate 701. Each interlayer insulating layer 775 and each gate electrode 770 may be arranged parallel to the substrate 701. The substrate 701 may include various materials. For example, the substrate 701 may include a single crystal silicon substrate, a compound semiconductor substrate, or a silicon-on-insulator (SOI) substrate, but the embodiments are not limited thereto. In addition, electronic devices such as impurity regions defined by doping, electronic devices such as transistors and / or diodes, and / or peripheral circuits for selecting and controlling the memory cells MC for storing data may be further arranged on the substrate 701.

[0079] The gate electrode 770 may include, for example, a metal material having excellent electrical conductivity such as gold (Au), a metal nitride, doped silicon, or a 2D conductive material, etc. However, this is merely an example, and the gate electrode 770 may include various other materials. A word line or a row line may be electrically connected to the gate electrode 770.

[0080] The interlayer insulating layer 775 may serve as a spacer layer for insulation between the gate electrodes 770. The interlayer insulating layer 775 may include, for example, silicon oxide, silicon nitride, etc., but the embodiments are not limited thereto. Channel holes may be formed in the interlayer insulating layer 775 and the gate electrode 770 to penetrate in a direction perpendicular to the substrate 701 (z-axis direction). For example, each of the channel holes may be formed to have a circular cross-section. As described below, the tunnel barrier layer 760, the barrier modulation layer 750, the charge trapping layer 740, the ferroelectric layer 730, and the channel layer 715 may be sequentially arranged on the inner wall of the channel hole.

[0081] Figure 10 Shown Figure 9 The cross-section of the cell column CS shown Figure 11 is Figure 10 an enlarged view of part B of

[0082] Refer to Figure 10 and Figure 11, each cell column CS may include a plurality of memory cells MC stacked in a direction perpendicular to the substrate 701 (z-axis direction). The cell column CS may include a plurality of gate electrodes 770 stacked to be spaced apart from each other in a direction perpendicular to the substrate 701 with an interlayer insulating layer 775 therebetween, and a tunnel barrier layer 760, a barrier modulation layer 750, a charge trapping layer 740, a ferroelectric layer 730, and a channel layer 715 that are sequentially arranged inside the gate electrode 770 and perpendicular to the substrate 701. The number and / or thickness of each of the gate electrode 770 and the interlayer insulating layer 775 are not limited thereto; for example, the thickness of at least one gate electrode 770 may be different from that of other gate electrodes 770, and / or the thickness of at least one interlayer insulating layer 775 may be different from that of other interlayer insulating layers 775. Each of the tunnel barrier layer 760, the barrier modulation layer 750, the charge trapping layer 740, the ferroelectric layer 730, and the channel layer 715 may be arranged to extend perpendicular to the substrate 701 and may be shared by a plurality of memory cells MC. An interface layer 720 may be further provided between the channel layer 715 and the ferroelectric layer 730. A filling insulating layer 790 may be provided inside the channel layer 715 to fill the channel holes. The filling insulating layer 790 may include, for example, silicon oxide or air, but the embodiments are not limited thereto.

[0083] Each memory cell MC may include a gate electrode 770, and a tunnel barrier layer 760, a barrier modulation layer 750, a charge trapping layer 740, a ferroelectric layer 730, and a channel layer 715 that are arranged to correspond to the gate electrode 770. A source and a drain may be provided below and above the channel layer 715, respectively, and a channel corresponding to each of the gate electrodes 770 may be formed on the channel layer 715 between the source and the drain.

[0084] The channel layer 715 may include a semiconductor material. For example, the channel layer 715 may include, for example, Si, Ge, SiGe, III-V group semiconductors, etc. In addition, the channel layer 715 may include one or more of, for example, an oxide semiconductor, a nitride semiconductor, a oxynitride semiconductor, a 2D semiconductor material, a quantum dot, or an organic semiconductor. Here, the oxide semiconductor may include, for example, InGaZnO, etc., the 2D semiconductor material may include one or more of, for example, transition metal dichalcogenides (TMDs) or graphene, and the quantum dot may include a colloidal QD, a nanocrystal structure, etc. However, this is merely an example, and the embodiments are not limited thereto.

[0085] The channel layer 715 may further include a dopant. Here, the dopant may include a p-type dopant or an n-type dopant. The p-type dopant may include, for example, one or more group III elements such as B, Al, Ga, In, etc., and the n-type dopant may include, for example, one or more group V elements such as P, As, Sb, etc. In various exemplary embodiments, the ferroelectric layer 730, the charge trapping layer 740, the barrier modulation layer 750, and the tunnel barrier layer 760 may be the same as those in the exemplary embodiments shown in Figure 1 and thus a detailed description thereof will be omitted.

[0086] Figure 12 is a cross-sectional view of a memory device 800 according to some exemplary embodiments. For convenience, Figure 12 only the main parts of the memory cells constituting or included in the memory device 800 are shown, and the same applies hereinafter.

[0087] Referring to Figure 12 , the tunnel barrier layer 760, the barrier modulation layer 750, the ferroelectric layer 730, and the channel layer 715 are sequentially stacked on the gate electrode 770. Since the channel layer 715, the ferroelectric layer 730, the barrier modulation layer 750, the tunnel barrier layer 760, and the gate electrode 770 are the same as those in the embodiments shown in Figure 5 , a detailed description thereof will be omitted.

[0088] Figure 13 is a cross-sectional view of a memory device 900 according to some exemplary embodiments.

[0089] Referring to Figure 13 , the tunnel barrier layer 760, the barrier modulation layer 750, the charge trapping layer 740, the ferroelectric layer 730, and the channel layer 715 may be sequentially stacked on the gate electrode 770. Here, the barrier modulation layer 750 may include a matrix 751 and metal nanocrystals 752 dispersed (e.g., uniformly dispersed) in the matrix 751. Since the channel layer 715, the ferroelectric layer 730, the charge trapping layer 740, the barrier modulation layer 750, the tunnel barrier layer 760, and the gate electrode 770 may be the same as those in the embodiments shown in Figure 7 , a detailed description thereof will be omitted. On the other hand, in Figure 13 , the charge trapping layer 740 may not be provided.

[0090] The memory devices 100, 200, 300, 700, 800, and 900 according to the embodiments described above may be used for data storage in various electronic devices. Figure 14 is a conceptual diagram schematically showing a device architecture that can be applied to an electronic device.

[0091] Referring to Figure 14, the cache memory 1510, the arithmetic logic unit (ALU) 1520, and the control unit 1530 may constitute a central processing unit (CPU) 1500, and the cache memory 1510 may include a static random access memory (SRAM). In addition to the CPU 1500, a main memory 1800 and an auxiliary storage 1900 may also be provided. An input / output device 2500 may also be provided. The main memory 1800 may include a dynamic random access memory (DRAM) device, and the auxiliary storage 1900 may include one or more of the above-described storage devices 100, 200, 300, 700, 800, or 900. In some cases, the device architecture may be implemented in a form in which computing unit elements and storage unit elements regardless of the classification of sub-units are arranged adjacent to each other in one chip.

[0092] The storage devices 100, 200, 300, 700, 800, and 900 according to the above-described embodiments may be implemented as chip-type storage blocks and may be used as a neuromorphic computing platform, or may be used to form a neural network.

[0093] Figure 15 is a block diagram showing a storage system 1600 according to some example embodiments.

[0094] Reference Figure 15 , the storage system 1600 may include a storage controller 1601 and a storage device 1602. The storage controller 1601 may perform control operations on the storage device 1602. For example, the storage controller 1601 may provide an address ADD and a command CMD for performing a programming (or recording), reading, and / or erasing operation on the storage device 1602 to the storage device 1602. Alternatively or additionally, data for a programming operation and a reading operation may be transferred between the storage controller 1601 and the storage device 1602.

[0095] The storage device 1602 may include a storage cell array 1610 and a voltage generator 1620. The storage cell array 1610 may include a plurality of storage cells and may include one or more of the storage devices 100, 200, 300, 700, 800, and 900 according to the above-described embodiments.

[0096] The storage controller 1601 may include: processing circuitry, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, more specifically, the processing circuitry may include a CPU, an ALU, a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. However, the embodiments are not limited thereto. The storage controller 1601 may operate in response to a request from a host (not shown), access the storage device 1602, and control the control operations (e.g., write / read operations) discussed above, and thus is configured to convert the storage controller 1601 into a dedicated controller. The storage controller 1601 may generate an address ADD and a command CMD for performing programming / read / erase operations on the memory cell array 1610. Moreover, a voltage generator 1620 (e.g., a power supply circuit) may generate a voltage control signal in response to an instruction from the storage controller 1601, and the voltage control signal is used to control the voltage level of a word line for data programming or data reading on the memory cell array 1610.

[0097] In addition, the storage controller 1601 may perform a determining operation on the data read from the storage device 1602. For example, the number of turned-on cells and / or turned-off cells may be determined by the data read from the memory cells. The storage device 1602 may provide a pass / fail signal P / F to the storage controller 1601 according to the read result of the read data. The storage controller 1601 may control the write and read operations of the memory cell array 1610 by referring to the pass / fail signal P / F.

[0098] Figure 16 is a block diagram showing a neuromorphic device 1700 and an external device connected to the neuromorphic device 1700 according to some example embodiments.

[0099] Referring to Figure 16 , the neuromorphic device 1700 may include processing circuitry 1710 and / or on-chip memory 1720. The neuromorphic device 1700 may include one or more of the storage devices 100, 200, 300, 700, 800, and 900 according to the above embodiments.

[0100] In some example embodiments, the processing circuit 1710 may be configured to control functions for driving the neuromorphic device 1700. For example, the processing circuit 1710 may be configured to control the neuromorphic device 1700 by executing a program stored in the on-chip memory 1720. In some embodiments, the processing circuit 1710 may include hardware such as logic circuits, a hardware / software combination such as a processor for executing software, or a combination thereof. For example, the processor may include a CPU, a graphics processing unit (GPU), an application processor (AP) included in the neuromorphic device 1700, an ALU, a digital signal processor, a microcomputer, an FPGA, an SoC, a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. However, the embodiments are not limited thereto. In some example embodiments, the processing circuit 1710 may be configured to read various data from an external device 1730 / write various data to the external device 1730 and / or execute the neuromorphic device 1700 by using the read / written data. In some example embodiments, the external device 1730 may include an external memory and / or a sensor array having an image sensor (e.g., a complementary metal oxide semiconductor (CMOS) image sensor circuit).

[0101] In some example embodiments, Figure 16 the neuromorphic device 1700 may be applied to a machine learning system. The machine learning system may use various artificial neural network organizations and processing models, such as a recurrent neural network (RNN) optionally including a convolutional neural network (CNN), a deconvolutional neural network, long short-term memory (LSTM) units, and / or gated recurrent units (GRU), a stacked neural network (SNN), a state space dynamic neural network (SSDNN), a deep belief network (DBN), a generative adversarial network (GAN), and / or a restricted Boltzmann machine.

[0102] Alternatively or additionally, these machine learning systems may include different types of machine learning models, such as linear and / or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, expert systems, and / or combinations thereof including ensemble learning such as random forests. Such machine learning models may be used to provide various services and / or applications, such as an image classification service, a user authentication service based on biometrics or biometric data, an advanced driver assistance system (ADAS) service, a voice assistant service, an automatic speech recognition (ASR) service, etc.

[0103] According to the various example embodiments described above, a barrier modulation layer including a material having a high electron affinity and a low bandgap may be inserted between the tunnel barrier layer and the charge trapping layer or between the tunnel barrier layer and the ferroelectric layer, so that the barrier for electrons can be increased, and thus the retention characteristics of the memory device in the erase operation state can be improved. The above-described memory devices 100, 200, 300, 700, 800, and 900 have been described with reference to the embodiments shown in the drawings, but these are merely examples, and those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom.

[0104] Any one of the elements and / or functional blocks disclosed above may include a processing circuit (such as hardware including logic circuits; a hardware / software combination such as a processor executing software; or a combination thereof) or be implemented as a processing circuit (such as hardware including logic circuits; a hardware / software combination such as a processor executing software; or a combination thereof). For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include electrical components such as at least one of transistors, resistors, capacitors, etc. The processing circuit may include electrical components such as logic gates including at least one of AND gates, OR gates, NAND gates, NOT gates, etc.

[0105] It should be understood that the various example embodiments described herein should be considered only in a descriptive sense and not for purposes of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

[0106] This application is based on and claims priority to Korean Patent Application No. 10-2023-0169854, filed with the Korean Intellectual Property Office on November 29, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Channel layer; a ferroelectric layer on the channel layer; a charge trapping layer on the ferroelectric layer; a barrier modulation layer on the charge trapping layer; a tunnel barrier layer on the barrier modulation layer; as well as a gate electrode on the tunnel barrier layer, The barrier modulation layer is configured to have a higher electron affinity than the tunnel barrier layer and the charge trapping layer, and a lower band gap than the tunnel barrier layer and the charge trapping layer. 2 . The semiconductor device according to claim 1 , wherein the barrier modulation layer comprises a material having a sum of an electron affinity and a band gap of 8 eV or less.

3. The semiconductor device according to claim 2, wherein the barrier modulation layer comprises at least one of TiO2, Ta2O5, SrTiO3 or ZnO. 4 . The semiconductor device according to claim 1 , wherein the barrier modulation layer has a thickness of 0.1 nm to 5 nm. The semiconductor device according to claim 1 , wherein the barrier modulation layer further comprises metal nanocrystals. 6 . The semiconductor device according to claim 1 , wherein the tunnel barrier layer comprises at least one of silicon oxide or aluminum oxide. 7 . The semiconductor device according to claim 1 , wherein the charge trap layer comprises silicon nitride.

8. A semiconductor device comprising: Channel layer; a ferroelectric layer on the channel layer; a barrier modulation layer on the ferroelectric layer; a tunnel barrier layer on the barrier modulation layer and comprising at least one of silicon oxide or aluminum oxide; as well as a gate electrode on the tunnel barrier layer, The barrier modulation layer is configured to have a higher electron affinity than the tunnel barrier layer and the ferroelectric layer, and a lower band gap than the tunnel barrier layer and the ferroelectric layer. 9 . The semiconductor device according to claim 8 , wherein the barrier modulation layer comprises a material having a sum of an electron affinity and a band gap of 8 eV or less. 10 . The semiconductor device according to claim 9 , wherein the barrier modulation layer comprises at least one of TiO 2 , Ta 2 O 5 , SrTiO 3 or ZnO. 11 . The semiconductor device according to claim 8 , wherein the barrier modulation layer has a thickness of 0.1 nm to 5 nm. 12 . The semiconductor device according to claim 8 , wherein the barrier modulation layer further comprises metal nanocrystals.

13. The semiconductor device according to claim 8, further comprising: A charge trapping layer is provided on the ferroelectric layer, wherein the charge trapping layer comprises silicon nitride.

14. A storage device comprising: Multiple cell columns, Each of the plurality of unit columns comprises: a channel layer extending perpendicular to the substrate; a ferroelectric layer on the channel layer; a charge trapping layer on the ferroelectric layer; a barrier modulation layer on the charge trapping layer; A tunnel barrier layer on the barrier modulation layer; and a plurality of gate electrodes on the tunnel barrier layer, and The barrier modulation layer is configured to have a higher electron affinity than the tunnel barrier layer and the charge trapping layer, and a lower band gap than the tunnel barrier layer and the charge trapping layer. 15 . The memory device of claim 14 , wherein the plurality of gate electrodes are stacked perpendicular to the substrate. 16 . The memory device according to claim 14 , wherein the barrier modulation layer comprises a material having a sum of an electron affinity and a band gap of 8 eV or less. 17 . The memory device of claim 16 , wherein the barrier modulation layer comprises at least one of TiO 2 , Ta 2 O 5 , SrTiO 3 , or ZnO.

18. The memory device of claim 14, wherein the barrier modulation layer further comprises metal nanocrystals. 19 . The memory device of claim 14 , wherein the tunnel barrier layer comprises at least one of silicon oxide or aluminum oxide.

20. The memory device of claim 14, wherein the charge trap layer comprises silicon nitride.

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