Semiconductor device

Abstract

The invention provides a semiconductor device, which comprises a semiconductor layer and a trench gate, and is characterized in that the semiconductor layer comprises a buried layer, and the buried layer is located in the semiconductor layer at the bottom of the trench gate and is adjacent to the bottom of the trench gate; the second source region is located in the buried layer, the upper surface of the second source region is adjacent to the bottom of the trench gate, and the lower surface is adjacent to the buried layer; the second body contact region is located in the buried layer, the upper surface of the second body contact region is adjacent to the bottom of the groove, the side wall is adjacent to the side wall of the second source region, and the lower surface is adjacent to the buried layer; wherein the trench gate comprises a first part and a second part, and current channels are respectively formed at the bottoms of the first part and the second part. According to the semiconductor device, the buried layer with the transverse size smaller than the transverse size of the groove is formed at the bottom of the wide groove, and then the channel is formed in the buried layer, so that the on-resistance of the semiconductor device is reduced through the channel density.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and more particularly, to a semiconductor device with a trench gate structure. Background Art

[0002] In power semiconductor devices, the electric field of a vertical transistor with a trench gate is concentrated at the corners at the bottom of the trench gate, resulting in poor breakdown voltage and reliability. In order to effectively disperse the electric field concentrated at the corners at the bottom of the trench gate, the industry has adopted many methods. Among them, a relatively traditional method is to form a buried layer under the bottom of the trench gate to protect the bottom of the trench gate.

[0003] However, in order to better protect the bottom of the trench gate, the lateral dimension of the buried layer needs to be larger than the lateral dimension of the trench gate. And a wider buried layer will hinder the current flow direction, thereby leading to an increase in the on-resistance. Summary of the Invention

[0004] In view of the above problems, the purpose of the present application is to provide a semiconductor device. By forming a buried layer with a lateral dimension smaller than the lateral dimension of the trench at the bottom of the wide trench, and then forming a channel in the buried layer, the on-resistance of the semiconductor device is reduced through the channel density.

[0005] According to an aspect of an embodiment of the present application, a semiconductor device is provided, including a semiconductor layer and a trench gate. The semiconductor layer has opposite first and second surfaces. The trench gate is located in a trench extending from the first surface to the second surface in the semiconductor layer. The semiconductor layer includes: a buried layer, which is located in the semiconductor layer at the bottom of the trench gate and is adjacent to the bottom of the trench gate; a second source region, which is located in the buried layer. The upper surface of the second source region is adjacent to the bottom of the trench gate, and the lower surface is adjacent to the buried layer; a second body contact region, which is located in the buried layer and separates the second source region into two parts. The upper surface of the second body contact region is adjacent to the bottom of the trench, the side wall is adjacent to the side wall of the second source region, and the lower surface is adjacent to the buried layer. Wherein, the trench gate includes a first part and a second part. The two parts of the second source region are respectively adjacent to the bottoms of the first part and the second part, and current channels are respectively formed at the bottoms of the first part and the second part.

[0006] Optionally, the upper surfaces of the second body contact region and the second source region extend to the same depth from the first surface to the second surface of the semiconductor layer, and the lower surfaces of the second body contact region and the second source region extend to the same depth from the first surface to the second surface of the semiconductor layer.

[0007] Optionally, the lateral dimension of the buried layer is smaller than the lateral dimension of the trench.

[0008] Optionally, it further includes: a doped region, located in the semiconductor layers on both sides of the trench, separated from the trench gate and the buried layer.

[0009] Optionally, the depth of the lower surface of the buried layer in the semiconductor layer from the first surface to the second surface is less than or equal to the depth of the lower surface of the doped region in the semiconductor layer from the first surface to the second surface.

[0010] Optionally, the depth of the lower surface of the buried layer extending from the bottom of the trench to the second surface of the semiconductor layer is greater than the depth of the lower surfaces of the second body contact region and the second source region extending from the bottom of the trench to the second surface of the semiconductor layer.

[0011] Optionally, the first part of the trench gate includes a first gate dielectric layer and a first gate conductor, the first gate dielectric layer surrounding the first gate conductor and separating the first gate conductor from the semiconductor layer; the second part of the trench gate includes a second gate dielectric layer and a second gate conductor, the second gate dielectric layer surrounding the second gate conductor and separating the second gate conductor from the semiconductor layer.

[0012] Optionally, there is a gap between the first part and the second part of the trench gate, and the gap exposes a part of the bottom surface of the trench.

[0013] Optionally, the lateral dimension of the gap is greater than the lateral dimension of the second body contact region.

[0014] Optionally, it further includes: an interlayer dielectric layer, located on the first surface of the semiconductor layer, covering the upper surface of the trench gate but exposing the gap; a first conductive layer, located on the first surface of the semiconductor layer, on the interlayer dielectric layer and in the gap, the first conductive layer being adjacent to the upper surfaces of the first body contact region, the second body contact, at least part of the first source region and at least part of the second source region; a second conductive layer, located on the second surface of the semiconductor layer.

[0015] Optionally, the semiconductor layer further includes: a body region, adjacent to the sidewall of the trench gate; a first source region, adjacent to the sidewall of the trench gate, the first source region extending from the first surface of the semiconductor layer towards the body region and being adjacent to a part of the upper surface of the body region; a first body contact region, adjacent to the sidewall of the first source region, extending from the first surface of the semiconductor layer towards the body region and being adjacent to a part of the upper surface of the body region; an epitaxial layer, at least part of the epitaxial layer being located between the body region and the second surface of the semiconductor layer and being connected and adjacent to the buried layer, the doped region and the body region, the epitaxial layer separating the doped region from the trench gate and separating the doped region from the buried layer.

[0016] The technical solution of the present application has the following beneficial effects:

[0017] For the semiconductor device provided by the present application, a buried layer is formed at the bottom of the trench. A second source region and a second body contact region are formed in the buried layer. The trench gate has a first part and a second part. A first conductive layer separates the first part and the second part of the trench gate. At the same time, the first conductive layer is adjacent to at least part of the surfaces of the second body contact region and the second source region at the bottom of the trench, so that channels can be formed at both the bottom and the side walls of the trench of the semiconductor device provided by the present application, increasing the number of channels in a cell, and further reducing the on-resistance of the device.

[0018] For the semiconductor device provided by the present application, the depths of the upper surfaces of the second body contact region and the second source region extending from the first surface to the second surface of the semiconductor layer are the same, and the depths of the lower surfaces of the second body contact region and the second source region extending from the first surface to the second surface of the semiconductor layer are the same. Therefore, the first conductive layer adjacent to at least part of the upper surfaces of the second body contact region and the second source region will not cause a short circuit with the buried layer, resulting in the failure of the horizontal channel, thereby improving the yield of the semiconductor device.

[0019] For the semiconductor device provided by the present application, the lateral dimension of the buried layer is smaller than the lateral dimension of the trench. On the one hand, the buried layer can adjust the electric field at the bottom corner of the trench. On the other hand, the buried layer will not shield the bottom corner of the trench, reducing the on-resistance of the current channel of the semiconductor device.

[0020] For the semiconductor device provided by the present application, a doped region is further formed in the semiconductor layer below the body regions on both sides of the trench. The depth of the bottom of the doped region extending from the first surface to the second surface in the semiconductor layer is approximately the same as the depth of the bottom of the buried layer extending from the first surface to the second surface in the semiconductor layer. Therefore, the doped region can adjust the electric field at the bottom corner of the trench, thereby improving the problem of electric field concentration at the corner of the trench gate and increasing the breakdown voltage capacity at the corner of the trench gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present application and do not limit the present application.

[0022] Figure 1 Shows a three-dimensional structural schematic diagram of the semiconductor device according to the embodiment of the present application;

[0023] Figure 2 Shows a cross-sectional structural schematic diagram of the semiconductor device according to the embodiment of the present application;

[0024] Figure 3The flowchart of the manufacturing method of the semiconductor device according to the embodiment of the present application is shown;

[0025] Figures 4a to 4d The cross-sectional schematic diagrams of each stage in the manufacturing method of the semiconductor device according to the embodiment of the present application are shown. Detailed implementation manners

[0026] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, a semiconductor structure obtained after several steps may be described in one drawing.

[0027] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above" or "over" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the device is flipped, this layer or region will be "below" or "beneath" the other layer or another region.

[0028] If it is for describing the case of being directly above another layer or another region, expressions such as "directly on... above" or "above and adjacent to..." will be used in this article.

[0029] Power devices generally include an active element region, an edge termination region, and a crack-stop or shielding region. The active element region includes an active element array. The present application relates to the active element structure. The sizes of the active elements may vary according to product requirements, and there may be a body region between the active elements in the active element region.

[0030] Many specific details of the present application, such as the structure, materials, sizes, processing techniques, and technologies of the device, are described below in order to understand the present application more clearly. However, as those skilled in the art can understand, the present application may be implemented without these specific details.

[0031] Figure 1 The three-dimensional structure schematic diagram of the semiconductor device according to the embodiment of the present application is shown, Figure 2 The cross-sectional structure schematic diagram of the semiconductor device according to the embodiment of the present application is shown.

[0032] Such as Figure 1 And Figure 2As shown, the semiconductor device of the present application includes a semiconductor layer 100, a plurality of trench gates 150, an interlayer dielectric layer 170, a first conductive layer 181, and a second conductive layer 182. The semiconductor layer 100 has opposite first and second surfaces. The first conductive layer 181 is located on the first surface of the semiconductor layer 100, and the second conductive layer 182 is located on the second surface of the semiconductor layer 100. The semiconductor layer 100 includes a plurality of trenches that extend from the first surface of the semiconductor layer 100 into the semiconductor layer 100 towards the second surface.

[0033] Among them, the semiconductor layer is, for example, SiC, GaN, Ga 2 O 3 , Al 2 O 3 substrate or a stacked structure composed of a substrate and an epitaxial layer. However, the embodiments of the present application are not limited thereto, and those skilled in the art can make other settings for the material and number of layers of the semiconductor layer according to needs, such as other wide-bandgap semiconductor materials, etc.

[0034] In the present application, the semiconductor layer 100 includes, for example, a substrate 110, an epitaxial layer 120, a body region 131, a first source region 141, a first body contact region 132, a doped region 161, a buried layer 162, a second source region 142, and a second body contact region 133.

[0035] Specifically, the epitaxial layer 120 is located above the substrate 110. The trench extends from the first surface of the semiconductor layer 100 to the second surface into the epitaxial layer 120. A plurality of trench gates 150 are located in the corresponding trenches in the semiconductor layer 100. The first source region 141 is located on both sides of the trench gate 150 and extends from the first surface of the semiconductor layer 100 to the second surface. The first source region 141 is adjacent to the sidewall of the trench gate 150; the body region 131 is adjacent to the lower surface of the first source region 141 and the sidewall of the trench gate 150, and at least part of the epitaxial layer 120 is located between the body region 131 and the second surface of the semiconductor layer 100; the first body contact region 132 is located on the side of the first source region 141 away from the trench gate 150, and the sidewall of the first body contact region 132 is adjacent to the first source region 141, and the lower surface is adjacent to the upper surface of the body region 131. Optionally, the first source region 141 and the first body contact region 132 may be adjacent or separated by the body region 131; the doped region 161 is located below the body region 131, and the upper surface of the doped region 161 is adjacent to the lower surface of the body region 131, and the lateral dimension of the doped region 161 is smaller than the lateral dimension of the body region 131. The doped region 161 is not adjacent to the trench gate 150, and at least part of the epitaxial layer 120 is located between the doped region 161 and the trench gate 150; the buried layer 162 is located below the trench gate 150, and the upper surface of the buried layer 162 is adjacent to the lower surface of the trench gate 150. The lateral dimension of the buried layer 162 is smaller than the lateral dimension of the trench gate 150, and the bottom corner of the trench gate 150 is not surrounded by the buried layer 162; the second source region 142 is located in the buried layer 162, and the upper surface of the second source region 142 is adjacent to the bottom of the trench gate 150. In the lateral direction, the buried layer 162 separates the second source region 142 and the epitaxial layer 120; the second body contact region 133 is located in the buried layer 162 and is located in the middle region of the second source region 142, separating the second source region 142 into two parts.

[0036] Specifically, as Figure 2 shown, the second source region 142 is separated into left and right parts by the second body contact region 133, and the left part of the second source region 142 is adjacent to the bottom of the second part of the trench gate 150. Thus, the left part of the second source region 142, the buried layer 162, and the epitaxial layer 120 form a current path, that is, a channel is formed at the bottom of the second part of the trench gate 150; similarly, the right part of the second source region 142 is adjacent to the bottom of the first part of the trench gate 150. Thus, the right part of the second source region 142, the buried layer 162, and the epitaxial layer 120 form a current path, that is, a channel is formed at the bottom of the first part of the trench gate 150. Therefore, current channels are respectively formed at the bottoms of the first part and the second part of the trench gate 150 to increase the number of current channels in the cell.

[0037] Among them, the upper surfaces of part of the buried layer 162, the upper surface of the second source region 142, and the upper surface of the second body contact region 133 are all adjacent to the bottom of the trench gate 150. The depths to which the upper surfaces of the second body contact region 133 and the second source region 142 extend from the first surface to the second surface of the semiconductor layer 100 are the same, and the depths to which the lower surfaces of the second body contact region 133 and the second source region 142 extend from the first surface to the second surface of the semiconductor layer 100 are the same. The depth to which the lower surface of the buried layer 162 extends from the bottom of the trench to the second surface of the semiconductor layer 100 is greater than the depth to which the lower surfaces of the second body contact region 133 and the second source region 142 extend from the bottom of the trench to the second surface of the semiconductor layer 100, such that the buried layer 162 covers the second source region 142 and the second body contact region 133.

[0038] The trench gate 150 located in the same trench includes two parts, namely the first part (such as Figure 2 the right part in Figure 2 ), and the second part (such as

[0039] the left part in

[0040] ), and the first part and the second part are separated by a certain distance in the trench to form a gap. The first part includes the first gate dielectric layer 152 and the first gate conductor 151, and the second part includes the second gate dielectric layer 154 and the second gate conductor 153. The first gate dielectric layer 152 and the second gate dielectric layer 154 respectively cover part of the inner surface of the trench, but the first gate dielectric layer 152 and the second gate dielectric layer 154 are not connected, so that part of the bottom surface of the trench is exposed in the gap. The first gate conductor 151 and the second gate conductor 153 are located in the trench and are respectively surrounded by the first gate dielectric layer 152 and the second gate dielectric layer 154, so that the gate dielectric layer separates the gate conductor from the semiconductor layer 100. Among them, the lateral dimension of the second body contact region 133 is smaller than the lateral dimension of the gap between the first gate dielectric layer 152 and the second gate dielectric layer 154. Figure 1As shown, the trench gate 150 extends in a first direction, that is, the length direction of the trench gate 150 is the first direction, for example, the Y-axis direction; the width direction is the second direction, for example, the X-axis direction; the depth direction is the third direction, for example, the Z-axis direction. Optionally, the first direction, the second direction, and the third direction are perpendicular to each other in pairs. Figure 2 That is, along Figure 1 The cross-section of the semiconductor structure is obtained by the plane where the second direction and the third direction are located in Figure 2 , and the aforementioned lateral dimension is also the dimension along the second direction.

[0041] The trench gate 150, the buried layer 162, the first source region 141, the second source region 142, the body region 131, the first body contact region 132, the second body contact region 133, and the doped region 161 all extend in the first direction.

[0042] In this embodiment, the depth of the bottom surface of the doped region 161 from the first surface to the second surface of the semiconductor layer 100 is greater than the depth of the bottom of the trench gate 150 from the first surface to the second surface of the semiconductor layer 100. The depth of the bottom surface of the buried layer 142 from the first surface to the second surface of the semiconductor layer 100 is greater than the depth of the bottom of the trench gate 150 from the first surface to the second surface of the semiconductor layer 100 and less than or equal to the depth of the bottom surface of the doped region 141 from the first surface to the second surface of the semiconductor layer 100. The depth of the bottom surface of the second source region 142 extending from the bottom of the trench to the second surface of the semiconductor layer 100 is less than the depth of the bottom surface of the buried layer 162 extending from the bottom of the trench to the second surface of the semiconductor layer 100 and is equal to the depth of the bottom surface of the second body contact region 133 extending from the bottom of the trench to the second surface of the semiconductor layer 100.

[0043] The interlayer dielectric layer 170 is located on the first surface of the semiconductor layer 100 and covers the upper surface of the trench gate 150. Corresponding to the trench gate 150 including two parts, the interlayer dielectric layer 170 also includes two parts, respectively covering the upper surfaces of the first part and the second part of the trench gate 150, and the gap between the first part and the second part of the trench gate 150 is not filled with the interlayer dielectric layer. The first conductive layer 181 serves as the source electrode, covering the first surface of the semiconductor layer 100 and the interlayer dielectric layer 170, and at the same time filling the gap between the two parts of the trench gate 150, so that the first conductive layer 181 is adjacent to at least a part of the upper surface of the first source region 141, and is adjacent to a part of the upper surface of the second source region 142 and the upper surface of the second body contact region 133.

[0044] The substrate 110 serves as the drain region, and the second conductive layer 182 serves as the drain electrode, and the second conductive layer 182 covers the lower surface of the substrate 110.

[0045] In this embodiment, along the second direction, a plurality of trench gates 150 are arranged at intervals, and the body region 131 and the first source region 141 are located between adjacent trench gates 150.

[0046] In this embodiment, the first source region 141, the second source region 142, the epitaxial layer 120, and the substrate 110 are of the first conduction type, the buried layer 162, the doped region 161, the body region 131, the first body contact region 132, and the second body contact region 133 are of the second conduction type, and the doping concentration of the first body contact region 132 is greater than that of the body region 131. The first conduction type is opposite to the second conduction type. The first conduction type is one of P-type and N-type, and the second conduction type is the other of P-type and N-type.

[0047] The semiconductor device of this embodiment can be used as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), or can be used as an Insulated Gate Bipolar Transistor (IGBT). For example, a drain contact region is provided on the second surface of the semiconductor layer, and the conduction type of the drain contact region is correspondingly set to the first conduction type or the second conduction type. However, the embodiments of the present application are not limited thereto, and those skilled in the art can make other settings for the conduction types of the regions in the semiconductor layer according to needs so as to use the semiconductor device as a MOSFET or an IGBT.

[0048] In this embodiment, when the device is turned on, the part of the body region 131 adjacent to the sidewall of the trench gate 150 and the part of the buried layer 162 adjacent to the sidewall of the trench gate 150 are inverted to form a channel. Carriers flow in from the second conductive layer 182, and then flow through the epitaxial layer 120, the channel to the first source region 141 and the second source region 142, and finally flow out from the first conductive layer 181, as Figure 2 shown by the dotted line with arrows in the figure (the current direction can also be opposite to the direction shown by the dotted line with arrows in the figure). Therefore, in the semiconductor device of the present application, a cell has double the number of channels, which can reduce the on-resistance of the device.

[0049] In the semiconductor device provided by the present application, a buried layer is formed at the bottom of the trench, and the lateral dimension of the buried layer is smaller than the lateral dimension of the trench. A second source region and a second body contact region are formed in the buried layer. At the same time, the trench also has a first trench gate and a second trench gate. The first conductive layer separates the first trench gate and the second trench gate, and is adjacent to at least part of the surfaces of the second body contact region and the second source region at the bottom of the trench, so that a channel can also be formed at the bottom of the trench of the semiconductor device of the present application, increasing the number of trenches in a cell, and further reducing the on-resistance of the device.

[0050] In the semiconductor device provided by the present application, doping regions are further formed in the semiconductor layer below the body regions on both sides of the trench. The depth of the bottom of the doping region extending from the first surface to the second surface in the semiconductor layer is approximately the same as the depth of the bottom of the buried layer extending from the first surface to the second surface in the semiconductor layer. Therefore, the doping regions can adjust the electric field at the bottom corner of the trench, thereby further improving the problem of electric field concentration at the corner of the trench gate and increasing the breakdown voltage capability at the corner of the trench gate.

[0051] Figure 3 The flowchart of the manufacturing method of the semiconductor device according to the embodiment of the present application is shown; Figures 4a to 4d The cross-sectional schematic diagrams of each stage in the manufacturing method of the semiconductor device according to the embodiment of the present application are shown. The following will be combined with Figures 2 to 4d to describe in detail the manufacturing method of the semiconductor device of the present application.

[0052] Step S201: An epitaxial layer is formed on the substrate by an epitaxial process, and a doping region, a body region, a first source region, and a first body contact region are sequentially formed in the epitaxial layer by an ion implantation process.

[0053] In this step, an epitaxial layer 120 is formed on the substrate 110 by an epitaxial process. The thickness of the epitaxial layer 120 is greater than the thickness of the substrate 110. Since the epitaxial layer 120 is formed by an epitaxial process, the epitaxial layer 120 has the same lattice orientation as the substrate 110.

[0054] Among them, the epitaxial layer 120 and the substrate 110 constitute the semiconductor layer 100.

[0055] Furthermore, a doping region 161, a body region 131, a first source region 141, and a first body contact region 132 are sequentially formed in the epitaxial layer 120 by an ion implantation process, as Figure 4a shown. Specifically, since the depth of the doping region 161 in the epitaxial layer 120 is greater than the depth of the body region 131 in the epitaxial layer 120, the energy of ion implantation when forming the doping region 161 is greater than the energy of ion implantation when forming the body region 131. In addition, the doping types of the first source region 141 and the first body contact region 132 are different, so they cannot be formed simultaneously.

[0056] The body region 131, the first body contact region 132, and the doping region 161 have the same doping type, but their extension depths in the semiconductor layer 100 are different. Therefore, they can be formed by ion implantation through different mask patterns.

[0057] Step S202: A mask layer is formed on the first surface of the semiconductor layer, and a trench is formed in the semiconductor layer through the mask layer.

[0058] In this step, a photoetching resist layer is formed on the first surface of the semiconductor layer 100, and then the photoetching resist layer is patterned through the processes of exposure and development, so as to form a mask layer 101. Among them, the mask layer 101 has grooves, and the grooves are located in the mask layer corresponding to the semiconductor layer 100 between adjacent doping regions 161 and are used to form trenches, as Figure 4b shown.

[0059] Further, an etching process is adopted, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching and other processes, to form trenches 102 in the semiconductor layer 100 via the mask layer 101, as Figure 4b shown.

[0060] The trench 102 penetrates through the first source region 141 and the body region 131 and extends into the epitaxial layer 120 below the body region 131, and the part of the first trench 103 located in the epitaxial layer 12 is located between adjacent doping regions 141, and the doping region 161 is separated from the trench 102 by the epitaxial layer 120.

[0061] In this embodiment, the trench 102 is, for example, a wide trench, and the lateral dimension of the trench 102 is, for example, greater than or equal to 1 μm.

[0062] Step S203: Form a shielding layer on the sidewalls in the trench, and form a buried layer, a second source region, and a second body contact region at the bottom of the trench.

[0063] In this step, first, a deposition process is adopted, such as physical vapor deposition, chemical vapor deposition and other processes, to deposit a shielding layer 103 on the surface of the mask layer 101, the sidewalls and the bottom in the trench 102. Among them, the part of the shielding layer 103 located in the trench 102 covers the sidewalls and the bottom of the trench 102.

[0064] Further, the shielding layer 103 on the surface of the mask layer 101 and the shielding layer 103 at the bottom of the trench 102 are removed, so that the remaining shielding layer 103 only covers the sidewalls of the trench 102 while exposing the bottom of the trench 102, as Figure 4c shown.

[0065] In this embodiment, the material of the shielding layer 103 includes polysilicon, nitride, oxide, etc. The shielding layer 103 serves as a mask layer during the implantation process to prevent unnecessary doping regions from being formed in the semiconductor layer 100 on the sidewalls of the trench.

[0066] Further, an ion implantation process is adopted to perform ion implantation into the semiconductor layer 100 through the bottom of the trench 102, so as to form a buried layer 162, a second source region 142, and a second body contact region 133, as Figure 4cAs shown in the figure. Among them, the buried layer 162 covers the second source region 142 and the second body contact region 133.

[0067] Since the shielding layer 103 forms a trench 102 with a smaller lateral dimension, the lateral dimension of the buried layer 162 formed by ion implantation through the trench 102 is smaller than the lateral dimension of the trench 102. Therefore, the lateral dimension of the buried layer 162 can be adjusted by adjusting the thickness of the shielding layer 103 on the sidewall of the trench 102.

[0068] In addition, when forming the second source region 142, the shielding layer can be deposited again in the trench 102. After further adjusting the lateral dimension of the bottom exposed by the trench 102, ion implantation can be performed to obtain the second source region 142 with a lateral dimension smaller than that of the buried layer 162. Similarly, for the second body contact region 133, the shielding layer can be deposited again on the basis of the shielding layer for forming the second source region 142 to adjust the lateral dimension and position of the second body contact region 133.

[0069] Among them, during the process of ion implantation through the bottom of the trench 102 to form the buried layer 162, the second source region 142 and the second body contact region 133, since the buried layer 162, the second source region 142 and the second body contact region 133 are located in the semiconductor layer 100 at the bottom of the trench 102, their positions can be accurately controlled.

[0070] For the buried layer 162 formed in this step, the depth of its bottom surface from the first surface to the second surface of the semiconductor layer 100 is greater than the depth of the bottom of the trench gate 150 from the first surface to the second surface of the semiconductor layer 100, and less than or equal to the depth of the bottom surface of the doped region 161 from the first surface to the second surface of the semiconductor layer 100. The depth of the bottoms of the second source region 142 and the second body contact region 133 from the bottom of the trench 102 to the second surface of the semiconductor layer 100 is less than the depth of the bottom of the buried layer 162 from the bottom of the trench 102 to the second surface of the semiconductor layer 100.

[0071] Step S204: Form a trench gate in the trench, and form an interlayer dielectric layer, a first conductive layer, and a second conductive layer.

[0072] In this step, first remove the shielding layer 103 and the mask layer 101, as Figure 4d shown, then sequentially form a gate dielectric layer 151 and a gate conductor 152 in the trench 102. Further, an etching process is used to etch a first through hole in the gate conductor to divide the gate conductor into two parts. Then, a dielectric layer is deposited in the first through hole. Then, an etching process is used again to form a second through hole in the dielectric layer in the first through hole. The lateral dimension of the second through hole is smaller than that of the first through hole, and the sidewall of the second through hole exposes the dielectric layer, and the bottom surface exposes the bottom of the trench 102, thereby forming as Figure 2The grooved gate 150 shown, which includes two parts.

[0073] As Figure 2 shown, the formed grooved gate 150 includes two parts, namely the first part (such as the right part in Figure 2 ) and the second part (such as the left part in Figure 2 ). The first part and the second part are separated by a certain distance in the groove to form a gap. The first part includes the first gate dielectric layer 152 and the first gate conductor 151, and the second part includes the second gate dielectric layer 154 and the second gate conductor 153. The first gate dielectric layer 152 and the second gate dielectric layer 154 respectively cover part of the inner surface of the groove, but the first gate dielectric layer 152 and the second gate dielectric layer 154 are not connected, so that part of the bottom surface of the groove is exposed in the gap. The first gate conductor 151 and the second gate conductor 153 are located in the groove and are respectively surrounded by the first gate dielectric layer 152 and the second gate dielectric layer 154, so that the gate dielectric layer separates the gate conductor from the semiconductor layer 100. Among them, the lateral dimension of the second body contact region 133 is smaller than the lateral dimension of the gap between the first gate dielectric layer 152 and the second gate dielectric layer 154.

[0074] Among them, in the step of depositing and filling the dielectric layer of the first through hole, the dielectric layer has a certain thickness on the first surface of the semiconductor layer 100. In the step of etching to form the second through hole, part of the dielectric layer on the first surface of the semiconductor layer 100 is also etched, so as to form the interlayer dielectric layer 170.

[0075] Furthermore, a first conductive layer 181 is formed on the first surface of the semiconductor layer 100 and a second conductive layer 182 is formed on the second surface of the semiconductor layer 100, as Figure 2 shown.

[0076] Among them, the first conductive layer 181 fills the second through hole that separates the grooved gate 150 and is adjacent to at least part of the upper surface of the second source region 142 and the second body contact region 133, and the second conductive layer 181 covers the first surface of the semiconductor layer 100 and the upper surface of the interlayer dielectric layer 170 and is adjacent to at least part of the upper surface of the first source region 141 and the first body contact region 132.

[0077] For the semiconductor device provided in this application, a buried layer is formed at the bottom of the groove. A second source region and a second body contact region are formed in the buried layer. The grooved gate has a first part and a second part. The first conductive layer separates the first part and the second part of the grooved gate. At the same time, the first conductive layer is adjacent to at least part of the surfaces of the second body contact region and the second source region at the bottom of the groove, so that channels can be formed on both the bottom and the side walls of the groove in the semiconductor device of this application, increasing the number of channels in a cell, and thus reducing the on-resistance of the device.

[0078] In the semiconductor device provided by the present application, the depths of the upper surfaces of the second body contact region and the second source region extending from the first surface to the second surface of the semiconductor layer are the same, and the depths of the lower surfaces of the second body contact region and the second source region extending from the first surface to the second surface of the semiconductor layer are the same. As a result, the first conductive layer adjacent to at least part of the upper surfaces of the second body contact region and the second source region will not cause a short circuit with the buried layer, leading to the failure of the horizontal channel, thereby improving the yield of the semiconductor device.

[0079] In the semiconductor device provided by the present application, the lateral dimension of the buried layer is smaller than the lateral dimension of the trench. On the one hand, the buried layer can adjust the electric field at the bottom corner of the trench. On the other hand, the buried layer will not shield the bottom corner of the trench, reducing the on-resistance of the current channel of the semiconductor device.

[0080] In the semiconductor device provided by the present application, doping regions are further formed in the semiconductor layer below the body regions on both sides of the trench. The depth of the bottom of the doping region extending from the first surface to the second surface in the semiconductor layer is approximately the same as the depth of the bottom of the buried layer extending from the first surface to the second surface in the semiconductor layer. Therefore, the doping regions can adjust the electric field at the bottom corner of the trench, further improving the problem of electric field concentration at the trench gate corner and increasing the breakdown voltage capacity at the corner of the trench gate.

[0081] The embodiments of the present application have been described above. However, these embodiments are only for illustrative purposes and not for limiting the scope of the present application. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A semiconductor device, comprising a semiconductor layer and a trench gate, wherein the semiconductor layer has a first surface and a second surface opposite to each other, the trench gate is located in a trench extending from the first surface to the second surface of the semiconductor layer, and the semiconductor layer comprises: A buried layer, the buried layer is located in the semiconductor layer at the bottom of the trench gate and is adjacent to the bottom of the trench gate; A second source region is located in the buried layer, wherein the upper surface of the second source region is adjacent to the bottom of the trench gate, and the lower surface of the second source region is adjacent to the buried layer; a second body contact region, located in the buried layer, dividing the second source region into two parts, wherein the second body contact region has an upper surface adjacent to the bottom of the trench, a side wall adjacent to the side wall of the second source region, and a lower surface adjacent to the buried layer; The trench gate includes a first part and a second part, two parts of the second source region are adjacent to the bottom of the first part and the second part respectively, and the bottoms of the first part and the second part respectively form current channels.

2. The semiconductor device according to claim 1, wherein The upper surfaces of the second body contact region and the second source region extend to the same depth from the first surface to the second surface of the semiconductor layer, and the lower surfaces of the second body contact region and the second source region extend to the same depth from the first surface to the second surface of the semiconductor layer.

3. The semiconductor device according to claim 1, wherein The lateral dimension of the buried layer is smaller than the lateral dimension of the trench.

4. The semiconductor device according to claim 1, wherein: Also includes: The doped region is located in the semiconductor layer on both sides of the trench and is separated from the trench gate and the buried layer.

5. The semiconductor device according to claim 4, wherein: A depth of a lower surface of the buried layer from the first surface to the second surface in the semiconductor layer is less than or equal to a depth of a lower surface of the doped region from the first surface to the second surface in the semiconductor layer.

6. The semiconductor device according to claim 1, wherein The depth at which the lower surface of the buried layer extends from the bottom of the trench to the second surface of the semiconductor layer is greater than the depth at which the lower surfaces of the second body contact region and the second source region extend from the bottom of the trench to the second surface of the semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The first portion of the trench gate includes a first gate dielectric layer and a first gate conductor, wherein the first gate dielectric layer surrounds the first gate conductor and separates the first gate conductor from the semiconductor layer; The second portion of the trench gate includes a second gate dielectric layer and a second gate conductor, wherein the second gate dielectric layer surrounds the second gate conductor and separates the second gate conductor from the semiconductor layer.

8. The semiconductor device according to claim 7, wherein: A gap is formed between the first portion and the second portion of the trench gate, and the gap exposes a portion of the bottom surface of the trench.

9. The semiconductor device according to claim 8, wherein: A lateral dimension of the gap is greater than a lateral dimension of the second body contact region.

10. The semiconductor device according to claim 8, wherein Also includes: an interlayer dielectric layer, located on the first surface of the semiconductor layer, covering the upper surface of the trench gate but exposing the gap; A first conductive layer, located on the first surface of the semiconductor layer, on the interlayer dielectric layer and in the gap, the first conductive layer being adjacent to the upper surfaces of the first body contact region, the second body contact region, at least a portion of the first source region and at least a portion of the second source region; The second conductive layer is located on the second surface of the semiconductor layer.

11. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor layer further comprises: a body region adjacent to a sidewall of the trench gate; A first source region, adjacent to a sidewall of the trench gate, the first source region extending from the first surface of the semiconductor layer toward the body region and adjacent to a portion of an upper surface of the body region; A first body contact region, adjacent to a side wall of the first source region, extending from the first surface of the semiconductor layer toward the body region, and adjacent to a portion of an upper surface of the body region; An epitaxial layer, at least part of which is located between the body region and the second surface of the semiconductor layer, and is connected and adjacent to the buried layer, the doped region and the body region, and the epitaxial layer separates the doped region and the trench gate and separates the doped region and the buried layer.

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