Trench gate silicon carbide power device and preparation method thereof, chip
By employing a cross-shaped trench gate and a P-type deep well shielding structure in SiC trench MOSFETs, the problem of electrical performance degradation of SiC trench MOSFETs under high breakdown field strength is solved, achieving high current density and improved reliability, while reducing on-resistance and reverse bias cutoff current.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN SIRIUS SEMICON CO LTD
- Filing Date
- 2026-01-16
- Publication Date
- 2026-05-15
AI Technical Summary
Existing SiC trench MOSFET devices are prone to electrical performance degradation and gate oxide failure under high breakdown field strength, leading to reliability issues. At the same time, the on-resistance increases, making it difficult to achieve a trade-off between trench gate reliability and on-resistance.
A cross-shaped trench gate structure is adopted, and a double-layer structure of P-type deep well and P-type heavily doped region is set in the trench gate intersection area. Combined with N-type heavily doped region, the electric field peak is reduced and the device depletion region is optimized through high channel density and deep well shielding region.
It significantly improves the current density and reliability of SiC trench gate, reduces the reverse bias cutoff current (IDSS) of the device, improves the reliability and switching frequency of the device, and optimizes the short-circuit characteristics.
Smart Images
Figure CN121568421B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power device technology, and in particular relates to a trench gate silicon carbide power device and its fabrication method and chip. Background Technology
[0002] Silicon carbide (SiC), as a third-generation semiconductor material, is widely used in electric vehicles, charging piles, and data electronics due to its advantages such as wide bandgap, high critical breakdown electric field, and high saturation drift velocity. Compared to SiC planar MOSFETs, SiC trench MOSFETs have higher current and power densities, lower on-resistance, higher switching speeds, and better thermal performance. However, due to the high breakdown field strength of SiC material and gate oxide interface defects, the gate corners of SiC trenches need to withstand ultra-high electric fields, which may lead to electrical performance degradation and gate oxide failure, posing a challenge to device reliability.
[0003] Existing technologies can effectively reduce the electric field strength at the corner of SiC trench gate and optimize reliability, but they often bring the side effect of increased on-resistance. Therefore, there is an urgent need for a technical solution that can improve the trade-off between trench gate reliability and on-resistance. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides a trench-gate silicon carbide power device, its fabrication method, and a chip, aiming to improve the current density of the trench-gate silicon carbide power device and enhance its reliability.
[0005] The first aspect of this application provides a trench-gate silicon carbide power device, the trench-gate silicon carbide power device comprising:
[0006] A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate;
[0007] The interlayer dielectric layer and the trench gate and gate dielectric layer formed in the N-type drift region, wherein the trench gate has a cross-shaped structure and is wrapped by the gate dielectric layer and the interlayer dielectric layer;
[0008] A P-type deep well is formed in the intersection region of the trench gate and extends into the central region of the N-type drift region;
[0009] A heavily doped P-type region formed on and in contact with the P-type deep well;
[0010] Multiple P-type well regions are formed on the N-type drift region and N-type heavily doped regions are located on the P-type well regions; adjacent P-type well regions and adjacent N-type heavily doped regions are isolated by the trench gate; and the P-type well regions and the trench gate are isolated by the gate dielectric layer.
[0011] A first electrode is covered on the interlayer dielectric layer, and the first electrode is electrically connected to the P-type heavily doped region through a contact hole on the interlayer dielectric layer; the contact hole is located above the P-type heavily doped region.
[0012] A second electrode is formed on the back side of the silicon carbide substrate.
[0013] In some embodiments, trench gates are provided around both the P-type deep well and the P-type heavily doped region, and are isolated by a gate dielectric layer.
[0014] The depth of the P-type deep well is greater than the depth of the trench gate, and the depth of the P-type well region is less than the depth of the trench gate.
[0015] In some embodiments, the depth of the P-type heavily doped region is greater than the depth of the trench gate, and a current spreading layer is further provided in a portion of the interface region between the P-type well region and the N-type drift region.
[0016] The P-type deep well is interconnected along the bottom of the P-type heavily doped region and the gate dielectric layer.
[0017] In some embodiments, the P-type well region extends along the outer surface of the gate dielectric layer toward the N-type drift region;
[0018] The P-type deep well includes a vertical deep well region and a horizontal deep well region, and the horizontal deep well region extends below the gate dielectric layer and isolates the gate dielectric layer from the N-type drift region.
[0019] In some embodiments, the first electrode has a convex structure, and the protrusion of the first electrode contacts the N-type drift region through the contact hole in the P-type heavily doped region and the P-type deep well. A Schottky metal layer is also disposed between the protrusion of the first electrode and the N-type drift region.
[0020] In some embodiments, the first electrode has a convex structure, and the protrusion of the first electrode extends into the P-type heavily doped region.
[0021] In some embodiments, the trench gate includes four gates, and adjacent gates are electrically connected to each other through an arched interconnect layer; wherein the included angle between adjacent gates is 90 degrees, the arched interconnect layer is located on the heavily doped P-type region, and is isolated from the heavily doped P-type region by the gate dielectric layer.
[0022] In some embodiments, the silicon carbide substrate is a P-type substrate;
[0023] The second electrode is the collector, and the first electrode is the emitter.
[0024] A second aspect of this application also provides a method for fabricating a trench-gate silicon carbide power device, the method comprising:
[0025] An N-type drift region is sequentially formed on the front side of a silicon carbide substrate, and a P-type well region is formed on the N-type drift region;
[0026] Under the protection of the first hard film, an N-type heavily doped region is formed in a predetermined region of the P-type well region by ion implantation;
[0027] Under the protection of the second hard film, multiple ion implantations are used to form a P-type deep well and a P-type heavily doped region that extend into the N-type drift region; the depth of the P-type well region is less than the depth of the P-type deep well.
[0028] The gate trench is etched deep into the N-type drift region, and after forming a gate dielectric layer, the gate material is filled to form a trench gate; wherein, the trench gate has a cross-shaped structure, and the P-type heavily doped region is located in the intersection region of the cross-shaped structure;
[0029] An interlayer dielectric layer is formed to cover the trench gate and the P-type heavily doped region, so that the trench gate is wrapped by the gate dielectric layer and the interlayer dielectric layer;
[0030] A contact hole is formed by etching along the region above the heavily doped P-type region, and a first electrode is formed covering the gate dielectric layer and contacting the heavily doped P-type region and the heavily doped N-type region, and a second electrode is formed covering the back side of the silicon carbide substrate.
[0031] A third aspect of this application also provides a chip including a trench gate silicon carbide power device as described in any of the above embodiments.
[0032] The beneficial effects of this application embodiment are as follows: By setting a cross-shaped trench gate and setting a double-layer structure of P-type deep well and P-type heavily doped region in the cross intersection area of the trench gate, and N-type heavily doped region on both sides of the trench gate in the first direction, the trench gate in the first direction and the P-type heavily doped region are periodically alternated. In this way, the current density of the device is greatly improved by the higher channel density. This novel structure can also set a deep well as a shielding region at the trench corner to transfer the electric field peak from the trench corner to the bottom of the deep well, so that the depletion region of the device can be closed, reducing the IDSS of the device, improving the BVDSS of the device, and effectively improving the reliability of the device. Attached Figure Description
[0033] Figure 1 This is a schematic diagram of a trench gate silicon carbide power device provided in an embodiment of this application;
[0034] Figure 2This is another schematic diagram of the trench gate silicon carbide power device provided in the embodiments of this application;
[0035] Figure 3 This is another schematic diagram of the trench gate silicon carbide power device provided in the embodiments of this application;
[0036] Figure 4 This is another schematic diagram of the trench gate silicon carbide power device provided in the embodiments of this application;
[0037] Figure 5 This is another schematic diagram of the trench gate silicon carbide power device provided in the embodiments of this application;
[0038] Figure 6 This is another schematic diagram of the trench gate silicon carbide power device provided in the embodiments of this application;
[0039] Figure 7 This is a schematic flowchart of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application;
[0040] Figure 8 This is a partial schematic diagram of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application;
[0041] Figure 9 This is a partial schematic diagram of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application;
[0042] Figure 10a , Figure 10b This is a partial schematic diagram of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application;
[0043] Figure 11 This is a partial schematic diagram of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application;
[0044] Figure 12a , Figure 12b This is a partial schematic diagram of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application;
[0045] Figure 13 This is a partial schematic diagram of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application;
[0046] Figure 14 This is a partial schematic diagram of the fabrication method of the trench gate silicon carbide power device provided in the embodiments of this application. Detailed Implementation
[0047] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0048] To address the aforementioned technical problems, this application provides a trench-gate silicon carbide power device, see [link to relevant documentation]. Figure 1 As shown, Figure 1 The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 1 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 1 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 1 The schematic structure (d) is a combination Figure 1 As shown, the trench gate silicon carbide power device in this embodiment includes: a silicon carbide substrate 210, an N-type drift region 220, a trench gate 320, a gate dielectric layer 310, an interlayer dielectric layer 311, a P-type deep well 410, a P-type heavily doped region 420, a P-type well region 231, an N-type heavily doped region 232, a first electrode 110, and a second electrode 120. The N-type drift region 220 is formed on the front side of the silicon carbide substrate 210. The trench gate 320 and the gate dielectric layer 310 are formed within the N-type drift region 220. The trench gate 320 has a cross-shaped structure and is wrapped by the gate dielectric layer 310.
[0049] A P-type deep well 410 is formed in the intersection region of the trench gate 320 and extends into the central region of the N-type drift region 220. A heavily doped P-type region 420 is formed on and in contact with the P-type deep well 410. A plurality of P-type well regions 231 are formed on the N-type drift region 220, and heavily doped N-type regions 232 are located on the P-type well regions 231. Adjacent P-type well regions 231 and adjacent heavily doped N-type regions 232 are isolated by the trench gate 320; and the P-type well regions 231 and the trench gate 320 are isolated by a gate dielectric layer 310.
[0050] The first electrode 110 covers the interlayer dielectric layer 311, and the trench gate 320 is wrapped by the gate dielectric layer 310 and the interlayer dielectric layer 311. The first electrode 110 is electrically connected to the P-type heavily doped region 420 through a contact hole on the interlayer dielectric layer 311. The contact hole is located above the P-type heavily doped region 420. The second electrode 120 is formed on the back side of the silicon carbide substrate 210.
[0051] In this embodiment, a cross-shaped trench gate 320 is provided. The trench gate 320 includes four branches. Adjacent branches are perpendicular in the horizontal cross section. The four branches of the trench gate 320 are electrically connected to each other in their intersection area. In the cross intersection area of the trench gate 320, a double-layer structure of a P-type deep well 410 and a P-type heavily doped region 420 is provided. The first electrode 110 is electrically connected to the P-type heavily doped region 420 through a contact hole on the interlayer dielectric layer 311. Two branches of the trench gate 320 are opposite each other and located in the first direction, while the other two branches are opposite each other and located in the second direction. The first direction and the second direction are perpendicular. The trench gate 320 in the first direction has N-type heavily doped regions 232 on both sides. The trench gate 320 and P-type heavily doped regions 420 in the first direction are periodically alternated. This allows the device in this embodiment to have a high channel density. The high channel density significantly increases the current density of the device. This novel structure can also set a deep well at the trench corner as a shielding region to transfer the electric field peak from the trench corner to the bottom of the deep well, so that the device depletion region can be closed, reducing the device's IDSS and increasing the device's BVDSS, effectively improving the device's reliability.
[0052] In some embodiments, the gate dielectric layer 310 is located on the inner wall of the trench in the N-type drift region 220, and the thickness of the interlayer dielectric layer 311 is greater than the thickness of the gate dielectric layer 310.
[0053] In some embodiments, the thickness of the interlayer dielectric layer 311 is at least 10 times the thickness of the gate dielectric layer 310, and the interlayer dielectric layer 311 isolates the mutual interference between the first electrode 110 and the trench gate 320.
[0054] In some embodiments, the first and second directions are perpendicular. With this topology layout, the current density of the device is 40%-50% higher than that of the strip structure layout and 10%-20% higher than that of the square / interlaced square / hexagonal structure.
[0055] In some embodiments, combined with Figure 1 As shown, trench gates 320 are provided around both the P-type deep well 410 and the P-type heavily doped region 420, and are isolated by the gate dielectric layer 310. The depth of the P-type deep well 410 is greater than the depth of the trench gate 320, and the depth of the P-type well region 231 is less than the depth of the trench gate 320.
[0056] In some embodiments, the trench gate 320 has a depth of 0.8-2.0 μm and the bottom corner of the trench gate 320 is arc-shaped.
[0057] In this embodiment, the bottom corner of the trench gate 320 can be rounded to reduce the peak electric field at the bottom of the trench gate 320.
[0058] In some embodiments, the depth of the P-type well region 231 is 0.4-0.6 μm.
[0059] In some embodiments, the total doping dose of the P-type well region 231 is 2E12-2E13 cm⁻¹. -2 .
[0060] In some embodiments, the depth of the P-type deep well 410 is 1-4 μm, and the total doping dose of the P-type deep well 410 is 8E12-1E14 cm⁻¹. -2 .
[0061] In some embodiments, the depth of the P-type heavily doped region 420 is 0.2-0.6 μm.
[0062] In some embodiments, the total doping dose of the heavily doped p-type region 420 is 3E15-8E15cm. -2 .
[0063] In some embodiments, the depth of the heavily doped p-type region 420 is 1-2.5 μm, and the doping dose of the heavily doped p-type region 420 is 3E15-8E15 cm⁻¹. -2 .
[0064] In some embodiments, the width of the heavily doped P-type region 420 is equal to the width of the deep P-type well 410, the depth of the heavily doped P-type region 420 is less than the depth of the trench gate 320, and the deep P-type well 410 and the heavily doped P-type region 420 are in contact with the gate dielectric layer 310.
[0065] In this embodiment, the doping concentration of the heavily doped P-type region 420 is greater than that of the deep P-type well 410, and the width of the heavily doped P-type region 420 is equal to the width of the deep P-type well 410. In the horizontal cross-section, the heavily doped P-type region 420 and the deep P-type well 410 have the same shape and can be formed using the same photomask by using different doses and concentrations of implanted P-type dopant ions.
[0066] In some embodiments, combined with Figure 1 As shown, the P-type well region 231 is square or rectangular, and a trench gate 320 is provided between adjacent P-type well regions 231.
[0067] In some embodiments, the doping concentration of the P-type deep well 410 is greater than that of the P-type well region 231. By setting the P-type deep well 410, the depletion region capacitance is increased, further reducing the gate drain charge of the device and increasing the switching frequency of the device. Furthermore, the P-type well region 231 in the cross-section C surrounds the trench gate 320 and the P-type deep well 410. The surrounding P-type well region 231 and P-type deep well 410 have a stronger depletion effect than other layouts, thus causing the device to enter the saturation region earlier, clamping the saturation current, and optimizing the short-circuit characteristics of the device.
[0068] In some embodiments, the doping of the P-type well region 231 is distributed in a box-like pattern.
[0069] In some embodiments, the doping of the P-type deep well 410 is distributed in a box-like pattern.
[0070] In some embodiments, the doping in the P-type heavily doped region 420 is distributed in a box-like pattern.
[0071] In some embodiments, within sections A and B, the P-type deep well 410 and the trench gate 320 are alternately arranged. Through this alternating array structure, the gate-source coupling effect is enhanced, which can shunt the displacement current in high dV / dt applications, reduce the voltage drop formed by the displacement current in the gate circuit, and thus avoid gate mis-turn-on. This is beneficial for the trench gate silicon carbide power device in this embodiment to achieve zero-voltage turn-off, and reduce the complexity of the application system and switching losses.
[0072] In some embodiments, the width of the P-type deep well 410 increases in a gradient from the silicon carbide substrate 210 to the P-type well region 231.
[0073] In this embodiment, the P-type deep well 410 can be formed by multiple different photomask P-type doped ion implantation processes, so that the width of the P-type deep well 410 is set in a gradient, and the doping concentration of the P-type deep well 410 can also be increased in a gradient from the silicon carbide substrate 210 to the P-type well region 231.
[0074] In some embodiments, see Figure 2 As shown, the P-type well region 231 extends along the outer surface of the gate dielectric layer 310 towards the N-type drift region 220. The P-type deep well 410 includes a vertical deep well region and a horizontal deep well region, and the horizontal deep well region extends below the gate dielectric layer 310 and isolates the gate dielectric layer 310 from the N-type drift region 220.
[0075] In this embodiment, Figure 2 The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 2 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 2 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 2The schematic diagram (d) shows a cross-sectional view of the trench gate silicon carbide power device. Multiple vertical deep well regions are connected through horizontal deep well regions to form a continuous deep well structure. This continuous deep well structure allows the P-type deep well 410 to completely cover the area below the trench gate 320, thus covering the area below the trench gate 320 with a reverse PN junction. This facilitates the equalization of the electric field below the trench gate 320, shifting the electric field peak from the trench corner to the bottom of the deep well. This allows the device's depletion region to close, reducing the device's IDSS, improving the device's BVDSS, and effectively enhancing the device's reliability.
[0076] In some embodiments, see Figure 3 As shown, the depth of the P-type heavily doped region 420 is greater than the depth of the trench gate 320, and a current spreading layer is also provided in part of the interface region between the P-type well region 231 and the N-type drift region 220; the P-type deep well 410 is interconnected along the bottom of the P-type heavily doped region 420 and the gate dielectric layer 310.
[0077] Figure 3 The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 3 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 3 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 3 The schematic diagram (d) shows a cross-sectional view of the trench gate silicon carbide power device. In this embodiment, the depth of the heavily doped P-type region 420 is greater than the depth of the trench gate 320, and the heavily doped P-type region 420 extends to the bottom of the trench gate 320. The heavily doped P-type region 420 is in contact with the gate dielectric layer 310. By setting the depth of the heavily doped P-type region 420 to be greater than the depth of the trench gate 320, and the heavily doped P-type region 420 extending below the gate dielectric layer 310, a through-type heavily doped P-type region 420 is formed. The heavily doped P-type region 420 and the N-type drift region 220 are isolated by a P-type deep well 410. This facilitates the setting of a shielding region in the trench corner area, migrating the electric field peak from the trench corner to the bottom of the deep well, allowing the device depletion region to close, reducing the device's IDSS, improving the device's BVDSS, and effectively improving the device's reliability.
[0078] In some embodiments, see Figure 4 As shown, the first electrode 110 has a convex structure. The protrusion of the first electrode 110 contacts the N-type drift region 220 through the contact holes in the P-type heavily doped region 420 and the P-type deep well 410. A Schottky metal layer 510 is also provided between the protrusion of the first electrode 110 and the N-type drift region 220.
[0079] Figure 4The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 4 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 4 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 4 The schematic diagram (d) shows a cross-sectional view of the trench-gate silicon carbide power device. In this embodiment, a Schottky metal layer 510 is provided between the protrusion of the first electrode 110 and the N-type drift region 220, thereby forming a Schottky diode between the first electrode 110 and the N-type drift region 220. By integrating the Schottky diode, it plays a role in reverse freewheeling, reducing the reverse freewheeling voltage of the device to 1-1.5V and improving the reverse freewheeling characteristics of the device.
[0080] In some embodiments, see Figure 5 As shown, the first electrode 110 has a convex structure, and the protrusion of the first electrode 110 extends into the P-type heavily doped region 420.
[0081] Figure 5 The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 5 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 5 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 5 The schematic diagram (d) shows a cross-sectional view of the trench gate silicon carbide power device. In this embodiment, the protrusion of the first electrode 110 extends into the groove of the heavily doped P-type region 420. The protrusion of the first electrode 110 is surrounded by the heavily doped P-type region 420 in the horizontal cross-section. The heavily doped P-type region 420 is annular in the horizontal cross-section, which has a stronger depletion effect compared with other layouts. This is beneficial for the device to enter the saturation region, clamp the saturation current, and optimize the short-circuit characteristics of the device.
[0082] In some embodiments, see Figure 6 As shown, the trench gate 320 includes four gates, and adjacent gates are electrically connected to each other through an arched interconnect layer; wherein, the included angle between adjacent gates is 90 degrees, the arched interconnect layer is located on the P-type heavily doped region 420, and is isolated from the P-type heavily doped region 420 by the gate dielectric layer 310.
[0083] Figure 6 The schematic diagram (a) shows a horizontal cross-section of a trench-gate silicon carbide power device. Figure 6 The schematic diagram (b) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 6 The schematic diagram (c) shows a cross-sectional view of the trench-gate silicon carbide power device. Figure 6The schematic diagram (d) shows a cross-sectional view (C) of the trench gate silicon carbide power device. In this embodiment, an arched polysilicon layer is used as the interconnect layer to interconnect four gates to form a cross-shaped trench gate 320. The interconnect layer facilitates the placement of the trench gate 320 within the trench. The upper surfaces of the four gates can be flush with the opening of the trench, thereby increasing the distance between the gate and the source layer and reducing interference between the source layer and the trench gate 320.
[0084] In some embodiments, the silicon carbide substrate 210 is a P-type substrate; the second electrode 120 is a collector electrode, and the first electrode 110 is an emitter electrode.
[0085] In some embodiments, the silicon carbide substrate 210 can be N-type doped, in which case the trench gate silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain.
[0086] In some embodiments, the silicon carbide substrate 210 includes a P-type substrate and an N-type substrate, with the N-type substrate located in the peripheral region of the P-type substrate. In this case, the trench gate silicon carbide power device can be an IGBT structure, with the first electrode 110 being the emitter and the second electrode 120 being the collector.
[0087] This application also provides a method for fabricating a trench-gate silicon carbide power device, see [link to relevant documentation]. Figure 7 As shown, the preparation method in this embodiment includes steps S100 to S600.
[0088] In step S100, an N-type drift region 220 is sequentially formed on the front side of the silicon carbide substrate 210, and a P-type well region 231 is formed on the N-type drift region 220.
[0089] In this embodiment, combined with Figure 8 As shown, N-type drift regions 220 are sequentially formed on the front side of a silicon carbide substrate 210. The silicon carbide substrate 210 can be a highly doped substrate, and a lightly doped epitaxial layer is formed on the silicon carbide substrate 210 as the N-type drift region 220. A P-type well region 231 is formed on the N-type drift region 220 using a P-type doped ion implantation process. Figure 9 The cross section C shown is illustrated.
[0090] In some embodiments, the doping concentration of the N-type drift region 220 is 3E15-1.5E16 cm⁻¹. -3 The thickness and concentration of the N-type drift region 220 depend on the device's voltage rating.
[0091] In some embodiments, the implantation depth of the P-type well region 231 can be 0.4um-0.6um, the number of implantations is 3-5, and the implantation energy decreases sequentially.
[0092] In some embodiments, the doping concentration of the P-type well region 231 is 1E16-2E18 cm⁻¹. -3 .
[0093] In step S200, under the protection of the first hard film 601, an N-type heavily doped region 232 is formed in a preset region of the P-type well region 231 by ion implantation.
[0094] In this embodiment, as Figure 10a As shown in section C, under the protection of the first hard film 601, an N-type heavily doped region 232 is formed in a predetermined region of the P-type well region 231 by ion implantation. Figure 10b This is a schematic diagram of device cross-sections A and B, with the first hard film 601 covering the regions of cross-sections A and B.
[0095] In some embodiments, under the protection of the first hard film 601, the implantation depth of the heavily doped N-type region 232 can be 0.2µm-0.3µm. The number of implantations of the heavily doped N-type region 232 is 3-5 times, with the implantation energy decreasing sequentially.
[0096] In some embodiments, the doping concentration of the N-type heavily doped region 232 is 1E19-1E20 cm⁻¹. -3 .
[0097] In step S300, under the protection of the second hard film 602, multiple ion implantations are used to form a P-type deep well 410 and a P-type heavily doped region 420 extending into the N-type drift region 220; the depth of the P-type well region 231 is less than the depth of the P-type deep well 410.
[0098] In this embodiment, as Figure 11 As shown in sections A and B, under the protection of the second hard film 602, multiple ion implantations are used to form a P-type deep well 410 and a P-type heavily doped region 420 extending into the N-type drift region 220. The doping concentration of the P-type heavily doped region 420 is greater than that of the P-type deep well 410, and the depth of the P-type deep well 410 is greater than that of the P-type well region 231.
[0099] In some embodiments, under the protection of the second hard film 602, a P-type deep well 410 is formed by high-energy P-type ion implantation (IMP). The implantation depth of the P-type deep well 410 is 1.0-4.0 μm, the number of implantations is 4-6, and the doping concentration is 1E16-2E18 cm⁻¹. -3 .
[0100] In some embodiments, after implantation of the P-type deep well 410, a heavily doped P-type region 420 is formed by P-type ion implantation. The implantation depth of the heavily doped P-type region 420 is approximately 0.2-0.6 μm, the number of implantations of the heavily doped P-type region 420 is 2-4 times, the implantation energy of the heavily doped P-type region 420 decreases sequentially, and the doping concentration of the heavily doped P-type region 420 is greater than 1E19cm⁻¹. -3 The implantation process of the P-type heavily doped region 420 ends with annealing and activation at 1600-1800℃.
[0101] In step S400, the gate trench is etched deep into the N-type drift region 220, and after forming the gate dielectric layer 310, the gate material is filled to form the trench gate 320; wherein, the trench gate 320 has a cross-shaped structure, and the P-type heavily doped region 420 is located in the intersection region of the cross-shaped structure.
[0102] In this embodiment, as Figure 12a and Figure 12b As shown, gate trench 621 is formed by etching, wherein, Figure 12b This is a schematic diagram of section A and section B. Figure 12a This is a schematic diagram of section C.
[0103] In some embodiments, the gate trench 621 can be formed by dry etching, the depth of the gate trench 621 being about 0.8-2.0 μm, and sacrificial oxidation can improve the trench and SiC surface morphology.
[0104] In step S500, a trench gate 320 and a P-type heavily doped region 420 are formed to cover the trench gate 320 by the gate dielectric layer 310.
[0105] In this embodiment, after the gate dielectric layer 310 is formed along the inner wall of the gate trench 621 by thermal oxidation or chemical vapor deposition (CVD), the gate material is filled in the gate trench 621, and then the gate dielectric layer 310 covering the gate material is formed.
[0106] In some embodiments, the sidewalls of the gate trench 621 are substantially the same thickness as the bottom gate oxide.
[0107] In step S600, contact holes are formed by etching along the region above the heavily doped P-type region 420, and a first electrode 110 is formed covering the gate dielectric layer 310 and contacting the heavily doped P-type region 420 and the heavily doped N-type region 232, and a second electrode 120 is formed covering the back side of the silicon carbide substrate 210, as shown below. Figure 14 As shown.
[0108] In some embodiments, if the silicon carbide substrate 210 in step S100 can be N-type doped, then the trench gate silicon carbide power device can be a MOS structure.
[0109] In some embodiments, if the silicon carbide substrate 210 in step S100 can be P-type doped, then the trench gate silicon carbide power device can be an IGBT structure.
[0110] This application also provides a chip including a trench gate silicon carbide power device as described in any of the above embodiments.
[0111] In some embodiments, the chip includes a chip substrate on which one or more trench gate silicon carbide power devices are disposed, the trench gate silicon carbide power devices including the trench gate silicon carbide power devices of any of the above embodiments.
[0112] In one specific application embodiment, when the silicon carbide substrate 210 is N-type doped, the trench-gate silicon carbide power device can be a MOS structure, with the first electrode 110 as the source and the second electrode 120 as the drain. When the silicon carbide substrate 210 is P-type doped, the trench-gate silicon carbide power device can be an IGBT structure, with the first electrode 110 as the emitter and the second electrode 120 as the collector.
[0113] Other related semiconductor devices, as well as MOSFETs, can be integrated on the chip substrate to form an integrated circuit.
[0114] In one specific application embodiment, the chip can be a switch chip or a driver chip.
[0115] In this embodiment, a trench gate silicon carbide power device is constructed within the chip. The trench gate 320 within the trench gate silicon carbide power device has a cross-shaped structure. A double-layer structure of a P-type deep well 410 and a P-type heavily doped region 420 is constructed in the cross-shaped area of the trench gate 320. Furthermore, N-type heavily doped regions 232 are located on both sides of the trench gate 320 in the first direction. The trench gate 320 and the P-type heavily doped region 420 are periodically alternated. In this way, the current density of the device is significantly increased through a higher channel density. This novel structure can also construct a deep well at the trench corner as a shielding area, migrating the electric field peak from the trench corner to the bottom of the deep well. This allows the device depletion region to close, reducing the device's IDSS and increasing the device's BVDSS, effectively improving the device's reliability.
[0116] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0117] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.
[0118] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0119] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0120] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A trench-gate silicon carbide power device, characterized in that, The trench gate silicon carbide power device includes: A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate; The interlayer dielectric layer and the trench gate and gate dielectric layer formed in the N-type drift region, wherein the trench gate has a cross-shaped structure and is wrapped by the gate dielectric layer and the interlayer dielectric layer; A P-type deep well is formed in the intersection region of the trench gate and extends into the central region of the N-type drift region; A heavily doped P-type region formed on and in contact with the P-type deep well; Multiple P-type well regions are formed on the N-type drift region, and N-type heavily doped regions are located on the P-type well regions; adjacent P-type well regions and adjacent N-type heavily doped regions are isolated by the trench gate; and the P-type well regions and the trench gate are isolated by the gate dielectric layer; the trench gate includes four branches, adjacent branches are perpendicular in the horizontal cross section, and adjacent branches are electrically connected to each other through an arched interconnect layer, the arched interconnect layer is located on the P-type heavily doped region, and is isolated from the P-type heavily doped region by the gate dielectric layer; a double-layer structure of P-type deep wells and P-type heavily doped regions is provided in the cross-shaped area of the trench gate; the N-type heavily doped regions are on both sides of the trench gate in the first direction; the trench gate and the P-type heavily doped region are periodically alternated in the first direction; and the P-type deep wells are provided at the trench corners of the trench gate. A first electrode is covered on the interlayer dielectric layer, and the first electrode is electrically connected to the P-type heavily doped region through a contact hole on the interlayer dielectric layer; the contact hole is located above the P-type heavily doped region. A second electrode is formed on the back side of the silicon carbide substrate.
2. The trench-gate silicon carbide power device as described in claim 1, characterized in that, The periphery of both the P-type deep well and the P-type heavily doped region is provided with a trench gate, which is isolated by a gate dielectric layer. The depth of the P-type deep well is greater than the depth of the trench gate, and the depth of the P-type well region is less than the depth of the trench gate.
3. The trench-gate silicon carbide power device as described in claim 1, characterized in that, The P-type well region extends along the outer surface of the gate dielectric layer toward the N-type drift region; The P-type deep well includes a vertical deep well region and a horizontal deep well region, and the horizontal deep well region extends below the gate dielectric layer and isolates the gate dielectric layer from the N-type drift region.
4. The trench-gate silicon carbide power device as described in claim 1, characterized in that, The depth of the P-type heavily doped region is greater than the depth of the trench gate, and a current spreading layer is also provided in part of the interface region between the P-type well region and the N-type drift region. The P-type deep well is interconnected along the bottom of the P-type heavily doped region and the gate dielectric layer.
5. The trench-gate silicon carbide power device as described in claim 1, characterized in that, The first electrode has a convex structure. The protrusion of the first electrode contacts the N-type drift region through the contact hole in the P-type heavy doped region and the P-type deep well. A Schottky metal layer is also disposed between the protrusion of the first electrode and the N-type drift region.
6. The trench-gate silicon carbide power device as described in claim 1, characterized in that, The first electrode has a convex structure, and the protrusion of the first electrode extends into the P-type heavily doped region.
7. The trench-gate silicon carbide power device as described in claim 1, characterized in that, The silicon carbide substrate is a P-type substrate; The second electrode is the collector, and the first electrode is the emitter.
8. A method for fabricating a trench-gate silicon carbide power device as described in any one of claims 1-7, characterized in that, The preparation method includes: An N-type drift region is sequentially formed on the front side of a silicon carbide substrate, and a P-type well region is formed on the N-type drift region; Under the protection of the first hard film, an N-type heavily doped region is formed in a predetermined region of the P-type well region by ion implantation; Under the protection of the second hard film, multiple ion implantations are used to form a P-type deep well and a P-type heavily doped region that extend into the N-type drift region; the depth of the P-type well region is less than the depth of the P-type deep well. The gate trench is etched deep into the N-type drift region, and after forming a gate dielectric layer, the gate material is filled to form a trench gate; wherein, the trench gate has a cross-shaped structure, and the P-type heavily doped region is located in the intersection region of the cross-shaped structure; An interlayer dielectric layer is formed to cover the trench gate and the P-type heavily doped region, so that the trench gate is wrapped by the gate dielectric layer and the interlayer dielectric layer; A contact hole is formed by etching along the region above the heavily doped P-type region, and a first electrode is formed covering the gate dielectric layer and contacting the heavily doped P-type region and the heavily doped N-type region, and a second electrode is formed covering the back side of the silicon carbide substrate.
9. A chip, characterized in that, Including the trench gate silicon carbide power device as described in any one of claims 1-7.