Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a manufacturing method thereof, which comprises a drift region with a first conductive type, a well region arranged near the top of the drift region with a second conductive type, a first trench gate, a second trench gate, and a plurality of active regions with the first conductive type, part of the active regions being arranged near the first trench gate on the side of the first trench gate, and part of the active regions being arranged near the second trench gate on the side of the second trench gate, wherein the thickness of the first gate dielectric layer is less than the thickness of the second gate dielectric layer, and the doping concentration of the well region where the first trench gate is located and the well region where the second trench gate is located is the same. The device with the first trench gate as the gate will reach the negative temperature coefficient region of the transfer characteristic curve first, and will reach the thermal steady state faster, so the above-mentioned semiconductor device as a whole will reach the thermal steady state faster, and has a larger safe working area.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] From the output characteristic curve of MOSFET (Metal Oxide Semiconductor Field Effect Transistor), MOSFET mainly has three working regions: variable resistance region (ohmic region), constant current region (saturation region), and pinch-off region. Referring to Figure 1 When the device enters the saturation region, under the condition that Vgs (gate-source voltage) is constant, since the output current and voltage have reached the maximum, the device will bear a large power at this time. The safe operating area (SOA) is used to evaluate that the maximum voltage and the maximum current should not exceed the limited range when the device is working, otherwise the device is easy to overheat and unstable, and even seriously damaged. However, for applications such as hot plug, load switch, and adjustment tube of discrete LDO (Low Dropout Linear Regulator), MOSFET will work in the linear region for a long time or all the time, and the requirement for the safe operating area is higher. SUMMARY

[0003] Therefore, it is necessary to provide a semiconductor device with a larger safe operating area.

[0004] A semiconductor device, comprising: a drift region having a first conductivity type; a well region disposed near a top of the drift region and having a second conductivity type, the first conductivity type and the second conductivity type being opposite conductivity types; a first trench gate including a first gate dielectric layer located on an inner surface of a first trench, and a first gate located in the first trench and surrounded by the first gate dielectric layer on all sides and a bottom, at least a partial region of the first trench gate being located in the well region; a second trench gate including a second gate dielectric layer located on an inner surface of a second trench, and a second gate located in the second trench and surrounded by the second gate dielectric layer on all sides and a bottom, at least a partial region of the second trench gate being located in the well region; a plurality of active regions having the first conductivity type, part of the active regions being disposed near the first trench gate on a side of the first trench gate, and part of the active regions being disposed near the second trench gate on a side of the second trench gate; wherein a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer, and a doping concentration of the well region in which the first trench gate is located and the well region in which the second trench gate is located is the same.

[0005] The semiconductor device has a first trench gate with a thin gate dielectric layer, so that the device with the first trench gate as the gate has a lower threshold voltage. Therefore, the device with the first trench gate as the gate reaches the negative temperature coefficient region of the transfer characteristic curve first, and reaches the thermal stable state faster. As a result, the semiconductor device reaches the thermal stable state faster and has a larger safe operating area.

[0006] In one embodiment, the bottom of the first trench gate is separated from the drift region by part of the well region.

[0007] In one embodiment, the depth of the second trench gate is greater than the depth of the well region, so that the bottom of the second trench gate reaches the drift region.

[0008] In one embodiment, the thickness of the first gate dielectric layer is 200-500 angstroms.

[0009] In one embodiment, the threshold voltage of the device with the first gate as the gate is not greater than 1.5V.

[0010] In one embodiment, the thickness of the second gate dielectric layer is greater than 1000 angstroms.

[0011] In one embodiment, the threshold voltage of the device with the second gate as the gate is greater than 3V.

[0012] In one embodiment, at least part of the first trench gate is located between different second trench gates.

[0013] In one embodiment, the semiconductor device is a metal oxide semiconductor field effect transistor or a vertical double diffused metal oxide semiconductor field effect transistor.

[0014] In one embodiment, the first conductivity type is N type and the second conductivity type is P type.

[0015] It is also necessary to provide a method for manufacturing a semiconductor device with a larger safe operating area.

[0016] A method for manufacturing a semiconductor device, comprising: forming a first trench gate and a second trench gate in a drift region of a first conductivity type; the first trench gate comprising a first gate dielectric layer on an inner surface of a first trench, and a first gate electrode in the first trench surrounded by the first gate dielectric layer on all sides and the bottom; the second trench gate comprising a second gate dielectric layer on an inner surface of a second trench, and a second gate electrode in the second trench surrounded by the second gate dielectric layer on all sides and the bottom; forming a well region of a second conductivity type at a position close to a top of the drift region; the first conductivity type and the second conductivity type being opposite conductivity types; forming a plurality of active regions of the first conductivity type, part of the active regions being formed on a side of the first trench gate and close to the first trench gate, and part of the active regions being formed on a side of the second trench gate and close to the second trench gate; wherein a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer, a doping concentration of a well region in which the first trench gate is located and a well region in which the second trench gate is located is the same, at least part of the first trench gate is located in the well region, and at least part of the second trench gate is located in the well region.

[0017] The method for manufacturing a semiconductor device as described above, by setting the first trench gate with a thinner gate dielectric layer, the device with the first trench gate as the gate electrode has a lower threshold voltage, thus the device with the first trench gate as the gate electrode reaches the negative temperature coefficient region of the transfer characteristic curve first, and the device with the first trench gate as the gate electrode reaches the thermal stable state faster, thus the whole semiconductor device reaches the thermal stable state faster, and has a larger safe operating area.

[0018] In one of the embodiments, in the step of forming the first trench gate and the second trench gate in the drift region of the first conductivity type, each of the first trench gate and each of the second trench gate are mixedly distributed on a plane of a wafer.

[0019] In one of the embodiments, a depth of the first trench is less than a depth of the well region, so that the bottom of the first trench gate is separated from the drift region by part of the well region. BRIEF DESCRIPTION OF DRAWINGS

[0020] For a better description and illustration of the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently understood of these inventions.

[0021] Figure 1 is a schematic diagram of an output characteristic curve of a MOSFET;

[0022] Figure 2is a schematic diagram of transfer characteristic curves of a MOSFET at 25 °C and 175 °C;

[0023] Figure 3 is a schematic diagram of a structure of a semiconductor device in an embodiment of the present application;

[0024] Figure 4 is a flow chart of a manufacturing method of a semiconductor device in an embodiment of the present application;

[0025] Figure 5 is a flow chart of a sub-step of step S410 in an embodiment of the present application;

[0026] Figure 6a is a schematic diagram of a cross-sectional structure of a device after step S412 is completed in an embodiment of the present application, Figure 6b is a schematic diagram of a cross-sectional structure of a device after step S413 is completed in an embodiment of the present application, Figure 6c is a schematic diagram of a cross-sectional structure of a device after step S415 is completed in an embodiment of the present application, Figure 6d is a schematic diagram of a cross-sectional structure of a device after step S412 is completed in an embodiment of the present application;

[0027] Figure 7 is a transfer characteristic curve of a semiconductor device in an embodiment of the present application and a comparative example. DETAILED DESCRIPTION

[0028] For the purpose of promoting an understanding of the application, the application will now be described in greater detail with reference to the drawings. The preferred embodiments of the application are illustrated in the drawings. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0031] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] Embodiments of the application are described herein with reference to the drawings, which are idealized representations of schematic cross-sectional views of embodiments of the application (and intermediate structures) as a practical implementation of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the application.

[0034] As used herein, semiconductor terminology is used in accordance with its common usage within the semiconductor industry, e.g., for P-type and N-type impurities, P+ is used to denote a heavily doped P-type, P is used to denote a moderately doped P-type, P- is used to denote a lightly doped P-type, N+ is used to denote a heavily doped N-type, N is used to denote a moderately doped N-type, and N- is used to denote a lightly doped N-type, for purposes of distinguishing between doping concentrations.

[0035] The safe operating area is mainly limited by 5 conditions. Respectively: on-state resistance limit, package current limit, maximum power limit, thermal instability limit, breakdown voltage limit. Among them, the thermal instability limit corresponds to when the device works in the saturation region for a period of time, the heat generated causes the device operating temperature to rise, which will cause the device to overheat and become unstable. Here we introduce a related concept called zero temperature coefficient point (ZTC), which is the intersection of the transfer characteristic curves of the device at 25°C and 175°C, refer to Figure 2 . It can be simply understood as: when Vgs < Vgs (ZTC), the higher the temperature, the larger the drain current I D (dielectric breakdown). When the local area of the chip becomes hotter than the adjacent area, it will conduct more drain current, thereby generating more heat, which will lead to device failure (thermal runaway) if no appropriate limit conditions are set. When Vgs > Vgs (ZTC), the higher the temperature, the smaller the I D (dielectric breakdown). When the local area of the chip becomes hotter than the adjacent area, it will conduct more drain current, thereby generating more heat, which will lead to device failure (thermal runaway) if no appropriate limit conditions are set. When Vgs > Vgs (ZTC), the higher the temperature, the smaller the I

[0036] Therefore, the key to optimizing the thermal instability limit is the ZTC point, which intersects the transfer characteristic curves at 25°C and 175°C when I D is very small or Vgs is very small, which can achieve the expansion of the safe operating area.

[0037] An exemplary VDMOS (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor) has a greater safe operating area by adjusting the concentration of P-type doping in the conductive channel under the gate in the cells in a portion of the chip to have lower threshold voltage.

[0038] However, the scheme of obtaining a greater safe operating area by adjusting the ion implantation dosage of the P-type body region has a problem of weakening the UIS (Unclamped Inductive Switching) capability of the chip. Taking an N-channel MOSFET as an example, the base resistance in the parasitic NPN transistor of the low threshold voltage cell will be significantly increased, making the parasitic transistor more likely to be turned on, which can easily cause device damage.

[0039] Figure 3 is a structural schematic diagram of a semiconductor device in an embodiment of the present application, comprising a drift region 110, a well region 122, a first trench gate 130, a second trench gate 140, and a plurality of active regions 124. The drift region 110 has a first conductivity type. The well region 122 is disposed near the top of the drift region 110 and has a second conductivity type. The first trench gate 130 comprises a first gate dielectric layer 132 on the inner surface of a first trench, and a first gate electrode 134 in the first trench and surrounded by the first gate dielectric layer 132 on the periphery and bottom. At least a portion of the first trench gate 130 is located in the well region 122. The second trench gate 140 comprises a second gate dielectric layer 142 on the inner surface of a second trench, and a second gate electrode 144 in the second trench and surrounded by the second gate dielectric layer 142 on the periphery and bottom. At least a portion of the second trench gate 140 is located in the well region 122. The active regions 124 have the first conductivity type, and part of the active regions 124 are disposed near the first trench gate 130 on the side of the first trench gate 130, and part of the active regions 124 are disposed near the second trench gate 140 on the side of the second trench gate 140. The thickness of the first gate dielectric layer 132 is less than the thickness of the second gate dielectric layer 134. The well region 122 where the first trench gate 130 is located and the well region 122 where the second trench gate 140 is located have the same doping concentration. Since Figure 3 is left-right symmetrical, only one side of the structure is labeled. In the embodiment shown, Figure 3 In the embodiment shown, the first conductivity type is N-type and the second conductivity type is P-type. Accordingly, the drift region 110 is an N- region, the well region 122 is a P-well, and the active regions 124 are N+ regions. In other embodiments, the first conductivity type can be P-type and the second conductivity type can be N-type.

[0040] The semiconductor device described above, by setting the first trench gate 130 with a thin gate dielectric layer, the device (cell) with the first trench gate 130 as the gate has a lower threshold voltage, so the device with the first trench gate 130 as the gate will reach the negative temperature coefficient region of the transfer characteristic curve first, and the device with the first trench gate 130 as the gate will also reach the thermal steady state faster, so the semiconductor device as a whole will also reach the thermal steady state faster, and has a larger safe operating area. And because the doping concentration of the well region 122 around the first trench gate 130 and the well region 122 around the second trench gate 140 is the same, there is no problem of the base region resistance of the parasitic NPN triode of the low threshold voltage cell being larger, that is, the problem of low UIS capability of the low threshold voltage cell is solved.

[0041] In an embodiment of the present application, the depth of the first trench gate 130 (i.e. the depth of the first trench) is less than the depth of the well region 122, so that the bottom of the first trench gate 130 is separated from the drift region 110 by a portion of the well region 122. In this way, when the conductive channel is inverted, the well region 122 at the bottom of the first trench gate 130 and the drift region 110 form a JFET region, increasing the on-resistance of this region. And the resistance value of the JFET region will increase with temperature, which is equivalent to connecting a resistor with a resistance value that increases with temperature in series with this region, thereby introducing a "negative feedback mechanism" - i.e. the higher the temperature, the greater the resistance, and the smaller the drain current I D . In this way, I D will be limited at high temperatures, and the upward trend of the transfer characteristic curve of the device at 175°C becomes flat, and the ZTC point moves down.

[0042] In an embodiment of the present application, the depth of the second trench gate 140 (i.e. the depth of the second trench) is greater than the depth of the well region 122, so that the bottom of the second trench gate 140 reaches the drift region 110.

[0043] In an embodiment of the present application, the thickness of the first gate dielectric layer 132 is 200-500 angstroms. Thus, the threshold voltage of the device with the first gate 134 as the gate is limited to 1.5V or lower.

[0044] In an embodiment of the present application, the thickness of the second gate dielectric layer 142 is 1000 angstroms or more; so that the threshold voltage of the device with the second gate 144 as the gate is 3V or more.

[0045] The first gate dielectric layer 132 and the second gate dielectric layer 142 can comprise conventional dielectric materials such as oxides, nitrides and oxynitrides of silicon having a dielectric constant from about 4 to about 20 (measured in vacuum), or the first gate dielectric layer 132 and the second gate dielectric layer 142 can comprise a generally higher dielectric constant dielectric material having a dielectric constant from about 20 to at least about 100. Such higher dielectric constant dielectric materials can include, but are not limited to, hafnium oxide, hafnium silicates, titanium oxide, barium strontium titanate (BSTs) and lead zirconium titanate (PZTs). In one embodiment of the present application, the first gate dielectric layer 132 and the second gate dielectric layer 142 are silicon dioxide.

[0046] In one embodiment of the present application, the first gate 134 and the second gate 144 are polysilicon material; in other embodiments, metals, metal nitrides, metal silicides or similar compounds can also be used as the material of the first gate 134 and the second gate 144.

[0047] In one embodiment of the present application, at least part of the first trench gate 130 is located between different second trench gates 140. That is, a plurality of first trench gates 130 and a plurality of second trench gates 140 are mixedly distributed in the plane of the wafer, each first trench gate 130 is surrounded by second trench gates 140, and each second trench gate 140 is also surrounded by first trench gates 130. In Figure 3 In the embodiment shown, two first trench gates 130 are provided between two second trench gates 140; in other embodiments, the number of first trench gates 130, the depth of the first trench gate 130, the spacing between the first trench gate 130 and the adjacent second trench gate 140, and the spacing between two adjacent first trench gates 130 can all be optimized and adjusted. By adjusting the depth and spacing of the first trench gate 130 and other parameters, the resistance in this region can be adjusted to achieve the best balance between the on-resistance and the safe operating area.

[0048] In one embodiment of the present application, part of the active region 124 is in direct contact with the first gate dielectric layer 132, and part of the active region 124 is in direct contact with the second gate dielectric layer 142.

[0049] In one embodiment of the present application, a USG (undoped silicon glass) layer 152 is further provided on the active region 124, the first trench gate 130 and the second trench gate 140. In one embodiment of the present application, a BPSG (boron phosphorus silicon glass) layer 154 is further provided on the USG layer 152. In one embodiment of the present application, the semiconductor device further comprises a contact hole 162 penetrating downwardly through the USG layer 152 and the BPSG layer 154, and the contact hole 162 is filled with a conductive material, for example, a tungsten plug, which is in direct contact with the active region 124. A metal interconnection layer electrically connected to the conductive material is provided on the contact hole 162.Figure 3 In the embodiment shown, the bottom of the contact hole 162 extends to the well region 122.

[0050] In one embodiment of the present application, the semiconductor device is a power device, such as a power MOSFET. The semiconductor device can also be a VDMOSFET, such that in the embodiment shown, the active region 124 is a source doped region of the device, and a drain of the VDMOSFET is also formed on the backside of the drift region 110. Figure 3 In the embodiment shown, the active region 124 is a source doped region of the device, and a drain of the VDMOSFET is also formed on the backside of the drift region 110.

[0051] Figure 7 The transfer characteristic curves of the semiconductor device of one embodiment of the present application and a comparative example can be seen in Figure 3. It can be seen that the ZTC point of the semiconductor device of the embodiment of the present application is lower, and the I D dissipation is smaller, so the semiconductor device of the embodiment of the present application has a larger safe operating area.

[0052] The present application also provides a method for manufacturing a semiconductor device. Figure 4 Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to one embodiment of the present application, including the following steps:

[0053] S410, forming a first trench gate and a second trench gate in the drift region of the first conductivity type.

[0054] The first trench gate 130 includes a first gate dielectric layer 132 on the inner surface of the first trench, and a first gate electrode 134 in the first trench 131, surrounded by the first gate dielectric layer 132 on all sides and the bottom. At least part of the first trench gate 130 is located in the well region 122. The second trench gate 140 includes a second gate dielectric layer 142 on the inner surface of the second trench, and a second gate electrode 144 in the second trench, surrounded by the second gate dielectric layer 142 on all sides and the bottom.

[0055] Figure 5 Figure 4 is a flow chart of a sub-step of step S410 according to one embodiment of the present application, including the following steps:

[0056] S411, forming a second trench in the drift region.

[0057] In one embodiment of the present application, the second trench 141 is formed in the wafer with the drift region 110 by photolithography and etching.

[0058] S412, forming a second gate dielectric layer on the inner surface of the second trench.

[0059] In one embodiment of the present application, a thick gate oxide is grown on the surface of the second trench 141 as the second gate dielectric layer 142, as shown in Figure 5. Figure 6aIn one embodiment of the application, the second gate dielectric layer 142 has a thickness of 1000 A or more.

[0060] S413, filling the second trench with gate material to form a second gate.

[0061] In one embodiment of the application, step S413 is to form the second gate 144 by depositing polysilicon in the second trench 141. In one embodiment of the application, after depositing the polysilicon, CMP (chemical mechanical planarization) is used to remove the excess polysilicon and other materials on the front side of the wafer to make the front side of the wafer flat, which facilitates the fabrication of the low threshold voltage region, see Figure 6b .

[0062] S414, forming a first trench in the drift region.

[0063] In one embodiment of the application, the first trench 131 is formed in the drift region by photolithography and etching. The spacing W between two adjacent first trenches 131 can be optimized, and the number of first trenches 131 in each cell can also be optimized.

[0064] S415, forming a first gate dielectric layer on the inner surface of the first trench.

[0065] In one embodiment of the application, a thin gate oxide is grown on the surface of the first trench 131 as the first gate dielectric layer 132, see Figure 6c In one embodiment of the application, the first gate dielectric layer 132 has a thickness of 200 A to 500 A.

[0066] S416, filling the first trench with gate material to form a first gate.

[0067] In one embodiment of the application, step S416 is to form the first gate 134 by depositing polysilicon in the first trench 131. After step S416 is completed, step S410 is ended.

[0068] S420, forming a well region of the second conductivity type at a location close to the top of the drift region.

[0069] In one embodiment of the present application, the well region 122 of the second conductivity type is formed by photolithography and ion implantation (implanting ions of the second conductivity type). In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type; in other embodiments, the first conductivity type can also be P-type and the second conductivity type can also be N-type. At least part of the first trench gate 130 is located in the well region 122, and at least part of the second trench gate 140 is located in the well region 122. Since the well region 122 around the first trench gate 130 and the well region 122 around the second trench gate 140 are formed in the same step (i.e. step S420), the doping concentration of the well region 122 around the first trench gate 130 and the well region 122 around the second trench gate 140 is the same (the dosage of the ions of the second conductivity type implanted in step S420 is constant throughout the chip area).

[0070] S430, forming a plurality of active regions of the first conductivity type.

[0071] In one embodiment of the present application, the active region 224 of the first conductivity type is formed by photolithography and ion implantation (implanting ions of the first conductivity type), see Figure 6d .

[0072] The manufacturing method of the semiconductor device described above, by setting the first trench gate 130 with a thinner gate dielectric layer, the device (cell) with the first trench gate 130 as the gate has a lower threshold voltage, so the device with the first trench gate 130 as the gate will reach the negative temperature coefficient region of the transfer characteristic curve first, and the device with the first trench gate 130 as the gate will also reach the thermal steady state faster, so the whole semiconductor device will also reach the thermal steady state faster, and has a larger safe operating area. And since the doping concentration of the well region 122 around the first trench gate 130 and the well region 122 around the second trench gate 140 is the same, there is no problem of the base region resistance of the parasitic NPN transistor of the low threshold voltage cell being larger, i.e. the problem of the UIS capability of the low threshold voltage cell being low is solved.

[0073] In one embodiment of the present application, the depth of the first trench 131 is smaller than the depth of the well region 122, so that the bottom of the first trench gate 130 is separated from the drift region 110 by part of the well region 122. In this way, when the conductive channel is inverted, the well region 122 at the bottom of the first trench gate 130 and the drift region 110 will form a JFET region, increasing the on-resistance of this region. And the resistance value of the JFET region will increase and increase with temperature, which is equivalent to connecting a resistance with a resistance value that increases and increases with temperature in series in this region, thereby introducing a "negative feedback mechanism" - i.e. the higher the temperature, the larger the resistance, and the smaller the drain current I D . In this way, I DThis will be limited at high temperatures, and the upward trend of the transfer characteristic curve of the device at 175°C will become flat, and the ZTC point will shift downward.

[0074] In one embodiment of this application, the first trench gate 130 and the second trench gate 140 formed in step S410 are mixed and distributed on the plane of the wafer, that is, each first trench gate 130 is surrounded by a second trench gate 140, and each second trench gate 140 is also surrounded by a first trench gate 130.

[0075] In one embodiment of this application, after step S430, a step of forming a USG layer 152 on the active region 124, the first trench gate 130, and the second trench gate 140 is further included. Further, a BPSG layer 154 may also be formed on the USG layer 152. Then, a contact hole 162 penetrating downwards through the USG layer 152 and the BPSG layer 154 is formed by photolithography and etching. The contact hole 162 is then filled with a conductive material, such as a tungsten plug, which is in direct contact with the active region 124. After filling the contact hole 162 with the conductive material, a metal interconnect layer electrically connected to the conductive material may also be formed thereon, see [link to relevant documentation]. Figure 3 .exist Figure 3 In the embodiment shown, the bottom of the contact hole 162 extends into the well region 122.

[0076] The semiconductor device manufacturing method of this application is based on the same inventive concept as the semiconductor device. For details not specifically described in the semiconductor device manufacturing method, please refer to the above introduction of the semiconductor device.

[0077] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0078] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0079] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, any combination of the technical features is deemed to be within the scope of the present disclosure as long as there is no inconsistency.

[0080] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a drift region having a first conductivity type; a well region disposed adjacent to a top portion of the drift region, having a second conductivity type, the first and second conductivity types being opposite conductivity types; a first trench gate comprising a first gate dielectric layer on an inner surface of a first trench, and a first gate electrode within the first trench and surrounded by the first gate dielectric layer on all sides and a bottom portion, at least a portion of the first trench gate being disposed in the well region; a second trench gate comprising a second gate dielectric layer on an inner surface of a second trench, and a second gate electrode within the second trench and surrounded by the second gate dielectric layer on all sides and a bottom portion, at least a portion of the second trench gate being disposed in the well region; a plurality of active regions having the first conductivity type, some of the active regions being disposed adjacent to the first trench gate on a side of the first trench gate, and some of the active regions being disposed adjacent to the second trench gate on a side of the second trench gate; wherein a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer, a doping concentration of the well region in which the first trench gate is disposed is the same as a doping concentration of the well region in which the second trench gate is disposed, and a bottom portion of the first trench gate is separated from the drift region by some of the well region.

2. The semiconductor device according to claim 1, wherein a depth of the second trench gate is greater than a depth of the well region, such that a bottom portion of the second trench gate reaches into the drift region.

3. The semiconductor device of claim 1, wherein the thickness of the first gate dielectric layer is 200A to 500A; and / or a threshold voltage of a device having the first gate electrode as a gate electrode is not greater than 1.5V.

4. The semiconductor device of claim 1, wherein the thickness of the second gate dielectric layer is 1000A or more; and / or a threshold voltage of a device having the second gate electrode as a gate electrode is 3V or more.

5. The semiconductor device of claim 1, wherein at least some of the first trench gates are disposed between different ones of the second trench gates.

6. The semiconductor device of claim 1, wherein the semiconductor device is a metal-oxide-semiconductor field-effect transistor or a vertical double-diffused metal-oxide-semiconductor field-effect transistor.

7. A method of manufacturing a semiconductor device, comprising: forming a first trench gate and a second trench gate in a drift region of a first conductivity type; the first trench gate comprising a first gate dielectric layer on an inner surface of a first trench, and a first gate electrode within the first trench and surrounded by the first gate dielectric layer on all sides and a bottom portion; the second trench gate comprising a second gate dielectric layer on an inner surface of a second trench, and a second gate electrode within the second trench and surrounded by the second gate dielectric layer on all sides and a bottom portion; forming a well region of a second conductivity type adjacent to a top portion of the drift region; the first and second conductivity types being opposite conductivity types; forming a plurality of active regions of the first conductivity type, some of the active regions being formed on a side of the first trench gate and adjacent to the first trench gate, and some of the active regions being formed on a side of the second trench gate and adjacent to the second trench gate. The first gate dielectric layer has a thickness smaller than that of the second gate dielectric layer, the first trench gate and the second trench gate are located in the same well region, at least part of the first trench gate is located in the well region, and at least part of the second trench gate is located in the well region. The first trench has a depth smaller than that of the well region, so that the bottom of the first trench gate is separated from the drift region by part of the well region.

8. The method of manufacturing a semiconductor device according to claim 7, wherein In the step of forming the first trench gate and the second trench gate in the drift region of the first conductivity type, each of the first trench gate and the second trench gate is mixedly distributed on the plane of the wafer.

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