Semiconductor layout pattern and semiconductor stack structure suitable for power amplifier

Abstract

A semiconductor layout pattern suitable for a power amplifier includes a substrate, a plurality of gate metal frames arranged on the substrate, including a plurality of source / drain patterns and a plurality of gate patterns extending along an X direction, the source / drain electrode pattern and the plurality of grid electrode patterns are alternately arranged along a Y direction, any two adjacent grid electrode metal frames are partially overlapped with each other, and the overlapped part of the two grid electrode metal frames is defined as an overlapped line.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and more particularly to a semiconductor layout pattern and a semiconductor stack structure suitable for a power amplifier. Background Art

[0002] A power amplifier is an important component in a radio frequency (RF) transmitting circuit. Its main function is to amplify and output signals, and it is usually designed at the front end of an antenna radiator, which is also the most power-consuming component in the entire RF front-end circuit.

[0003] Power amplifiers are mainly applied to electronic products or devices that require bandwidth, such as mobile phones, tablet computers, WiMAX, Wi-Fi, Bluetooth, RFID readers, satellite communications, and other network communication products.

[0004] There is still room for improvement in current power amplifiers. For example, the area occupied by their layout patterns is relatively large, which is not conducive to the miniaturization of products. Summary of the Invention

[0005] The present invention provides a semiconductor layout pattern, which includes a substrate, and a plurality of gate metal frames arranged on the substrate. Each gate metal frame contains a plurality of source / drain patterns and a plurality of gate patterns extending along an X direction, and the source / drain patterns and the plurality of gate patterns are alternately arranged along a Y direction. Wherein, a part of any two adjacent gate metal frames overlaps each other, and the overlapping part of the two gate metal frames is defined as an overlapping line.

[0006] The present invention provides a semiconductor stack structure, which includes a substrate, a first chip and a second chip stacked on the substrate. The first chip and the second chip each include a first power amplifier and a second power amplifier. The first power amplifier and the second power amplifier each include a source terminal, a drain terminal and a gate terminal. The drain terminal of the first power amplifier is electrically connected to the source terminal of the second power amplifier, and after the first power amplifier and the second power amplifier are stacked, they form a cascode amplifier.

[0007] The present invention is characterized in that it provides a semiconductor layout pattern suitable for forming a power amplifier, and a power amplifier formed by stacking the above semiconductor layout patterns on top of each other. Among them, each power amplifier layout pattern contains a plurality of gate metal frames, and each gate metal frame is arranged adjacent to each other, that is to say, there is no gap between the gate metal frames, and the subsequent formed contact structure or wire partially overlaps the gate metal frame. In this way, the gate metal frames can be arranged more closely to each other, and the area of the overall semiconductor layout pattern can be reduced. According to the experimental results of the applicant, when the improved semiconductor layout pattern provided by the present invention is applied to a power amplifier, the performance of the power amplifier can also be effectively improved. In addition, the present invention also provides a structure in which two semiconductor layout patterns are stacked to form a cascode amplifier. The cascode amplifier formed by the present invention has better performance and a smaller area. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To make the following text easier to understand, the accompanying drawings and their detailed written descriptions can be referred to simultaneously when reading the present invention. Through the specific embodiments in this text and with reference to the corresponding accompanying drawings, the specific embodiments of the present invention are explained in detail, and the principle of action of the specific embodiments of the present invention is expounded. In addition, for clarity, the features in the drawings may not be drawn to actual scale, so the dimensions of some features in certain drawings may be deliberately enlarged or reduced.

[0009] Figure 1 A top view schematic diagram of a semiconductor unit pattern according to an embodiment of the present invention;

[0010] Figure 2 A top view layout pattern of a power amplifier unit according to an embodiment of the present invention;

[0011] Figure 3 For Figure 2 The structure shown, a top view layout pattern after forming a wire and a contact structure;

[0012] Figure 4 A top view layout pattern of a power amplifier unit according to another embodiment of the present invention;

[0013] Figure 5 For Figure 4 The structure shown, a top view layout pattern after forming a wire and a contact structure;

[0014] Figure 6 A circuit schematic diagram of a cascode amplifier;

[0015] Figure 7 A schematic diagram of the relative positions of the layout patterns of two power amplifiers stacked on top of each other;

[0016] Figure 8 It is a schematic cross-sectional structure diagram of two power amplifiers stacked on each other.

[0017] Symbol Explanation

[0018] 10: Semiconductor unit pattern

[0019] 12: Gate metal frame

[0020] 14: Gate pattern

[0021] 16: Source / drain pattern

[0022] 18: Wire

[0023] 20: Source / drain contact structure

[0024] 21: Gate contact structure

[0025] 22: Source / drain line layer

[0026] 24: Region

[0027] 25: Conductive pattern

[0028] 26: Common gate pad

[0029] 30: Back contact post

[0030] 32: Rewiring layer

[0031] 34: Thermal slot

[0032] 100: Power amplifier pattern

[0033] 200: Power amplifier pattern

[0034] 300A: First chip

[0035] 300B: Second chip

[0036] A1: Overlap line

[0037] A2: Overlap line

[0038] BOX: Buried oxide layer

[0039] CESL: Contact etch stop layer

[0040] C: Capacitor

[0041] CT: Contact structure

[0042] D: Drain terminal

[0043] G: Gate terminal

[0044] GND: Ground potential

[0045] HB: Heterogeneous Contact

[0046] ILD: Interlayer Dielectric Layer

[0047] IMD: Intermetal Dielectric Layer

[0048] L: Inductor

[0049] MET: Metal Layer

[0050] MCG: Second Power Amplifier

[0051] MCS: First Power Amplifier

[0052] PEOX: Oxide Layer

[0053] PAS: Passivation Layer

[0054] RFin: Input Signal

[0055] RFout: Output Signal

[0056] S: Source Terminal

[0057] Sub: Substrate

[0058] STI: Shallow Trench Isolation

[0059] Via: Contact Post

[0060] Vcas: Voltage Source

[0061] Vdd: Voltage Source Detailed Implementation Manner

[0062] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the preferred embodiments of the present invention are specifically listed below, and in conjunction with the accompanying drawings, the composition and the effects to be achieved of the present invention are described in detail.

[0063] For the convenience of description, the drawings of the present invention are only schematic for easier understanding of the present invention, and their detailed proportions can be adjusted according to design requirements. Regarding the up-and-down relationship of the relative components in the drawings described in the text, those skilled in the art should understand that it refers to the relative positions of the objects, so they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification. This is hereby stated first.

[0064] Although the present invention uses terms such as first, second, third, etc. to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and they do not imply or represent any previous ordinal number of the element, nor the arrangement order of one element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below can also be referred to by the term of the second element, component, region, layer, or section.

[0065] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, such as within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0066] The term "coupled", "coupled to", "electrically connected" mentioned in the present invention includes any direct and indirect electrical connection means. For example, if it is described in the text that the first component is coupled to the second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0067] Although the following describes the invention of the present invention through specific embodiments, the inventive principle of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and the omitted details are within the knowledge scope of those of ordinary skill in the art.

[0068] Please refer to Figure 1 , Figure 1 a top view schematic diagram showing a semiconductor unit pattern according to an embodiment of the present invention. As Figure 1As shown, a semiconductor cell pattern 10 is provided, which includes a gate metal frame 12. Inside the gate metal frame 12, a plurality of mutually parallel gate patterns 14 and a plurality of source / drain patterns 16 are arranged. The plurality of gate patterns 14 and the plurality of source / drain patterns 16 extend, for example, along the X direction, and the plurality of gate patterns 14 and the plurality of source / drain patterns 16 are arranged alternately along the Y direction. That is to say, when viewed along the Y direction, the patterns inside the gate metal frame 12 are arranged in the order of source / drain pattern 16, gate pattern 14, source / drain pattern 16, gate pattern 14, source / drain pattern 16... Each gate pattern 14 is electrically connected to the gate metal frame 12, and may be electrically connected to the gate metal frame 12 through a contact structure (not shown in the figure). The source / drain patterns 16 are located on the upper and lower sides of the gate patterns 14 inside the gate metal frame 12, and in the subsequent process, the source / drain patterns 16 will be electrically connected to a source terminal S and a drain terminal D. In the manufacturing process, a plurality of mutually parallel gate patterns 14 and a plurality of source / drain patterns 16 can be first formed on a substrate (not shown in the figure), and then the gate metal frame 12 can be formed to surround and electrically connect the gate patterns 14, but the present invention is not limited thereto.

[0069] In addition, Figure 1 the semiconductor cell pattern 10 further includes a conductive pattern 25 connecting the gate metal frame 12. The conductive pattern 25 may be an integrally formed structure with the gate metal frame 12, that is, the two can be formed simultaneously and include the same material. The function of the conductive pattern 25 is to electrically connect the conductive metal frame to a gate terminal G. In this embodiment, the gate metal frame 12 refers to the part (such as a rectangular frame) that surrounds and is adjacent to the plurality of gate patterns 14 and the plurality of source / drain patterns 16. For the remaining part directly connected to the gate metal frame 12, although it is an integrally formed structure with the gate metal frame 12, since it does not surround the plurality of gate patterns 14 and the plurality of source / drain patterns 16, it is still defined as the conductive pattern 25. In addition, the conductive pattern 25 defines a region 24, which is used to accommodate the subsequent formed contact structure (not shown in the figure), and the details will be continued to be described in the subsequent paragraphs.

[0070] The semiconductor cell pattern 10 further includes a plurality of conductive lines 18, a plurality of source / drain contact structures 20, and a plurality of source / drain line layers 22. The conductive lines 18 connect each source / drain pattern 16 to the source / drain contact structures 20, and the source / drain line layers 22 further connect the plurality of source / drain contact structures 20 to a source terminal S or a drain terminal D. Herein, the materials of the conductive lines 18, the source / drain contact structures 20, and the source / drain line layers 22 may include metals with good conductivity such as tungsten, cobalt, copper, aluminum, gold, etc., but are not limited thereto. Additionally, it is worth noting that the source / drain contact structures 20 are accommodated in the two side regions 24 of the gate metal frame 12. The region 24 is a blank area on both sides of the gate metal frame 12, in which no gate pattern 14 or source / drain pattern 16 is formed. The function of the region 24 is to provide a space for accommodating the source / drain contact structures 20. The source / drain line layers 22 connect the plurality of source / drain contact structures 20 located in the region 24 and are connected to the source terminal S or the drain terminal D. That is, the source terminal S or the drain terminal D is electrically connected to each source / drain pattern 16 through the paths of the source / drain line layers 22, the source / drain contact structures 20, and the conductive lines 18.

[0071] In addition, the gate patterns 14 are connected to each other through the gate metal frame 12 and are electrically connected to a gate terminal G through the gate metal frame 12. The above-mentioned gate metal frame 12 and the gate patterns 14 may be structures formed separately in different steps or an integrally formed structure formed simultaneously, and both are within the scope of the present invention.

[0072] Figure 1 The shown semiconductor cell pattern 10 can be regarded as the smallest unit of the circuit layout pattern of a power amplifier. By inputting appropriate signals at each end point (gate terminal G, source terminal S, and drain terminal D), an amplified signal can be output at the other end point. Or the Figure 1 shown semiconductor cell pattern 10 can be combined with other circuits to form a power amplifier with higher performance or be combined into other types of power amplifiers.

[0073] For example, the Figure 1 semiconductor cell patterns 10 can be arranged in an array to form patterns as shown in Figure 2 and Figure 3 shown. Figure 2 Shows a top view of the layout pattern of a power amplifier unit according to an embodiment of the present invention. Figure 3 Shows according to Figure 2 the shown structure, a top view of the layout pattern after forming the conductive lines and the contact structures. As shown in Figure 2 and Figure 3As shown, a power amplifier pattern 100 can be composed of a plurality of the above-mentioned semiconductor unit patterns 10. More specifically, the plurality of semiconductor unit patterns 10 can be arranged in an array. In terms of the equivalent circuit, it is regarded as connecting the plurality of semiconductor unit patterns 10 in parallel with each other. Therefore, a more powerful power amplifier can be formed.

[0074] In this embodiment, each gate metal frame 12 is connected to a common gate pad 26 through a conductive pattern 25. As described above, the gate metal frame 12 refers to a metal frame line pattern (preferably a rectangular frame pattern) that surrounds a plurality of source / drain patterns 16 and a gate pattern 14 and is adjacent to the source / drain pattern 16. The common gate pad 26 is formed beside the array in which the plurality of semiconductor unit patterns 10 are arranged. A gate contact structure 21 can be formed on the common gate pad 26 and is electrically connected to a gate terminal G. As for the conductive pattern 25 described here, it refers to Figure 2 the metal line in the X direction that electrically connects the gate metal frame 12 and the common gate pad 26, and the metal line surrounding the above-mentioned region 24 also belongs to a part of the conductive pattern 25. That is to say, in Figure 2 or Figure 3 the gate metal frame 12, the common gate pad 26, and the conductive pattern 25 can be an integrally formed structure, that is, having the same material and formed simultaneously. The conductive pattern 25 is other conductive patterns except the gate metal frame 12 and the common gate pad 26.

[0075] It should be noted that in Figure 2 and Figure 3 the embodiments shown, since there are regions 24 on both sides of the gate metal frame 12, when the plurality of semiconductor unit patterns 10 are arranged in an array, the regions 24 will be repeatedly arranged on both sides of each gate metal frame 12. The more gate metal frames 12 are arranged, the larger the total area occupied by the regions 24 will be, which is not conducive to the miniaturization of the product.

[0076] In the concept of the above invention, the region 24 is a region for accommodating the source / drain contact structure 20. Therefore, from a top view, the source / drain contact structure 20 does not overlap with the source / drain pattern 16 or the gate metal frame 12. However, since the source / drain contact structure 20, the source / drain pattern 16, and the gate metal frame 12 are formed in different layers (that is, first form the source / drain pattern 16, then form the gate metal frame 12, and then form the wire 18 and the source / drain contact structure 20 in different layers), in other embodiments of the present invention, the gate metal frames 12 can also be closely arranged to omit the region 24, and the wire 18 and the source / drain contact structure 20 formed in different layers are electrically connected to the source / drain pattern 16 in the underlying layer.

[0077] More specifically, please refer to Figure 4 andFigure 5 。 Figure 4 A top view of a layout pattern of a power amplifier unit according to another embodiment of the present invention is shown. Figure 5 Shown according to Figure 4 the structure shown, a top view of the layout pattern after forming the wire and the contact structure. In this embodiment, a power amplifier pattern 200 is provided, where most of the components included in the power amplifier pattern 200 are the same as those in the above embodiment and will not be repeated here. However, in this embodiment, the gate metal frames 12 are closely arranged with each other, that is, the region 24 in the above embodiment is not included between the gate metal frames 12. More specifically, there may be partial overlap between two gate metal frames 12, and the overlapping part is defined as an overlapping line. If two gate metal frames 12 are adjacent to each other in the X direction, the overlapping line A1 is arranged along the Y direction. On the other hand, if two gate metal frames 12 are adjacent to each other in the Y direction, the overlapping line A2 is arranged along the X direction.

[0078] In Figure 4 and Figure 5 for the sake of simplicity of the drawings, some components are not labeled in detail, but their detailed structures can be referred to together Figure 1 , where the components located within the gate metal frame 12 are the same.

[0079] In this embodiment, the gate metal frame 12 is formed in a dielectric layer (not shown in the figure), and the wire 18 and the source / drain contact structure 20 are formed in another dielectric layer (not shown in the figure) above. Therefore, even though the source / drain contact structure 20 overlaps with the gate metal frame 12 in the top view, actually the source / drain contact structure 20 is not electrically connected to the gate metal frame 12, and the source / drain contact structure 20 is electrically connected to the source / drain pattern 16 through the wire 18. Compared with the above embodiment, in this embodiment, since the space of the region 24 is saved, the total area of the components can be significantly reduced, and the component density is improved. According to the experimental results of the applicant, when accommodating the same number of components, the total area of the components in this embodiment is reduced by about 55% compared with the Figure 2 and Figure 3 shown embodiment, thus significantly reducing the area occupied by the components.

[0080] In addition, according to the experimental results of the applicant, Figure 5 the power amplifier formed by the embodiment shown Figure 3 also has better performance than the embodiment shown. From the experimental results, at an input frequency of 28 GHz, its gain is increased by about 2 dB (from the original 6 dB to about 8 dB).

[0081] In addition to simply using Figure 3 or Figure 5In addition to the layout pattern manufacturing success rate amplifier shown, the present invention can also stack multiple layout patterns to form other types of power amplifiers. Please refer to Figure 6 , Figure 7 and Figure 8 . Among them, Figure 6 shows a circuit schematic diagram of a cascode amplifier, Figure 7 shows a schematic diagram of the relative positions of the layout patterns of two power amplifiers stacked on each other, Figure 8 shows a schematic cross-sectional structure diagram of two power amplifiers stacked on each other. As Figure 6 shown, a cascode amplifier includes a first power amplifier MCS and a second power amplifier MCG connected to each other, where the first power amplifier MCS is a common source amplifier circuit,

[0082] its gate terminal G is connected to an input signal RFin, and its source terminal S is connected to the ground potential GND. The second power amplifier MCG is a common gate amplifier circuit, its gate terminal G is connected to a voltage source Vcas, its drain terminal D is connected to the output signal RFout, and the drain terminal D of the first power amplifier MCS is connected to the source terminal S of the second power amplifier MCG. In addition, in Figure 6 the circuit diagram also includes partial inductors L, capacitors C, and a voltage source Vdd connected to the circuit. These contents belong to the existing circuit technology of cascode amplifiers and are not the key features of the present invention, so they will not be repeated here.

[0083] The present invention Figure 5 shown power amplifier 200 can be composed of the first power amplifier MCS or the second power amplifier MCG in Figure 6 the circuit diagram by connecting different signal sources or components to the gate terminal G, source terminal S, and drain terminal D. For example, Figure 7 shown, two Figure 5 shown power amplifiers 200 are respectively connected to different signals at the gate terminal G, source terminal S, and drain terminal D to form Figure 6 and Figure 7The first power amplifier MCS and the second power amplifier MCG shown. For example, the gate terminal G of the first power amplifier MCS is connected to the input signal RFin, and the source terminal S of the first power amplifier MCS is connected to the ground potential GND. The gate terminal G of the second power amplifier MCG is connected to a voltage source Vcas, the drain terminal D is connected to the output signal RFout, and then the drain terminal D of the first power amplifier MCS is connected to the source terminal S of the second power amplifier MCG. Among them, the drain terminal D of the first power amplifier MCS and the source terminal S of the second power amplifier MCG can be connected to each other through a hybrid bond HB, that is, a hybrid contact can be formed on the wire layer on its surface, and then the two hybrid contacts are directly touched together and bonded.

[0084] In addition, Figure 7 In order to clearly mark the connection signal sources of the two power amplifiers (i.e., the first power amplifier MCS and the second power amplifier MCG) located above and below, the two power amplifiers are respectively drawn Figure 7 below and above, but in fact these two power amplifiers should be stacked vertically with each other. Therefore, from the top view, in fact, these two power amplifiers should overlap each other at the hybrid contact HB. In addition, Figure 7 The partial contact structure CT is marked for connecting the power amplifier to the signal source (such as RFin, RFout or ground, etc.).

[0085] Figure 7 For other components of the power amplifier, reference can be made to Figure 4 and Figure 5 As shown, for the simplicity of the drawings, some components are not marked with reference numerals.

[0086] Figure 8 The cross-sectional structure diagram showing the two power amplifiers stacked on each other is shown. Please refer to Figure 7 and Figure 8 , the first power amplifier MCS and the second power amplifier MCG can be formed on different chips respectively, and then the two chips are bonded in a hybrid contact manner. As Figure 8As shown, the first chip 300A includes a substrate Sub, a buried oxide layer BOX stacked on the substrate Sub, a first power amplifier MCS formed on the buried oxide layer BOX, a shallow trench isolation STI around the first power amplifier MCS, a contact etch stop layer CESL and an interlayer dielectric layer ILD covering the top. Then a contact structure CT is connected above the first power amplifier MCS, and a multi-layer metal layer MET or a plurality of contact vias Via are further formed above, located in the multi-layer dielectric layer IMD, and a heterogeneous contact HB is formed on the topmost metal layer MET. Similarly, the second chip 300B includes a buried oxide layer BOX, a second power amplifier MCG, a contact etch stop layer CESL, an interlayer dielectric layer ILD, a plurality of contact structures CT, a multi-layer metal layer MET, a plurality of contact vias Via and a heterogeneous contact HB. In addition, on the back surface of the second chip 300B (i.e., Figure 8 the upward direction) further includes a back contact post 30, electrically connected to a redistribution layer (RDL) 32, the redistribution layer 32 is located in an oxide layer PEOX, and part of it is exposed by the oxide layer PEOX, and further includes a passivation layer PAS covering the oxide layer PEOX. In addition, in some embodiments, a heat sink 34 can be formed on the back surface (i.e., the top) of the second power amplifier MCG to improve the heat dissipation efficiency and prevent the component from overheating.

[0087] The material of the substrate Sub described above is, for example, silicon, and the materials of the buried oxide layer BOX and the oxide layer PEOX are, for example, silicon oxide. The materials of the shallow trench isolation STI, the contact etch stop layer CESL, the interlayer dielectric layer ILD, the inter-metal dielectric layer IMD, and the passivation layer PAS are, for example, silicon oxide, silicon nitride or silicon oxynitride, while the materials of the contact structure CT, the metal layer MET, the contact via Via, the heterogeneous contact HB, the back contact post 30, and the redistribution layer 32 are, for example, metals such as tungsten, cobalt, copper, aluminum, gold, etc., but are not limited thereto.

[0088] To more clearly indicate the connection relationship between the first power amplifier MCS and the second power amplifier MCG and other signal sources, in Figure 8 some of the metal layers MET are marked with, for example, a source terminal S, a drain terminal D, an input signal RFin, an output signal RFout, a voltage source Vcas, etc. Therefore, it can be seen from Figure 8 that the drain terminal D of the first power amplifier MCS and the source terminal S of the second power amplifier MCG can be connected to each other through a heterogeneous contact (hybrid bond) HB and form Figure 6 the cascode amplifier shown.

[0089] Based on the above description and drawings, the present invention provides a semiconductor layout pattern 200, which includes a substrate Sub, and a plurality of gate metal frames 12 arranged on the substrate Sub. Each gate metal frame 12 includes a plurality of source / drain patterns 16 and a plurality of gate patterns 14 extending along an X direction, and the source / drain patterns 16 and the plurality of gate patterns 14 are alternately arranged along a Y direction. Among them, a part of any two adjacent gate metal frames 12 overlaps with each other, and the overlapping part of the two gate metal frames 12 is defined as an overlapping line (overlapping line A1 or overlapping line A2, please refer to Figure 4 ).

[0090] In some embodiments of the present invention, for two adjacent gate metal frames 12, if they are adjacent to each other in the X direction, the overlapping line A1 extends along the Y direction.

[0091] In some embodiments of the present invention, for two adjacent gate metal frames 12, if they are adjacent to each other in the Y direction, the overlapping line A2 extends along the X direction.

[0092] In some embodiments of the present invention, the plurality of gate patterns 14 and the gate metal frames 12 are electrically connected to a common gate pad 26.

[0093] In some embodiments of the present invention, the plurality of gate metal frames 12 are arranged in an array.

[0094] In some embodiments of the present invention, the common gate pad 26 is located beside the array.

[0095] In some embodiments of the present invention, it further includes a plurality of source / drain contacts 20, which are electrically connected to the plurality of source / drain patterns 16.

[0096] In some embodiments of the present invention, from a top view, the plurality of source / drain contacts 20 overlap with some of the gate metal frames 12.

[0097] In some embodiments of the present invention, it further includes a source / drain line layer 22, and the source / drain line layer 22 is electrically connected to the plurality of source / drain contacts 20.

[0098] In some embodiments of the present invention, from a top view, the source / drain line layer 22 overlaps with some of the source / drain patterns 16.

[0099] The present invention further provides a semiconductor stack structure, including a substrate Sub, a first chip 300A and a second chip 300B stacked on the substrate Sub, wherein the first chip 300A and the second chip 300B each include a first power amplifier MCS and a second power amplifier MCG. The first power amplifier MCS and the second power amplifier MCG each include a source terminal S, a drain terminal D and a gate terminal G, and the drain terminal D of the first power amplifier MCS is electrically connected to the source terminal S of the second power amplifier MCG. After the first power amplifier MCS and the second power amplifier MCG are stacked, a cascode amplifier is formed.

[0100] In some embodiments of the present invention, when viewed from a top view, the first chip 300A or the second chip 300B each includes a plurality of gate metal frames 12 arranged on the substrate Sub. Each gate metal frame 12 includes a plurality of source / drain patterns 16 and a plurality of gate patterns 14 extending along an X direction, and the plurality of source / drain patterns 16 and the plurality of gate patterns 14 are alternately arranged along a Y direction. A part of any two adjacent gate metal frames 12 overlaps each other.

[0101] In some embodiments of the present invention, when viewed from a top view, the first chip 300a or the second chip 300b each includes a plurality of source / drain contacts 20 electrically connected to a part of the source / drain patterns 16, and a source / drain line layer 22 electrically connected to the plurality of source / drain contacts 16 and connected to the source terminal S or the drain terminal D. When viewed from a top view, the plurality of source / drain contacts 20 overlap with a part of the gate metal frames 12.

[0102] In some embodiments of the present invention, the gate terminal G of the first power amplifier MCS of the first chip 300A is connected to an input signal RFin, and the source terminal S of the first power amplifier MCS is grounded (connected to the ground potential GND).

[0103] In some embodiments of the present invention, the gate terminal G of the second power amplifier MCG of the second chip 300B is connected to a voltage source Vcas, and the drain terminal D of the second power amplifier MCG is connected to an output signal RFout.

[0104] In some embodiments of the present invention, the drain terminal D of the first power amplifier MCS and the source terminal S of the second power amplifier MCG are electrically connected through a hybrid bond HB.

[0105] In some embodiments of the present invention, a heat sink 34 is further included and is located on the back of the second power amplifier MCG of the second chip 300B.

[0106] The present invention is characterized in that it provides a semiconductor layout pattern suitable for forming a power amplifier, and a power amplifier formed by stacking the above semiconductor layout patterns. Among them, each power amplifier layout pattern includes a plurality of gate metal frames, and each gate metal frame is arranged adjacent to each other. That is to say, there is no gap between the gate metal frames, and the subsequent formed contact structure or wire partially overlaps the gate metal frame. In this way, the gate metal frames can be arranged more closely to each other, and the area of the overall semiconductor layout pattern can be reduced. According to the experimental results of the applicant, when the improved semiconductor layout pattern provided by the present invention is applied to a power amplifier, the performance of the power amplifier can also be effectively improved. In addition, the present invention also provides a structure of a cascode amplifier formed by stacking two semiconductor layout patterns. The cascode amplifier formed by the present invention has better performance and a smaller area.

[0107] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor layout pattern, comprising: A substrate; A plurality of gate metal frames arranged on the substrate, wherein each gate metal frame contains: A plurality of source / drain patterns and a plurality of gate patterns extending along the X direction, and the plurality of source / drain patterns and the plurality of gate patterns are alternately arranged along the Y direction; and Wherein, A part of any two adjacent gate metal frames overlaps each other, and the overlapping part of the two gate metal frames is defined as an overlapping line.

2. The semiconductor layout pattern according to claim 1, wherein for the two adjacent gate metal frames, if they are adjacent to each other in the X direction, the overlapping line extends along the Y direction.

3. The semiconductor layout pattern according to claim 1, wherein for the two adjacent gate metal frames, if they are adjacent to each other in the Y direction, the overlapping line extends along the X direction.

4. The semiconductor layout pattern according to claim 1, wherein the plurality of gate patterns and the gate metal frames are electrically connected to a common gate pad.

5. The semiconductor layout pattern according to claim 4, wherein the plurality of gate metal frames are arranged in an array.

6. The semiconductor layout pattern according to claim 5, wherein the common gate pad is located beside the array.

7. The semiconductor layout pattern according to claim 1, further comprising a plurality of source / drain contacts electrically connecting the plurality of source / drain patterns.

8. The semiconductor layout pattern according to claim 7, wherein in a top view, the plurality of source / drain contacts overlap with some of the gate metal frames.

9. The semiconductor layout pattern according to claim 8, further comprising a source / drain line layer electrically connected to the source / drain line layer and the plurality of source / drain contacts.

10. The semiconductor layout pattern according to claim 9, wherein in a top view, the source / drain line layer overlaps with some of the gate metal frames.

11. A semiconductor stacked structure, comprising: A substrate; A first chip and a second chip are stacked on the substrate, wherein the first chip and the second chip each include a first power amplifier and a second power amplifier, the first power amplifier and the second power amplifier each include a source terminal, a drain terminal, and a gate terminal, and the drain terminal of the first power amplifier is electrically connected to the source terminal of the second power amplifier, and after the first power amplifier and the second power amplifier are stacked, they form a cascode amplifier.

12. The semiconductor stacked structure according to claim 11, wherein in a top view, each of the first power amplifier or the second power amplifier includes: A plurality of gate metal frames arranged on the substrate, wherein each gate metal frame contains a plurality of source / drain patterns and a plurality of gate patterns extending along the X direction, and the plurality of source / drain patterns and the plurality of gate patterns are alternately arranged along the Y direction, Wherein, A part of any two adjacent gate metal frames overlaps each other.

13. The semiconductor stacked structure according to claim 12, wherein in the top view, each of the first chip or the second chip includes: Multiple source / drain contacts, electrically connecting a part of the source / drain pattern; A source / drain line layer, electrically connecting the multiple source / drain contacts and connecting to the source terminal or the drain terminal; Wherein, viewed from the top view, the multiple source / drain contacts overlap with a part of the metal gate frame.

14. The semiconductor stack structure according to claim 11, wherein the gate terminal of the first power amplifier of the first chip is connected to an input signal, and the source terminal of the first power amplifier is grounded.

15. The semiconductor stack structure according to claim 11, wherein the gate terminal of the second power amplifier of the second chip is connected to a voltage source, and the drain terminal of the second power amplifier is connected to an output signal.

16. The semiconductor stack structure according to claim 11, wherein the drain terminal of the first power amplifier and the source terminal of the second power amplifier are electrically connected through a hybrid bond.

17. The semiconductor stack structure according to claim 11, further comprising a heat sink located on the back of the second power amplifier of the second chip.

Images