Cascade noise reduction planar avalanche photodiode and preparation method thereof

Abstract

The invention relates to the field of infrared photoelectric devices, in particular to a cascade noise reduction planar avalanche photodiode, which comprises a cascade multiplication region between a substrate and a cap layer. A PN junction is formed in the cascade multiplication region, and the PN junction is a planar PN junction. The invention also comprises a preparation method of the cascaded noise-reduction planar avalanche photodiode. The structure of the linear avalanche photodiode is improved and innovated, a multiplication region and a cascade gain stage are introduced, a plurality of gain stages are connected in series, and each stage can amplify a signal once to maximize collision ionization caused by electrons and minimize hole ionization at the same time. By optimizing the thickness and doping concentration of each sub-layer in each gain stage, additional multiplication noise and dark current are reduced, thereby improving device gain and reducing device noise. According to the preparation method, a planar junction process is utilized, and a P-type region is formed by two times of diffusion to realize a planar junction, so that the dark current of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of infrared optoelectronic devices, and particularly to a cascaded noise-reducing planar avalanche photodiode and a preparation method thereof. Background Art

[0002] Since near-infrared light is generally safer for the human eye than visible light, and the InGaAs linear avalanche photodiode (APD) can respond to short-wavelength infrared light of 950 to 1700 nm, it is a high-sensitivity photodetector and is widely used in fields such as optical fiber communication, laser ranging, photon counting, and lidar. Its main advantages include characteristics such as high gain, low noise, fast response, and linear output. Since it operates near the breakdown voltage, the excess noise and dark current are relatively large, which limits its development. For mesa-type avalanche photodiodes, the leakage caused by the passivation and etching of the mesa will lead to an excessive dark current, and the large dark current will cause the saturation of the dark signal during the coupling process with the circuit. Summary of the Invention

[0003] The purpose of the present invention is to provide a cascaded noise-reducing planar avalanche photodiode and a preparation method thereof, mainly solving the problems existing in the above-mentioned prior art, which can improve the gain of the linear avalanche photodiode and reduce its noise.

[0004] To achieve the above purpose, the technical solution adopted by the present invention is to provide a cascaded noise-reducing planar avalanche photodiode, which is characterized in that it includes a substrate, a cascaded multiplication region, and a cap layer; the bottom layer is the substrate, and the top layer is the cap layer; the cascaded multiplication region is located between the substrate and the cap layer and is generated using a molecular beam epitaxy system; a PN junction is formed in the cap layer; the PN junction is a planar PN junction.

[0005] Further, starting from the bottom substrate upwards, it successively includes a buffer layer, the cascaded multiplication region, a blocking layer, a charge layer, and a light absorption layer, and finally the cap layer located at the top layer.

[0006] Further, the cascaded multiplication region includes a plurality of multiplication layers; the plurality of multiplication layers are stacked in a periodic repetition to form a cascaded structure.

[0007] Further, the number of the multiplication layers is 2 to 10.

[0008] Further, within the multiplication layer, from bottom to top, it successively includes a first multiplication blocking layer, a multiplication potential well layer, a second multiplication blocking layer, and a multiplication sub-charge layer.

[0009] Further, the materials of the first multiplication blocking layer and the second multiplication blocking layer are In 0.52 Al 0.48AS, with a thickness of 0.02 micrometers and a doping concentration of N-type 5×10 14 cm -3 ; The material of the multiplication potential well layer is In 0.52 Al 0.24 AS, with a thickness of 0.01 micrometers and a doping concentration of N-type 5×10 14 cm -3 ; The material of the multiplication charge layer is In 0.52 Al 0.48 AS, with a thickness of 0.02 micrometers and a doping concentration of N-type 1×10 17 cm -3 。

[0010] Furthermore, the substrate material is InP, with a doping concentration of N-type 1×10 18 cm -3 ; The material of the buffer layer is InP, with a thickness of 200 nanometers and a doping concentration of N-type 5×10 17 cm -3 ; The material of the blocking layer is In 0.52 Al 0.48 As, with a thickness of 0.05 micrometers and a doping concentration of N-type 5×10 14 cm -3 ; The material of the charge layer is In 0.52 Al 0.48 As, with a thickness of 130 nanometers and a doping concentration of N-type 2.3×10 17 cm -3 ; The material of the light absorption layer is In 0.53 Ga 0.47 As, with a thickness of 1.5 micrometers and a doping concentration of N-type 5×10 14 cm -3 ; The material of the cap layer is In 0.52 Al 0.48 As, with a thickness of 2 micrometers and a doping concentration of N-type 5×10 14 cm -3 。

[0011] The present invention also discloses a preparation method of the above-mentioned cascaded noise reduction planar avalanche photodiode, which is characterized by comprising the steps of:

[0012] Step S101, obtaining a substrate material; the bottom layer of the substrate material is the substrate, and the top layer is the cap layer; between the substrate and the cap layer, a cascaded multiplication region is generated using a molecular beam epitaxy system;

[0013] Step S102, forming a first diffusion hole and completing the first diffusion; the depth of the first diffusion is equivalent to the thickness of the cap layer;

[0014] Step S103: Form the second diffusion holes and complete the second diffusion; the depth of the second diffusion is shallower than that of the first diffusion.

[0015] Step S104: Thermally activate the substrate material.

[0016] Step S105: Open N grooves on the surface and deposit a passivation film.

[0017] Step S106: Open electrode holes on the surface of the substrate material and grow electrodes; the electrode holes are located directly above the diffusion region.

[0018] Step S107: Anneal the entire substrate material thermally.

[0019] Step S108: Grow thickened electrodes on the electrodes.

[0020] Furthermore, the second diffusion holes and the first diffusion holes form concentric circles, and the diameter of the second diffusion holes is smaller than that of the first diffusion holes.

[0021] Furthermore, in Step S104 and Step S107, the diffusion is the closed-tube diffusion of zinc atoms, which includes the steps of:

[0022] Step S201: Deposit a silicon nitride mask on the surface of the substrate material.

[0023] Step S202: Cover a layer of photoresist on the silicon nitride mask.

[0024] Step S203: Transfer the mask pattern of the first diffusion holes or the second diffusion holes to the silicon nitride mask by photolithographic positioning.

[0025] Step S204: Etch on the silicon nitride mask to generate the first diffusion holes or the second diffusion holes.

[0026] Step S205: Put zinc powder into a glass tube and heat it through a diffusion furnace, so that zinc atoms diffuse downward through the first diffusion holes or the second diffusion holes into the substrate material.

[0027] In view of the above technical features, the cascaded noise reduction planar avalanche photodiode and the preparation method of the present invention have the following advantages:

[0028] 1. The cascade-noise-reducing planar avalanche photodiode of the present invention improves and innovates the structure of the linear avalanche photodiode, introducing a multiplication region and a cascade gain stage. By connecting multiple gain stages in series, each stage can amplify the signal once to maximize electron-induced impact ionization while minimizing hole ionization. By optimizing the thickness and doping concentration of each sub-layer in each gain stage, the additional multiplication noise is reduced and the dark current is minimized, thereby increasing the device gain and reducing the device noise.

[0029] 2. The manufacturing method of the cascade-noise-reducing planar avalanche photodiode of the present invention uses a planar junction process and forms a P-type region through two diffusions to achieve a planar junction, thereby reducing the device dark current. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of a preferred embodiment of the cascade-noise-reducing planar avalanche photodiode of the present invention;

[0031] Figure 2 is a flowchart of a preferred embodiment of the manufacturing method of the cascade-noise-reducing planar avalanche photodiode of the present invention;

[0032] Figure 3 is a schematic structural diagram of a non-cascade control avalanche photodiode corresponding to a preferred embodiment of the cascade-noise-reducing planar avalanche photodiode of the present invention;

[0033] Figure 4 is a simulation result diagram of the avalanche gain of a preferred embodiment of the cascade-noise-reducing planar avalanche photodiode of the present invention and a non-cascade control avalanche photodiode;

[0034] Figure 5 is a simulation measurement result diagram of the excess noise factor of a preferred embodiment of the cascade-noise-reducing planar avalanche photodiode of the present invention and a non-cascade control avalanche photodiode.

[0035] In the figure: 1 - substrate, 2 - buffer layer, 3 - cascade multiplication region, 4 - blocking layer, 5 - charge layer, 6 - light absorption layer, 7 - cap layer, 8 - multiplication layer, 9 - non-cascade charge layer;

[0036] 81 - first multiplication blocking layer, 82 - multiplication potential well layer, 82 - second multiplication blocking layer, 84 - multiplication sub-charge layer. DETAILED DESCRIPTION OF THE INVENTION

[0037] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0038] Please refer to Figure 1 , the present invention discloses a cascaded noise reduction planar avalanche photodiode. As shown in the figure, in one of its preferred embodiments, it includes a plurality of semiconductor material layers. Starting from the bottommost substrate 1 upwards, they are buffer layer 2, cascaded multiplication region 3, blocking layer 4, charge layer 5, light absorption layer 6, and the topmost cap layer 7 in sequence. The PN junction forming the diode is a planar junction, and is formed by active doping downward from the cap layer 7 and located in the cascaded multiplication region 3. In this embodiment, the material of the substrate 1 is InP, and the doping concentration is N-type 1×10 18 cm -3 . The material of the buffer layer 2 is InP, the thickness is 200 nanometers, and the doping concentration is N-type 5×10 17 cm -3 . The material of the blocking layer 4 is In 0.52 Al 0.48 As, the thickness is 0.05 micrometers, and the doping concentration is N-type 5×10 14 cm -3 . The material of the charge layer 5 is In 0.52 Al 0.48 As, the thickness is 130 nanometers, and the doping concentration is N-type 2.3×10 17 cm -3 . The material of the light absorption layer 6 is In 0.53 Ga 0.47 As, the thickness is 1.5 micrometers, and the doping concentration is N-type 5×10 14 cm -3 . The material of the cap layer 7 is In 0.52 Al 0.48 As, the thickness is 2 micrometers, and the doping concentration is N-type 5×10 14 cm -3 .

[0039] This method uses the cascaded multiplication region 3 to adjust the internal electric field, realizes the control of the movement of carriers, enables the carriers to multiply at a specified position, thereby effectively reducing edge breakdown and suppressing dark current. In the cascaded multiplication region 3, it includes a plurality of multiplication layers 8. The internal structures of these multiplication layers 8 are the same, and they are stacked repeatedly according to a period, thus forming a cascaded structure.

[0040] The cascade structure of the cascade multiplication region 3 is achieved by reducing the thickness of the multiplication layer 8 and changing the material structure design of the multiplication layer 8, thereby restricting the region where carrier impact ionization occurs and reducing the local impact ionization threshold and impact ionization rate to achieve the purpose of increasing gain and reducing noise. By reasonably designing the composition, thickness, and doping concentration of each multiplication sub-layer in the multiplication layer 8, a special electric field distribution can be obtained. The thickness of the high-field multiplication layer is specially designed to suppress the impact ionization caused by holes and locally increase the impact ionization caused by electrons, achieving quasi-unipolar carrier multiplication, thereby reducing noise. At the same time, by increasing the number of multiplication stages, this process occurs repeatedly, and high gain can be obtained while maintaining low noise. The number of multiplication stages (i.e., the number) of the multiplication layer 8 varies in different implementations, generally ranging from 2 to 10. By adjusting and increasing the number of stages of the multiplication layer 8, the quasi-unipolar carrier multiplication process occurs repeatedly, and high gain can be obtained while maintaining low noise. In this embodiment, a three-stage cascade structure is adopted, that is, a total of 3 groups of multiplication layers 8 with the same structure are included, and they are stacked together to form the cascade multiplication region 3.

[0041] Inside the multiplication layer 8, multiple multiplication sub-layers are included. By reasonably designing the composition and doping concentration of each multiplication sub-layer in the multiplication layer 8, the electric field distribution can be adjusted, and the thickness of the multiplication sub-layer can be adjusted to be equivalent to the hole relaxation space length, thereby suppressing the impact ionization caused by electrons and locally increasing the impact ionization caused by holes, achieving quasi-unipolar carrier multiplication, thereby reducing noise. In this embodiment, from the substrate 1 to the cap layer 7, they are, in sequence, the first multiplication blocking layer 81, the multiplication potential well layer 82, the second multiplication blocking layer 83, and the multiplication sub-charge layer 84. Among them, the parameters of the first multiplication blocking layer 81 and the second multiplication blocking layer 83 are the same, and the material used is In 0.52 Al 0.48 AS, with a thickness of 0.02 microns and a doping concentration of N-type 5×10 14 cm -3 ⁻³. The material of the multiplication potential well layer 82 is In 0.52 Al 0.24 AS, with a thickness of 0.01 microns and a doping concentration of N-type 5×10 14 cm -3 ⁻³. The material of the multiplication sub-charge layer 84 is In 0.52 Al 0.48 AS, with a thickness of 0.02 microns and a doping concentration of N-type 1×10 17 cm -3 ⁻³.

[0042] Next, compare the performance differences between the three-stage cascade noise reduction avalanche photodiode device and the non-cascade avalanche photodiode device. Please refer to Figure 3, the cascode-free avalanche photodiode as a control has exactly the same device structure parameters except for the cascode multiplication region 3. In the cascode multiplication region 3 corresponding to the three-stage cascode noise-reducing avalanche photodiode, the position corresponding to the cascode-free avalanche photodiode is a non-cascode charge layer 9 composed of In 0.52 Al 0.48 AS with a thickness of 0.210 microns.

[0043] Please refer to Figure 4 , and perform DC dark current and photocurrent simulations on the obtained three-stage cascode noise-reducing avalanche photodiode device and the cascode-free avalanche photodiode device respectively to obtain the gain coefficients of the devices. The actual measurement results are as Figure 4 shown. Figure 4 In, the black solid line is the photocurrent and dark current curves of the three-stage cascode noise-reducing avalanche photodiode, the gray dashed line is the photocurrent and dark current curves of the cascode-free avalanche photodiode, the black dots are the gain curves of the three-stage cascode noise-reducing avalanche photodiode, and the gray diamond frames are the gain curves of the cascode-free avalanche photodiode. It can be seen that the gain of the three-stage cascode noise-reducing avalanche photodiode device is about 220, while the gain of the cascode-free avalanche photodiode device is only about 100, and the gain is enhanced by about 2.2 times.

[0044] Please refer to Figure 5 , which shows the measurement results of the excess noise factor. In Figure 5 , the square solid dots are the excess noise data of the three-stage cascode APD, and the circular solid dots are the excess noise data of the cascode-free APD. The dashed line is the excess noise curve calculated theoretically under different impact ionization coefficient ratios (k). It can be seen that the excess noise factor of the three-stage cascode noise-reducing avalanche photodiode drops to close to k = 0.01, which is significantly lower than the excess noise of the cascode-free avalanche photodiode. From the Figure 4 and 5 results, it fully confirms the feasibility of the device structure of the cascade noise-reducing planar avalanche photodiode of the present invention in enhancing the gain of the avalanche detector and reducing the excess noise.

[0045] Please refer to Figure 2 , the present invention also uses the preparation method of the above cascade noise-reducing planar avalanche photodiode. As shown in the figure, a preferred embodiment thereof includes the steps of:

[0046] Step S1, obtaining a substrate material.

[0047] The bottom layer of the substrate material is an N-type substrate, and the top layer is a cap layer. From the substrate to the cap layer, a buffer layer, a cascade multiplication region, a blocking layer, a charge layer, and a light absorption layer are sequentially included in the middle. The cascade multiplication region adopts a three-stage cascade structure and altogether includes three groups of the same structure of stacked multiplication layers. Each multiplication layer, from bottom to top, includes four multiplication sub-layers, namely a first multiplication blocking layer, a multiplication potential well layer, a second multiplication blocking layer, and a multiplication sub-charge layer. The substrate material is obtained by growing on the substrate using a molecular beam epitaxy system.

[0048] Step S21, deposit the mask for the first time.

[0049] On the surface of the substrate material, that is, above the cap layer, deposit a layer of silicon nitride mask.

[0050] Step S22, cover the photoresist for the first time.

[0051] Cover a layer of photoresist on the silicon nitride mask.

[0052] Step S23, perform the first photolithography.

[0053] Transfer the first diffusion hole mask pattern to the silicon nitride mask by photolithography positioning.

[0054] Step S24, perform the first etching.

[0055] Etch the silicon nitride mask to generate the first diffusion holes. The first diffusion holes are round holes.

[0056] Step S25, perform the first diffusion.

[0057] Adopt the zinc atom closed-tube diffusion technology to complete the first P diffusion. Specifically, put zinc powder into a glass tube and heat it through a diffusion furnace, so that zinc atoms diffuse downward through the first diffusion holes into the substrate material. By controlling the diffusion time, the depth of the first diffusion is about the thickness of the cap layer.

[0058] Step S31, deposit the mask for the second time.

[0059] On the surface of the substrate material that has completed the first diffusion, deposit another layer of silicon nitride mask.

[0060] Step S32, cover the photoresist for the second time.

[0061] Cover a layer of photoresist on the silicon nitride mask.

[0062] Step S33, perform the second photolithography.

[0063] Transfer the first diffusion hole mask pattern to the silicon nitride mask by photolithography positioning.

[0064] Step S34, perform the second etching.

[0065] Etch and generate the second diffusion holes on the silicon nitride mask. The second diffusion holes are round holes, which form concentric circles with the first diffusion holes, and the diameter of the second diffusion holes is smaller than that of the first diffusion holes.

[0066] Step S35, the second diffusion.

[0067] Adopt the zinc atom closed-tube diffusion technology to complete the second P diffusion. Specifically, put zinc powder into the glass tube, and heat it through a diffusion furnace to make zinc atoms diffuse downward through the second diffusion holes into the substrate material.

[0068] By controlling the diffusion time, make the depth of the second diffusion shallower than that of the first diffusion.

[0069] The specific depths of the first diffusion and the second diffusion are determined through multiple single diffusion experiments.

[0070] Step S4, thermal activation.

[0071] Conduct thermal activation on the substrate material.

[0072] Step S5, surface grooving.

[0073] Open N grooves on the surface and deposit a passivation film.

[0074] Step S6, grow the P electrode.

[0075] Open electrode holes on the surface of the substrate material and grow the P electrode. The electrode holes are located directly above the P diffusion region;

[0076] Step S7, thermal annealing.

[0077] Conduct overall thermal annealing on the substrate material;

[0078] Step S8, grow the thickened electrode.

[0079] Continue to grow the thickened electrode on the P electrode.

[0080] The above are only the preferred embodiments of the present invention, and do not limit the patent scope of the present invention accordingly. Any equivalent structure or equivalent process transformation made by using the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present invention.

Claims

1. A cascade noise reduction planar avalanche photodiode, characterized in that: It comprises a substrate, a cascade multiplication region and a cap layer; the bottom layer is the substrate, and the top layer is the cap layer; the cascade multiplication region is located between the substrate and the cap layer, and is generated using a molecular beam epitaxy system; a PN junction is formed in the cap layer; and the PN junction is a planar PN junction.

2. The cascaded noise reduction planar avalanche photodiode according to claim 1, characterized in that: Starting from the substrate at the bottom layer upwards, it includes in sequence a buffer layer, the cascade multiplication region, a blocking layer, a charge layer and a light absorption layer, and finally the cap layer at the top layer.

3. The cascaded noise reduction planar avalanche photodiode according to claim 1, characterized in that: The cascade multiplication zone includes a plurality of multiplication layers; the plurality of multiplication layers are repeatedly stacked in a periodic manner to form a cascade structure.

4. The cascaded noise reduction planar avalanche photodiode according to claim 3, characterized in that: The number of the multiplication layers is 2 to 10.

5. The cascaded noise reduction planar avalanche photodiode according to claim 3, characterized in that: The multiplication layer includes, from bottom to top, a first multiplication barrier layer, a multiplication potential well layer, a second multiplication barrier layer and a multiplication sub-charge layer.

6. The cascaded noise reduction planar avalanche photodiode according to claim 5, characterized in that: The materials of the first multiplication barrier layer and the second multiplication barrier layer are In 0.52 Al 0.48 AS, thickness is 0.02 μm, doping concentration is N-type 5×10 14 cm -3 ; The material of the multiplication potential well layer is In 0.52 Al 0.24 AS, thickness is 0.01 μm, doping concentration is N-type 5×10 14 cm -3 ; The material of the multiplier charge layer is In 0.52 Al 0.48 AS, thickness is 0.02 μm, doping concentration is N-type 1×10 17 cm -3 .

7. The cascaded noise reduction planar avalanche photodiode according to claim 2, characterized in that: The substrate material is InP, and the doping concentration is N-type 1×10 18 cm -3 The buffer layer material is InP, with a thickness of 200 nanometers and a doping concentration of N-type 5×10 17 cm -3 ; The barrier layer material is In 0.52 Al 0.48 As, thickness 0.05 μm, doping concentration N-type 5×10 14 cm -3 ; The charge layer material is In 0.52 Al 0.48 As, thickness is 130 nm, doping concentration is N-type 2.3×10 17 cm -3 ; The light absorbing layer material is In 0.53 Ga 0.47 As, thickness 1.5 μm, doping concentration N-type 5×10 14 cm -3 ; The cap layer material is In 0.52 Al 0.48 As, thickness 2 μm, doping concentration N-type 5×10 14 cm -3 .

8. A method for preparing a cascade noise reduction planar avalanche photodiode as claimed in claim 1, characterized in that: Contains steps: Step S101, obtaining a base material; the bottom layer of the base material is the substrate, and the top layer is the cap layer; between the substrate and the cap layer, a molecular beam epitaxy system is used to generate the cascade multiplication region; Step S102, forming a first diffusion hole and completing the first diffusion; the first diffusion depth is equivalent to the thickness of the cap layer; Step S103, forming a second diffusion hole and completing a second diffusion; the second diffusion depth is shallower than the first diffusion; Step S104, thermally activating the base material; Step S105, opening an N groove on the surface and depositing a passivation film; Step S106, opening electrode holes on the surface of the substrate material and growing electrodes; the electrode holes are located directly above the diffusion region; Step S107, thermally annealing the entire base material; Step S108, growing a thickened electrode on the electrode.

9. The method for preparing a cascade noise reduction planar avalanche photodiode according to claim 8, characterized in that: The second diffusion hole and the first diffusion hole form concentric circles, and the diameter of the second diffusion hole is smaller than that of the first diffusion hole.

10. The method for preparing a cascade noise reduction planar avalanche photodiode according to claim 8, characterized in that: In step S104 and step S107, the diffusion is a closed tube diffusion of zinc atoms, comprising the steps of: Step S201, depositing a silicon nitride mask on the surface of the substrate material; Step S202, covering the silicon nitride mask with a layer of photoresist; Step S203, transferring the mask pattern of the first diffusion hole or the second diffusion hole onto the silicon nitride mask by photolithography positioning; Step S204, etching on the silicon nitride mask to form the first diffusion hole or the second diffusion hole; Step S205, putting zinc powder into a glass tube, and heating it in a diffusion furnace, so that zinc atoms diffuse downward into the base material through the first diffusion hole or the second diffusion hole.

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