Light detection pixel using vertical gate

Abstract

The invention relates to a light detection pixel using a vertical gate. Various embodiments provide systems, apparatuses, articles, and methods for light detection. In various embodiments, a pixel for detecting light is provided. In various embodiments, the pixel includes a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed inside the substrate; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal. In various embodiments, the first vertical gate and the second vertical gate are configured to direct the one or more charge carriers to the first sensing node or the second sensing node using a first gate control signal and a second gate control signal.

Description

Technical Field

[0001] Example embodiments of the present disclosure generally relate to light detection and, more particularly, to light detection pixels. Background Art

[0002] Light detection pixels are used in various technologies, such as in three-dimensional (3D) and two-dimensional (2D) imaging systems. New developments in technologies using light detection pixels require the pixels to have improved performance. The applicant has recognized many technical challenges and difficulties associated with light detection pixels. Through applied effort, ingenuity, and innovation, the applicant has solved problems associated with light detection pixels by developing the solutions implemented in the present disclosure, which will be described in detail below. Summary of the Invention

[0003] Various embodiments described herein relate to systems, devices, products, and methods for light detection. In various embodiments, a pixel for detecting light is provided. In various embodiments, the pixel includes: a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate deployed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a first sensing node or a second sensing node; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first gate control signal and the second gate control signal.

[0004] In various embodiments, the first vertical gate is configured to be activated using the first gate control signal and, when activated, direct the one or more carriers to the first sensing node; and the second vertical gate is configured to be activated using the second gate control signal and, when activated, direct the one or more carriers to the second sensing node.

[0005] In various embodiments, when the second vertical gate is activated, the first vertical gate is deactivated; and when the first vertical gate is activated, the second vertical gate is deactivated. In various embodiments, the first gate control signal and the second gate control signal include periodic waveforms and are complementary to each other.

[0006] In various embodiments, a pixel includes: a third vertical gate disposed within a substrate; a fourth vertical gate disposed within the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to a first sensing node or a second sensing node; a third gate input electrically coupled to the third vertical gate and configured to receive a third gate control signal; and a fourth gate input electrically coupled to the fourth vertical gate and configured to receive a fourth gate control signal, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to the first sensing node or the second sensing node using the first gate control signal, the second gate control signal, the third gate control signal, and the fourth gate control signal.

[0007] In various embodiments, the pixel further includes: a first deep insulating trench located on a first side of the substrate; and a second deep insulating trench located on a second side of the substrate, wherein the first deep insulating trench and the second deep insulating trench are configured to create a pinned potential at the substrate to deplete the substrate.

[0008] In various embodiments, the first vertical gate and the second vertical gate are configured to be alternately activated using the first gate control signal and the second gate control signal, wherein at a given time the first gate control signal is the complement of the second gate control signal, and wherein the pixel is configured to determine an indirect time of flight (iToF).

[0009] In various embodiments, the first vertical gate and the second vertical gate are configured to be simultaneously deactivated using the first gate control signal and the second gate control signal for a first time period, and for a second time period either the first vertical gate or the second vertical gate is activated, and wherein the pixel is configured to provide two-dimensional imaging.

[0010] In various embodiments, a pixel is provided. The pixel may include: a substrate configured to generate one or more carriers in response to an incident light beam; a first vertical gate and a second vertical gate disposed within the substrate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to a first capacitor or a second capacitor; a first vertical gate input electrically coupled to the first vertical gate and configured to receive a first gate control signal; and a second vertical gate input electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to direct the one or more carriers to the first capacitor or the second capacitor using the first gate control signal and the second gate control signal.

[0011] In various embodiments, a first vertical gate is configured to be activated using a first gate control signal and, when activated, direct the one or more charge carriers to a first capacitor; and a second vertical gate is configured to be activated using a second gate control signal and, when activated, direct the one or more charge carriers to a second capacitor.

[0012] In various embodiments, when the second vertical gate is activated, the first vertical gate is deactivated; and when the first vertical gate is activated, the second vertical gate is deactivated. In various embodiments, the first gate control signal and the second gate control signal include periodic waveforms and are complementary to each other.

[0013] According to various embodiments of the present disclosure, a method is provided. The method may include: deploying a first vertical gate and a second vertical gate inside a substrate, wherein the first vertical gate and the second vertical gate are configured to direct one or more charge carriers to a first sensing node or a second sensing node, wherein the one or more charge carriers are generated inside the substrate in response to an incident light beam; configuring a first vertical gate input terminal to receive a first gate control signal, wherein the first vertical gate input terminal is electrically coupled to the first vertical gate; and configuring a second vertical gate input terminal to receive a second gate control signal, wherein the second vertical gate input terminal is electrically coupled to the second vertical gate, wherein the first vertical gate and the second vertical gate are configured to direct the one or more charge carriers to the first sensing node or the second sensing node using the first gate control signal and the second gate control signal.

[0014] In various embodiments, the method includes: configuring the first vertical gate to be activated using the first gate control signal and, when the first vertical gate is activated, directing the one or more charge carriers to the first sensing node; and configuring the second vertical gate to be activated using the second gate control signal and, when the second vertical gate is activated, directing the one or more charge carriers to the second sensing node.

[0015] In various embodiments, the method includes: configuring the first vertical gate to be deactivated when the second vertical gate is activated; and configuring the second vertical gate to be deactivated when the first vertical gate is activated. In various embodiments, the first gate control signal and the second gate control signal include periodic waveforms and are complementary to each other.

[0016] In various embodiments, the method includes: deploying a third vertical gate inside a substrate; deploying a fourth vertical gate inside the substrate, wherein the first vertical gate, the second vertical gate, and the fourth vertical gate are configured to direct the one or more carriers to a first sensing node or a second sensing node; electrically coupling a third gate input terminal to the third vertical gate to receive a third gate control signal; electrically coupling a fourth gate input terminal to the fourth vertical gate to receive a fourth gate control signal; and directing the one or more carriers to the first sensing node or the second sensing node using the first gate control signal, the second gate control signal, the third gate control signal, or the fourth gate control signal.

[0017] In various embodiments, the method includes: deploying a first deep insulating trench on a first side of a substrate; and deploying a second deep insulating trench on a second side of the substrate, wherein the first deep insulating trench and the second deep insulating trench are configured to create a pinned potential at the substrate to deplete the substrate.

[0018] In various embodiments, the method includes alternately activating the first vertical gate and the second vertical gate using the first gate control signal and the second gate control signal, wherein at a given time, the first gate control signal is the complement of the second gate control signal.

[0019] In various embodiments, the method includes: electrically coupling a first sensing node to a first supplementary capacitor; electrically coupling a second sensing node to a second supplementary capacitor; and configuring the first supplementary capacitor and the second supplementary capacitor to determine an indirect time-of-flight or a two-dimensional density image using a first charge value of the first supplementary capacitor and a second charge value of the second supplementary capacitor.

[0020] The foregoing summary of the invention is only for the purpose of outlining some example embodiments to provide a basic understanding of some aspects of the present disclosure. It should, therefore, be appreciated that the above embodiments are merely examples and should not be construed as limiting the scope or spirit of the present disclosure in any way. It should also be appreciated that the scope of the present disclosure covers many potential embodiments in addition to the embodiments summarized herein, some of which will be further described below. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Certain example embodiments of the present disclosure have been generally described above and will now be described with reference to the drawings, which are not necessarily drawn to scale, wherein:

[0022] Figure 1 is a schematic diagram illustrating an iToF determination system.

[0023] Figure 2 is a schematic diagram illustrating a pixel.

[0024] Figure 3It is a schematic diagram showing pixels according to various embodiments of the present disclosure.

[0025] Figure 4 It is a schematic diagram showing the operation of pixels according to various embodiments of the present disclosure.

[0026] Figure 5A It is a schematic diagram showing pixels according to various embodiments of the present disclosure.

[0027] Figure 5B It is a schematic diagram showing pixels according to various embodiments of the present disclosure.

[0028] Figure 5C It is a schematic diagram showing pixels according to various embodiments of the present disclosure.

[0029] Figure 5D It is a schematic diagram showing pixels according to various embodiments of the present disclosure.

[0030] Figure 5E It is a schematic diagram showing pixels according to various embodiments of the present disclosure.

[0031] Figure 5F It is a schematic diagram showing pixels according to various embodiments of the present disclosure.

[0032] Figure 6 It is a flowchart showing a method according to various embodiments of the present disclosure.

[0033] Figure 7 It is a flowchart showing a method according to various embodiments of the present disclosure.

[0034] Figure 8 An example computing device according to one or more embodiments of the present disclosure is illustrated. Detailed Description

[0035] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings, in which some, but not all, embodiments of the present disclosure are shown. In fact, the various embodiments of the present disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals always denote like elements.

[0036] Phrases such as "in one embodiment", "according to one embodiment", "in some embodiments", "in various embodiments", etc. generally mean that the specific features, structures, or characteristics following the phrase may be included in at least one embodiment of the present disclosure and may be included in more than one embodiment of the present disclosure (importantly, such phrases do not necessarily refer to the same embodiment).

[0037] As used herein, the terms "example" or "exemplary" are used to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

[0038] If the specification states that a component or feature "may," "is capable of," "might," "should," "would," "preferably," "has the potential to," "generally," "optionally," "for example," "often," or "may" (or other similar language) be included or have a characteristic, then that particular component or feature is not required to be included or have that characteristic. In some embodiments, such a component or feature may optionally be included or may be excluded.

[0039] The terms "electrically coupled," "communicate with," "electronically communicate with," or "connected" in this disclosure mean that two or more elements or components are connected by wired means and / or wireless means such that signals, voltage / current, data, and / or information can be sent to and / or received from these elements or components.

[0040] Various embodiments of the present disclosure are directed to improved systems, devices, products, and methods for optical detection, such as by using an improved optical detection system. In various embodiments, the optical detection system can be used in 3D imaging, such as using indirect time-of-flight (iToF) measurements.

[0041] In 3D imaging, the distance to an object can be determined. One method of measuring the distance to an object is time-of-flight (ToF) measurement. In a ToF system, the time it takes for a measurement beam to travel from a transmitter to an object and back to a detector is measured. Using the speed of light and the propagation time, the distance to the object can be measured.

[0042] In an indirect time-of-flight (iToF) system, the phase shift of the received beam relative to the transmitted beam is used to indirectly measure the distance to an object.

[0043] Now referring Figure 1 , a schematic diagram illustrating an indirect time-of-flight (iToF) measurement system 100 is provided. The iToF measurement system 100 includes a transmitter 102 configured to transmit a beam 104 having, for example, a sine wave 106. In an example, the transmitted beam 104 can be an intensity-modulated continuous wave. The transmitted beam can be reflected from an object 108. The reflected beam 110 will be detected by a pixel 112. In various embodiments, the pixel 112 is an optical detection pixel.

[0044] To determine the phase shift between the reflected beam and the transmitted beam, the pixel 112 can reconstruct its sine wave after detecting the reflected beam 110.

[0045] To reconstruct the sine wave, the pixel 112 samples the detected light beam. When the light beam is received by the pixel 112, the pixel generates electron carriers (e) and holes (h). The carriers are sampled using switches S1 and S2 and directed to the corresponding sensing node SN1 or SN2 for detection.

[0046] The carriers detected at the sensing nodes SN1 and SN2 charge the corresponding capacitors. For example, the sensing node SN1 charges the first capacitor 122, and the sensing node SN2 charges the second capacitor 124. The controller 114 can compare the charges stored at the capacitors to reconstruct the phase value of the reflected light beam.

[0047] The sensing nodes SN1 and SN2 may be floating nodes, and the voltage of the sensing nodes may need to be reset after each detection cycle to prepare for another charge acquisition and measurement. Switches 116 and 118 may use a reset signal to reset the voltage to V DC .

[0048] In some examples, the emitted light beam may be in a near infrared (NIR) wavelength range of 800nm-1100nm, for example 940nm. In some examples, the emitted light beam may be in a short wave infrared (SWIR) wavelength range of 1100nm-3000nm. Therefore, suitable materials in the pixel 112 may be used to detect light beams in the corresponding wavelength range. For example, silicon has good absorption in the NIR wavelength range and can be used in pixels 112 for iToF and other imaging systems. Other materials (such as Ge, InGaAs) may be used in the SWIR wavelength range.

[0049] Reference now Figure 2 , a schematic diagram illustrating a pixel 200 according to various embodiments that have been used is provided. The pixel 200 may include a substrate 202. In various embodiments, the substrate 202 is a silicon substrate. The pixel 200 includes a PN junction 208 located at the center of the pixel between a first planar gate 204 and a second planar gate 206. The PN junction 208 may be created, for example, by an N well 210. The N well 210 may be an N implant region located approximately at the center of the pixel 200.

[0050] When the light beam is incident on the substrate 202, carriers are generated in the substrate 202. The PN junction 208 creates an electrostatic potential gradient that transfers the carriers to the top of the pixel. By switching between activation of the first planar gate 204 and the second planar gate 206, the charge is driven to the first sense node 212 or the second sense node 214. The first and second planar nodes can be controlled using an AC signal V AC is activated.

[0051] The first and second sensing nodes can be electrically coupled to the N+ regions of the semiconductor. The N+ regions can have a high concentration of N-type impurity dopants. In an example, the N+ regions can reduce the contact resistance with the sensing nodes. For example, the N+ regions can be N-fuse diffusions doped with arsenic or phosphorus.

[0052] Now referring Figure 3 , there is provided a schematic diagram illustrating a pixel 300 according to various embodiments of the present disclosure. In various embodiments, the pixel 300 includes a substrate 302. The substrate 302 can be configured to generate one or more carriers in response to an incident light beam (e.g., the reflected light beam 110). In various embodiments, the pixel 300 includes a transparent layer 322 at the surface of the substrate 302, at which surface the substrate is configured to absorb the incident light beam. The transparent layer 322 can include any of an anti-reflection layer, a lens, a microlens array, etc.

[0053] In various embodiments, the pixel 300 includes a first vertical gate 304 and a second vertical gate 306 disposed inside the substrate. In various embodiments, the first vertical gate 304 and the second vertical gate 306 are implanted in the substrate 302. The first vertical gate 304 and the second vertical gate 306 can be deep trenches disposed inside the substrate 302.

[0054] In an example embodiment, when operating in the NIR wavelength range, the height of the substrate can be between 5 microns and 12 microns. In an example embodiment, the depth of the first vertical gate 304 and the second vertical gate 306 can be between 0.3 microns and 2 microns, such as 1 micron. In an example embodiment, if a material different from silicon with higher absorbability is used, then the height of the substrate can be smaller. In various embodiments, the height of the general vertical gate can be between about 5% and 30% of the substrate height.

[0055] In various embodiments, the first and second vertical gates are used for the effective transfer of carriers from the substrate 302 to the first sensing node 310 and the second sensing node 312.

[0056] In various embodiments, the first vertical gate 304 and the second vertical gate 306 are activated using a first gate control signal applied to the first vertical gate input terminal 314 and a second gate control signal applied to the second vertical gate input terminal 316. In various embodiments, the first and second vertical gates are configured to direct one or more carriers to the first sensing node 310 or the second sensing node 312 using the first and second gate control signals.

[0057] For example, by alternately activating the first and second vertical gates, a potential is generated in the substrate 302, and one or more carriers are directed from a lower region of the substrate 302 to a higher region, such as region 308 of the substrate closer to the vertical gates. In various embodiments, due to the appropriate doping profile of the substrate 302 and due to the potentials applied to the deep insulating trenches 324 and 326, a potential is also generated in the generation region 308, as further described below. In various embodiments, when the first vertical gate 304 is activated, carriers are directed in the direction towards the first vertical gate and the first sensing node. When the second vertical gate 306 is activated, carriers are directed in the direction towards the second vertical gate and the second sensing node.

[0058] In an example embodiment, pixel 300 directs carriers to the corresponding sensing nodes without a P-N junction created by deep N implantation (e.g., as described with respect to pixel 200). By not requiring an N well, various embodiments provide a reduction in process variations for fabricating pixels, while increasing the transfer efficiency of carriers to the sensing nodes. Reducing process variations for fabricating pixels can reduce mismatches and / or inconsistencies between individual pixels in a pixel array or matrix.

[0059] In various embodiments, when the second vertical gate is activated, the first vertical gate is deactivated, and when the first vertical gate is activated, the second vertical gate is deactivated. The vertical gates can be activated using a periodic signal generated by a voltage and / or current source 320. Source 320 can generate a first gate control signal and a second gate control signal. The first and second control signals can have a periodic waveform and can be complementary to each other. For example, at a given time, the first gate control signal applied to the input of the first vertical gate can have a high value, while the second gate control signal applied to the input of the second vertical gate will have a low value.

[0060] In an example embodiment, pixel 300 provides a more homogeneous electrostatic potential in the substrate, for example as compared to pixel 200, which has a gradient that is towards the vertical gates and then towards the corresponding sensing nodes when each vertical gate is activated.

[0061] In various embodiments, the first and second sensing nodes are floating junctions, and the voltages they generate will change as carriers are directed to each sensing node. This can be because each sensing node has an inherent capacitance, and when carriers are transferred to the corresponding sensing node, the charge of the inherent capacitance and its corresponding voltage can change. In various embodiments, the inherent capacitance of each sensing node is supplemented using an external capacitance. In various embodiments, when pixel 300 is used as an iToF pixel, the charge accumulated on each sensing node and / or on a supplementary capacitor electrically coupled in parallel with the sensing node is measured for iToF determination, as described, for example, with reference to Figure 1 as described.

[0062] In various embodiments, by switching between activations of the vertical gates, the pixel alternates between charge collection at the first and second sensing nodes. By doing so over a period of time, the controller 114 can integrate the first charge collection on the first sensing node and the second charge collection on the second sensing node. Using the integrated values, a reconstruction of the phase shift suffered when a light beam is reflected from an object and received by the pixel is determined.

[0063] In various embodiments, by faster alternating between charge collections at different sensing nodes, the pixel 300 can provide a more accurate measurement of the phase shift of the reflected signal for iToF determination. In an example embodiment, for example compared to the pixel 200, the pixel 300 enables the vertical gates to be activated and deactivated at a higher frequency, and thus enables faster alternating of charge collection at the first and second sensing nodes to achieve a more accurate iToF measurement.

[0064] In various embodiments, by deeply etching the vertical gates in the substrate of the pixel 300, a higher driving potential is created in the substrate volume, thus more efficiently guiding carriers to the sensing nodes with a lower amplitude requirement for the gate control signal.

[0065] In various embodiments, the pixel 300 includes a first deep insulating trench 324 and a second deep insulating trench 326. The deep insulating trenches can extend as deep as the substrate. In various embodiments, the substrate can be completely surrounded by a plurality of deep insulating trenches.

[0066] In various embodiments, the first deep insulating trench 324 and the second deep insulating trench 326 create a pining potential at the substrate to deplete the substrate. In various embodiments, a DC voltage signal can be applied to the deep insulating trenches to create the pining potential.

[0067] In an example embodiment, using the vertical gates and the deep insulating trenches, a uniform electrostatic field can be generated in the substrate from bottom to top to guide the carriers to the top, and then guide the carriers near the top in an appropriate direction to the appropriate sensing node according to which vertical gate is activated.

[0068] In various embodiments, the deep insulating trenches create a lateral gradient of the electrostatic field to deplete the substrate volume, and the vertical gates create a vertical gradient of the electrostatic field that is upward and reaches the sensing node corresponding to the vertical gate activated at a given time.

[0069] In various embodiments, the deep insulating trenches and the vertical gates utilize a dielectric liner (e.g., SiO 2 or HK material, HfO 2 、Al2 O 3 etc.), and then filled with a conductive material (e.g., doped polysilicon or a metal such as Al, W, Ag, etc.). In various embodiments, the substrate is made of silicon, Ge, InGaAs, etc., as described above.

[0070] Now refer to Figure 4 , which provides a schematic diagram illustrating examples of the operation of pixel 300 according to various embodiments of the present disclosure in three-dimensional (3D) imaging or iToF measurement and in two-dimensional (2D) imaging. As Figure 4 shown, line 402 is a schematic diagram of the electrostatic potential level in pixel 300 according to various embodiments.

[0071] In various embodiments, pixel 300 can operate in 3D imaging or iToF mode. When in iToF mode, the first vertical gate and the second vertical gate of the pixel can be configured to be alternately activated using a first gate control signal and a second gate control signal. In various embodiments, at a given time, the first control signal is the complement of the second control signal.

[0072] In various embodiments, when the first vertical gate is disabled, it creates a low gate that acts as a barrier between the carriers in the integration region (e.g., Figure 3 region 308 therein) and the first sensing node. In iToF mode, when the first vertical gate is disabled, the second vertical gate can be activated. When the second vertical gate is activated, it creates a high gate that acts as a potential gradient to guide the carriers to the second sensing node. By alternately activating and disabling the first gate and / or the second gate, when operating in iToF mode, pixel 300 alternately guides the charge to the corresponding first or second sensing node.

[0073] In an exemplary embodiment, by not using a P-N junction or an N-well in the integration region, the activation and / or deactivation of the first and second gates in pixel 300 can be performed at a higher frequency and with a lower amplitude. Therefore, the accuracy of the measurement can be increased, and the power consumption of the pixel can be reduced.

[0074] In various embodiments, pixel 300 can operate in 2D imaging, such as using light intensity acquisition. When operating in 2D imaging, for a first time period, the first vertical gate and the second vertical gate can be configured to be simultaneously disabled, and this first time period can be referred to as the integration time. Then, for a second time period, the first vertical gate or the second vertical gate can be activated, and this second time period can be referred to as the readout time. In various embodiments, the vertical gates are activated and deactivated using the first and second gate control signals.

[0075] During the integration period, the first and second vertical gates can be deactivated to create a low gate that acts as a barrier between the carriers in the integration region of the substrate (e.g., Figure 3 region 308 in

[0076] ), and the first and second sense nodes. Thus, during the integration region, charge is integrated in the integration region. In various embodiments, the barrier created during the integration period can be a stronger barrier than the barrier created during the iToF mode to allow for greater charge accumulation for 2D imaging.

[0077] During the readout period, either the first or second vertical gate can be activated. When the vertical gate is activated, it creates a high gate that acts as a potential gradient that guides the integrated carriers to the corresponding sense node for readout representing the 2D image captured in the pixel.

[0078] In an example embodiment, greater carrier integration in the integration region can be achieved by not using a P-N junction or an N-well in the integration region. Using vertically implanted gates deep in the pixel can allow for the provision of gates with very low bias, thereby creating a significantly low gate barrier and allowing for the storage of a significantly large number of carriers in the volume of the pixel.

[0079] Now referring to Figure 5A , a schematic diagram illustrating a pixel 500 is provided in accordance with various embodiments of the present disclosure. In various embodiments, the pixel 500 includes a first vertical gate 504, a second vertical gate 506, a third vertical gate 508, and a fourth vertical gate 510 disposed inside a substrate 502. In various embodiments, the vertical gates are implanted in the substrate 502. The vertical gates can be deep trenches disposed inside the substrate 502.

[0080] In various embodiments, the first, second, third, and fourth vertical gates are configured to guide one or more carriers generated inside the substrate 502 in response to an incident light beam to a first sense node 522 or a second sense node 524. In various embodiments, the first and second vertical gates are configured to guide one or more carriers to the first sense node 522, while the third and fourth vertical gates are configured to guide one or more carriers to the second sense node 524.

[0081] In various embodiments, a first sensing node may be deployed near the first and second vertical gates, while a second sensing node may be deployed near the third and fourth vertical gates. For example, the first sensing node may be deployed between the first and second vertical gates, while the second sensing node may be deployed between the third and fourth vertical gates.

[0082] In various embodiments, the first vertical gate is electrically coupled to a first vertical gate input 514 and configured to receive a first gate control signal. In various embodiments, the second vertical gate is electrically coupled to a second vertical gate input 516 and configured to receive a second gate control signal. In various embodiments, a third gate input 518 is electrically coupled to the third vertical gate and configured to receive a third gate control signal. In various embodiments, a fourth gate input 520 is electrically coupled to the fourth vertical gate and configured to receive a fourth gate control signal. Figure 5B is a schematic diagram showing the arrangement of components in a top view.

[0083] In various embodiments, the first, second, third, and fourth vertical gates are configured to use the first, second, third, and fourth gate control signals to direct one or more carriers to the first sensing node or the second sensing node. In an example embodiment, when the first and / or second vertical gates are activated using the first and / or second gate control signals, carriers are directed to the first sensing node. In an example embodiment, when the third and / or fourth vertical gates are activated using the third and / or fourth gate control signals, carriers are directed to the second sensing node.

[0084] In various embodiments, the first and second vertical gates may be activated and deactivated in a manner similar to and at the same frequency as the third and fourth vertical gates. In various embodiments, each vertical gate may be activated and / or deactivated at various frequencies and / or with a certain time shift relative to each other to provide a higher sampling rate of the reflected light beam in iToF determination.

[0085] In various embodiments, the pixel 500 may include a first deep insulating trench 526 on a first side of the substrate 502 and a second deep insulating trench 528 on a second side of the substrate. The first and second deep insulating trenches may be configured to create a pinned potential at the substrate to deplete the substrate.

[0086] In various embodiments, any number of two or more vertical gates and / or any arrangement of the vertical gates relative to the first and second sensing nodes may be used. For example, the vertical gates and the sensing nodes and their corresponding N+ regions may be arranged in a single line, as Figure 5AAs shown. In various embodiments, the first set of vertical gates guides carriers from the substrate to the first sensing node, while the second set of vertical gates guides carriers to the second sensing node. The first sensing node may be deployed near the first set of vertical gates, and the second sensing node may be deployed near the second set of vertical gates. For example, the first and second vertical gates may be the first set of vertical gates, and the third and fourth vertical gates may be the second set of vertical gates.

[0087] For example, referring to Figure 5C , a schematic diagram 550 is provided that illustrates the arrangement of vertical gates relative to sensing nodes in pixels according to various embodiments of the present disclosure. Schematic diagram 550 illustrates the arrangement of components from a top view.

[0088] In various embodiments, the first vertical gate 504, the second vertical gate 506, the first sensing node 522, and the N+ region corresponding to the first node may be arranged in a first line, while the third vertical gate 508, the fourth vertical gate 510, the second sensing node 524, and the N+ region corresponding to the second sensing node may be arranged in a second line. In various embodiments, the first line and the second line may be approximately parallel.

[0089] In various embodiments, when more than one vertical gate corresponds to each sensing node, as for example Figure 5A - 5C shown, at least one of the vertical gates corresponding to each sensing node may be electrically coupled to and biased with the same DC bias voltage. Other vertical gates corresponding to the sensing nodes may be operated using complementary and variable gate control signals as described above. For example, the vertical gates 504 and 510 may be electrically coupled to and biased with the same DC bias voltage, while the vertical gates 506 and 508 may be electrically coupled to and biased with complementary AC bias signals. In an example embodiment, the DC bias signal applied to at least one of the vertical gates may also facilitate guiding one or more carriers from a lower region of the substrate (e.g., region 302) to a higher region of the substrate (e.g., region 308) closer to the vertical gates and the sensing nodes.

[0090] In various embodiments, the vertical gates can have various cross-sectional shapes. For example, at least one or all of the first, second, third, or fourth vertical gates can have various cross-sectional shapes around the corresponding sense nodes and can completely or partially surround the corresponding sense nodes. In various embodiments, at least one or all of the vertical gates can partially surround the sense nodes, for example, by having a C cross-sectional shape, an F cross-sectional shape, or an h cross-sectional shape. In various embodiments, at least one or all of the vertical gates can completely surround the corresponding sense nodes, for example, by having a circular (e.g., O) cross-sectional shape or a b cross-sectional shape that surrounds the corresponding sense nodes. In various embodiments, when more than one vertical gate corresponds to a sense node, the vertical gates that completely or partially surround the sense node can be concentric or eccentric with respect to each other.

[0091] For example, now referring to Figure 5D , there is provided a schematic diagram 555 illustrating a first vertical gate 556 and a second vertical gate 558 according to various embodiments of the present disclosure. As shown in Figure 5D , the vertical gates can partially surround the sense nodes 522 and 524. As shown in the example of Figure 5D , the vertical gates have a cross-section in the shape of a square that partially surrounds the sense nodes, but the vertical gates can have a circular cross-sectional shape, such as a partial circle (e.g., C-shaped) or a partial oval shape.

[0092] For example, now referring to Figure 5E , there is provided a schematic diagram 560 illustrating a first vertical gate 566 and a second vertical gate 568 according to various embodiments of the present disclosure. As shown in Figure 5E , the vertical gates can partially surround the sense nodes 522 and 524 and have extensions 567 and 569, for example, for electrically coupling to a first vertical gate input 565 and a second vertical gate input 564, respectively. As shown in the example of Figure 5E , the vertical gates have a cross-section in the shape of a square that partially surrounds the sense nodes, but the vertical gates can have a circular cross-sectional shape that partially surrounds the sense nodes, such as a partial circle or a partial oval shape.

[0093] For example, now referring to Figure 5F , there is provided a schematic diagram 570 illustrating a first vertical gate 576 and a second vertical gate 578 according to various embodiments of the present disclosure. As shown in Figure 5F , the vertical gates can completely surround the sense nodes 522 and 524. As shown in the example of Figure 5F , the vertical gates have a cross-section in the shape of a square that completely surrounds the sense nodes, but the vertical gates can have a circular cross-sectional shape, such as a circle (e.g., annular) or an oval shape.

[0094] In an example embodiment, the vertical gates provided herein can have a higher driving capability throughout the volume of the pixel substrate than planar gates. For example, a small difference in the electrostatic potential between the vertical gates can provide for the transfer of charge to the corresponding sensing nodes, thereby increasing the efficiency of the pixel by requiring a lower amplitude of the gate control signal needed to operate the pixel.

[0095] In an example embodiment, the use of vertical gates and their higher driving capability can enable an increase in the volume of the substrate without degrading the frequency performance of the pixel. For example, due to the uniform and strong electrostatic field gradient generated by the vertical gates and the resulting strong driving force on the charge carriers, the use of vertical gates increases the quantum efficiency (QE) of the pixel by increasing the thickness of the volume of the substrate silicon without degrading performance. In an example embodiment, QE can represent the ratio of the total charge carriers measured by the sensing nodes of the pixel to the total incident photons on the pixel. In an example embodiment, the use of vertical gates can also maintain a high demodulation contrast (DMC) in the pixel. DMC can indicate an estimate of the rate at which the pixel collects and / or detects photons at the operating frequency.

[0096] Now referring to Figure 6 , a schematic diagram of a method 600 in accordance with various embodiments of the present disclosure is illustrated. In various embodiments, the method 600 can be used to fabricate and / or prepare a light detection pixel, such as the pixel 300 described above. In various embodiments, at step 602, the method 600 disposes a first vertical gate 304 and a second vertical gate 306 inside a substrate 302. In various embodiments, the first and second vertical gates are configured to direct one or more charge carriers to a first sensing node 310 or a second sensing node 312. In various embodiments, in response to an incident light beam on the pixel (which can be the reflected light beam 110), one or more charge carriers are generated inside the substrate.

[0097] In various embodiments, at step 604, the method 600 configures a first vertical gate input 314 to receive a first gate control signal. The first vertical gate input can be electrically coupled to the first vertical gate.

[0098] In various embodiments, at step 606, the method 600 configures a second vertical gate input 316 to receive a second gate control signal. The second vertical gate input can be electrically coupled to the second vertical gate. In various embodiments, the first and second vertical gates are configured to direct one or more charge carriers to the first sensing node or the second sensing node using the first and second gate control signals. In an example embodiment, the first and second sensing nodes have an inherent capacitance and are the first and second sensing nodes. In various embodiments, the capacitance of the first and second sensing nodes is supplemented by an external capacitor, such as as shown and described above in Figure 1 .

[0099] Now referring to Figure 7 FIG. [FIG. number not provided in the original, so it remains as Figure 7 ], which illustrates a schematic diagram of a method 700 according to various embodiments of the present disclosure. In various embodiments, the method 700 can be used to fabricate and / or prepare a photodetection pixel, such as the pixel 300 described above. In various embodiments, at step 702, the method 700 configures a first vertical gate to be activated using a first gate control signal and directs one or more carriers to a first sensing node when the first vertical gate is activated.

[0100] In various embodiments, at step 704, the method 700 configures a second vertical gate to be activated using a second gate control signal and directs one or more carriers to a second sensing node when the second vertical gate is activated.

[0101] In various embodiments, at step 706, the method 700 configures the first vertical gate to be deactivated when the second vertical gate is activated. In various embodiments, at step 708, the method 700 configures the second vertical gate to be deactivated when the first vertical gate is activated. In various embodiments, the method 700 uses a periodic first gate control signal and a periodic second gate control signal to activate and deactivate the vertical gates, where the first and second gate control signals are complementary to each other as described above. Thus, in various embodiments, the first and second control signals include periodic waveforms and are complementary to each other.

[0102] In various embodiments, the method 700 can include deploying a third vertical gate inside the substrate and deploying a fourth vertical gate inside the substrate, where the first, second, and fourth vertical gates are configured to direct one or more carriers to the first sensing node or the second sensing node. In various embodiments, the method 700 can include electrically coupling a third gate input terminal to the third vertical gate to receive a third gate control signal and electrically coupling a fourth gate input terminal to the fourth vertical gate to receive a fourth gate control signal. In various embodiments, the method 700 can include using the first, second, third, or fourth gate control signal to direct one or more carriers to the first sensing node or the second sensing node.

[0103] In various embodiments, the method 700 can include deploying a first deep insulating trench on a first side of the substrate and deploying a second deep insulating trench on a second side of the substrate, where the first and second deep insulating trenches are configured to create a pinned potential at the substrate to deplete the substrate.

[0104] In various embodiments, method 700 may include alternately activating a first vertical gate and a second vertical gate using a first gate control signal and a second gate control signal, where the first control signal is the complement of the second control signal at a given time. In various embodiments, method 700 may include determining an indirect time of flight using a first charge value of a first intrinsic capacitance of a first sense node and a second charge value of an intrinsic capacitance of a second sense node.

[0105] In various embodiments, method 700 may include electrically coupling the first sense node to a first supplementary capacitor and electrically coupling the second sense node to a second supplementary capacitor, as, for example, referenced Figure 1 as shown. In various embodiments, method 700 may include configuring the first and second supplementary capacitors to determine an indirect time of flight or a two-dimensional density image using a first charge value of the first supplementary capacitor and a second charge value of the second supplementary capacitor.

[0106] It should be readily appreciated that, in addition to the ways explicitly described herein, various additional and alternative ways may be employed to configure embodiments of the systems, devices, and methods described herein.

[0107] Figure 8 An example light detection system 800 in accordance with one or more embodiments of the present disclosure is illustrated.

[0108] The light detection system 800 may include a computing device 810 and / or one or more light detection pixels 820 communicatively coupled to the computing device 810 using one or more wired and / or wireless communication technologies. Generally, the terms computing device, computer, system, device, entity, and / or similar words that may be used interchangeably herein may refer to, for example, one or more computers, computing entities, desktops, mobile phones, tablets, notebooks, laptop computers, distributed systems, kiosks, input terminals, servers or server networks, blade servers, gateways, switches, processing devices, processing entities, controllers, control systems, set-top boxes, repeaters, routers, network access points, base stations, etc. and / or any combination of devices or entities suitable for performing the functions, operations, and / or processes described herein. Such functions, operations, and / or processes may include, for example, sending, receiving, operating, processing, displaying, storing, determining, creating / generating, monitoring, evaluating, comparing, and / or similar terms that may be used interchangeably herein. In one embodiment, these functions, operations, and / or processes may be performed on data, content, information, and / or similar terms that may be used interchangeably herein. The computing device 810 may include any computing device, including, for example, a light detection processing device configured to perform one or more steps / operations of one or more light detection techniques described herein. In some examples, the computing device 810 may determine indirect time-of-flight (iToF) as described herein. In some examples, the computing device 810 may detect a 2D image as described herein. In some embodiments, the computing device 810 may include one or more mobile devices, (one or more) desktop computers, (one or more) laptop computers, (one or more) servers, and / or (one or more) cloud computing platforms, etc., and / or be associated therewith. In some example embodiments, the computing device 810 may be configured to receive and / or send light detection instructions, data, etc. between one or more light detection pixels 820 to perform one or more steps / operations of one or more light detection techniques described herein.

[0109] The computing device 810 may include one or more processing elements 802 (also referred to as processors, processing circuitry, digital circuitry, and / or similar terms that may be used interchangeably herein), or communicate with one or more processing elements 802, which communicate with other elements within the computing device 810 via, for example, a bus. As will be understood, the processing element 802 may be implemented in a variety of different ways.

[0110] For example, processing element 802 may be implemented as one or more complex programmable logic devices (CPLDs), microprocessors, multi-core processors, coprocessing entities, application specific instruction set processors (ASIPs), microcontrollers, and / or controllers. Additionally, processing element 802 may be implemented as one or more other processing devices or circuitry. The term circuitry may refer to an all-hardware embodiment or a combination of hardware and a computer program product. Thus, processing element 802 may be implemented as an integrated circuit, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, and / or a digital circuitry, among others.

[0111] Thus, as will be appreciated, processing element 802 may be configured for a particular purpose or configured to execute instructions stored in a volatile or non-volatile medium or otherwise accessible to processing element 802. Accordingly, whether configured by hardware or a computer program product or by a combination thereof, processing element 802, when appropriately configured, is capable of performing the steps or operations in accordance with embodiments of the present disclosure.

[0112] In one embodiment, computing device 810 may also include or communicate with one or more memory elements 104. The one or more memory elements 104 may include non-volatile and / or volatile media. For example, memory element 804 may include non-volatile media (also referred to as non-volatile storage devices, memories, memory storage devices, memory circuitry, and / or similar terms used interchangeably herein). In one embodiment, non-volatile storage devices or memories may include one or more non-volatile storage device or memory media, including but not limited to: hard disks, ROMs, PROMs, EPROMs, EEPROMs, flash memories, MMCs, SD memory cards, memory sticks, CBRAMs, PRAMs, FeRAMs, NVRAMs, MRAMs, RRAMs, SONOSs, FJG RAMs, Millipede memories, and / or racetrack memories, among others.

[0113] As will be recognized, non-volatile storage devices or memory media may store databases, database instances, database management systems, data, applications, programs, program modules, scripts, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, among others. The terms database, database instance, database management system, and / or similar terms used interchangeably herein may refer to a collection of records or data stored in a computer-readable storage medium using one or more database models such as hierarchical database models, network models, relational models, entity-relationship models, object models, document models, semantic models, and / or graph models, among others.

[0114] Additionally or alternatively, the memory element 804 may include volatile memory. For example, the computing device 810 may also include a volatile medium (also referred to as volatile memory, memory storage, memory circuitry, and / or similar terms that may be used interchangeably herein) or communicate with the volatile medium. In one embodiment, the volatile storage device or memory may also include one or more volatile storage devices or memory media, including but not limited to: RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, TTRAM, T-RAM, Z-RAM, RIMM, DIMM, SIMM, VRAM, cache memory, and / or register memory, etc.

[0115] As will be appreciated, the volatile storage device or memory medium may be used to store at least a portion of a database, database instance, database management system, data, application, program, program module, script, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, etc., executed by, for example, the processing element 802. Accordingly, the database, database instance, database management system, data, application, program, program module, script, source code, object code, byte code, compiled code, interpreted code, machine code, and / or executable instructions, etc., may be used to control certain aspects of the operation of the computing device 810 with the help of the processing element 802 and the operating system.

[0116] As indicated, in one embodiment, computing device 810 may also include one or more communication interfaces 808 for communicating with various computing entities by, for example, transmitting data, content, information, and / or similar terms that may be used interchangeably herein, such as data that may be sent, received, operated on, processed, displayed, and / or stored. Such communication may be performed using a wired data transmission protocol (such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Cable Data Service Interface Specification (DOCSIS), or any other wired transmission protocol). Similarly, computing device 810 may be configured to communicate via a wireless external communication network using any of a variety of protocols, such as General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Time Division - Synchronous Code Division Multiple Access (TD - SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E - UTRAN), Evolution - Data Optimized (EVDO), High - Speed Packet Access (HSPA), High - Speed Downlink Packet Access (HSDPA), IEEE 802.11 (Wi - Fi), Wi - Fi Direct, 802.16 (WiMAX), Ultra - Wideband (UWB), Infrared (IR) protocol, Near - Field Communication (NFC) protocol, Wibree, Bluetooth protocol, Wireless Universal Serial Bus (USB) protocol, and / or any other wireless protocol.

[0117] The light detection system 800 may include input / output circuitry for communicating with one or more users or other systems or devices. For example, the input / output circuitry may include one or more interfaces for providing and / or receiving information with one or more users of the light detection system 800 or other systems or devices, or vice versa. The input / output circuitry may be configured to receive user input or input from various other systems or devices through one or more interfaces of the light detection system 800.

[0118] Conclusion

[0119] Those skilled in the art will envision many modifications and other embodiments of the disclosure described herein after benefiting from the foregoing description and the teachings presented in the associated drawings. Although the figures only show certain components of the devices and systems described herein, it should be understood that various other components may be used in conjunction with the systems. Accordingly, it should be understood that the disclosure is not limited to the specific embodiments disclosed and is intended to include modifications and other embodiments within the scope of the appended claims. The steps in the foregoing methods need not occur in the order depicted in the drawings, and in some instances, one or more of the depicted steps may occur substantially simultaneously or may involve additional steps. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

[0120] Although various embodiments in accordance with the principles disclosed herein have been shown and described above, those skilled in the art may make modifications thereto without departing from the spirit and teachings of the disclosure. The embodiments described herein are merely representative and are not intended to be limiting. Many variations, combinations, and modifications are possible and are within the scope of the disclosure. Alternative embodiments resulting from combining, integrating, and / or omitting features of (one or more) embodiments are also within the scope of the disclosure. Accordingly, the scope of protection is not limited by the foregoing description.

[0121] Furthermore, the section headings used herein are provided to be consistent with the recommendations of 37 C.F.R. 1.77 or to otherwise provide organizational cues. These headings should not limit or characterize the disclosure(s) set forth in any claims that may issue from the present disclosure.

[0122] The use of broader terms such as "comprising," "including," and "having" should be understood to support narrower terms such as "consisting of," "consisting essentially of," and "substantially consisting of." The use of terms such as "optionally," "may," "might," "could" with respect to any element of an embodiment indicates that the element is not required, or alternatively, that the element is required, with both alternatives being within the scope of (one or more) embodiments. Additionally, the reference to examples is for illustrative purposes only and is not intended to be exclusive.

[0123] Although this detailed description has set forth some embodiments of the present disclosure, the appended claims cover other embodiments of the present disclosure that differ from the foregoing embodiments in various modifications and improvements.

Claims

1. A pixel comprising: a substrate configured to generate one or more carriers in response to an incident light beam; A first vertical gate and a second vertical gate are disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node; a first vertical gate input terminal electrically coupled to the first vertical gate and configured to receive a first gate control signal; as well as A second vertical gate input terminal is electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node using the first gate control signal and the second gate control signal.

2. The pixel of claim 1, wherein: The first vertical gate is configured to be activated using a first gate control signal and to direct the one or more carriers to the first sensing node when activated; as well as The second vertical gate is configured to be activated using a second gate control signal and to guide the one or more carriers to the second sensing node when activated.

3. The pixel of claim 2, wherein: When the second vertical gate is activated, the first vertical gate is deactivated; and When the first vertical gate is activated, the second vertical gate is deactivated. 4 . The pixel of claim 3 , wherein the first gate control signal and the second gate control signal comprise periodic waveforms and are complementary to each other.

5. The pixel of claim 1, further comprising: A third vertical gate is disposed inside the substrate; a fourth vertical gate disposed inside the substrate, wherein the first vertical gate, the second vertical gate, the third vertical gate, and the fourth vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node; a third gate input terminal electrically coupled to the third vertical gate and configured to receive a third gate control signal; as well as A fourth gate input terminal is electrically coupled to the fourth vertical gate and configured to receive a fourth gate control signal, wherein the first vertical gate, the second vertical gate, the third vertical gate and the fourth vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node using the first gate control signal, the second gate control signal, the third gate control signal and the fourth gate control signal.

6. The pixel of claim 1, further comprising: a first deep isolation trench on a first side of the substrate; as well as A second deep isolation trench is located on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

7. A pixel as described in claim 1, wherein the first vertical gate and the second vertical gate are configured to be alternately activated using a first gate control signal and a second gate control signal, wherein at a given time the first gate control signal is the complement of the second gate control signal, and wherein the pixel is configured to determine an indirect time of flight (iToF).

8. A pixel as described in claim 1, wherein the first vertical gate and the second vertical gate are configured to be simultaneously deactivated for a first time period using a first gate control signal and a second gate control signal, and the first vertical gate or the second vertical gate is activated for a second time period, and wherein the pixel is configured to provide two-dimensional imaging.

9. A pixel comprising: a substrate configured to generate one or more carriers in response to an incident light beam; A first vertical gate and a second vertical gate disposed inside the substrate, wherein the first vertical gate and the second vertical gate are configured to guide the one or more carriers to the first capacitor or the second capacitor; a first vertical gate input terminal electrically coupled to the first vertical gate and configured to receive a first gate control signal; as well as A second vertical gate input terminal is electrically coupled to the second vertical gate and configured to receive a second gate control signal, wherein the first vertical gate and the second vertical gate are configured to guide the one or more carriers to the first capacitor or the second capacitor using the first gate control signal and the second gate control signal.

10. The pixel of claim 9, wherein: The first vertical gate is configured to be activated by a first gate control signal and to direct the one or more carriers to the first capacitor when activated; as well as The second vertical gate is configured to be activated by a second gate control signal and to direct the one or more carriers to the second capacitor when activated.

11. The pixel of claim 10, wherein: When the second vertical gate is activated, the first vertical gate is deactivated; and When the first vertical gate is activated, the second vertical gate is deactivated. 12 . The pixel of claim 11 , wherein the first gate control signal and the second gate control signal comprise periodic waveforms and are complementary to each other.

13. A method comprising: disposing a first vertical gate and a second vertical gate inside the substrate, wherein the first vertical gate and the second vertical gate are configured to guide one or more carriers to the first sensing node or the second sensing node, wherein the one or more carriers are generated inside the substrate in response to an incident light beam; configuring a first vertical gate input to receive a first gate control signal, wherein the first vertical gate input is electrically coupled to the first vertical gate; and The second vertical gate input is configured to receive a second gate control signal, wherein the second vertical gate input is electrically coupled to the second vertical gate, wherein the first vertical gate and the second vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node using the first gate control signal and the second gate control signal.

14. The method of claim 13, comprising: configuring the first vertical gate to be activated by a first gate control signal and to direct the one or more carriers to the first sensing node when the first vertical gate is activated; as well as The second vertical gate is configured to be activated by a second gate control signal and to guide the one or more carriers to the second sensing node when the second vertical gate is activated.

15. The method of claim 14, comprising: configuring the first vertical gate to be deactivated when the second vertical gate is activated; as well as The second vertical gate is configured to be deactivated when the first vertical gate is activated. 16 . The method of claim 15 , wherein the first gate control signal and the second gate control signal comprise periodic waveforms and are complementary to each other.

17. The method of claim 13, comprising: disposing a third vertical gate inside the substrate; disposing a fourth vertical gate within the substrate, wherein the first vertical gate, the second vertical gate, and the fourth vertical gate are configured to guide the one or more carriers to the first sensing node or the second sensing node; electrically coupling a third gate input terminal to the third vertical gate to receive a third gate control signal; electrically coupling a fourth gate input terminal to the fourth vertical gate to receive a fourth gate control signal; as well as The one or more carriers are guided to the first sensing node or the second sensing node using the first gate control signal, the second gate control signal, the third gate control signal, or the fourth gate control signal.

18. The method of claim 13, comprising: disposing a first deep isolation trench on a first side of a substrate; as well as A second deep isolation trench is disposed on a second side of the substrate, wherein the first deep isolation trench and the second deep isolation trench are configured to create a pinning potential at the substrate to deplete the substrate.

19. The method of claim 13, comprising alternately activating the first vertical gate and the second vertical gate using a first gate control signal and a second gate control signal, wherein at a given time, the first gate control signal is the complement of the second gate control signal.

20. The method of claim 19, comprising: electrically coupling the first sensing node to the first supplementary capacitor; electrically coupling the second sensing node to a second supplemental capacitor; as well as The first supplement capacitor and the second supplement capacitor are configured to determine an indirect time-of-flight or two-dimensional density image using a first charge value of the first supplement capacitor and a second charge value of the second supplement capacitor.

Images