SOTB-based low-power-consumption CIS and embedded controller

Abstract

The invention discloses a low-power-consumption CIS based on an SOTB and an embedded controller, and belongs to the technical field of semiconductors, the low-power-consumption CIS based on the SOTB comprises a CIS wafer and an SOTB wafer, the CIS wafer and the SOTB wafer are connected, the SOTB wafer operates by collecting environmental energy, the working voltage of a core device in the CIS wafer is 0.75 V, and the process node of the SOTB wafer is 55 nm. The CIS wafer and the 55nm SOTB wafer are connected, so that a core device of the CIS wafer can operate under the low voltage of 0.75 V, the SOTB wafer can be used for collecting environmental energy, operates by means of the environmental energy and can supply power to the CIS wafer, external power supply is not needed, and the power consumption of the whole device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a low-power CIS and an embedded controller based on SOTB. Background Art

[0002] The SOTB manufacturing process is a new transistor technology using SOI (Silicon on Insulator). SOTB can reduce both the active power consumption and the standby power consumption, which are usually difficult to balance, to the limit. At the same time, it is also compatible with the SOTB and Bulk hybrid structure on a single chip. An extremely thin insulating layer (BOX: Buried Oxide) is formed under the thin silicon layer on the wafer substrate. The SOTB technology breaks the limitation that only one of the low operating current and low standby current consumption can be selected in the past. Through SOTB, both can be achieved without loss. In addition, SOTB supports high operating frequencies and enables small silicon node geometries for high performance and high density memory. It supports battery-free applications in fields such as industry, home, infrastructure, and medical devices, and the operating and standby currents are equivalent to one-tenth of those of traditional low-power MCUs.

[0003] CIS (Cmos Image Sensor) is the core component of a camera. Benefiting from the growth of application fields such as automotive electronics, smartphones, security monitoring, and under-screen fingerprint, the market demand for CIS has increased rapidly. In order to reduce power consumption, CIS often realizes by connecting to logic wafers with lower process nodes such as 22nm or 28nm, but the effect of reducing power consumption is not ideal.

[0004] It should be noted that the information disclosed in the background art of this invention is only intended to deepen the understanding of the general background technology of this invention, and should not be regarded as an admission or any form of implication that this information constitutes the prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of the present invention is to provide a low-power CIS and an embedded controller based on SOTB to solve the problem of high power consumption of CIS.

[0006] To solve the above technical problems, the present invention provides a low-power CIS based on SOTB, including a CIS wafer and an SOTB wafer. The CIS wafer and the SOTB wafer are interconnected. The SOTB wafer operates by collecting ambient energy. The operating voltage of the core device in the CIS wafer is 0.75V, and the process node of the SOTB wafer is 55nm.

[0007] Preferably, the CIS wafer and the SOTB wafer are connected by TSV.

[0008] Preferably, the CIS wafer and the SOTB wafer are connected by the HB method.

[0009] Preferably, the process node of the CIS wafer is 40 nm.

[0010] Preferably, the process node of the CIS wafer is 55 nm.

[0011] Based on the same technical concept, the present invention also provides an SOTB-based embedded controller, including a CIS wafer and an SOTB wafer, the CIS wafer and the SOTB wafer are interconnected, the SOTB wafer operates by collecting environmental energy, the operating voltage of the core device in the CIS wafer is 0.75 V, and the process node of the SOTB wafer is 55 nm.

[0012] Preferably, the CIS wafer and the SOTB wafer are connected by the TSV method.

[0013] Preferably, the CIS wafer and the SOTB wafer are connected by the HB method.

[0014] Preferably, the process node of the CIS wafer is 40 nm.

[0015] Preferably, the process node of the CIS wafer is 55 nm.

[0016] In the SOTB-based low-power CIS provided by the present invention, by connecting the CIS wafer and the 55-nm SOTB wafer, the core device of the CIS wafer can operate at a low voltage of 0.75 V. The SOTB wafer can be used to collect environmental energy, operate by means of environmental energy, and can also supply power to the CIS wafer without external power supply, thereby reducing the power consumption of the entire device.

[0017] The SOTB-based embedded controller provided by the present invention and the SOTB-based low-power CIS provided by the present invention belong to the same inventive concept. Therefore, the SOTB-based embedded controller provided by the present invention has at least all the advantages of the SOTB-based low-power CIS provided by the present invention, which will not be elaborated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0019] Figure 1 is a schematic structural diagram of an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of a transistor in the SOTB wafer in an embodiment of the present invention;

[0021] Figure 3 It is a schematic structural diagram of the I / O device and the core device in the CIS wafer in an embodiment of the present invention.

[0022] In the drawings:

[0023] 100, CIS wafer; 200, SOTB wafer; 201, well region; 202, isolation structure; 203, bias control region; 204, thin buried oxide layer; 205, source region; 206, drain region; 207, undoped channel; 208, gate. Detailed implementation manners

[0024] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the emphases to be shown in the respective drawings are different, and sometimes different scales are used.

[0025] As used in the present invention, the singular forms "a", "an" and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more". In addition, the terms "first", "second", "third" are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. The term "proximal end" generally refers to the end close to the operator, the term "distal end" generally refers to the end close to the patient, "one end" and "the other end" as well as "proximal end" and "distal end" generally refer to corresponding two parts, which include not only the endpoints. The terms "mounted", "connected", "coupled" shall be construed broadly. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and may be the communication inside two elements or the interaction relationship between two elements. In addition, as used in the present invention, one element being disposed on another element generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and should not be construed as indicating or implying the spatial position relationship between the two elements, that is, one element may be inside, outside, above, below or on one side of the other element, etc. in any orientation, unless otherwise explicitly stated in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0026] The inventors' research found that in order to reduce power consumption, CIS often realizes by connecting logic wafers with lower process nodes such as 22nm or 28nm, but the effect of reducing power consumption is not ideal.

[0027] Based on this, the core idea of the present invention is that by connecting the CIS wafer and the 55nm SOTB wafer, the core device of the CIS wafer can operate at a low voltage of 0.75V. The SOTB wafer can be used to collect environmental energy and operate by means of the environmental energy, and can also supply power to the CIS wafer without external power supply, thereby reducing the power consumption of the entire device.

[0028] Specifically, please refer to Figures 1 - 3 , which is a schematic diagram of an embodiment of the present invention. As Figure 1As shown, a low-power CIS based on SOTB includes a CIS wafer 100 and an SOTB wafer 200. The CIS wafer 100 and the SOTB wafer 200 are interconnected. The SOTB wafer 200 operates by collecting ambient energy. The operating voltage of the core devices in the CIS wafer 100 is 0.75V, and the process node of the SOTB wafer 200 is 55nm.

[0029] In one embodiment, a 55nm or 40nm CIS wafer 100 is bonded to a 55nm SOTB wafer 200 to achieve an operating voltage of 0.75V for the core devices. Reference can be made to Figure 3 the IO devices and core devices (Coredevice) in the CIS wafer 100. The entire device structure can operate by collecting ambient energy (without a battery) and can be used in space in the future.

[0030] Exemplarily, the SOTB wafer 200 operates by collecting ambient energy, and the energy sources are, for example, light, temperature, vibration, liquid or air flow, piezoelectricity, etc. Thereby reducing the external power consumption required for the operation of the SOTB wafer 200 itself. Furthermore, in some usage scenarios, the SOTB wafer 200 can also supply power to the CIS wafer 100, reducing the power consumption of the entire device.

[0031] Specifically, the CIS wafer 100 and the SOTB wafer 200 are connected by TSV. The CIS wafer 100 and the SOTB wafer 200 are connected by HB. The CIS wafer 100 and the SOTB wafer 200 can achieve the interconnection of corresponding devices through TSV (Through Silicon Via, silicon via technology) or HB (hybrid bonding, hybrid bonding process).

[0032] As Figure 2 shown in the device structure of the SOTB wafer 200, a well region 201 is arranged in the SOTB wafer 200, and three isolation structures 202 are arranged at intervals on the well region 201. A bias control region 203 is arranged between the two left isolation structures 202 to reduce leakage. A source region 205, an undoped channel 207, and a drain region 206 are sequentially arranged from left to right in the gap of the right isolation structure 202, and a thin buried oxide layer 204 is arranged at the bottom of the source region 205, the undoped channel 207, and the drain region 206. In addition, a gate 208 is arranged on the top of the undoped channel 207.

[0033] Among them, the process node of the CIS wafer 100 is 40nm. The process node of the CIS wafer 100 is 55nm.

[0034] Based on the same inventive concept, the present disclosure also provides an embedded controller based on SOTB, including a CIS wafer 100 and an SOTB wafer 200. The CIS wafer 100 and the SOTB wafer 200 are interconnected. The SOTB wafer 200 operates by collecting environmental energy. The operating voltage of the core device in the CIS wafer 100 is 0.75V, and the process node of the SOTB wafer 200 is 55nm.

[0035] Specifically, the CIS wafer 100 and the SOTB wafer 200 are connected by TSV. The CIS wafer 100 and the SOTB wafer 200 are connected by HB. Among them, the process node of the CIS wafer 100 is 40nm. The process node of the CIS wafer 100 is 55nm.

[0036] In one embodiment, bonding a 55nm or 40nm CIS wafer 100 to a 55nm SOTB wafer 200 can achieve an operating voltage of 0.75V for the core device. For reference, Figure 3 Regarding the device structure, the IO device and the core device in the CIS wafer 100. The entire device structure can operate by collecting environmental energy (without a battery) and can be used in space in the future.

[0037] Exemplarily, the SOTB wafer 200 operates by collecting environmental energy, and the energy sources are, for example, light, temperature, vibration, liquid or air flow, piezoelectricity, etc. Thereby reducing the external power consumption required for the operation of the SOTB wafer 200 itself. Furthermore, in some usage scenarios, the SOTB wafer 200 can also supply power to the CIS wafer 100, reducing the power consumption of the entire device.

[0038] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the scope of protection of the technical solution of the present invention.

Claims

1. A low-power CIS based on SOTB, characterized in that: It comprises a CIS wafer and a SOTB wafer, wherein the CIS wafer and the SOTB wafer are interconnected, the SOTB wafer operates by collecting environmental energy, the operating voltage of the core device in the CIS wafer is 0.75V, and the process node of the SOTB wafer is 55nm.

2. The low-power CIS based on SOTB according to claim 1, characterized in that: The CIS wafer and the SOTB wafer are connected via TSV.

3. The low-power CIS based on SOTB according to claim 1, characterized in that: The CIS wafer and the SOTB wafer are connected via HB.

4. The low-power CIS based on SOTB according to claim 1, characterized in that: The process node of the CIS wafer is 40nm.

5. The low-power CIS based on SOTB according to claim 1, characterized in that: The process node of the CIS wafer is 55nm.

6. A SOTB-based embedded controller, characterized in that: It comprises a CIS wafer and a SOTB wafer, wherein the CIS wafer and the SOTB wafer are interconnected, the SOTB wafer operates by collecting environmental energy, the operating voltage of the core device in the CIS wafer is 0.75V, and the process node of the SOTB wafer is 55nm.

7. The SOTB-based embedded controller according to claim 6, characterized in that: The CIS wafer and the SOTB wafer are connected via TSV.

8. The SOTB-based embedded controller according to claim 6, characterized in that: The CIS wafer and the SOTB wafer are connected via HB.

9. The SOTB-based embedded controller according to claim 6, characterized in that: The process node of the CIS wafer is 40nm.

10. The SOTB-based embedded controller according to claim 6, characterized in that: The process node of the CIS wafer is 55nm.

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