Preparation method of magnetic random storage unit
By using a non-metal hard mask layer as a mask during the manufacturing process of magnetic random memory, the device short circuit problem caused by metal sputter aggregation and adhesion is solved, and the device yield and stability are improved.
Patent Information
- Application Number
- CN202311602960.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-28
- Publication Date
- 2025-05-30
AI Technical Summary
In the manufacturing process of magnetic random memory, the existing metal hard mask etching process leads to aggregation and adhesion of metal sputters, causing short circuits in the device and affecting yields, especially when the cell density is greater, the more significant the problem.
A non-metallic hard mask layer is used as a mask to etch during the formation of a magnetic tunnel junction to avoid aggregation and adherence of metal sputters, thereby improving device yield. The hard mask layer may be made of carbon-containing medium or carbon-free dielectric oxide and eliminated or removed by specific process steps.
By using a non-metallic hard mask layer, the aggregation and adhesion of metal sputters during the etching process is avoided, the yield of magnetic random memory is significantly improved, the manufacturing cost is reduced, and the stability of the device is improved.
Smart Images
Figure CN120076701A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of magnetic memories, and particularly to a method for manufacturing a magnetic random access memory cell. Background Art
[0002] With the rapid development of electronic technology, non-volatile memories have become the focus of research. Non-volatile memories have the characteristics of high density, fast read / write, and extremely long working life, and have broad market application prospects. As a representative of the next-generation non-volatile memories, magnetic random access memory (MRAM) is one of the most promising candidates for mass production. In the manufacturing process of magnetic random access memories, the magnetic tunnel junction (MTJ) etching process is a key technology that determines whether MRAM can be mass-produced.
[0003] In the existing MTJ etching process, since the hard mask generally uses a metal material, the metal sputtering products generated during the etching of the hard mask will accumulate and adhere to the sidewalls of adjacent magnetic tunnel junctions. In the case of incomplete cleaning, it will cause device short circuits, thereby affecting the device yield. Moreover, the larger the cell density, the greater the difficulty in cleaning the metal sputtering products, and the more significant the impact on the yield. Summary of the Invention
[0004] To solve the above problems, the present invention provides a method for manufacturing a magnetic random access memory cell, which can improve the device yield.
[0005] The present invention provides a method for manufacturing a magnetic random access memory cell, comprising:
[0006] forming a multi-layer film of a magnetic tunnel junction on a bottom electrode;
[0007] forming a non-metallic hard mask layer film on the multi-layer film of the magnetic tunnel junction;
[0008] patterning the hard mask layer film to obtain a hard mask layer;
[0009] using the hard mask layer as a mask to etch the multi-layer film of the magnetic tunnel junction to obtain a magnetic tunnel junction;
[0010] forming a protective layer to cover the magnetic tunnel junction;
[0011] forming a dielectric layer on the protective layer and performing polishing;
[0012] forming a top interconnect structure using the dielectric layer.
[0013] Optionally, the hard mask layer film is a carbon-containing dielectric, and the carbon-containing dielectric has the property of being oxidizable into a volatile gas, and is selected from one of SiCN, SiOC, SiC, C elemental substance, and C-containing organic dielectrics.
[0014] Optionally, a top interconnect structure is formed using the dielectric layer, including:
[0015] Etch the dielectric layer to form trenches and vias in the dielectric layer, exposing the protective layer;
[0016] Etch the exposed protective layer to expose the hard mask layer;
[0017] Apply a reactive atmosphere, and use the reaction of the reactive atmosphere and the hard mask layer to convert the hard mask layer into a volatile gaseous product for elimination;
[0018] Fill with metal to form the top interconnect structure.
[0019] Optionally, the reactive atmosphere is O 2 、O 3 、NO、N 2 O、CO 2 、CO and H 2 O, or a combination thereof, or O 2 、O 3 、NO、N 2 O、CO 2 、CO and H 2 O, or a combination thereof, or a plasma generated by a combination thereof.
[0020] Optionally, the hard mask layer film is a carbon-free dielectric oxide selected from SiO x 、SiON and SiN.
[0021] Optionally, a top interconnect structure is formed using the dielectric layer, including:
[0022] Etch the dielectric layer to form trenches and vias in the dielectric layer, exposing the protective layer;
[0023] Etch the exposed protective layer to expose the hard mask layer;
[0024] Remove the hard mask layer through an etching process;
[0025] Fill with metal to form the top interconnect structure.
[0026] Optionally, a non-metallic hard mask layer film is formed by a spin coating process, a magnetron sputtering process or a CVD deposition process.
[0027] Optionally, the thickness of the hard mask layer film is 100 - 200 nm.
[0028] Optionally, the material of the protective layer is one of SiN, SiCN and SiOC.
[0029] Optionally, a protective layer is formed by ALD or PECVD. The specific process conditions are as follows: the Si source precursor for deposition is hexamethylcyclotrisilazane, trimethylsilylamine (TSA), or SiH 4 , and the deposition temperature is 200 - 300 °C.
[0030] A method for preparing a magnetic random access memory cell provided by the present invention uses a non-metallic hard mask layer as a mask. In this way, during the formation of the MTJ, the sidewall adhesion generated by etching the hard mask layer will not contribute to any short circuit, thereby improving the device yield. Description of the Drawings
[0031] Figure 1 is a schematic flow chart of a method for preparing a magnetic random access memory cell according to an embodiment of the present invention;
[0032] Figure 2 is a schematic cross-sectional structure diagram of a memory cell before forming a top interconnect structure according to an embodiment of the present invention;
[0033] Figures 3 to 5 is a schematic cross-sectional structure diagram of a memory cell at each step during the formation of a top interconnect structure according to an embodiment of the present invention;
[0034] Figures 6 to 8 is a schematic cross-sectional structure diagram of a memory cell at each step during the formation of a top interconnect structure according to another embodiment of the present invention. Detailed Embodiments
[0035] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. However, it should be understood that these descriptions are exemplary and are not intended to limit the scope of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention. In addition, in the following description, the descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present disclosure.
[0036] Various schematic structure diagrams according to embodiments of the present disclosure are shown in the drawings. These figures are not drawn to scale, where for the purpose of clear expression, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.
[0037] In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component.
[0038] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0039] An embodiment of the present invention provides a method for fabricating a magnetic random access memory cell, as Figure 1 shown, the method includes the following steps:
[0040] S101. Form a multi-layer thin film of a magnetic tunnel junction on a bottom electrode;
[0041] S102. Form a non-metallic hard mask layer thin film on the multi-layer thin film of the magnetic tunnel junction;
[0042] S103. Pattern the hard mask layer thin film to obtain a hard mask layer;
[0043] S104. Use the hard mask layer as a mask to etch the multi-layer thin film of the magnetic tunnel junction to obtain a magnetic tunnel junction;
[0044] S105. Form a protective layer to cover the magnetic tunnel junction;
[0045] S106. Form a dielectric layer on the protective layer and perform polishing;
[0046] S107. Use the dielectric layer to form a top interconnect structure.
[0047] Figure 2 Shows a schematic cross-sectional structure diagram of the magnetic random access memory cell formed after steps S101 to S106. Combining Figure 2 , the following will elaborate on steps S101 to S106 in detail.
[0048] In step S101, before depositing the multi-layer thin film of the magnetic tunnel junction, the formation process of the bottom electrode is as follows:
[0049] First, grow a layer of bottom electrode metal at the bottom. Through a photolithography and etching process, form a plurality of discontinuous and independent bottom electrodes (BE) 110. At this time, the CD size of the bottom electrode is 150 - 250 nm. Then grow an insulating dielectric layer (ILD) 111 with a certain thickness on it. After introducing the insulating dielectric layer 111, CMP processing needs to be performed on the basis of its complete filling and the oxide layer on the BE needs to be polished away to expose the bottom electrode.
[0050] To form a magnetic tunnel junction multi-layer thin film on the bottom electrode 110, a PVD process can be used. In this application, the thin film structure of the magnetic tunnel junction is not limited. The MTJ thin film structure includes at least a free layer 112, a tunneling layer 113, and a reference layer 114, and its structural features include but are not limited to a single-barrier structure and a double-barrier structure.
[0051] In step S102, a non-metallic hard mask layer thin film can be formed by a spin coating process, a magnetron sputtering process, or a CVD deposition process. Optionally, the thickness of the hard mask layer thin film is 100 - 200 nm.
[0052] In step S103, a photoresist is spin-coated, and after exposure and development, the hard mask layer 115 is etched and formed.
[0053] In step S104, using the hard mask layer 115 as a mask, the multi-layer thin film of the magnetic tunnel junction is etched by an IBE process to obtain a magnetic tunnel junction, and the etching depth is precisely controlled by means of OSE endpoint determination. The cross-sectional shape of the formed magnetic tunnel junction is not limited. Commonly used is a cylindrical shape, which can be called an MTJ pillar. After this step, there is a remainder of the non-metallic hard mask layer 115.
[0054] In step S105, a protective layer 116 is formed by an ALD or PECVD method to cover the periphery of the magnetic tunnel junction. Optionally, the material of the protective layer 116 is one of SiN, SiCN, and SiOC. The thickness of the protective layer 116 is between 20 - 100 nm.
[0055] Specific process conditions: The deposited Si source precursor is hexamethylcyclotrisilazane, trimethylsilylamine (TSA), or SiH 4 , and the deposition temperature is 200 - 300 °C.
[0056] In step S106, a dielectric layer 117 is formed on the protective layer 116 to cover the entire device and polished. Optionally, the material of the dielectric layer 117 includes but is not limited to SiO 2 , SiON, SiN, SiCN, etc., with a thickness of 20 - 100 nm, a deposition temperature of 200 - 300 °C, and the deposition method is PECVD.
[0057] Regarding step S107, the formation of the top interconnect structure is related to the material of the non-metallic hard mask layer 115, which will be discussed in different cases below.
[0058] In one embodiment, the hard mask layer film for forming the hard mask layer 115 is a carbon-containing medium, which has the property of being oxidizable into volatile gases and is selected from one of SiCN, SiOC, SiC, elemental C, and C-containing organic media. The hard mask layer 115 composed of the carbon-containing medium has sufficient etch blocking ability and can meet the requirements of IBE and RIE etching processes.
[0059] Reference Figures 3 to 5 , such as Figure 3 shown, first etch the dielectric layer 117 to form trenches and vias in the dielectric layer 117, exposing the protective layer 116. The common opening and grooving etching of the dielectric layer 117 uses CFx based plasma, including but not limited to CF 4 , C 4 F 8 , C 4 F 6 , SF 6 , etc. Then etch away the exposed protective layer 116 to further expose the hard mask layer 115 and stop at the top of the hard mask layer 115.
[0060] Such as Figure 4 shown, after the hard mask layer 115 is exposed, apply a reaction atmosphere and use the reaction of the reaction atmosphere with the hard mask layer to convert the hard mask layer 115 into volatile gaseous products for elimination. Taking elemental C as an example, elemental C generates volatile C, O mixtures such as CO / CO2 under the action of O plasma. In this embodiment, the reaction atmosphere can be a single gas or a mixed gas, or a dissociation group or oxidation radical of a single gas or a mixed gas, including but not limited to O 2 , O 3 , NO, N 2 O, CO 2 , CO and H 2 O and a combination of one of them, or O 2 , O 3 , NO, N 2 O, CO 2 , CO and H 2 O and a combination of one of them, or the plasma generated by a combination of one of them.
[0061] Such as Figure 5 shown, fill with metal to form a top interconnect structure. The metal includes but is not limited to one of Cu, Al, and W.
[0062] It should be further noted that in view of the characteristic that the hard mask layer of the carbon-containing medium can be eliminated by using a reaction atmosphere, the above top interconnect process can be simplified:
[0063] Such as Figure 6As shown, only trenches need to be etched in the dielectric layer, breaking through the MTJ protection layer and stopping at the top of the hard mask layer 115. Then, as Figure 7 shown, the hard mask layer 115 is removed using a reaction atmosphere. At this time, a dual damascene structure with self-alignment characteristics is formed, and this structure can be directly used for the interconnection metal deposition process to meet the device requirements. Finally, as Figure 8 shown, the metal is filled to form the top interconnection structure.
[0064] For the hard mask layer of carbon-containing dielectric, the reaction atmosphere is used to convert the hard mask layer into volatile gaseous products and completely remove it, laying the foundation for the connection of the top electrode. This process simplifies the processes such as VIA opening and top electrode TE CMP, greatly reducing the manufacturing cost and improving the device stability. At the same time, self-aligned vias are formed after the hard mask layer is removed, which also saves the photolithography alignment process and greatly improves the filling accuracy.
[0065] In another embodiment, the hard mask layer film used to form the hard mask layer 115 is a carbon-free dielectric oxide, selected from one of SiOx, SiON, and SiN. For the hard mask layer of carbon-free dielectric oxide, it does not have the characteristic of being removed using a reaction atmosphere and can only be removed secondly by subsequent dielectric etching methods. The formation of the top interconnection structure specifically includes:
[0066] Etch the dielectric layer to form trenches and vias in the dielectric layer, exposing the protection layer;
[0067] Etch the exposed protection layer to expose the hard mask layer;
[0068] Remove the hard mask layer through an etching process;
[0069] Fill the metal to form the top interconnection structure.
[0070] The cross-sectional structure schematic diagrams corresponding to the above steps of forming the top interconnection structure are the same as Figures 3 to 5 , except that there are differences in the process of removing the hard mask layer.
[0071] A method for preparing a magnetic random access memory cell provided by an embodiment of the present invention uses a non-metallic hard mask layer as a mask. In this way, during the formation of the MTJ, the sidewall adhesion generated by etching the hard mask layer will not contribute to any short circuit, thereby improving the device yield.
[0072] In the above description, no detailed explanations are given for the technical details such as the composition and etching of each layer. However, those skilled in the art should understand that various technical means can be adopted to form layers, regions, etc. of the desired shapes. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used in combination advantageously.
[0073] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. A method for preparing a magnetic random access memory cell, characterized in that, comprising: forming a multi-layer thin film of a magnetic tunnel junction on a bottom electrode; forming a non-metallic hard mask layer thin film on the multi-layer thin film of the magnetic tunnel junction; patterning the hard mask layer thin film to obtain a hard mask layer; etching the multi-layer thin film of the magnetic tunnel junction using the hard mask layer as a mask to obtain a magnetic tunnel junction; forming a protective layer to cover the magnetic tunnel junction; forming a dielectric layer on the protective layer and polishing it; forming a top interconnect structure using the dielectric layer.
2. The method according to claim 1, characterized in that, the hard mask layer thin film is a carbon-containing medium, and the carbon-containing medium has the property of being oxidizable into a volatile gas, and is selected from one of SiCN, SiOC, SiC, elemental C, and a C-containing organic medium.
3. The method according to claim 2, characterized in that, forming a top interconnect structure using the dielectric layer includes: etching the dielectric layer to form trenches and vias in the dielectric layer, exposing the protective layer; etching the exposed protective layer to expose the hard mask layer; applying a reaction atmosphere, and using the reaction of the reaction atmosphere and the hard mask layer to convert the hard mask layer into a volatile gaseous product for elimination; filling with metal to form a top interconnect structure.
4. The method according to claim 3, characterized in that, The reaction atmosphere is O 2 、O 3 、NO、N 2 O、CO 2 、CO and H 2 O and a combination thereof, or O 2 、O 3 、NO、N 2 O、CO 2 、CO and H 2 O and a combination thereof, or a plasma generated by O 5. The method according to claim 1, characterized in that, The hard mask layer film is a carbon-free dielectric oxide selected from one of SiO x , SiON, and SiN.
6. The method according to claim 5, characterized in that, forming a top interconnect structure using the dielectric layer includes: etching the dielectric layer to form trenches and vias in the dielectric layer, exposing the protective layer; etching the exposed protective layer to expose the hard mask layer; removing the hard mask layer through an etching process; filling with metal to form a top interconnect structure.
7. The method according to claim 1, characterized in that, a non-metallic hard mask layer thin film is formed by a spin coating process, a magnetron sputtering process, or a CVD deposition process.
8. The method according to claim 1, characterized in that, the thickness of the hard mask layer thin film is 100 - 200 nm.
9. The method according to claim 1, characterized in that, the material of the protective layer is one of SiN, SiCN, and SiOC.
10. The method according to claim 9, characterized in that, The protective layer is formed by ALD or PECVD. The specific process conditions are as follows: the Si source precursor for deposition is hexamethylcyclotrisilazane, trimethylsilylamine (TSA) or SiH 4 , and the deposition temperature is 200 - 300 °C.