Heating electrode preparation method and semiconductor process equipment

Abstract

The invention provides a heating electrode preparation method and semiconductor process equipment, and the method comprises the steps: an etching step: carrying out the graphical etching of a metal layer formed on an insulating dielectric layer with a groove through a graphical mask structure; a trimming step: removing etching by-products; circularly executing the etching step and the finishing step until the part, which is not covered by the patterned mask structure, of the metal layer is removed, so as to form a heating electrode; wherein the groove is provided with two opposite groove side surfaces in the first direction, and a groove bottom surface; the heating electrode comprises a plurality of electrode split bodies which are arranged at intervals in the first direction and the second direction, and each electrode split body is at least arranged on the side face and the bottom face of the groove in an overlapped mode. The first direction and the second direction are parallel to the bottom face of the groove and are perpendicular to each other. According to the invention, the problems of line width load effect and device short circuit caused by metal residue in the prior art can be solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and specifically, to a method for preparing a heating electrode and a semiconductor process device. Background Art

[0002] Phase change memory is a new type of non-volatile memory that uses the resistance difference of certain special reversible phase change materials between different crystalline states and amorphous states to record and store information. It has received extensive attention due to its high integration, low power consumption, fast storage speed, high reliability, compatibility with CMOS process, and low cost. As Figure 1 shown, the storage unit of a typical phase change memory mainly includes a top electrode 101, a phase change material layer 102, a heating resistor 103 (also known as a heating electrode), and a bottom electrode 104.

[0003] When writing information in a phase change memory, a short and strong voltage pulse is input to heat the heating resistor above the melting temperature of the phase change material, and then rapid cooling is performed to transform the phase change material into an amorphous high-resistance state. When erasing information in a phase change memory, a long and low-intensity voltage pulse is input to heat the heating resistor above the crystallization temperature and below the melting temperature of the phase change material and maintain it for a certain time, so that the phase change material is transformed from an amorphous state to a crystalline state, completing the transformation from high resistance to low resistance.

[0004] The heating resistor plays an important role in a phase change memory. It needs to generate more heat under a small current to complete the phase change of the phase change material. The resistance uniformity and film quality of the heating resistor directly affect the realization and reliability of the functions of the phase change memory. The heating resistor can be formed by metal thin film deposition, photolithography, and etching in sequence.

[0005] However, in the related art, when etching a metal layer (i.e., a metal thin film), a linewidth loading effect will occur between the top and bottom of the step due to the step height difference of the metal layer, resulting in a narrower linewidth at the top of the heating resistor than at the bottom, and a trapezoidal structure with a narrower top and a wider bottom is formed in the vertical part, thereby changing the electrical performance and resistance heat generation of the heating resistor. In addition, under the conditions of the same etching thickness and the same etching time, the top and bottom of the step of the metal layer have been removed, while the vertical part remains unremoved, resulting in metal residue and ultimately causing device short circuit. Summary of the Invention

[0006] The present application aims to at least solve one of the technical problems existing in the prior art, and provides a method for preparing a heating electrode and a semiconductor process device, which can solve the problems of linewidth loading effect and device short circuit caused by metal residue in the related art.

[0007] To achieve the object of the present application, a method for preparing a heating electrode is provided, including:

[0008] An etching step of patterning and etching a metal layer formed on an insulating dielectric layer having a groove by using a patterned mask structure;

[0009] A trimming step of removing etching by-products;

[0010] The etching step and the trimming step are repeatedly executed until the portion of the metal layer not covered by the patterned mask structure is removed to form the heating electrode;

[0011] Wherein, the groove has two groove side surfaces opposite to each other in a first direction and a groove bottom surface; the heating electrode includes a plurality of electrode segments arranged at intervals in the first direction and a second direction, and each electrode segment is at least stacked on the groove side surface and the groove bottom surface; the first direction and the second direction are both parallel to the groove bottom surface and perpendicular to each other.

[0012] In some embodiments, in the etching step, the metal layer is etched at a preset etching rate;

[0013] The preset etching rate is greater than or equal to And less than or equal to

[0014] In some embodiments, in the etching step, the lower radio frequency power supply outputs a pulsed power signal.

[0015] In some embodiments, in the etching step, the duty cycle of the pulsed power signal is greater than or equal to 30% and less than or equal to 50%; the frequency of the pulsed power signal is greater than or equal to 180 Hz and less than or equal to 220 Hz.

[0016] In some embodiments, in the etching step, the lower radio frequency power output by the lower radio frequency power supply is greater than or equal to 30 W and less than or equal to 50 W; or,

[0017] The upper radio frequency power output by the upper radio frequency power supply is greater than or equal to 250 W and less than or equal to 450 W.

[0018] In some embodiments, in the etching step, the chamber pressure is greater than or equal to 3 mT and less than or equal to 10 mT.

[0019] In some embodiments, the material of the metal layer includes W; the process gas used in the etching step includes a main etching gas, a dilution gas, and an auxiliary etching gas;

[0020] The main etching gas includes NF 3 And Cl 2 ,NF 3The flow rate of [substance] is greater than or equal to 10 sccm and less than or equal to 100 sccm; Cl 2 The flow rate of [substance] is greater than or equal to 10 sccm and less than or equal to 100 sccm; the dilution gas includes He, and the flow rate of He is greater than or equal to 50 sccm and less than or equal to 150 sccm; the auxiliary etching gas includes N 2 , N 2 The flow rate of [substance] is greater than or equal to 50 sccm and less than or equal to 150 sccm.

[0021] In some embodiments, the material of the metal layer includes TiN; the process gas used in the etching step includes a main etching gas, a dilution gas, and an etching protection gas;

[0022] The main etching gas includes Cl 2 , Cl 2 The flow rate of [substance] is greater than or equal to 30 sccm and less than or equal to 70 sccm; the dilution gas includes N 2 , N 2 The flow rate of [substance] is greater than or equal to 50 sccm and less than or equal to 150 sccm; the etching protection gas includes CH 4 , CH 4 The flow rate of [substance] is greater than or equal to 5 sccm and less than or equal to 15 sccm.

[0023] In some embodiments, the material of the metal layer includes at least one of Ti, TiN, Ta, TaN, TiO 2 , Ta 5 O 2 ;

[0024] The process gas used in the etching step includes a main etching gas, a dilution gas, and an etching protection gas;

[0025] The main etching gas includes BCl 3 and Cl 2 , BCl 3 The flow rate of [substance] is greater than or equal to 0 sccm and less than or equal to 100 sccm; Cl 2 The flow rate of [substance] is greater than or equal to 30 sccm and less than or equal to 70 sccm; the dilution gas includes N 2 , N 2 The flow rate of [substance] is greater than or equal to 50 sccm and less than or equal to 150 sccm; the etching protection gas includes CH 4 , CH 4 The flow rate of [substance] is greater than or equal to 5 sccm and less than or equal to 15 sccm.

[0026] In some embodiments, the process gas used in the trimming step includes H 2 and N2 ,the flow rate of H 2 is greater than or equal to 100 sccm and less than or equal to 200 sccm; the flow rate of N 2 is greater than or equal to 100 sccm and less than or equal to 200 sccm.

[0027] In some embodiments, in the trimming step, the chamber pressure is greater than or equal to 10 mT and less than or equal to 20 mT; or,

[0028] the lower radio frequency voltage output by the lower radio frequency power supply is greater than or equal to 30 V and less than or equal to 50 V; or,

[0029] the upper radio frequency power output by the upper radio frequency power supply is greater than or equal to 600 W and less than or equal to 800 W.

[0030] In some embodiments, in the same plasma etching chamber, the step of forming the patterned mask structure and the etching step and the trimming step that are cyclically executed are sequentially performed.

[0031] In some embodiments, the step of forming the patterned mask structure includes:

[0032] forming a hard mask layer, a soft mask layer, an anti-reflection layer, and a patterned photoresist layer on the metal layer in sequence;

[0033] using the patterned photoresist layer as a mask to etch the anti-reflection layer and removing the part of the anti-reflection layer not covered by the patterned photoresist layer to form an anti-reflection pattern;

[0034] using the anti-reflection pattern as a mask to etch the soft mask layer and removing the part of the soft mask layer not covered by the anti-reflection pattern to form a soft mask pattern;

[0035] using the soft mask pattern as a mask to etch the hard mask layer and removing the part of the hard mask layer not covered by the soft mask pattern to form a hard mask pattern and retaining the soft mask pattern;

[0036] The patterned mask structure includes the hard mask pattern and the soft mask pattern.

[0037] As another technical solution, the present invention also provides a semiconductor process equipment, including a process chamber, a gas inlet assembly, an upper electrode assembly, a lower electrode assembly, and a controller. The controller includes at least one processor and at least one memory. A computer program is stored in the memory, and when the computer program is executed by the processor, the above-mentioned heating electrode preparation method provided by the present invention is implemented.

[0038] This application has the following beneficial effects:

[0039] In the technical solutions of the heating electrode preparation method and the semiconductor process equipment provided by this application, by etching to form a heating electrode with a stepped structure in a "Z" shape or an "L" shape by cyclically performing an etching step and a trimming step. On the one hand, the part of the metal layer not covered by the patterned mask structure is removed by means of step-by-step etching. Since the etching thickness of each etching step in multiple step-by-step etching is less than the total etching thickness, and the etching time of each etching step is shorter. Therefore, compared with the related art where the corresponding part of the metal layer is removed by one-time etching at a lower etching speed, which will exacerbate the linewidth loading effect due to the need for a longer over-etching time, it is easier to control the etching speed in each etching step of this application. Even when a lower etching speed is used, the linewidth loading effect will not be exacerbated due to too long an etching time. And a lower etching speed helps to reduce the etching speed difference in the vertical direction, making the etching speed at each position in the vertical direction tend to be consistent, thereby reducing the linewidth loading effect. At the same time, for the metal layer with a step height difference, it is possible to avoid the situation where the metal layer has been completely removed at some positions (such as the top of the step), while not completely removed at some other positions (such as the vertical part), resulting in metal residue, thereby improving the etching uniformity and avoiding device short-circuit. On the other hand, since etching by-products will be generated on both the side and the bottom of the groove after each etching step, the accumulation of etching by-products will cause the etching speed at the top of the step to be faster than that at the bottom and the vertical part of the step, resulting in the linewidth loading effect and metal residue. Therefore, by performing a trimming step after each etching step to remove the etching by-products, the metal to be etched can be exposed in time, thereby reducing the linewidth loading effect, removing the metal residue, and improving the etching uniformity and topography controllability. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a schematic diagram of a storage cell of a typical phase change memory;

[0041] Figure 2 is a film layer structure diagram before preparing a heating electrode by a heating electrode preparation method adopted in Related Art One;

[0042] Figure 3 is a structure diagram of the heating electrode obtained in Related Art One;

[0043] Figure 4 is a top view of an array of heating electrodes obtained in Related Art Two;

[0044] Figure 5 is along Figure 4 the cross-sectional view of the dotted line x in;

[0045] Figure 6 is along Figure 4 the cross-sectional view of the dotted line y in;

[0046] Figure 7 It is a flowchart of the method for preparing a heating electrode provided by an embodiment of the present application;

[0047] Figure 8 It is a three-dimensional view of an array of heating electrodes obtained by the method for preparing a heating electrode provided by an embodiment of the present application;

[0048] Figure 9 It is along Figure 10 A cross-sectional view of a repeating array unit in the x direction in;

[0049] Figure 10 It is a top view of an array of multiple repeating array units of a patterned photoresist layer;

[0050] Figure 11 It is along Figure 10 A cross-sectional view of a repeating array unit in the y direction in;

[0051] Figure 12 It is a flowchart of the formation steps of the patterned mask structure adopted by an embodiment of the present application;

[0052] Figure 13 It is a film layer structure diagram after completing step S102 in an embodiment of the present application;

[0053] Figure 14 It is a film layer structure diagram after completing step S103 in an embodiment of the present application;

[0054] Figure 15 It is a film layer structure diagram after completing step S104 in an embodiment of the present application;

[0055] Figure 16 The structure diagram of the semiconductor process equipment according to the embodiment of the present application is shown as follows. Detailed implementation manners

[0056] To enable those skilled in the art to better understand the technical solutions of the present application, the method for preparing a heating electrode and the semiconductor process equipment provided by the present application will be described in detail below with reference to the accompanying drawings.

[0057] The method for preparing a heating electrode adopted in related art one has a film layer structure before preparing the heating electrode as shown in Figure 2 including an insulating dielectric layer 201 (such as SiO 2 ) having a groove 204 and a metal layer 202 of the heating electrode sequentially disposed on the insulating dielectric layer 201

[0058] (e.g., Ti) and a patterned photoresist layer 203. The pattern of the photoresist layer 203 can be obtained through an exposure and development process, and the pattern is a stepped structure in the shape of a "Z". The method for preparing the heating electrode adopted in Related Art One includes: dry-etching the portion of the metal layer 202 of the heating electrode that is not covered by the photoresist layer 203 to copy the pattern of the photoresist layer 203 onto the metal layer 202 of the heating electrode, forming a heating electrode 202a with a stepped structure in the shape of a "Z", as Figure 3 shown.

[0059] However, Related Art One only uses a photoresist layer to achieve pattern transfer, and the pattern transfer ability is limited. For a phase change memory with a high distribution density of storage cells and small sizes of each storage cell, it is difficult to ensure the consistency of the width and morphology of the heating electrode at the nanoscale, which easily leads to uneven resistance values of the etched heating electrode, resulting in inconsistent currents generated by the phase change cells when the same voltage is applied, affecting the stability of the phase change memory. In addition, if the metal layer of the heating electrode with a small thickness, such as a thickness below 100 nm, is etched using Related Art One, the main etching step will end in an extremely short time, and its uniformity is difficult to control.

[0060] To solve the above problems, the patterned mask structure adopted in Related Art Two for etching the metal layer of the heating electrode has a "sandwich structure" for the mask layer before patterning. Specifically, the "sandwich structure" includes a hard mask layer, a soft mask layer, and an anti-reflection layer sequentially disposed on the metal layer of the heating electrode. During the patterning process of these three layers, first, the anti-reflection layer is etched using the patterned photoresist layer as a mask to obtain an anti-reflection pattern; then, the soft mask layer (the main component is, for example, carbon) is etched using the anti-reflection pattern as a mask to obtain a soft mask pattern; then, the hard mask layer is etched using the soft mask pattern as a mask to obtain a hard mask pattern. This process can achieve a smaller critical dimension of the pattern and more accurate pattern transfer. In addition, before preparing the heating electrode, Related Art Two removes the soft mask pattern and the anti-reflection pattern, and only retains the hard mask pattern. Then, when preparing the heating electrode, the metal layer of the heating electrode is etched in a one-step etching manner using the hard mask pattern as a mask to obtain a heating electrode with a stepped structure in the shape of a "Z".

[0061] However, due to the step height difference existing in the metal layer of the heating electrode, during the etching process, there are differences in the plasma concentration and etching by-products at the top and bottom of the step, as Figures 4 to 6As shown, after the etching is completed, the load effect of the line width will be obvious at the step top 202a1 and the step bottom 202a2 of the finally obtained heating electrode 202a, that is, the line width of the step top 202a1 is smaller than that of the step bottom 202a2, and the vertical part 202a3 forms a trapezoidal structure that is narrower at the top and wider at the bottom. This structure will change the electrical performance and the resistance heat generation of the heating electrode.

[0062] Moreover, the applicant has found through research that: during the etching process of the metal layer, the plasma etching machine performs metal etching through the combined action of chemical etching and physical bombardment. However, the vertical part of the metal layer is less affected by the plasma bombardment and mainly relies on chemical etching, resulting in a slower etching rate compared to the etching rates of the step top and the step bottom. Under the conditions of the same etching thickness and the same etching time, the step top and the step bottom of the metal layer have been removed, while the vertical part remains unremoved. Longer over-etching is required to ensure that there is no metal residue in the vertical part, and the long over-etching exacerbates the load effect of the line width. That is to say, in the related art two, a one-step etching method is used to etch the metal layer of the heating electrode. If a relatively high etching rate is used, the load effect of the line width will occur; at the same time, in the related art two, the etching rate cannot be reduced, otherwise the load effect of the line width will be exacerbated due to the increase in the etching time.

[0063] In order to reduce the load effect of the line width and avoid problems such as metal residue and device short circuit, an embodiment of the present application provides a method for preparing a heating electrode. This method is applied to the preparation of the heating electrode in a phase change memory, and this heating electrode can also be called a heating resistor and has a stepped structure in the shape of a "Z" or an "L".

[0064] Specifically, please refer to Figure 7 , the method for preparing a heating electrode provided by the embodiment of the present application includes:

[0065] S201, an etching step, using a patterned mask structure to pattern-etch the metal layer formed on the insulating dielectric layer with grooves;

[0066] S202, a trimming step, removing the etching by-products;

[0067] The above steps S201 (i.e., the etching step) and S202 (i.e., the trimming step) are repeatedly executed until the part of the metal layer not covered by the patterned mask structure is removed to form a heating electrode.

[0068] In some embodiments, the number of cycles is a preset value, and this preset value should satisfy: ensuring that the part of the metal layer not covered by the patterned mask structure is removed. For example, the number of cycles is greater than or equal to 2 times and less than or equal to 5 times.

[0069] The above metal layer is a thin film covering the entire surface of the insulating dielectric layer and serves as a complete film layer before the etching of the heating electrode. Since the insulating dielectric layer has grooves, there is a height difference in the metal layer covering the entire surface of the insulating dielectric layer at the grooves. As Figure 8 shown, the above grooves have two groove sides 303b opposite to each other in the first direction and a groove bottom surface 303c. After completing the above cyclic etching process on the metal layer, the obtained heating electrode includes a plurality of electrode segments 301 arranged at intervals in the first direction and the second direction. The above first direction (i.e., the direction parallel to Figure 8 the x-axis in Figure 8 and the second direction (i.e., the direction parallel to

[0070] the y-axis in Figure 8 are both parallel to the groove bottom surface 303c and perpendicular to each other.

[0071] Specifically, each electrode segment 301 is at least stacked on the groove side 303b and the groove bottom surface 303c. In some examples, as Figure 8 shown, each electrode segment 301 is stacked on the top surface 303a, the groove side 303b, and the groove bottom surface 303c of the insulating dielectric layer 303 having the groove 302, that is, a stepped structure in the shape of a "Z" is formed. In some other examples not shown in the drawings, each electrode segment 301 is stacked on the groove side 303b and the groove bottom surface 303c of the insulating dielectric layer 303 having the groove 302, that is, a stepped structure in the shape of an "L" is formed. Hereinafter, taking the preparation of a heating electrode with a "Z" - shaped stepped structure as an example, the preparation method adopted in the embodiments of the present application will be described in detail.

[0071] Specifically, the part where the electrode segment 301 (or the metal layer before its etching) is stacked on the top surface 303a of the insulating dielectric layer 303 is hereinafter referred to as the "step top", for example Figure 8 the step top 301a of the electrode segment 301 shown in Figure 8 The part where the electrode segment 301 (or the metal layer before its etching) is stacked on the groove bottom surface 303c of the insulating dielectric layer 303 is hereinafter referred to as the "step bottom", for example Figure 8 the step bottom 301b of the electrode segment 301 shown in

[0072] In the embodiments of the present application, a patterned mask structure is used to copy the target pattern onto the metal layer, and finally a heating electrode with a "Z" - shaped or "L" - shaped stepped structure is formed. The mask film layer of the patterned mask structure before patterning is, for example, a "sandwich structure". Specifically, as Figure 9As shown, the intermediate structure of the phase change memory includes, for example, an insulating dielectric layer 303 (e.g., SiO 2 ) with a groove 302, and a metal layer 3011, a "sandwich structure" 310, and a patterned photoresist layer 308 sequentially disposed on the insulating dielectric layer 303. Among them, the insulating dielectric layer 303 is, for example, disposed on the insulating dielectric 304; in addition, a plurality of columnar contact holes 309 for electrical contact with the metal layer 3011 are also provided through the insulating dielectric 304. The groove 302 of the insulating dielectric layer 303 penetrates along the thickness direction of the insulating dielectric layer 303. Taking the preparation of a heating electrode with a "Z" - shaped step structure as an example, the film layers in the metal layer 3011 and the "sandwich structure" 310 are all thin films covering the top surface, the side surface of the groove, and the bottom surface of the groove of the insulating dielectric layer 303, and there are step height differences at the groove 302 for these thin films. As Figure 10 shown, the patterned photoresist layer 308 includes a plurality of repeated array units arranged in an array. Among them, Figure 9 is a cross - sectional view of a repeated array unit along the Figure 10 x - direction in Figure 11 is a cross - sectional view of a repeated array unit along the Figure 10 y - direction in Figure 9 and Figure 11 shown, the "sandwich structure" 310 includes a hard mask layer 305, a soft mask layer 306, and an anti - reflection layer 307 sequentially disposed on the metal layer 3011. The patterned mask structure obtained by patterning the "sandwich structure" 310 can achieve smaller critical dimensions of the pattern and more accurate pattern transfer, so that etching of a heating electrode with smaller critical dimensions can be realized, which is beneficial to improving the storage unit distribution density of the phase change memory. Of course, in practical applications, the above - mentioned patterned mask structure can also use other mask structures to achieve patterning of the metal layer 3011, and the embodiments of the present application have no limitation on this.

[0073] In some embodiments, the insulating dielectric layer 303 includes, for example, SiO 2 .

[0074] In some embodiments, in order to reduce the standing - wave effect, the anti - reflection layer 307 further includes an organic bottom anti - reflection layer 307b and an inorganic dielectric anti - reflection layer 307a. The main component of the inorganic dielectric anti - reflection layer 307a includes, for example, SiOC. The main component of the soft mask layer 306 includes, for example, organic materials such as amorphous carbon, ODL, and APF. The main component of the hard mask layer 305 includes, for example, SiO 2 .

[0075] In some embodiments, the metal layer 3011 includes, for example, W, TiN, Ti, Al, Ta, AlO, TaN, TiO 2 , Ta 5O 2 At least one of etc.

[0076] In the above step S201, the patterned mask structure is a mask structure with a target pattern, and it is obtained after patterning the "sandwich structure" 310 shown in Figure 9 and Figure 11 In some examples, the patterned mask structure adopted in the above step S201 includes, for example, a hard mask pattern and a soft mask pattern obtained after patterning the hard mask layer and the soft mask layer, while the anti-reflection pattern obtained after patterning the anti-reflection layer and the patterned photoresist layer 308 have been basically etched away during the patterning process. That is to say, in the above step S201, the metal layer 3011 is etched using the hard mask pattern and the soft mask pattern as masks.

[0077] Each time the above step S201 (i.e., the etching step) is executed, a certain etching thickness is etched from the metal layer 3011. This etching thickness is less than the total etching thickness, and the total etching thickness is the thickness of the metal layer 3011. Moreover, the sum of the etching thicknesses of all the etching steps is equal to the total etching thickness. In this way, after all the etching steps are completed, it is possible to remove the part of the metal layer 3011 that is not covered by the patterned mask structure (the thickness of this part is equal to the total etching thickness). On this basis, after each execution of the above step S201 (i.e., the etching step), the above step S202 (i.e., the trimming step) is executed to remove the etching by-products generated in the previous etching step.

[0078] In the embodiments of the present application, the heating electrode with a "Z" - shaped or "L" - shaped stepped structure is etched by cyclically performing an etching step and a trimming step. On the one hand, the part of the metal layer 3011 not covered by the patterned mask structure is removed by means of step - by - step etching. Since the etching thickness of each etching step in multiple step - by - step etching is less than the total etching thickness, the etching time of each etching step is shorter. Therefore, compared with the related art where the corresponding part of the metal layer is removed by one - time etching at a lower etching speed, which will exacerbate the line - width loading effect due to the need for a longer over - etching time, it is easier to control the etching speed in each etching step of the present application. Even when a lower etching speed is used, the line - width loading effect will not be exacerbated due to too long an etching time. And a lower etching speed helps to reduce the etching speed difference in the vertical direction, making the etching speeds at various positions in the vertical direction tend to be consistent, thereby reducing the line - width loading effect. At the same time, for the metal layer 3011 with a step height difference, it can be avoided that the metal layer 3011 has been completely removed at some positions (such as the top of the step), while not completely removed at some other positions (such as the vertical part), resulting in metal residue, so as to improve the etching uniformity and avoid device short - circuit. On the other hand, since etching by - products are generated on both the side and bottom surfaces of the groove after each etching step, the accumulation of etching by - products will cause the etching speed at the top of the step to be faster than that at the bottom and vertical parts of the step, resulting in the line - width loading effect and metal residue. Therefore, by performing a trimming step after each etching step to remove the etching by - products, the metal to be etched can be exposed in time, thereby reducing the line - width loading effect, removing metal residue, and at the same time improving the etching uniformity and topography controllability.

[0079] In some embodiments, the above - mentioned step S201 (i.e., the etching step) and step S202 (i.e., the trimming step) both adopt an Inductive Coupled Plasma (ICP) device, for example. The ICP device has higher process precision compared with the CCP device and is suitable for scenarios with higher requirements for process precision. As Figure 16As shown, the ICP device 200 includes a process chamber 20, a gas inlet assembly 20A, an upper electrode assembly 20B, and a lower electrode assembly 20C. Among them, the gas inlet assembly 20A is used to introduce corresponding process gases into the interior of the process chamber 20; the upper electrode assembly 20B includes a radio frequency coil 21, an upper radio frequency power supply 23, and an upper matcher 25. The upper radio frequency power supply 23 supplies upper electrode power to the radio frequency coil 21 through the upper matcher 25, so that the radio frequency coil 21 excites the process gases inside the process chamber 20 to generate plasma. The radio frequency of the upper radio frequency power supply 23 is, for example, 13.56 MHz, and the power application method is continuous wave. The lower electrode assembly 20C includes a wafer carrier device 22, a lower radio frequency power supply 24, and a lower matcher 26. The wafer carrier device 22 is, for example, an electrostatic chuck. The lower radio frequency power supply 24 supplies lower electrode power to the lower electrode of the wafer carrier device 22 through the lower matcher 26 and supplies a lower radio frequency bias voltage to the lower electrode of the wafer carrier device 22 to attract the plasma above the wafer carrier device 22 to move toward the object 100 to be etched on the wafer carrier device 22, so as to achieve etching. The radio frequency of the lower radio frequency power supply 24 is, for example, 13.56 MHz, and the power application method is continuous wave or pulse wave. The object 100 to be etched is the metal layer 3011.

[0080] In some embodiments, in the above step S201 (i.e., the etching step), the metal layer 3011 is etched at a preset etching rate. The setting of the preset etching rate satisfies: reducing the etching rate difference existing in the extending direction (i.e., the vertical direction) from the top of the self-step to the bottom of the step, so that the etching rates at various positions in this extending direction tend to be consistent, thereby reducing the loading effect of the line width. The range of the preset etching rate to achieve this effect is, for example, greater than or equal to and less than or equal to Preferably etc. In practical applications, the above range of the preset etching rate can be set according to factors such as the thickness of the metal layer 3011, the step height difference, the device model, and the chip size.

[0081] In the above step S201 (i.e., the etching step), the preset etching rate includes a lateral etching rate and a longitudinal etching rate. The lateral etching rate mainly affects factors such as the critical dimensions and width uniformity of the heating electrode, and these factors ultimately affect the electrical performance of the device; the longitudinal etching rate mainly affects factors such as etching efficiency and etching defects.

[0082] The method for controlling the above-mentioned preset etching rate within the required range includes, for example: in the above step S201 (i.e., the etching step), the lower RF power supply 24 outputs a pulsed power signal. The RF frequency of the lower RF power supply 24 is, for example, 13.56 MHz, the power application mode is a pulsed wave, and the control mode of the lower RF power supply 24 can be selected between a power mode and a voltage mode. By applying a pulsed power signal to the lower electrode in the pulsed wave power application mode, not only can the above-mentioned preset etching rate be controlled by controlling the duty cycle and / or frequency of the pulsed power signal, but also it is beneficial to the discharge of etching by-products.

[0083] Further, in some embodiments, in order to reduce the etching rate to reduce the loading effect of the line width, in the above step S201 (i.e., the etching step), the duty cycle of the pulsed power signal is greater than or equal to 30% and less than or equal to 50%.

[0084] In some embodiments, in order to reduce the etching rate to reduce the loading effect of the line width, in the above step S201 (i.e., the etching step), the frequency of the pulsed power signal is greater than or equal to 180 Hz and less than or equal to 220 Hz.

[0085] The method for controlling the above-mentioned preset etching rate within the required range also includes, for example: in the above step S201 (i.e., the etching step), a lower chamber pressure is adopted. Further, in some embodiments, in order to reduce the etching rate to reduce the loading effect of the line width, the chamber pressure is greater than or equal to 3 mT and less than or equal to 10 mT.

[0086] The method for controlling the above-mentioned preset etching rate within the required range also includes, for example: in the above step S201 (i.e., the etching step), a lower RF power output by the lower RF power supply is adopted. Further, in some embodiments, in order to reduce the etching rate to reduce the loading effect of the line width, the lower RF power output by the lower RF power supply is greater than or equal to 30 W and less than or equal to 50 W.

[0087] The method for controlling the above-mentioned preset etching rate within the required range also includes, for example: in the above step S201 (i.e., the etching step), a lower RF power output by the upper RF power supply is adopted. Further, in some embodiments, in order to reduce the etching rate to reduce the loading effect of the line width, the upper RF power output by the upper RF power supply is greater than or equal to 250 W and less than or equal to 450 W.

[0088] Any one or a combination of the above several methods can be selected to control the above-mentioned preset etching rate within the required range to reduce the loading effect of the line width, and finally obtain Figure 8The heating electrode with a uniform line width as shown. However, the embodiments of the present application are not limited to the above several methods for controlling the etching rate. In practical applications, any other method capable of controlling the etching rate can also be used, which all fall within the protection scope of the present application.

[0089] In the above step S201 (i.e., the etching step), for metal layers 3011 of different materials, different types and flow rates of process gases are used. For example, when the material of the metal layer 3011 includes tungsten (W), the process gases used in the above step S201 (i.e., the etching step) include a main etching gas, a dilution gas, and an auxiliary etching gas. Among them, the main etching gas includes NF 3 and Cl 2 , the flow rate of NF 3 is greater than or equal to 10 sccm and less than or equal to 100 sccm; the flow rate of Cl 2 is greater than or equal to 10 sccm and less than or equal to 100 sccm; the dilution gas includes He, and the flow rate of He is greater than or equal to 50 sccm and less than or equal to 150 sccm; the auxiliary etching gas includes N 2 , the flow rate of N 2 is greater than or equal to 50 sccm and less than or equal to 150 sccm.

[0090] For another example, when the material of the metal layer 3011 includes titanium nitride (TiN), the process gases used in the etching step include a main etching gas, a dilution gas, and an etching protection gas. Among them, the main etching gas includes Cl 2 , the flow rate of Cl 2 is greater than or equal to 30 sccm and less than or equal to 70 sccm; the dilution gas includes N 2 , the flow rate of N 2 is greater than or equal to 50 sccm and less than or equal to 150 sccm; the etching protection gas includes CH 4 , the flow rate of CH 4 is greater than or equal to 5 sccm and less than or equal to 15 sccm.

[0091] For yet another example, when the material of the metal layer 3011 includes Ti, TiN, Ta, TaN, TiO 2 , Ta 5 O 2 , the process gases used in the etching step include a main etching gas, a dilution gas, and an etching protection gas. Among them, the main etching gas includes BCl 3 and Cl 2 , the flow rate of BCl 3 is greater than or equal to 0 sccm and less than or equal to 100 sccm; the flow rate of Cl 2 is greater than or equal to 30 sccm and less than or equal to 70 sccm; the dilution gas includes N2 , N 2 has a flow rate greater than or equal to 50 sccm and less than or equal to 150 sccm; the etching protection gas includes CH 4 , CH 4 has a flow rate greater than or equal to 5 sccm and less than or equal to 15 sccm. The addition of BCl 3 can enhance the physical bombardment effect of the etching step and expand the applicable range of metal materials. In practical applications, the flow rate of BCl 3 can be set according to the characteristics of different materials of the metal layer 3011. In addition, the materials of the metal layer 3011 applicable to the above parameters are not limited to the above materials, but also applicable to other materials similar to the characteristics of these materials.

[0092] In some embodiments, in the above step S202 (i.e., the trimming step), the process gas used includes H 2 and N 2 , H 2 has a flow rate greater than or equal to 100 sccm and less than or equal to 200 sccm; N 2 has a flow rate greater than or equal to 100 sccm and less than or equal to 200 sccm. The plasma generated by H 2 and N 2 can react with the by-products containing elements such as Cl, F, N, C, Ti, etc. generated during the metal etching process to produce gaseous by-products that are more volatile, and are discharged from the process chamber by the vacuum pumping device along with the gas flow, so as to remove the etching by-products attached to the side of the groove and expose the metal to be etched to the etching environment again.

[0093] In some embodiments, in the above step S202 (i.e., the trimming step), in order to enable the etching by-products to be smoothly discharged from the process chamber, the chamber pressure is greater than or equal to 10 mT and less than or equal to 20 mT.

[0094] In some embodiments, in the above step S202 (i.e., the trimming step), the lower radio frequency power supply outputs a continuous power signal, and the output lower radio frequency voltage is greater than or equal to 30 V and less than or equal to 50 V.

[0095] In some embodiments, in the above step S202 (i.e., the trimming step), the upper radio frequency power output by the upper radio frequency power supply is greater than or equal to 600 W and less than or equal to 800 W.

[0096] As a comparative example of the embodiments of the present application, when the material of the metal layer 3011 includes titanium nitride, the comparative example uses a one-step etching method to etch the metal layer 3011, and the process parameters used in the comparative example are: the process gas includes Cl 2 , Cl 2The flow rate is equal to 120 sccm, the chamber pressure is equal to 10 mT, the upper RF power output by the upper RF power supply is equal to 800 W, and the lower RF bias voltage output by the lower RF power supply is equal to 55 V; the process time is 15 s. Experiments using these process parameters show that the process parameters used in the comparative example meet the strong etching conditions, and the bottom of the step is etched away after 15 s of etching time. of the thickness, and the etching rate at the bottom of the step is approximately while the etching rate at the top of the step is twice that at the bottom of the step, the etching rate is relatively fast. Finally, the line width at the top of the step of the heating electrode obtained is approximately 50 nm, and the line width at the bottom is approximately 100 nm. Therefore, the line width at the top of the step of the heating electrode obtained in the comparative example is smaller than the line width at the bottom of the step, showing an obvious line width loading effect. Moreover, due to the too-fast etching rate, this will cause the position where the top of the step contacts the plasma to be etched too fast, while the bottom and vertical parts of the step have not been etched, resulting in problems such as metal residue and device short circuit.

[0097] As another comparative example of the embodiment of the present application, when the material of the metal layer 3011 includes titanium nitride, this comparative example uses a one-step etching method to etch the metal layer 3011, and the process parameters used in the comparative example are: the process gas includes Cl 2 、N 2 and CH 4 , the flow rate of Cl 2 is equal to 60 sccm, the flow rate of N 2 is equal to 50 sccm, and the flow rate of CH 4The flow rate is equal to 15 sccm, the chamber pressure is equal to 5 mT, the upper RF power output by the upper RF power supply is equal to 600 W, and the lower RF bias voltage output by the lower RF power supply is equal to 70 V; the process time is 15 s. The lower RF power supply outputs a pulsed power signal. The difference between this comparative example and the embodiment of the present application is that multi-step etching is not used and a trimming step is not used. It can be known from the experiment using the process parameters of this comparative example that the process parameters used in the comparative example meet the weak etching conditions, and by making the lower RF power supply output a pulsed power signal, the etching rates at the top and bottom of the step can be made basically the same, and the line widths at the top and bottom of the step of the heating electrode obtained after etching are similar. However, due to the absence of a trimming step, there is a problem of accumulation of etching by-products, resulting in the inability to etch the metal on the side and bottom of the groove, so that more unetched metal remains at the bottom of the groove, and there is also unetched metal on the side of the groove, and the lateral etching amount is significantly insufficient, ultimately leading to device short circuit. On this basis, if the etching time is extended to 30 s, the line width at the top of the step of the obtained heating electrode will be significantly reduced, resulting in an aggravated loading effect, while the unetched metal at the bottom and side of the groove still exists. In addition, if the lower RF bias voltage output by the lower RF power supply in the comparative example is increased, the vertical etching can be increased to remove the unetched metal remaining at the bottom of the groove, but there is still unetched metal on the side of the groove, and at the same time, the higher lower RF bias voltage will again cause an etching rate difference between the top and top of the step, aggravating the loading effect.

[0098] In the embodiment of the present application, by adopting the method of cyclically executing the etching step and the trimming step, it is easier to control the etching rate, and the etching rate can be controlled within a lower range, for example, less than or equal to It can effectively reduce the loading effect of the line width, and the step-by-step etching method will not aggravate the loading effect of the line width due to too long etching time. Moreover, it can avoid the situation where the metal layer has been completely removed at some positions (such as the top of the step) due to too fast etching rate, while not being completely removed at some other positions (such as the vertical part), thereby improving the etching uniformity and avoiding device short circuit. In addition, by performing a trimming step after each etching step to remove the etching by-products, the metal to be etched can be exposed in time, thereby reducing the loading effect of the line width, removing metal residues, and at the same time improving the etching uniformity and topography controllability.

[0099] In Related Art 2, a capacitively coupled plasma (CCP) chamber is usually used to etch and form a patterned mask structure, and then it is transferred to an ICP chamber to etch the metal layer. This etching method has low efficiency and requires multiple devices, which is not conducive to large-scale production.

[0100] To solve the above problems, in the embodiments of the present application, the steps of forming a patterned mask structure and the repeatedly executed etching step and trimming step are sequentially performed in the same plasma etching chamber. This can improve production efficiency. The plasma etching chamber is, for example, an ICP chamber.

[0101] In an embodiment where the mask layer before patterning of the patterned mask structure is a "sandwich structure", as Figure 12 shown, the steps of forming the patterned mask structure may include:

[0102] S101, as Figure 9 shown, a hard mask layer 305, a soft mask layer 306, an anti-reflection layer 307, and a patterned photoresist layer 308 are sequentially formed on the metal layer 3011;

[0103] S102, using the patterned photoresist layer 308 as a mask, etching the anti-reflection layer 307 to remove the portion of the anti-reflection layer 307 not covered by the patterned photoresist layer 308 to form an anti-reflection pattern;

[0104] The above step S102 is used to etch the anti-reflection layer 307 using the patterned photoresist layer 308 as a mask, so as to copy the pattern of the patterned photoresist layer 308 onto the anti-reflection layer 307, thereby forming an anti-reflection pattern. Taking the anti-reflection layer 307 including an organic bottom anti-reflection layer 307b and an inorganic dielectric anti-reflection layer 307a as an example, the anti-reflection pattern includes an organic bottom anti-reflection pattern 3072 and an inorganic dielectric anti-reflection pattern 3071, as Figure 13 shown.

[0105] The above step S102 can detect the end time of dry etching by controlling the etching time or by using the endpoint detection method of OES (Optical Emission Spectroscopy).

[0106] In some embodiments, the above step S102 uses an inductively coupled plasma (ICP) etching device to Figure 9 etch the anti-reflection layer 307 as shown. As Figure 16 shown in the ICP device 200.

[0107] The process parameters of the above step S102 are, for example, as follows: The process gas used in step S102 includes a main etching gas, an auxiliary etching gas, and a dilution gas. Among them, the main etching gas includes CF 4 , CF 4 The gas flow rate of is greater than or equal to 50 sccm and less than or equal to 150 sccm; The auxiliary etching gas is used to cooperate with the main etching gas to etch the anti-reflection layer 307. The auxiliary etching gas includes CH 2F 2 、CHF 3 、N 2 , where at least one of CH 2 F 2 and CHF 3 can be introduced. By controlling the flow rate ratios of various different gases in the auxiliary etching gas, the critical dimension of the etched antireflection layer can be controlled. The gas flow rate of CH 2 F 2 is greater than or equal to 0 sccm and less than or equal to 150 sccm; the gas flow rate of CHF 3 is greater than or equal to 0 sccm and less than or equal to 150 sccm; the gas flow rate of N 2 is greater than or equal to 20 sccm and less than or equal to 80 sccm; the dilution gas includes He, and the gas flow rate of He is greater than or equal to 0 sccm and less than or equal to 100 sccm. The chamber pressure used in step S102 is greater than or equal to 5 mT and less than or equal to 30 mT; the upper electrode power output by the upper RF power supply is greater than or equal to 400 W and less than or equal to 800 W; the RF bias provided by the lower electrode of the wafer carrier device is greater than or equal to 50 V and less than or equal to 200 V. The etching time is greater than or equal to 5 s and less than or equal to 100 s, and the heating temperature of the wafer carrier device is greater than or equal to 25 °C and less than or equal to 35 °C.

[0108] S103. Using the antireflection pattern as a mask, etch the soft mask layer 306 to remove the portion of the soft mask layer 306 not covered by the antireflection pattern, thereby forming a soft mask pattern;

[0109] The above step S103 is used to etch the soft mask layer 306 with the antireflection pattern (the patterned photoresist layer 308 has not been removed before step S103) as a mask, so as to copy the pattern of the patterned photoresist layer 308 onto the soft mask layer 306, thereby forming a soft mask pattern 3061. The soft mask pattern 3061 is as shown in Figure 14 . It is easy to understand that after completing the above step S103, the antireflection pattern and the patterned photoresist layer 308 are basically etched away and do not require additional steps to remove.

[0110] The process parameters of the above step S103 are as follows, for example: The process gas used in step S103 includes a main etching gas, an auxiliary etching gas, and a dilution gas (carrier gas). Among them, the main etching gas includes O 2 , and at least one of Cl 2 and HBr. The gas flow rate of O 2 is greater than or equal to 50 sccm and less than or equal to 150 sccm; the gas flow rate of Cl 2The gas flow rate is greater than or equal to 30 sccm and less than or equal to 100 sccm; the gas flow rate of HBr is greater than or equal to 30 sccm and less than or equal to 100 sccm; the auxiliary etching gas includes N 2 , N 2 The gas flow rate is greater than or equal to 0 sccm and less than or equal to 50 sccm; the dilution gas (carrier gas) includes He, and the gas flow rate of He is greater than or equal to 0 sccm and less than or equal to 100 sccm. Among them, O 2 and Cl 2 / HBr combination forms a plasma to etch the soft mask layer 306. Cl / HBr can form a polymer anti-etching layer, thereby improving anisotropic etching. A high flow rate of O 2 can increase the etching rate. By adjusting the flow rate ratio of O 2 , Cl 2 and HBr, a vertical etching profile can be obtained while achieving a relatively fast etching rate. The addition of N 2 can form polymers with C / Cl / Br, etc., which helps to avoid the generation of bow-shaped profiles.

[0111] The chamber pressure used in step S103 is greater than or equal to 5 mT and less than or equal to 30 mT; the upper electrode power output by the upper RF power supply is greater than or equal to 300 W and less than or equal to 800 W; the lower electrode of the wafer carrier provides an RF bias voltage greater than or equal to 200 V and less than or equal to 400 V. The etching time is greater than or equal to 20 s and less than or equal to 100 s, and the heating temperature of the wafer carrier is greater than or equal to 25 °C and less than or equal to 35 °C.

[0112] The above step S103 can detect the end time of dry etching by controlling the etching time or by using the endpoint detection method of OES (Optical Emission Spectroscopy).

[0113] In some embodiments, the above step S103 uses an inductively coupled plasma (ICP) etching device to etch the anti-reflection layer 307. For example, the ICP device 200 as shown in Figure 16 is used.

[0114] S104. Using the soft mask pattern 3061 as a mask, etch the hard mask layer 305 to remove the part of the hard mask layer 305 not covered by the soft mask pattern 3061 to form a hard mask pattern, and retain the soft mask pattern 3061.

[0115] The above step S104 is used to etch the hard mask layer 305 with the soft mask pattern 3061 as a mask, so as to copy the soft mask pattern 3061 onto the hard mask layer 305, thereby forming a hard mask pattern 3051. The hard mask pattern 3051 is as Figure 15 shown.

[0116] Using the hard mask pattern 3051 can transfer the pattern more accurately. A relatively thin hard mask pattern 3051 can achieve film layer transfer. At the same time, by retaining the hard mask pattern 3051, the surface of the heating electrode can be protected.

[0117] The above step S104 can detect the end time of the dry etching by controlling the etching time or by using the endpoint detection method of OES (Optical Emission Spectroscopy).

[0118] In some embodiments, the above step S104 uses an inductively coupled plasma (ICP) etching device to etch the anti-reflection layer 307. For example, an ICP device 200 as Figure 16 shown is used.

[0119] The process parameters of the above step S104 are as follows: The process gas used in step S104 includes a main etching gas, an auxiliary etching gas, and a dilution gas (carrier gas). Among them, the main etching gas includes CF 4 , CF 4 The gas flow rate of is greater than or equal to 80 sccm and less than or equal to 120 sccm; the auxiliary etching gas includes CHF 3 , CHF 3 The gas flow rate of is greater than or equal to 20 sccm and less than or equal to 80 sccm; the dilution gas (carrier gas) includes He, and the gas flow rate of He is greater than or equal to 0 sccm and less than or equal to 100 sccm. The gas combination of CF 4 / CHF 3 / He has a relatively high etching selectivity ratio and can achieve relatively accurate pattern transfer.

[0120] The chamber pressure used in step S104 is greater than or equal to 3 mT and less than or equal to 10 mT; the upper electrode power output by the upper radio frequency power supply is greater than or equal to 400 W and less than or equal to 800 W; the lower electrode of the wafer carrier device provides a radio frequency bias voltage greater than or equal to 50 V and less than or equal to 200 V. The etching time is greater than or equal to 5 s and less than or equal to 35 s, and the heating temperature of the wafer carrier device is greater than or equal to 25 °C and less than or equal to 35 °C.

[0121] In Related Art Two, generally, the patterning of the soft mask layer and the hard mask layer is first performed using a CCP chamber, then the soft mask layer is ashed and removed, and then the metal layer 3011 is etched using the hard mask layer as a mask. In contrast, as Figure 15 shown, after completing the above step S104 in the embodiment of the present application, the soft mask pattern 3061 and the hard mask pattern 3051 are retained, and when performing the etching step, the metal layer 3011 is etched using the soft mask pattern 3061 and the hard mask pattern 3051 as masks. That is, the patterning mask structure used in the etching step includes the soft mask pattern 3061 and the hard mask pattern 3051. In this way, it is more convenient to sequentially perform the formation step of the patterning mask structure and the repeatedly executed etching step and trimming step in the same plasma etching chamber.

[0122] It should be noted that in the above step S104, by adopting a lower chamber pressure, the generated polymers (including the C-containing by-products generated by etching the soft mask layer) can be timely discharged from the process chamber by the vacuum pumping device, so as to avoid the by-products in the grooves with smaller openings being not easily carried away by the gas flow and hindering the etching reaction, resulting in a line width loading effect between the pattern sparse area and the pattern dense area.

[0123] After completing the cycle process of the above step S201 (i.e., the etching step) and step S202 (i.e., the trimming step), the heating electrode preparation method provided by the embodiment of the present application may further include:

[0124] S301. An over-etching step for etching the dielectric layer under the heating electrode.

[0125] The dielectric layer includes, for example, an insulating dielectric layer under the top of the step of the heating electrode and an insulating dielectric under the bottom of the step of the heating electrode.

[0126] The process parameters adopted in the above step S301 are, for example, substantially the same as those adopted in the above step S104, and the etching time is greater than or equal to 5 s and less than or equal to 10 s.

[0127] S302. Remove the soft mask pattern 3061 and the remaining patterned photoresist layer and C-containing by-products.

[0128] The process parameters of the above step S302 are, for example, as follows: The process gas adopted in step S302 includes O 2 , O 2The gas flow rate is greater than or equal to 300 sccm and less than or equal to 500 sccm; the chamber pressure is greater than or equal to 5 mT and less than or equal to 20 mT; the upper electrode power output by the upper RF power supply is greater than or equal to 1000 W and less than or equal to 1500 W; the lower electrode power output by the lower RF power supply is greater than or equal to 0 W and less than or equal to 50 W. The etching time is greater than or equal to 60 s and less than or equal to 100 s, and the heating temperature of the wafer carrier device is 50 °C.

[0129] By retaining the hard mask pattern 3051, the surface of the heating electrode is protected from being oxidized to metal oxide, avoiding the change of its resistance value or open circuit. Thus, the etching process of the heating electrode of the phase change memory is completed.

[0130] Figure 16 The figure shows a schematic structural diagram of a semiconductor process equipment according to an embodiment of the present application.

[0131] As Figure 16 shown, the semiconductor process equipment 200 includes a process chamber 20, an intake component 20A, an upper electrode component 20B, a lower electrode component 20C, and a controller ( Figure 11 not shown in the figure). The controller includes at least one processor and at least one memory, and a computer program is stored in the memory. When the computer program is executed by the processor, the method of any of the above embodiments is implemented.

[0132] Exemplarily, the controller can be a host computer or a slave computer. Among them, the controller can control the opening of the valve of the intake component 20A to introduce the corresponding process gas into the interior of the process chamber 20; the controller can also control the opening degree of the valve of the intake component 20A to control the gas flow rate. The controller can also control the evacuation of the interior of the process chamber 20 by the evacuation component to control the pressure inside the process chamber 20 and discharge reaction by-products, etc.

[0133] The upper electrode component 20B includes a radio frequency coil 21, an upper RF power supply 23, and an upper matcher 25. The controller is further configured to control the upper RF power supply 23 to provide upper electrode power to the radio frequency coil 21 through the upper matcher 25, so that the radio frequency coil 21 excites the process gas inside the process chamber 20 to generate plasma.

[0134] The lower electrode component 20C includes a wafer carrier device 22, a lower RF power supply 24, and a lower matcher 26. The controller is further configured to control the lower RF power supply 24 to provide lower electrode power to the lower electrode of the wafer carrier device 22 through the lower matcher 26, so that the lower electrode of the wafer carrier device 22 provides a radio frequency bias voltage to adsorb the plasma above the object to be etched 100 and bombard the object to be etched 100.

[0135] The semiconductor process equipment 200 according to the embodiments of the present application may be an inductively coupled plasma (ICP) etching equipment, or may be a capacitively coupled plasma (CCP) etching equipment. The embodiments of the present application do not limit the type of the semiconductor process equipment 200.

[0136] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present application. However, the present application is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present application, and these modifications and improvements are also regarded as the protection scope of the present application.

Claims

1. A method for preparing a heating electrode, characterized in that: include: An etching step, using a patterned mask structure to pattern-etch the metal layer formed on the insulating dielectric layer having the groove; A trimming step to remove etching byproducts; cyclically executing the etching step and the trimming step until the portion of the metal layer not covered by the patterned mask structure is removed to form the heating electrode; Wherein, the groove has two groove side surfaces opposite to each other in a first direction, and a groove bottom surface; the heating electrode includes a plurality of electrode splits arranged at intervals along the first direction and the second direction, and each of the electrode splits is at least overlapped on the groove side surface and the groove bottom surface; the first direction and the second direction are both parallel to the groove bottom surface and perpendicular to each other.

2. The method for preparing a heating electrode according to claim 1, characterized in that: In the etching step, the metal layer is etched at a preset etching speed; The preset etching speed is greater than or equal to and less than or equal to 3. The method for preparing a heating electrode according to claim 1 or 2, characterized in that: In the etching step, the lower radio frequency power supply outputs a pulse power signal.

4. The method for preparing a heating electrode according to claim 3, characterized in that: In the etching step, the duty cycle of the pulse power signal is greater than or equal to 30% and less than or equal to 50%; the frequency of the pulse power signal is greater than or equal to 180 Hz and less than or equal to 220 Hz.

5. The method for preparing a heating electrode according to claim 4, characterized in that: In the etching step, the lower RF power output by the lower RF power supply is greater than or equal to 30W and less than or equal to 50W; or, The upper RF power output by the upper RF power supply is greater than or equal to 250 W and less than or equal to 450 W.

6. The method for preparing a heating electrode according to claim 1 or 2, characterized in that: In the etching step, the chamber pressure is greater than or equal to 3 mT and less than or equal to 10 mT.

7. The method for preparing a heating electrode according to claim 1 or 2, characterized in that: The material of the metal layer includes W; the process gas used in the etching step includes a main etching gas, a dilution gas and an auxiliary etching gas; The main etching gas includes NF3 and Cl2, the flow rate of NF3 is greater than or equal to 10sccm and less than or equal to 100sccm; the flow rate of Cl2 is greater than or equal to 10sccm and less than or equal to 100sccm; the dilution gas includes He, the flow rate of He is greater than or equal to 50sccm and less than or equal to 150sccm; the auxiliary etching gas includes N2, the flow rate of N2 is greater than or equal to 50sccm and less than or equal to 150sccm.

8. The method for preparing a heating electrode according to claim 1 or 2, characterized in that: The material of the metal layer includes TiN; the process gas used in the etching step includes a main etching gas, a dilution gas and an etching protection gas; The main etching gas includes Cl2, and the flow rate of Cl2 is greater than or equal to 30sccm and less than or equal to 70sccm; the dilution gas includes N2, and the flow rate of N2 is greater than or equal to 50sccm and less than or equal to 150sccm; the etching protection gas includes CH4, and the flow rate of CH4 is greater than or equal to 5sccm and less than or equal to 15sccm.

9. The method for preparing a heating electrode according to claim 1 or 2, characterized in that: The material of the metal layer includes at least one of Ti, TiN, Ta, TaN, TiO2, and Ta5O2; The process gas used in the etching step includes main etching gas, dilution gas and etching protection gas; The main etching gas includes BCl3 and Cl2, the flow rate of BCl3 is greater than or equal to 0 sccm and less than or equal to 100 sccm; the flow rate of Cl2 is greater than or equal to 30 sccm and less than or equal to 70 sccm; the dilution gas includes N2, the flow rate of N2 is greater than or equal to 50 sccm and less than or equal to 150 sccm; the etching protection gas includes CH4, the flow rate of CH4 is greater than or equal to 5 sccm and less than or equal to 15 sccm.

10. The method for preparing a heating electrode according to claim 1 or 2, characterized in that: The process gases used in the trimming step include H2 and N2, the flow rate of H2 is greater than or equal to 100 sccm and less than or equal to 200 sccm; the flow rate of N2 is greater than or equal to 100 sccm and less than or equal to 200 sccm.

11. The method for preparing a heating electrode according to claim 1 or 2, characterized in that: In the trimming step, the chamber pressure is greater than or equal to 10 mT and less than or equal to 20 mT; or, The lower RF voltage output by the lower RF power supply is greater than or equal to 30V and less than or equal to 50V; or, The upper RF power output by the upper RF power supply is greater than or equal to 600 W and less than or equal to 800 W.

12. The method for preparing a heating electrode according to claim 1, characterized in that: The step of forming the patterned mask structure and the etching step and the trimming step are performed cyclically in the same plasma etching chamber.

13. The method for preparing a heating electrode according to claim 12, characterized in that: The step of forming the patterned mask structure comprises: forming a hard mask layer, a soft mask layer, an anti-reflection layer, and a patterned photoresist layer on the metal layer in sequence; Using the patterned photoresist layer as a mask, etching the anti-reflection layer to remove the portion of the anti-reflection layer not covered by the patterned photoresist layer, so as to form an anti-reflection pattern; Using the anti-reflection pattern as a mask, etching the soft mask layer to remove the portion of the soft mask layer not covered by the anti-reflection pattern, so as to form a soft mask pattern; Using the soft mask pattern as a mask, etching the hard mask layer to remove the portion of the hard mask layer not covered by the soft mask pattern to form a hard mask pattern, and retaining the soft mask pattern; The patterned mask structure includes the hard mask pattern and the soft mask pattern.

14. A semiconductor process equipment, comprising a process chamber, an air intake assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that: The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method for preparing a heating electrode according to any one of claims 1 to 13 is implemented.

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