Array substrate and display device

Abstract

An array substrate and a display device. The array substrate comprises a substrate (13) and a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially arranged on one side of the substrate (13); the fourth conductive layer comprises a common electrode (21), the material of the fourth conductive layer is transparent conductive oxide material, the material of the third conductive layer is metal conductive material, and at least part of the surface of the third conductive layer away from the substrate (13) is in contact with at least part of the surface of the fourth conductive layer close to the substrate (13).

Description

TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, the technical field of display, and in particular to an array substrate and a display device. BACKGROUND

[0002] Liquid Crystal Display (LCD) is a common display type. LCD display uses two polarized materials between which is a liquid crystal solution. When current passes through the liquid, the crystals are rearranged so that light cannot pass through them. Therefore, each crystal is like a louver that can allow light to pass through and block light. Currently, liquid crystal display (LCD) is developing towards the goal of light, thin, short and small. SUMMARY

[0003] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present application provide an array substrate and a display device.

[0005] In one aspect, the embodiments of the present application provide an array substrate. The array substrate comprises a substrate, and a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are sequentially stacked on one side of the substrate; the fourth conductive layer comprises a common electrode, the material of the fourth conductive layer is a transparent conductive oxide material, the material of the third conductive layer is a metal conductive material, and at least part of the surface of the third conductive layer away from the substrate side is in contact with at least part of the surface of the fourth conductive layer close to the substrate side.

[0006] In an exemplary embodiment, the third conductive layer comprises at least one signal line extending in a first direction, or the third conductive layer comprises at least one signal line extending in a second direction, the first direction and the second direction intersecting;

[0007] At least part of the surface of the at least one signal line away from the substrate side is in contact with at least part of the surface of the common electrode close to the substrate side.

[0008] In an exemplary embodiment, the second conductive layer comprises a plurality of gate lines, and the plurality of gate lines extend in the first direction and are spaced apart in the second direction; the at least one signal line comprises at least one common electrode line, and the at least one common electrode line extends in the first direction, and at least part of the surface of the at least one common electrode line away from the substrate side is in contact with at least part of the surface of the common electrode close to the substrate side.

[0009] In an example embodiment, the common electrode line is located within the projection of the gate line on the array substrate.

[0010] In an example embodiment, the first conductive layer comprises a plurality of data lines, and the plurality of data lines are arranged spaced apart along the first direction and extend along the second direction; the at least one signal line comprises at least one touch control line, and the at least one touch control line extends along the second direction, and at least part of the surface of the at least one touch control line away from the substrate side is in contact with at least part of the surface of the common electrode close to the substrate side.

[0011] In an example embodiment, the projection of the touch control line on the array substrate at least partially overlaps the projection of the data line on the array substrate.

[0012] In an example embodiment, the projection of the touch control line on the array substrate is located within the projection of the data line on the array substrate.

[0013] In an example embodiment, the array substrate comprises a display area and a frame area located at the periphery of the display area; the display area comprises at least one first transistor, the first transistor comprises a first active layer and a first gate, the first active layer is located between the first conductive layer and the second conductive layer, the first gate is located on the second conductive layer, and the first conductive layer comprises a plurality of data lines.

[0014] The first active layer and the data line are electrically connected via a data connection electrode, and at least part of the data connection electrode is located on the third conductive layer.

[0015] In an example embodiment, the data connection electrode comprises a bottom connection electrode and a top connection electrode arranged in a stack, the bottom connection electrode is located on the third conductive layer, the top connection electrode is located on the fourth conductive layer, and at least part of the surface of the bottom connection electrode away from the substrate side is in contact with at least part of the surface of the top connection electrode close to the substrate side.

[0016] In an example embodiment, the projection of the top connection electrode on the array substrate comprises the projection of the bottom connection electrode on the array substrate.

[0017] In an example embodiment, the array substrate comprises a display area and a frame area located at the periphery of the display area; the frame area comprises at least one second transistor, the second transistor comprises a second active layer and a second gate, the second active layer is located between the first conductive layer and the second conductive layer, and the second gate is located on the second conductive layer.

[0018] The frame region comprises a first connection electrode, the second active layer is electrically connected with the first connection electrode, and at least part of the first connection electrode is located on the third conductive layer.

[0019] In an exemplary embodiment, the first connection electrode comprises a first sub-electrode and a second sub-electrode arranged in a stack, the first sub-electrode is located on the third conductive layer, the second sub-electrode is located on the fourth conductive layer, and at least part of a surface of the first sub-electrode away from the substrate side is in contact with at least part of a surface of the second sub-electrode close to the substrate side.

[0020] In an exemplary embodiment, the second sub-electrode comprises a projection on the array substrate.

[0021] In an exemplary embodiment, the array substrate comprises a display region and a frame region located at a periphery of the display region; the frame region comprises at least one second transistor, the second transistor comprises a second active layer and a second gate electrode, the second active layer is located between the first conductive layer and the second conductive layer, and the second gate electrode is located on the second conductive layer.

[0022] The frame region further comprises a first auxiliary electrode, the first auxiliary electrode is located on the second conductive layer, and the first auxiliary electrode is electrically connected with the second active layer via a first connection electrode, at least part of the first connection electrode is located on the third conductive layer.

[0023] In an exemplary embodiment, the first connection electrode comprises a first sub-electrode and a second sub-electrode arranged in a stack, the first sub-electrode is located on the third conductive layer, the second sub-electrode is located on the fourth conductive layer, and at least part of a surface of the first sub-electrode away from the substrate side is in contact with at least part of a surface of the second sub-electrode close to the substrate side.

[0024] In another aspect, the embodiments of the present disclosure provide a display device. The display device comprises the array substrate of any of the above-mentioned embodiments, a counter substrate, and a liquid crystal layer; the array substrate and the counter substrate are arranged oppositely, and the liquid crystal layer is located between the array substrate and the counter substrate.

[0025] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0026] SUMMARY

[0027] The accompanying drawings are used to provide further understanding of the technical solutions of the present disclosure, and form a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shapes and sizes of one or more components in the drawings do not reflect true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0028] Figure 1 A front view of an array substrate of an embodiment of the present disclosure;

[0029] Figure 2 A partial cross-sectional view of a display area of an array substrate of an embodiment of the present disclosure;

[0030] Figure 3 A partial cross-sectional view of a second frame area of an array substrate of an embodiment of the present disclosure;

[0031] Figure 4 A partial cross-sectional view of a second frame area of an array substrate of another embodiment of the present disclosure;

[0032] Figure 5A A top view of a partial formation of a first conductive layer pattern of a display area of an array substrate of an embodiment of the present disclosure;

[0033] Figure 5B A cross-sectional view of a partial formation of a first conductive layer pattern of a display area of an array substrate of an embodiment of the present disclosure;

[0034] Figure 5C A cross-sectional view of a partial formation of a first conductive layer pattern of a second frame area of an array substrate of an embodiment of the present disclosure;

[0035] Figure 6A A top view of a partial formation of a semiconductor layer pattern of a display area of an array substrate of an embodiment of the present disclosure;

[0036] Figure 6B A cross-sectional view of a partial formation of a semiconductor layer pattern of a display area of an array substrate of an embodiment of the present disclosure;

[0037] Figure 6C A cross-sectional view of a partial formation of a semiconductor layer pattern of a second frame area of an array substrate of an embodiment of the present disclosure;

[0038] Figure 7A A top view of a partial formation of a second conductive layer pattern of a display area of an array substrate of an embodiment of the present disclosure;

[0039] Figure 7B A cross-sectional view of a partial formation of a second conductive layer pattern of a display area of an array substrate of an embodiment of the present disclosure;

[0040] Figure 7C A cross-sectional view of a second frame region of an array substrate of an embodiment of the present disclosure partially forming a second conductive layer pattern;

[0041] Figure 8A A top view of a display region of an array substrate of an embodiment of the present disclosure partially forming a third insulating layer pattern;

[0042] Figure 8B A cross-sectional view of a display region of an array substrate of an embodiment of the present disclosure partially forming a third insulating layer pattern;

[0043] Figure 8C A cross-sectional view of a second frame region of an array substrate of an embodiment of the present disclosure partially forming a third insulating layer pattern;

[0044] Figure 9A A top view of a display region of an array substrate of an embodiment of the present disclosure partially forming a third conductive layer pattern;

[0045] Figure 9B A cross-sectional view of a display region of an array substrate of an embodiment of the present disclosure partially forming a third conductive layer pattern;

[0046] Figure 9C A cross-sectional view of a second frame region of an array substrate of an embodiment of the present disclosure partially forming a third conductive layer pattern;

[0047] Figure 10A A top view of a display region of an array substrate of an embodiment of the present disclosure partially forming a fourth conductive layer pattern;

[0048] Figure 10B A cross-sectional view of a display region of an array substrate of an embodiment of the present disclosure partially forming a fourth conductive layer pattern;

[0049] Figure 10C A cross-sectional view of a second frame region of an array substrate of an embodiment of the present disclosure partially forming a fourth conductive layer pattern;

[0050] Figure 11 A cross-sectional view of a second frame region of an array substrate of another embodiment of the present disclosure partially forming a second conductive layer pattern;

[0051] Figure 12 A cross-sectional view of a second frame region of an array substrate of another embodiment of the present disclosure partially forming a third insulating layer pattern;

[0052] Figure 13A A top view of a display region of an array substrate of another embodiment of the present disclosure partially forming a third conductive layer pattern;

[0053] Figure 13B A cross-sectional view of a partial formation of a third conductive layer pattern in a display area of an array substrate according to another embodiment of the present disclosure;

[0054] Figure 13C A cross-sectional view of a partial formation of a third conductive layer pattern in a second bezel area of an array substrate according to another embodiment of the present disclosure;

[0055] Figure 14A A top view of a partial formation of a fourth conductive layer pattern in a display area of an array substrate according to another embodiment of the present disclosure;

[0056] Figure 14B A cross-sectional view of a partial formation of a fourth conductive layer pattern in a display area of an array substrate according to another embodiment of the present disclosure;

[0057] Figure 14C A cross-sectional view of a partial formation of a fourth conductive layer pattern in a second bezel area of an array substrate according to another embodiment of the present disclosure;

[0058] Figure 15 A cross-sectional view of a display device according to an embodiment of the present disclosure.

[0059] Reference Signs:

[0060] 10 - pixel electrode, 11 - first transistor, 12 - second transistor, DL - data line, DL-1 - extension section, DL-2 - protruding section, GL - gate line, 13 - substrate, 14 - first insulating layer, 15 - second insulating layer, 16 - third insulating layer, 17 - first light shielding block;

[0061] 18 - first active layer, 18-1 - first region, 18-2 - second region, 18-3 - first channel region, 18-4 - first area, 18-5 - second area, 18-6 - third area;

[0062] 19 - first gate, 20 - data connection electrode, 20-1 - bottom connection electrode, 20-2 - top connection electrode, 21 - common electrode, 21-1 - connection portion, 21-2 - comb-tooth portion, 22 - common electrode line, 23 - second light shielding block, 24 - second active layer, 24-1 - second channel region, 24-2 - third region, 24-3 - fourth region;

[0063] 25 - second gate, 26 - first connection electrode, 26-1 - first sub-electrode, 26-2 - second sub-electrode, 27 - second connection electrode, 27-3 - third sub-electrode, 27-4 - fourth sub-electrode, 28 - first auxiliary electrode, 29 - second auxiliary electrode, 30 - touch line, 30-1 - straight section, 30-2 - bent section;

[0064] 1- Opposite substrate, 2- Liquid crystal layer, 3- Black matrix, 4- Color filter layer.

[0065] Detailed Explanation

[0066] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0067] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0068] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. "Multiple" in this disclosure includes two or more quantities.

[0069] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0070] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0071] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0072] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0073] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0074] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0075] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0076] In this disclosure, "about" or "approximately" means values ​​that are not strictly defined and are within the allowable range of process and measurement errors.

[0077] In this disclosure, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined, but can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, and chamfers, curved edges, and other deformations are possible.

[0078] This disclosure provides an array substrate. The array substrate includes a substrate and a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked on one side of the substrate; the fourth conductive layer includes a common electrode, the material of the fourth conductive layer is a transparent conductive oxide material, the material of the third conductive layer is a metallic conductive material, and at least a portion of the surface of the third conductive layer away from the substrate is in contact with at least a portion of the surface of the fourth conductive layer near the substrate.

[0079] The array substrate provided in this embodiment reduces the resistance of the fourth conductive layer and improves its contactability and resistance to water and oxygen by providing a third conductive layer with a material different from that of the fourth conductive layer, and by making at least a portion of the surface of the third conductive layer away from the substrate contact at least a portion of the surface of the fourth conductive layer near the substrate.

[0080] Figure 1 This is a front view schematic diagram of an array substrate according to an embodiment of the present disclosure. Figure 1 As shown, the array substrate may include a display area AA and a border area BB surrounding the display area AA. The border area BB may include a first border area B1 located on one side of the display area AA and a second border area B2 located on the remaining sides of the display area AA. For example, the first border area B1 may include the bottom border of the array substrate, and the second border area B2 may include the top border, left border, and right border of the array substrate.

[0081] In one exemplary embodiment, such as Figure 1 As shown, the display area AA may include multiple data lines DL and multiple gate lines GL disposed on a substrate. The multiple gate lines GL may extend along a first direction X and be arranged sequentially along a second direction Y different from the first direction X. The multiple data lines DL may extend along the second direction Y and be arranged sequentially along the first direction X. The first direction X and the second direction Y may intersect; for example, the first direction X may be perpendicular to the second direction Y. The multiple data lines DL and the multiple gate lines GL may be located in different film layers; for example, the multiple data lines DL may be located on the side of the multiple gate lines GL closer to the substrate.

[0082] In one exemplary embodiment, such as Figure 1As shown, multiple data lines DL and multiple gate lines GL can intersect to form multiple sub-pixel regions. The area defined by the intersection of adjacent data lines DL and adjacent gate lines GL can be a sub-pixel region. One sub-pixel can be correspondingly set within a sub-pixel region. A sub-pixel region can include an open area and a non-open area surrounding the open area. The non-open area can be an area obscured by the black matrix of the opposing substrate of the array substrate, and the open area can be an area not obscured by the black matrix of the opposing substrate. Adjacent gate lines GL and data lines DL can both be located within the non-open area. The array substrate of this embodiment can be used to implement a display function, and the open area of ​​each sub-pixel region can be configured for display. The non-open area surrounds the open area and is not displayed. However, this embodiment is not limited in this respect. In some examples, the array substrate can be used to implement other functions.

[0083] In one exemplary embodiment, the display area AA may include a plurality of pixel units disposed on a substrate. At least one pixel unit may include three sub-pixels (e.g., a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged sequentially along a first direction X). The three sub-pixels of the pixel unit may, for example, be a blue sub-pixel, a red sub-pixel, and a green sub-pixel, and the three sub-pixels may be arranged sequentially in the order of blue sub-pixel, green sub-pixel, and red sub-pixel. Figure 1 As shown, at least one sub-pixel may include: a pixel electrode 10 and a common electrode ( Figure 1 (Not shown), and the orthographic projections of the pixel electrode 10 and the common electrode of the sub-pixel onto the substrate may overlap. The common electrode of multiple sub-pixels in the display area AA may be a single structure. For example, the common electrode may be located on the side of the pixel electrode 10 away from the substrate. The sub-pixel may also include a first transistor 11. The first transistor 11 may be located near the intersection of the data line DL and the gate line GL. The first transistor 11 may include a first gate, a first electrode, and a second electrode. The first gate may be electrically connected to the gate line GL, the first electrode of the first transistor 11 may be electrically connected to the data line DL, and the second electrode may be electrically connected to the pixel electrode 10 of a sub-pixel. The first transistor 11 may be configured to provide the data signal transmitted by the data line DL to the pixel electrode 10 of the sub-pixel under the control of the gate line GL.

[0084] In one exemplary embodiment, the second frame region B2 may include at least a gate driving circuit (e.g., including multiple cascaded shift registers), which may be electrically connected to multiple gate lines GL in the display region AA. The gate driving circuit may also include a second transistor. The second transistor may include a second gate, a third electrode, and a fourth electrode. In this disclosure, the third electrode may be a drain electrode and the fourth electrode may be a source electrode, or the third electrode may be a source electrode and the fourth electrode may be a drain electrode.

[0085] Liquid crystal display devices have various display modes, such as ADS (Advanced Super Dimension Switch) mode, TN (twisted nematic) mode, and VA (Vertical Alignment) mode. In ADS mode, both the pixel electrode and the common electrode are located on one side of the array substrate. In TN and VA modes, the pixel electrode and the common electrode are respectively located on opposite sides of the liquid crystal layer, with the pixel electrode on one side of the array substrate and the common electrode on the opposite substrate side.

[0086] The working principle of ADS mode is that liquid crystal molecules lie in a plane parallel to the glass substrate. Without voltage, light passing through the lower polarizer forms linearly polarized light parallel to the short axis of the liquid crystal molecules. The polarization direction cannot rotate, therefore it is absorbed by the upper polarizer and cannot escape. When a voltage is applied, a lateral electric field is formed on both sides of the liquid crystal, and the liquid crystal molecules align along the direction of the electric field. Light passing through the lower polarizer and the liquid crystal layer becomes elliptically polarized and can pass through the upper polarizer and escape.

[0087] The working principle of TN mode is as follows: In the absence of voltage, liquid crystal molecules are twisted and aligned at 90° under the action of the alignment film. Light passes through the lower polarizer and the liquid crystal molecules and is emitted from the upper polarizer. When voltage is applied, except for the liquid crystal near the upper and lower alignment films, most of the other liquid crystal molecules are vertically aligned. Light passing through the lower polarizer passes through the liquid crystal layer without deflection. Because it is parallel to the polarization axis of the upper polarizer, the light is absorbed and cannot be emitted.

[0088] The working principle of VA mode is that the liquid crystal molecules are aligned vertically to the glass substrate. When there is no voltage, the light passes through the lower polarizer and forms linearly polarized light parallel to the short axis of the liquid crystal molecules. The polarization direction cannot be rotated, so it is absorbed by the upper polarizer and cannot be emitted. When a voltage is applied, the liquid crystal molecules deflect along the direction of the electric field. The light passes through the lower polarizer and the liquid crystal layer and becomes elliptically polarized, allowing it to pass through the upper polarizer and be emitted.

[0089] The structure of the array substrate is described below using the ADS mode array substrate structure as an example.

[0090] Figure 2 This is a partial cross-sectional schematic diagram of the display area of ​​an array substrate according to an embodiment of the present disclosure. Figure 2As shown, the display area of ​​the array substrate may include a substrate 13 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 13. The display area of ​​the array substrate may also include a first insulating layer 14 located between the first conductive layer and the semiconductor layer, a second insulating layer 15 located between the semiconductor layer and the second conductive layer, and a third insulating layer 16 located between the second conductive layer and the third conductive layer. In this embodiment, the first insulating layer may also be referred to as a buffer layer, the second insulating layer may also be referred to as a gate insulating (GI) layer, and the third insulating layer may also be referred to as a planarization (PLN) layer. The first conductive layer may include a data line DL and a first light-shielding block 17. The semiconductor layer may include a first active layer 18 of a first transistor 11, and the pixel electrode 10 and the first active layer 18 may be an integral structure interconnected. The second conductive layer may include a first gate 19 of the first transistor 11, and the first active layer 18 may be electrically connected to the data line DL via a data connection electrode 20. The third conductive layer may include a portion of the data connection electrode 20, and the fourth conductive layer may include a common electrode 21 and another portion of the data connection electrode 20. In other examples, the data line DL may be located on a different film layer from the first light-shielding block 17. For example, the first light-shielding block may be located on the side of the data line closer to the substrate. In embodiments of this disclosure, by placing the data line DL on the side of the first transistor closer to the substrate 13, the capacitance between the data line DL and the pixel electrode 10 can be reduced, the power consumption of the data line can be reduced, and the performance of the array substrate can be improved.

[0091] In one exemplary embodiment, such as Figure 2 As shown, the data line DL and the first light-shielding block 17 can be configured as a co-layer structure, which can simplify the fabrication process of the array substrate, reduce the number of masks used, and lower the manufacturing cost of the display substrate.

[0092] In an exemplary embodiment, substrate 13 may provide support for film layers other than substrate 13 in the array substrate. For example, substrate 13 may be a transparent substrate. For instance, substrate 13 may be a rigid substrate or a flexible substrate. For example, the material of a rigid substrate may include, but is not limited to, one or more of glass and quartz. The material of a flexible substrate may include, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. However, this disclosure is not limiting in this regard.

[0093] In an exemplary embodiment, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be metallic materials, such as any one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). Alternatively, the materials of the first conductive layer, the second conductive layer, and the third conductive layer can be alloys of metallic materials such as molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), for example, aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-nickel-titanium alloy (MoNiTi). The first conductive layer, the second conductive layer, and the third conductive layer can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Nb / Cu, MoNiTi / Cu, MoNb / Cu / MoNiTi, or MoNiTi / Cu / MoNiTi, etc.

[0094] In an exemplary embodiment, the material of the fourth conductive layer can be a transparent conductive oxide material, which may include indium tin oxide (ITO) or indium zinc oxide (IZO). For example, the fourth conductive layer can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0095] In one exemplary embodiment, such as Figure 2 As shown, the orthographic projection of the first insulating layer 14 onto the array substrate may include the orthographic projection of the first conductive layer onto the array substrate. The first insulating layer 14 can block water and oxygen from corroding the data line DL and the first light-shielding block 17, thereby improving the reliability of the array substrate.

[0096] In an exemplary embodiment, the materials of the first insulating layer 14 and the second insulating layer 15 can be inorganic materials. Examples of inorganic materials include silicon oxynitride (SiO₂). x N y ) or silicon nitride (SiN) x ) or silicon oxide (SiO) x The materials of the first insulating layer 14 and the second insulating layer 15 can be one or more of the following: ) . Organic materials can be used. Examples of organic materials include epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, polyether resin, etc., any one or more of these. The first insulating layer 14 and the second insulating layer 15 can be a single layer, multiple layers, or composite layers.

[0097] In an exemplary embodiment, the material of the third insulating layer 16 may be an organic material. Examples of organic materials include any one or more of epoxy resin, phenolic resin, urea-formaldehyde resin, melamine-formaldehyde resin, furan resin, silicone resin, polyester resin, polyamide resin, acrylic resin, polyurethane, vinyl resin, hydrocarbon resin, and polyether resin. The third insulating layer 16 may be a single layer, multiple layers, or a composite layer.

[0098] In one exemplary embodiment, such as Figure 2 As shown, the orthographic projection of the first active layer 18 onto the array substrate may overlap with the orthographic projections of the data line DL and the first light-shielding block 17 onto the array substrate. The first active layer 18 may include a first channel region 18-3, a first region 18-1 located on opposite sides of the first channel region 18-3, and a second region 18-2. For example, during the fabrication of the array substrate, a portion of the first active layer 18 may be partially conductiveized, such that portions of the first active layer 18 form the first region 18-1 and the second region 18-2, respectively. The first region 18-1 of the first active layer 18 can be used as the first electrode of the first transistor, and the second region 18-2 of the first active layer 18 can be used as the second electrode of the first transistor. This disclosure does not limit the conductiveization process of the semiconductor layer.

[0099] In one exemplary embodiment, the first active layer 18 may include two or more sub-active layers. For example, the first active layer 18 may include two sub-active layers, or the first active layer 18 may include three sub-active layers, etc.

[0100] In an exemplary embodiment, the material of the first active layer 18 may include a metal oxide semiconductor material. The materials of the plurality of sub-active layers may be the same or different. The metal oxide semiconductor material may include one or more metal oxide materials such as indium gallium zinc oxide (IGZO), zinc oxynitride (ZnON), and indium zinc tin oxide (IZTO); however, this disclosure does not limit the metal oxide semiconductor material.

[0101] In one exemplary embodiment, such as Figure 2 As shown, the data connection electrode 20 can be electrically connected to the data line DL and the first region 18-1 via a via located in the third insulating layer 16. The data connection electrode 20 can be a stacked structure, comprising a bottom connection electrode 20-1 and a top connection electrode 20-2 stacked sequentially. The bottom connection electrode 20-1 can be located in the third conductive layer, and the top connection electrode 20-2 can be located in the fourth conductive layer. Figure 2As shown, the orthographic projection of the top connection electrode 20-2 onto the array substrate can include the orthographic projection of the bottom connection electrode 20-1 onto the array substrate. For example, the orthographic projections of the top connection electrode 20-2 and the bottom connection electrode 20-1 onto the array substrate can overlap. By setting a stacked data connection electrode structure, and using a metallic conductive material for the bottom connection electrode, which has good contact and water / oxygen resistance, a relatively stable resistance can be ensured at the via, thus guaranteeing the switching characteristics of the first transistor.

[0102] In one exemplary embodiment, such as Figure 2 As shown, the third conductive layer may further include a common electrode line 22. The common electrode line 22 can be electrically connected to the common electrode 21 of multiple sub-pixels. A portion of the surface of the common electrode line 22 away from the substrate 13 can be in contact with a portion of the surface of the common electrode 21 near the substrate 13, so that the connection between the common electrode and the common electrode line does not require vias, which can reduce the resistance of the common electrode, improve the uniformity of the common electrode voltage, reduce the size of the non-aperture area, and increase the aperture ratio of the display area.

[0103] In an exemplary embodiment, the common electrode line 22 may extend along the first direction X, and the orthographic projection of the common electrode line 22 on the array substrate and the orthographic projection of the gate line GL on the array substrate may at least partially overlap. For example, the orthographic projection of the common electrode line 22 on the array substrate may be located within the orthographic projection of the gate line GL on the array substrate.

[0104] Figure 3 This is a partial cross-sectional view of the second border region of an array substrate according to an embodiment of the present disclosure. Figure 3 As shown, the second border region of the array substrate may include a substrate 13 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 13. The second border region of the array substrate may also include a first insulating layer 14 located between the first conductive layer and the semiconductor layer, a second insulating layer 15 located between the semiconductor layer and the second conductive layer, and a third insulating layer 16 located between the second conductive layer and the third conductive layer. The first conductive layer may include a second light-shielding block 23. The semiconductor layer may include a second active layer 24 of the second transistor 12. The second conductive layer may include a second gate 25 of the second transistor 12. The third conductive layer may include a portion of the first connecting electrode 26 and a portion of the second connecting electrode 27, and the fourth conductive layer may include another portion of the first connecting electrode 26 and another portion of the second connecting electrode 27.

[0105] In one exemplary embodiment, such as Figure 3As shown, the orthographic projection of the second active layer 24 onto the array substrate and the orthographic projection of the second light-shielding block 23 onto the array substrate may at least partially overlap. The second active layer 24 may include a second channel region 24-1, a third region 24-2, and a fourth region 24-3 located on opposite sides of the second channel region 24-1. For example, during the fabrication of the array substrate, a portion of the second active layer 24 may be partially conductiveized to form the third region 24-2 and the fourth region 24-3, respectively. The third region 24-2 of the second active layer 24 can be used as the third electrode of the second transistor, and the fourth region 24-3 of the second active layer 24 can be used as the fourth electrode of the second transistor. This disclosure does not limit the conductiveization process of the semiconductor layer. Figure 3 As shown, the first connecting electrode 26 can be electrically connected to the third region 24-2 of the second active layer 24, and the second connecting electrode 27 can be electrically connected to the fourth region 24-3 of the second active layer 24.

[0106] In one exemplary embodiment, such as Figure 3 As shown, the first connecting electrode 26 can be electrically connected to the third region 24-2 of the second active layer 24 via a via located in the third insulating layer 16. The first connecting electrode 26 can be a stacked structure, comprising a first sub-electrode 26-1 and a second sub-electrode 26-2 sequentially stacked. The first sub-electrode 26-1 can be located in the third conductive layer, and the second sub-electrode 26-2 can be located in the fourth conductive layer. Figure 3 As shown, the orthographic projection of the second sub-electrode 26-2 onto the array substrate can include the orthographic projection of the first sub-electrode 26-1 onto the array substrate. For example, the orthographic projection of the second sub-electrode 26-2 onto the array substrate and the orthographic projection of the first sub-electrode 26-1 onto the array substrate can overlap. By setting a first connecting electrode with a stacked structure, and the first sub-electrode being made of a metallic conductive material, which has good contact and water and oxygen resistance, the first connecting electrode can be guaranteed to have a relatively stable resistance at the via, thus ensuring the switching characteristics of the second transistor.

[0107] In one exemplary embodiment, such as Figure 3 As shown, the second connecting electrode 27 can be electrically connected to the fourth region 24-3 of the second active layer 24 via a via located in the third insulating layer 16. The second connecting electrode 27 can be a stacked structure, comprising a third sub-electrode 27-3 and a fourth sub-electrode 27-4 sequentially stacked. The third sub-electrode 27-3 can be located in the third conductive layer, and the fourth sub-electrode 27-4 can be located in the fourth conductive layer. Figure 3As shown, the orthographic projection of the fourth sub-electrode 27-4 onto the array substrate may include the orthographic projection of the third sub-electrode 27-3 onto the array substrate. For example, the orthographic projections of the fourth sub-electrode 27-4 and the third sub-electrode 27-3 onto the array substrate may overlap. By providing a second connecting electrode with a stacked structure, and using a metallic conductive material for the third sub-electrode, which has good contact and water / oxygen resistance, a relatively stable resistance can be ensured at the via, thus guaranteeing the switching characteristics of the second transistor.

[0108] Figure 4 This is a partial cross-sectional schematic diagram of the second border region of an array substrate according to another embodiment of this disclosure. Figure 4 As shown, the second border region of the array substrate may include a substrate 13 and a first conductive layer, a semiconductor layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on one side of the substrate 13. The second border region of the array substrate may also include a first insulating layer 14 located between the first conductive layer and the semiconductor layer, a second insulating layer 15 located between the semiconductor layer and the second conductive layer, and a third insulating layer 16 located between the second conductive layer and the third conductive layer. The first conductive layer may include a second light-shielding block 23. The semiconductor layer may include a second active layer 24 of the second transistor 12. The second conductive layer may include a second gate 25 of the second transistor 12. The third conductive layer may include a portion of the first connecting electrode 26 and a portion of the second connecting electrode 27, and the fourth conductive layer may include another portion of the first connecting electrode 26 and another portion of the second connecting electrode 27.

[0109] In one exemplary embodiment, such as Figure 4 As shown, the second conductive layer may further include a first auxiliary electrode 28 and a second auxiliary electrode 29. The first connecting electrode 26 may be electrically connected to both the third region 24-2 of the second active layer 24 and the first auxiliary electrode 28 via a via located in the third insulating layer 16. The second connecting electrode 27 may be electrically connected to both the fourth region 24-3 of the second active layer 24 and the second auxiliary electrode 29 via a via located in the third insulating layer 16.

[0110] The structure of the array substrate is illustrated below through an example of the fabrication process of the array substrate. The "patterning process" described in the embodiments of this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metallic, inorganic, or transparent conductive materials; and processes such as organic material coating, mask exposure, and development for organic materials. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; and etching can be performed using any one or more of dry and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. A "layer" after the patterning process contains at least one "pattern." The "A and B co-layer structure" described in this disclosure refers to A and B being formed through the same patterning process.

[0111] The fabrication process of the array substrate may include the following steps:

[0112] (11) Forming a first conductive layer pattern. Forming the first conductive layer pattern may include: depositing a first conductive thin film on one side of the substrate 13, and patterning the first conductive thin film using a patterning process to form a first conductive layer pattern located on one side of the substrate 13. The first conductive layer may include a data line DL, a first light-shielding block 17, and a second light-shielding block 23, such as... Figure 5A , Figure 5B as well as Figure 5C As shown. Figure 5B for Figure 5A A cross-sectional view of the area marked AA.

[0113] like Figure 5A As shown, the data line DL may include an extension segment DL-1 and a protruding segment DL-2. The extension segment DL-1 and the protruding segment DL-2 can be an integral structure interconnected. The extension segment DL-1 can be a line extending along a second direction Y. The first end of the protruding segment DL-2 can be connected to the extension segment DL-1, and the second end of the protruding segment DL-2 can extend in the opposite direction of the first direction X. The protruding segment DL-2 can be rectangular. The protruding segment DL-2 can be configured to be electrically connected to subsequently formed data connection electrodes. Figure 5A As shown, the first light-blocking block 17 can be rectangular.

[0114] (12) Forming a semiconductor layer pattern. Forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on one side of the substrate 13 on which the aforementioned pattern is formed, and patterning the semiconductor film using a patterning process to form a first insulating layer 14 located on the side of the first conductive layer away from the substrate 13, and a semiconductor layer pattern located on the side of the first insulating layer 14 away from the substrate 13. The semiconductor layer may include a first active layer 18 of a first transistor and a second active layer 24 of a second transistor, such as... Figure 6A , Figure 6B as well as Figure 6C As shown. Figure 6B for Figure 6A A cross-sectional view of the area marked AA.

[0115] like Figure 6A As shown, the first active layer 18 may include a first region 18-4, a second region 18-5, and a third region 18-6. The second region 18-5 may be located between the first region 18-4 and the third region 18-6, and the first region 18-4, the second region 18-5, and the third region 18-6 may be connected sequentially. The first region 18-4 may be rectangular, the second region 18-5 may be L-shaped, and the third region 18-6 may be rectangular. The first end of the first region 18-4 may be connected to the first end of the second region 18-5, and the second end of the first region 18-4 may extend in the opposite direction of the first direction X. The first end of the third region 18-6 may be connected to the second end of the second region 18-5, and the second end of the third region 18-6 may extend in the second direction Y. The first region 18-4 may be configured to be electrically connected to a subsequently formed data connection electrode, and at least a portion of the third region 18-6 may be configured to be used as a pixel electrode after being conductiveized.

[0116] like Figure 6B As shown, the orthographic projection of the first light-shielding block 17 onto the array substrate may include the orthographic projection of the first channel region of the first active layer 18 onto the array substrate, which can prevent light from shining onto the first channel region from the side closest to the substrate, and can prevent light from affecting the performance of the first transistor.

[0117] (13) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on one side of the substrate 13 on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer 15 located on the side of the semiconductor layer away from the substrate 13, and a second conductive layer pattern located on the side of the second insulating layer 15 away from the substrate 13. The second conductive layer may include a gate line GL, a first gate 19 of the first transistor, and a second gate 25 of the second transistor, such as... Figure 7A , Figure 7B as well as Figure 7C As shown.Figure 7B for Figure 7A A cross-sectional view of the area marked AA.

[0118] like Figure 7A As shown, the gate line GL and the first gate 19 can be an integral structure that is interconnected, and the portion of the gate line GL that overlaps with the first channel region of the first active layer 18 can serve as the first gate 19.

[0119] In one exemplary embodiment, such as Figure 7B As shown, forming the second conductive layer pattern may further include using the first gate 19 as a mask to perform a conductive treatment on a portion of the first active layer 18. The conductive treatment can be performed on a portion of the first active layer 18 so that a portion of the first active layer 18 forms a first region 18-1 and a second region 18-2, respectively. The first region 18-1 of the first active layer 18 can be used as the first electrode of the first transistor, and the second region 18-2 of the first active layer 18 can be used as the second electrode of the first transistor. This disclosure does not limit the conductive process of the semiconductor layer. The first active layer 18 may further include a first channel region 18-3 located between the first region 18-1 and the second region 18-2.

[0120] In one exemplary embodiment, such as Figure 7B As shown, the pixel electrode 10 and the first active layer 18 can be an integral structure that is interconnected. This avoids the need to set vias on the insulating layer to connect the pixel electrode and the first active layer, improves the resistance of the array substrate to water and oxygen, and enables the pixel electrode to have stable resistance.

[0121] In one exemplary embodiment, such as Figure 7C As shown, forming the second conductive layer pattern may further include using the second gate 25 as a mask to perform a conductive treatment on a portion of the second active layer 24. The second active layer 24 may include a second channel region 24-1, a third region 24-2, and a fourth region 24-3 located on opposite sides of the second channel region 24-1. The conductive treatment on a portion of the second active layer 24 is performed such that portions of the second active layer 24 form the third region 24-2 and the fourth region 24-3, respectively. The third region 24-2 of the second active layer 24 can be used as the third electrode of the second transistor, and the fourth region 24-3 of the second active layer 24 can be used as the fourth electrode of the second transistor. This disclosure does not limit the conductive process of the semiconductor layer.

[0122] (14) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include: depositing a third insulating film on one side of the substrate 13 on which the aforementioned pattern is formed. The third insulating film may be patterned using a half-tone mask patterning process to form a third insulating layer pattern located on the side of the second conductive layer away from the substrate 13, such as... Figure 8A , Figure 8B as well as Figure 8C As shown. Figure 8B for Figure 8A A cross-sectional view of the area marked AA.

[0123] The third insulating layer 16 may include multiple vias, and the multiple vias may include at least one first via K1 and two second vias K2. The vias may be circular, elliptical, or rectangular, etc. Figure 8A As shown, the orthographic projection of the first via K1 on the array substrate overlaps with the orthographic projections of the data line DL and the first active layer 18 on the array substrate. Figure 8B As shown, the third insulating film and the first insulating layer within the first via K1 are etched away, exposing a portion of the surface of the first region 18-1 of the first active layer 18 away from the substrate 13, and a portion of the surface of the data line DL away from the substrate 13. The first via K1 enables the subsequently formed data connection electrode to be electrically connected to the data line DL and the first region 18-1 of the first active layer 18 via the via.

[0124] like Figure 8C As shown, two second vias K2 can be respectively arranged on opposite sides of the second channel region 24-1. The third insulating film within both second vias K2 is etched away, exposing a portion of the surface of the third region 24-2 away from the substrate 13, and a portion of the surface of the fourth region 24-3 away from the substrate 13, respectively. One second via K2 allows a subsequently formed first connection electrode to be electrically connected to the third region 24-2 via this via, and the other second via K2 allows a subsequently formed second connection electrode to be electrically connected to the fourth region 24-3 via this via.

[0125] (15) Forming a third conductive layer pattern. Forming a third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 13, and patterning the third conductive film using a patterning process to form a third conductive layer pattern located on the side of the third insulating layer 16 away from the substrate 13. The third conductive layer may include a bottom connection electrode 20-1, a common electrode line 22, a first sub-electrode 26-1, and a third sub-electrode 27-3, such as Figure 9A , Figure 9B as well as Figure 9C As shown. Figure 9B for Figure 9A A cross-sectional view of the area marked AA.

[0126] like Figure 9A As shown, the common electrode line 22 can be a line extending along the first direction X. The orthographic projection of the common electrode line 22 on the array substrate can at least partially overlap with the orthographic projection of the gate line on the array substrate. For example, the orthographic projection of the common electrode line 22 on the array substrate can be located within the orthographic projection of the gate line on the array substrate, which can reduce or avoid the occupation of the pixel opening area by the common electrode line and improve the display performance of the array substrate.

[0127] like Figure 9A As shown, the orthographic projection of the bottom connection electrode 20-1 onto the array substrate can be rectangular and can cover the first via K1. For example... Figure 9B As shown, the bottom connection electrode 20-1 can be connected to a portion of the surface of the first region 18-1 away from the substrate 13 via the first via K1, and to a portion of the surface of the data line DL away from the substrate 13.

[0128] like Figure 9C As shown, the first sub-electrode 26-1 can cover a second via K2, and the first sub-electrode 26-1 is in contact with a portion of the surface of the third region 24-2 away from the substrate 13 through the second via K2. The third sub-electrode 27-3 can cover a second via K2, and the third sub-electrode 27-3 is in contact with a portion of the surface of the fourth region 24-3 away from the substrate 13 through the second via K2.

[0129] (16) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive thin film on one side of the substrate 13, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern located on the side of the third conductive layer away from the substrate 13. The fourth conductive layer may include a top connection electrode 20-2, a common electrode 21, a second sub-electrode 26-2, and a fourth sub-electrode 27-4. Figure 10A , Figure 10B as well as Figure 10C As shown. Figure 10B for Figure 10A A cross-sectional view of the area marked AA.

[0130] like Figure 10A As shown, the orthographic projection of the top connection electrode 20-2 on the array substrate and the orthographic projection of the bottom connection electrode 20-1 on the array substrate at least partially overlap. For example, the orthographic projection of the top connection electrode 20-2 on the array substrate may include the orthographic projection of the bottom connection electrode 20-1 on the array substrate.

[0131] In some exemplary embodiments, the common electrode 21 may have multiple slits. For example... Figure 10AAs shown, the common electrode 21 may include a connecting portion 21-1 and a plurality of comb-tooth portions 21-2, with a slit formed between adjacent comb-tooth portions 21-2. A first end of each comb-tooth portion 21-2 is connected to the connecting portion 21-1, and a second end of each comb-tooth portion 21-2 extends along a second direction Y. The plurality of comb-tooth portions 21-2 are arranged at intervals along a first direction X; for example, the plurality of comb-tooth portions 21-2 may be arranged at equal intervals along the first direction X.

[0132] like Figure 10C As shown, the orthographic projection of the second sub-electrode 26-2 onto the array substrate and the orthographic projection of the first sub-electrode 26-1 onto the array substrate at least partially overlap. For example, the orthographic projection of the second sub-electrode 26-2 onto the array substrate may include the orthographic projection of the first sub-electrode 26-1 onto the array substrate.

[0133] like Figure 10C As shown, the orthographic projection of the fourth sub-electrode 27-4 onto the array substrate and the orthographic projection of the third sub-electrode 27-3 onto the array substrate at least partially overlap. For example, the orthographic projection of the fourth sub-electrode 27-4 onto the array substrate may include the orthographic projection of the third sub-electrode 27-3 onto the array substrate.

[0134] In another embodiment of this disclosure, the fabrication process of the array substrate may include the following steps:

[0135] (21) The first conductive layer pattern and the semiconductor layer pattern are formed sequentially. This step can be referred to the description of the foregoing embodiment, and will not be elaborated here.

[0136] (22) Forming a second conductive layer pattern. Forming the second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on one side of the substrate 13 on which the aforementioned pattern is formed, and patterning the second conductive film using a patterning process to form a second insulating layer 15 located on the side of the semiconductor layer away from the substrate 13, and a second conductive layer pattern located on the side of the second insulating layer 15 away from the substrate 13. The second conductive layer located in the display area can be referred to the description in the foregoing embodiments. The second conductive layer located in the second border area may include a second gate 25, a first auxiliary electrode 28, and a second auxiliary electrode 29 of the second transistor, such as... Figure 11 As shown.

[0137] like Figure 11As shown, the second gate 25, the first auxiliary electrode 28, and the second auxiliary electrode 29 are spaced apart. Forming the second conductive layer pattern may further include conducting a portion of the second active layer 24 to form a third region 24-2 and a fourth region 24-3 in the portion of the second active layer 24. The third region 24-2 can be used as the third electrode of the second transistor, and the fourth region 24-3 can be used as the fourth electrode of the second transistor. The present disclosure does not limit the semiconductor layer conducting process. The third region 24-2 and the first auxiliary electrode 28 can be electrically connected via a subsequently formed first connection electrode, and the fourth region 24-3 and the second auxiliary electrode 29 can be electrically connected via a subsequently formed second connection electrode. (23) Forming a third insulating layer pattern. Forming the third insulating layer pattern may include depositing a third insulating film on one side of the substrate 13 on which the aforementioned pattern is formed. The third insulating film can be patterned using a half-tone mask patterning process to form a third insulating layer pattern located on the side of the second conductive layer away from the substrate 13. The third insulating layer located in the display area can refer to the aforementioned embodiment. The third insulating layer located in the second border region may include at least two third vias K3, such as Figure 12 As shown. The third via can be a round hole, an elliptical hole, or a rectangular hole, etc.

[0138] like Figure 12 As shown, two third vias K3 can be respectively arranged on opposite sides of the second channel region 24-1. The third insulating film within both third vias K3 is etched away. One third via K3 exposes a portion of the surface of the third region 24-2 away from the substrate 13, and a portion of the surface of the first auxiliary electrode 28 away from the substrate 13. The other third via K3 exposes a portion of the surface of the fourth region 24-3 away from the substrate 13, and a portion of the surface of the second auxiliary electrode 29 away from the substrate 13. One third via K3 allows a subsequently formed first connection electrode to be electrically connected to the third region 24-2 and the first auxiliary electrode 28 via this via, and the other third via K3 allows a subsequently formed second connection electrode to be electrically connected to the fourth region 24-3 and the second auxiliary electrode 29 via this via.

[0139] (24) Forming a third conductive layer pattern. Forming the third conductive layer pattern may include: depositing a third conductive film on one side of the substrate 13, and patterning the third conductive film using a patterning process to form a third conductive layer pattern located on the side of the third insulating layer 16 away from the substrate 13. The third conductive layer may include a bottom connection electrode 20-1, a touch line 30, a first sub-electrode 26-1, and a third sub-electrode 27-3, such as Figure 13A , Figure 13B as well as Figure 13C As shown. Figure 13B for Figure 13AA cross-sectional view of the area marked BB.

[0140] like Figure 13A As shown, the main body of the touch line 30 can be a line extending along the second direction Y. The orthographic projection of the touch line 30 onto the array substrate can at least partially overlap with the orthographic projection of the data line DL onto the array substrate. For example, the orthographic projection of the touch line 30 onto the array substrate can be located within the orthographic projection of the data line DL onto the array substrate, which can reduce or avoid the touch line occupying the area of ​​the pixel opening region and improve the display performance of the array substrate.

[0141] like Figure 13A As shown, the touch line 30 may include a straight segment 30-1 and a bent segment 30-2 connected to each other. The straight segment 30-1 may extend along a second direction Y, and the bent segment 30-2 may protrude along a first direction X in a direction away from the straight segment 30-1. The bent segment 30-2 may form a clearance space to avoid contact with the bottom connecting electrode 20-1.

[0142] like Figure 13A As shown, the orthographic projection of the bottom connecting electrode 20-1 onto the array substrate can be rectangular. Figure 13B As shown, the bottom connection electrode 20-1 can cover the first via K1. The bottom connection electrode 20-1 can be connected to a portion of the surface of the first region 18-1 away from the substrate 13 through the first via K1, and to a portion of the surface of the data line DL away from the substrate 13.

[0143] like Figure 13C As shown, the first sub-electrode 26-1 can cover a third via K3, and the first sub-electrode 26-1 is in contact with the third region 24-2 and the portion of the surface of the first auxiliary electrode 28 away from the substrate 13 through the third via K3. The third sub-electrode 27-3 can cover a third via K3, and the third sub-electrode 27-3 is in contact with the fourth region 24-3 and the portion of the surface of the second auxiliary electrode 29 away from the substrate 13 through the third via K3.

[0144] (25) Forming a fourth conductive layer pattern. Forming the fourth conductive layer pattern may include: depositing a fourth conductive thin film on one side of the substrate 13, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern located on the side of the third conductive layer away from the substrate 13. The fourth conductive layer may include a top connection electrode 20-2, a common electrode 21, a second sub-electrode 26-2, and a fourth sub-electrode 27-4. Figure 14A , Figure 14B as well as Figure 14C As shown. Figure 14B for Figure 14A A cross-sectional view of the area marked BB.

[0145] likeFigure 14B As shown, the orthographic projection of the top connection electrode 20-2 onto the array substrate and the orthographic projection of the bottom connection electrode 20-1 onto the array substrate at least partially overlap. For example, the orthographic projection of the top connection electrode 20-2 onto the array substrate may include the orthographic projection of the bottom connection electrode 20-1 onto the array substrate. The top connection electrode 20-2 and the bottom connection electrode 20-1 together form the data connection electrode 20.

[0146] like Figure 14C As shown, the orthographic projection of the second sub-electrode 26-2 onto the array substrate at least partially overlaps with the orthographic projection of the first sub-electrode 26-1 onto the array substrate. For example, the orthographic projection of the second sub-electrode 26-2 onto the array substrate may include the orthographic projection of the first sub-electrode 26-1 onto the array substrate. The second sub-electrode 26-2 and the first sub-electrode 26-1 together form the first connecting electrode 26.

[0147] like Figure 14C As shown, the orthographic projection of the fourth sub-electrode 27-4 onto the array substrate at least partially overlaps with the orthographic projection of the third sub-electrode 27-3 onto the array substrate. For example, the orthographic projection of the fourth sub-electrode 27-4 onto the array substrate may include the orthographic projection of the third sub-electrode 27-3 onto the array substrate. The fourth sub-electrode 27-4 and the third sub-electrode 27-3 together form the second connecting electrode 27.

[0148] Figure 15 This is a cross-sectional schematic diagram of a display device according to an embodiment of the present disclosure. Figure 15 As shown, one embodiment of this disclosure also provides a display device. Taking the display device as an example, which can implement ADS (Advanced Super Dimension Switch) mode, the display device may include the array substrate described in any of the foregoing embodiments.

[0149] The display device may further include a counter substrate 1 and a liquid crystal layer 2 disposed between an array substrate and the counter substrate 1. The pixel electrodes and common electrodes included in the array substrate can be configured to generate an electric field that controls the deflection of liquid crystal molecules in the liquid crystal layer 2. For example... Figure 15 As shown, both the pixel electrode 10 and the common electrode 21 are located on the array substrate, while no electrodes are disposed on the side opposite the substrate 1. Figure 15 As shown, the liquid crystal molecules in the liquid crystal layer 2 can be arranged horizontally on the array substrate. In this embodiment, the horizontal direction is parallel to the plane where the array substrate is located.

[0150] In one exemplary embodiment, such as Figure 15 As shown, the opposing substrate 1 may include a substrate, and a black matrix 3 and a color filter layer 4 disposed on the substrate. However, the embodiments disclosed herein are not limited thereto.

[0151] This disclosure also provides a display device. The display device includes the array substrate described in any of the foregoing embodiments. The display device can be any product or component with display function, such as a liquid crystal panel, electronic paper, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. This disclosure is not limited in this respect.

[0152] While the embodiments disclosed in this invention have been described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. It should be noted that the above embodiments or implementation methods are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the content specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. An array substrate, comprising a substrate and a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially stacked on one side of the substrate; the fourth conductive layer includes a common electrode, the fourth conductive layer is made of a transparent conductive oxide material, the third conductive layer is made of a metallic conductive material, and at least a portion of the surface of the third conductive layer away from the substrate is in contact with at least a portion of the surface of the fourth conductive layer near the substrate; The third conductive layer includes at least one signal line extending along a first direction, or the third conductive layer includes at least one signal line extending along a second direction, the first direction intersecting the second direction; at least a portion of the surface of the at least one signal line on the side away from the substrate is in contact with at least a portion of the surface of the common electrode on the side near the substrate.

2. The array substrate as claimed in claim 1, wherein, The second conductive layer includes a plurality of gate lines, which extend along the first direction and are spaced apart along the second direction; the at least one signal line includes at least one common electrode line, which extends along the first direction, and at least a portion of the surface of the at least one common electrode line away from the substrate is in contact with at least a portion of the surface of the common electrode line near the substrate.

3. The array substrate as described in claim 2, wherein, The orthographic projection of the common electrode line onto the array substrate lies within the orthographic projection of the gate line onto the array substrate.

4. The array substrate as claimed in claim 1, wherein, The first conductive layer includes a plurality of data lines, which are spaced apart along the first direction and extend along the second direction; the at least one signal line includes at least one touch line, which extends along the second direction, and at least a portion of the surface of the at least one touch line away from the substrate is in contact with at least a portion of the surface of the common electrode near the substrate.

5. The array substrate as claimed in claim 4, wherein, The projection of the touch line onto the array substrate and the projection of the data line onto the array substrate overlap at least partially.

6. The array substrate as claimed in claim 5, wherein, The orthographic projection of the touch line onto the array substrate lies within the orthographic projection of the data line onto the array substrate.

7. The array substrate as described in any one of claims 1 to 6, comprising a display area and a border area surrounding the display area; the display area includes at least one first transistor, the first transistor including a first active layer and a first gate, wherein the first active layer is located between a first conductive layer and a second conductive layer, the first gate is located in the second conductive layer, and the first conductive layer includes a plurality of data lines; The first active layer is electrically connected to the data line via a data connection electrode, at least a portion of which is located in the third conductive layer.

8. The array substrate as claimed in claim 7, wherein, The data connection electrode includes a bottom connection electrode and a top connection electrode stacked together, wherein the bottom connection electrode is located in the third conductive layer, the top connection electrode is located in the fourth conductive layer, and at least a portion of the surface of the bottom connection electrode away from the substrate is in contact with at least a portion of the surface of the top connection electrode near the substrate.

9. The array substrate as claimed in claim 8, wherein, The orthographic projection of the top connecting electrode onto the array substrate includes the orthographic projection of the bottom connecting electrode onto the array substrate.

10. The array substrate as claimed in any one of claims 1 to 6, comprising a display area and a border area surrounding the display area; the border area includes at least one second transistor, the second transistor including a second active layer and a second gate, wherein the second active layer is located between the first conductive layer and the second conductive layer, and the second gate is located in the second conductive layer; The border region includes a first connection electrode, the second active layer is electrically connected to the first connection electrode, and at least a portion of the first connection electrode is located in the third conductive layer.

11. The array substrate as claimed in claim 10, wherein, The first connection electrode includes a first sub-electrode and a second sub-electrode stacked together, wherein the first sub-electrode is located in the third conductive layer, the second sub-electrode is located in the fourth conductive layer, and at least a portion of the surface of the first sub-electrode on the side away from the substrate is in contact with at least a portion of the surface of the second sub-electrode on the side closer to the substrate.

12. The array substrate as claimed in claim 11, wherein, The orthographic projection of the second sub-electrode onto the array substrate includes the orthographic projection of the first sub-electrode onto the array substrate.

13. The array substrate as claimed in any one of claims 1 to 6, comprising a display area and a border area surrounding the display area; the border area includes at least one second transistor, the second transistor including a second active layer and a second gate, wherein the second active layer is located between the first conductive layer and the second conductive layer, and the second gate is located in the second conductive layer; The border area further includes a first auxiliary electrode, which is located in the second conductive layer and electrically connected to the second active layer via a first connection electrode. At least a portion of the first connection electrode is located in the third conductive layer.

14. The array substrate as claimed in claim 13, wherein, The first connection electrode includes a first sub-electrode and a second sub-electrode stacked together, wherein the first sub-electrode is located in the third conductive layer, the second sub-electrode is located in the fourth conductive layer, and at least a portion of the surface of the first sub-electrode on the side away from the substrate is in contact with at least a portion of the surface of the second sub-electrode on the side closer to the substrate.

15. A display device comprising an array substrate, a counter substrate, and a liquid crystal layer as described in any one of claims 1 to 14; wherein the array substrate and the counter substrate are disposed opposite to each other, and the liquid crystal layer is located between the array substrate and the counter substrate.

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