Stacked dynamic random access memory (DRAM) device with multiple master die

Abstract

A stacked die device includes a first master dynamic random access memory (DRAM) die having a first command interface to receive a first command and a first data interface to transfer first data. The second main DRAM die is stacked with the first main DRAM die and includes a second command interface to receive a second command independent of the first command and a second data interface to transmit second data independent of the first data. The first main DRAM die and the second main DRAM die form respective portions of the first memory channel and the second memory channel. A third DRAM die is stacked with the first main DRAM die and the second main DRAM die, and includes a first selectively enabled data input / output (I / O) circuit coupled to the first main DRAM die. A fourth DRAM die is stacked with the other die and includes a second selectively enabled data input / output (I / O) circuit coupled to the second main DRAM die.

Description

Technical Field

[0001] The disclosure herein relates to memory systems, memory devices, and associated methods. Brief Description of the Drawings

[0002] Embodiments of the present disclosure are illustrated in the drawings by way of example and not limitation, where like reference numerals indicate like elements, and in the drawings:

[0003] Figure 1 An embodiment of a multi-channel and multi-column memory device employing a stacked die architecture is illustrated.

[0004] Figure 2 Illustrated is Figure 1 the data configuration logic (magnified callout 2-1) and command / address configuration logic (magnified callout 2-2) employed by each die of the stacked die architecture shown.

[0005] Figure 3A Illustrated is Figure 1 an embodiment of the data and C / A signal flow of the first channel of the memory device shown.

[0006] Figure 3B Illustrated is Figure 1 an embodiment of the data and C / A signal flow of the second channel of the memory device shown.

[0007] Figure 4 Illustrated is a multi-channel memory device similar to the embodiment of Figure 1 and including a wider data interface than the embodiment of Figure 1 shown.

[0008] Figure 5 Illustrated is Figure 4 the interface circuitry employed by the multi-channel memory device shown.

[0009] Figure 6A Illustrated is Figure 4 an embodiment of the data and C / A signal flow of the first channel of the memory device shown.

[0010] Figure 6B Illustrated is Figure 4 an embodiment of the data and C / A signal flow of the second channel of the memory device shown.

[0011] Figure 7 Illustrated is a multi-channel and multi-column memory device similar to the embodiment of Figure 1 and including a wider data interface than the embodiment of Figure 1 shown.

[0012] Figure 8 Another embodiment of a stacked memory device that utilizes wire bonding technology to interconnect die stacks organized in a staggered configuration is illustrated.

[0013] Figure 9 Another embodiment of a stacked memory device that utilizes wire bonding technology to interconnect die stacks organized in a non - staggered configuration is illustrated. Detailed Description

[0014] Memory devices, modules, systems, and related methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes a first master DRAM die having a first command interface for receiving a first command and a first data interface for transmitting first data. The first master DRAM die forms at least a portion of a first memory channel and buffers signals transmitted between an external integrated circuit (IC) device and other portions of the first memory channel. A second master DRAM die is stacked with the first master DRAM die and includes a second command interface for receiving a second command independent of the first command and a second data interface for transmitting second data independent of the first data. The second master DRAM die forms at least a portion of a second memory channel and buffers signals transmitted between the external IC device and other portions of the second memory channel. A third DRAM die is stacked with the first master DRAM die and the second master DRAM die and includes a first selectively - enabled data input / output (I / O) circuit coupled to the first master DRAM die. A fourth DRAM die is stacked with the first master DRAM die, the second master DRAM die, and the third DRAM die and includes a second selectively - enabled data input / output (I / O) circuit coupled to the second master DRAM die. Some embodiments described herein may configure the third DRAM die and the fourth DRAM die as responder dies to add a second column of memory for each channel by disabling the first selectively - enabled data I / O circuit and the second selectively - enabled data I / O circuit. Other embodiments may configure the third DRAM die and the fourth DRAM die as sub - master dies to form a channel with a larger data width. In some embodiments, each die includes a register storage device for storing configuration information for configuring the die. By using multiple master dies to define multiple channels in a stacked DRAM device, power consumption and device footprint can be reduced, thereby correspondingly reducing the cost of memory modules, for example, within a data center environment.

[0015] Now refer to Figure 1, shows a stacked memory device generally labeled 100, which includes a plurality of memory dies 102, 104, 106, and 108 vertically stacked into a single semiconductor package. For one embodiment, the plurality of memory dies 102, 104, 106, and 108 are in the form of dynamic random access memory (DRAM) integrated circuit (IC) dies or chips having substantially the same structure, and include configuration circuitry for configuring each die as a master die, a responder die, or a secondary master die according to the die's application and location in the stack. Further details regarding embodiments of data configuration circuitry and C / A configuration circuitry for performing the configuration are described below and shown in Figure 2 in which further details of embodiments of data configuration circuitry and C / A configuration circuitry for performing the configuration are shown.

[0016] Further referring to Figure 1 , for one embodiment, the bottommost first DRAM die 102 of the stacked memory device 100 is configured as a first main memory die, which forms at least a part of the first memory channel CH0. As a main memory die, the first DRAM die 102 interfaces directly with an external memory controller (not shown) and provides a buffering function for the first memory channel CH0 between the external memory controller and any other die that may be placed in the stacked memory device 100. The first main memory die 102 also serves as the first column memory of the first memory channel CH0. Since the first DRAM die 102 acts as a buffer, from the perspective of the memory controller, the entire first memory channel CH0 is regarded as a single load, thereby reducing the capacitance on the first memory channel and improving the signaling performance. For one embodiment, the first main memory die 102 is formed with an external data interface DATA 114 and an external C / A interface C / A 116, the external data interface including a first set of data contacts CH0d for the first memory channel CH0, and the external C / A interface including a first set of C / A contacts CH0ca for the first memory channel CH0. The first main memory die 102 is also formed with a second set of data contacts CH1d for the second memory channel CH1 and a second set of C / A contacts CH1ca for the second memory channel CH1. The external data and C / A interfaces DATA 114 and C / A 116 are coupled to an external memory controller (not shown) via respective data buses and C / A buses (not shown).

[0017] Continuing to refer to Figure 1 , for one embodiment, the second DRAM die 104 of the stacked memory device 100 is directly stacked on the first DRAM die 102. The second DRAM die is configured as a second main memory die, which forms the first column of the second memory channel CH1. As Figure 2As shown, the second DRAM die 104 includes an internal data interface coupled to a second set of data contacts CH1d of the first DRAM die 102, and an internal C / A interface coupled to a second set of C / A contacts CH1ca of the first DRAM die 102. For one embodiment, the routing of data signals and C / A signals between the first master die 102 and the second master die 104 is performed through sets of through-silicon vias (TSVs) at 118 and 120 as shown and described below with reference to Figure 2 the sets shown and described.

[0018] As described above, for one embodiment, the first DRAM die 102 and the second DRAM die 104 are configured as master dies that form the first column of a corresponding first memory channel CH0 and the first column of a second memory channel CH1. The separate channels CH0 and CH1 transmit data independently of each other in response to commands received independently of each other. This allows for finer-grained accesses that can be performed in parallel or substantially concurrently.

[0019] Further reference is made to Figure 1 , the third DRAM die 106 of the stacked memory device 100 is configured as a first responder memory die that forms another portion of the first memory channel CH0 by adding storage capacity in the form of a second column. As a responder memory die, the third DRAM die 106 interfaces indirectly with an external memory controller (not shown) via the first main DRAM die 102. Since the third DRAM die 106 communicates with the memory controller through the first main DRAM die, the data and C / A input / output (I / O) circuitry for the third DRAM die can be disabled, thereby saving power. For one embodiment, the routing of data signals and C / A signals between the first DRAM die 102 and the third DRAM die 106 is performed through sets of through-silicon vias (TSVs) at 122 and 124 as shown and described below with reference to Figure 2 the sets shown and described.

[0020] Continuing to refer to Figure 1 , the fourth DRAM die 108 of the stacked memory device 100 is configured as a second responder memory die that forms another portion of the second memory channel CH1 by adding storage capacity in the form of a second column. Similar to the third DRAM die 106, the fourth DRAM die 108 interfaces indirectly with an external memory controller (not shown) via the second main DRAM die 104 and is also configured such that its data and C / A I / O circuitry is disabled. For one embodiment, the routing of data signals and C / A signals between the second DRAM die 104 and the fourth DRAM die 108 is performed through sets of through-silicon vias (TSVs) as shown and described below with reference to Figure 2performed by respective groups of through - silicon vias (TSVs) at 126 and 128 as shown and described.

[0021] Further reference Figure 1 , specific embodiments of the DRAM memory dies 102, 104, 106, and 108 can conform to various DRAM standards, including double - data - rate (DDR) variants, low - power (LPDDR) versions, high - bandwidth (HBM), and graphics (GDDR) types. Other embodiments can stack the memory dies together in a common package or in separate packages stacked on top of each other. However, in a memory - module configuration for high - volume applications, other embodiments can employ multiple memory devices on a substrate (not shown). Although Figure 1 only four dies are shown, the architectures described herein are scalable to support any number of channels and columns depending on the application.

[0022] Figure 2 is illustrated in more detail Figure 1 an embodiment of the stacked memory device 100. Each of the four DRAM dies 102, 104, 106, and 108 includes a selectively - enabled data (DQ) input / output (I / O) circuit device 202 coupled to a memory core 204 via a data configuration circuit device 206. The C / A I / O circuit device 208 is coupled to the memory core 204 via a C / A configuration circuit device 210. For some embodiments, a register storage device 212 is included in each die to store the configuration settings of a given die.

[0023] For one embodiment, further reference Figure 2 , each die includes an external data TSV region at 214 and an internal data TSV region at 216. The external data TSV region 214 is patterned such that the TSV connections between adjacent dies offset or shift the TSV positions. The pattern can take the form of a spiral, a "double - S", or any other pattern to achieve the desired position shift between adjacent (immediately above or below) dies. For some embodiments, when configuring which die is the master or responder for a particular channel, its position at a particular level in the die stack is determined by the TSV pattern. In the case of the external data TSV region 214, and for Figure 2Specific embodiments are such that the pattern is directly connected only to the data contact groups labeled CH0 and CH1. Other TSV paths (such as at 219 and 221) are not connected to the external interface and thus do not create a load on the channels. Thus, the external data TSV domain 214 allows stacking of substantially identical dies while presenting only a single data I / O load per channel to the memory controller (not shown). The internal data TSV domain 216 is also configured to shift the TSV connection locations between dies and determine the data column selection for a given die. Each die also includes an external C / A TSV domain at 218 and an internal C / A TSV domain 220. Similar to the data TSV domains 214 and 216, from the perspective of the memory controller, the external C / A TSV domain 218 allows the die stack to present a single C / A I / O load. For some embodiments, the internal C / A TSV domain 220 indicates a specific memory column or secondary die selection.

[0024] Continuing to refer Figure 2 , and more specifically referring to the enlarged annotation 2-1, one embodiment of the data configuration circuitry 206 includes a data I / O selector 222 that bi-directionally transfers signals between the data I / O circuitry 202 and the memory core 204 or the internal data TSV domain 216 to connect to different dies. The I / O selector 222 can be enabled / disabled in response to a control signal CTLa. A set of internal data TSV path selectors 224, 226, and 228 corresponds to the internal data TSV domain 216 from a lower die and steers data signals in response to respective control signals CTLb, CTLc, and CTLd between a given lower TSV location and the memory core 204 or an upper TSV location shifted from the lower TSV location. For one embodiment, the control signals are fed from the register storage device 212 to the selectors to configure the memory device during an initialization operation mode.

[0025] Further referring Figure 2 , and more specifically referring to the enlarged annotation 2-2, the C / A configuration circuitry 210 includes a C / A I / O selector 230 that unidirectionally transfers C / A signals from the C / A I / O circuitry 208 to the memory core 204. The C / A I / O selector 230 can be enabled / disabled in response to a control signal CTLe. A set of internal data TSV path selectors 232, 234, and 236 corresponds to the internal C / A TSV domain 220 and steers command and address signals from the C / A I / O circuitry 208 or a given lower TSV location shifted from the upper TSV location, as shown at 238, for example.

[0026] Configuration Figure 2 The multi-die memory device

[0026] configured to implement a dual-channel, dual-rank memory device can occur in a variety of ways. For one embodiment, before the packaged DRAM device is installed in a higher-level component, the data configuration circuitry 206 and the C / A configuration circuitry 210 for each die can be pre-configured or fixed during the manufacturing process. For other embodiments, the configuration circuitry 206 and 210 can be partially or fully programmed or configured by the user in the field. This can be performed by manually setting the pins of the module or board on which the device is mounted to generate the desired control signals, or during an initialization operation mode, in which the control signals can be retrieved from a register storage device or received via calibration control signals from a memory controller. In some cases, an on-the-fly reconfiguration of a particular package topology of the memory device 100 can be performed during a data transfer operation mode, such as via one or more MRS control signals included in the C / A signal stream. Additionally, it is assumed that the external package interface typically only directly connects to a smaller subset of the possible TSV locations of the external data TSV domain 214 and the external C / A TSV domain 218. Thus, the smaller subset of locations can be considered to be only directly connected to a starting reference location group of the first master die 102, where subsequent dies above the first master die 102 are connected to shifted TSV locations that are decoupled from the direct connection to the external interface.

[0027] Further reference Figure 2 will describe the specific configuration settings of the data configuration circuitry 206 and the C / A configuration circuitry 210 for a specific embodiment to configure the DRAM device 100 as a dual-channel, dual-rank memory device. Since the per-die configuration is described relative to other dies, the identifier for each die will be specified with a subscript indicating the die level. The data configuration circuitry 206 for the first master die 102 1 is configured such that the data I / O selector 222 is enabled, resulting in a direct signal flow between the data I / O circuitry 202 of the first die 102 1 and the memory core 204 of the first die 102 1 . The data configuration circuitry 206 1 also provides a choice between a connection to the memory core 204 of the first die 102 1 or a first location of the internal data TSV domain 216 of the first die 102. The internal data selectors 224, 226, and 228 of the first die 102 are disabled because there are no dies below the first master die 102 and thus no signals from a lower-level internal data TSV domain. The C / A configuration circuitry 210 for the first master die 102 1configured such that the C / A I / O selector 230 is enabled, resulting in a direct command and address signal flow from the C / A I / O circuitry 208 1 to the memory core 204 of the first die 102 1 . Additionally, a second internal C / A TSV selector in a group of internal C / A TSV selectors of the first die 102 is enabled to pass the C / A signal upward to the second DRAM die 104 at the first TSV location.

[0028] The data configuration circuitry of the second DRAM die 104 is similarly configured such that the first internal data TSV path selector in the group of internal data TSV path selectors at 224 is enabled and the remaining selectors 226 and 228 are disabled. The enabled selector 224 provides a first channel CH0 data path from the first DRAM die 102 to the second TSV location of the third DRAM die 106. As the second master die and the first column for the second channel CH1, the selector circuitry 222 is enabled to provide a direct connection between the data I / O circuitry 202 of the second die 2 and the memory core 204 of the second die 2 . The selector 222 also provides a choice between a connection to the memory core 204 of the second die 2 or a first location in the internal data TSV domain 216 of the second die. The C / A configuration circuitry 210 of the second die 104 2 is configured such that the first internal C / A TSV path selector in the group of internal C / A TSV path selectors at 232 is enabled to pass the C / A signal for the first channel to the third die 106. The second internal C / A TSV path selector in the group of internal C / A TSV path selectors at 234 is also enabled to pass the C / A signal for the second channel to the third die 106. The third internal C / A TSV selector in the group of internal C / A TSV selectors at 236 is disabled.

[0029] Continuing to refer to Figure 2 , the third DRAM die 106 is configured as a responder die, where the data I / O circuitry 202 3 and the C / A I / O circuitry 208 3Both are disabled. The first internal data TSV selector 224 in the internal data TSV selector is enabled and coupled to the second DRAM die 104 through the first internal data TSV position to transfer data for the second channel between the second die 104 and the fourth die 108. The second internal data TSV selector 226 in the internal data TSV selector is enabled and coupled to the second DRAM die 104 through the second internal data TSV position. The internal data TSV selector 226 is also configured to be connected to the memory core 204 of the third DRAM die 106 3 , rather than the next-level TSV domain. The C / A configuration circuitry 210 of the third die 106 3 is configured with a C / A I / O selector 230, which is enabled to receive the C / A signal from the first TSV domain position fed from the second DRAM die 104. The first internal C / A TSV selector 232 is enabled to transfer the C / A signal for the second channel CH1 from the second die 104 to the fourth die 108.

[0030] Further reference Figure 2 , the fourth die 108 is configured with data I / O circuitry 202 4 and C / A I / O circuitry 208 4 both are disabled. When only supporting data transfer for the second column of the second channel CH1, the data configuration circuitry 206 for the fourth die 108 4 enables the second internal data TSV selector 226 to transfer data between the third die 106 (from the first internal data TSV selector 224) and the memory core 204 of the fourth die 108 4 . The first internal data TSV selector 224 and the third internal data TSV selector 228 can be disabled. The C / A configuration circuitry 210 of the fourth die 4 is configured such that the C / A selector 230 is enabled to receive the C / A signal from the internal TSV domain 220 of the third die 106. The internal C / A TSV selectors 232, 234, and 236 can be disabled (because there are no other dies above the fourth die in the stack).

[0031] Now refer to Figure 3A, where the first die 102, the second die 104, the third die 106, and the fourth die 108 are configured as described above, showing data and C / A signal flows related to data transmission for two columns for the first memory channel CH0. For a given transaction on the first channel CH0, at 302, various command and address signals are received at the external C / A interface contact of the first DRAM die 102 of the first channel CH0. At 304, the C / A signal is fed to the C / A I / O circuitry 208 1 , and then at 306 it is forwarded to the C / A configuration circuitry 210 of the first DRAM die 102 1 . The C / A signal is conditionally fed from the C / A configuration circuitry 210 of the first die 102 1 to one or both of the following: at 307 to the memory core 204 1 , and at 308 via the internal C / A TSV pattern to the C / A configuration circuitry 210 of the second die 104 2 . Then, at 310, the C / A configuration circuitry 210 of the second die 104 2 passes the C / A signal to the C / A configuration circuitry 210 of the third die 106 via the internal C / A TSV pattern 3 . At 312, the C / A signal is fed by the C / A configuration circuitry 210 of the third memory die 106 3 to the memory core 204 of the third memory die 106 3 . For one embodiment, based on the value of the chip select control signal in the C / A signal flow, the memory core 204 of the first die 102 1 or the memory core 204 of the third die 106 3 is accessed for the first channel CH0 transfer operation.

[0032] Further referring Figure 3A , based on whether the transaction involves a write operation or a read operation, the data involved in the transaction specified by the C / A signal passes through the die in the signal flow direction. For a write operation, at 314, write data is received by the external data interface, and at 316, the write data is passed to the data I / O circuitry 202 of the first memory die 102 1 . Then, at 318, the data I / O circuitry 202 1 drives the write data to the data configuration circuitry 206 of the first die 102 1 . Then, based on the value of the chip select control signal or other similar control signal in the C / A signal flow, the data configuration circuitry 206 of the first die 102 1 conditionally forwards the write data to the memory core 204 at 3191 or the data configuration circuitry 206 that forwards to the second die 104 at 320 2 . If the data is forwarded to 206 2 , then at 322, further vertical transmission occurs between the data configuration circuitry 206 of the second die 104 2 and the data configuration circuitry 206 of the third die 106 3 . At 324, the data configuration circuitry 206 of the third die 106 3 then feeds the write data to the memory core 204 3 . The memory core selected by the chip select signal (i.e., the memory core 204 1 or 204 3 ) receives the write data and performs a write operation in the accessed memory core. The read operation is similar but follows a signal path opposite to that of the write operation.

[0033] Figure 3B illustrates Figure 1 the signal flow of the stacked memory device 100 for the second memory channel CH1 during a data transfer operation mode. Although only the second DRAM die 104 and the fourth DRAM die 108 are used for the second memory channel CH1, the first DRAM die 102 and the third DRAM die 106 are still involved in the internal TSV signal routing between the second DRAM die 104 and the fourth DRAM die 108. The first DRAM die 102 and the third DRAM die 106 are accordingly configured to perform signal routing support. It should also be understood that all of the configuration settings described above for the first memory channel CH0 remain configured for each die in addition to the settings for configuring each die to support the second memory channel CH1.

[0034] Further referring to Figure 3B , the external data TSV domain 214 and the external C / A TSV domain 218 ( Figure 2 ) are connected to the external interface contacts assigned to the second memory channel CH1, such as at 342 and 326, and shift the respective data and C / A paths by a TSV position for the second DRAM die 104. The data configuration circuitry 206 1 and the C / A configuration circuitry 210 1 of the first DRAM die 102 are not configured to support the second channel CH1 and thus do not require further description.

[0035] Continuing to refer to Figure 3B, the data configuration circuitry 206 of the second DRAM die 104, the third DRAM die 106, and the fourth DRAM die 108 2 , 206 3 and 206 4 is typically configured for the second memory channel CH1 in a manner similar to that used for the first DRAM die 102, the second DRAM die 104, and the third DRAM die 106 of the first memory channel CH0, except that the enabled internal data TSV selector is shifted in TSV position. For the C / A configuration circuitry 210 of the second die 104, the third die 106, and the fourth DRAM die 108 2 , 210 3 and 210 4 , a similar configuration scheme is presented.

[0036] Further reference Figure 3B , in the case of a stack of DRAM dies configured as described above, a data and C / A signal flow involving data transfer for two columns for the second memory channel CH1 is shown. For a given transaction on the second channel CH1, at 326, command and address signals are received at the external C / A interface contact of the first DRAM die 102 of the second channel CH1. At 328, the C / A signal bypasses the C / A I / O circuitry 208 of the first die 1 (which may be disabled to save power) via the external C / A TSV pattern of the first die, and then at 330, is fed to the C / A input / output circuitry 208 via the external C / A TSV pattern of the second die 104 2 . At 332, the C / A signal is then forwarded to the C / A configuration logic 210 of the second DRAM die 104 2 . Based on the value of the chip select control signal or other similar control signals in the C / A signal flow, the C / A signal is fed from the C / A configuration circuitry 210 of the second die 104 2 to one or both of the following: fed to the memory core 204 at 334 2 , and fed to the C / A configuration circuitry 210 of the third die 106 via the internal C / A TSV pattern at 336 3 . In a second case, at 338, the C / A configuration circuitry 210 of the third die 106 3 then passes the C / A signal to the C / A configuration circuitry 210 of the fourth die 108 via the internal C / A TSV pattern 4 . At 340, the C / A signal is received by the C / A configuration circuitry 210 of the fourth memory die 108 4Memory cores 204 fed to the fourth memory die 108 4 Based on the value of the chip select control signal or other similar control signals in the C / A signal stream, access the memory cores 204 of the second die 104 2 or the memory cores 204 of the fourth die 108 4 for transfer operations.

[0037] For further reference Figure 3B , for a write operation, at 342, write data is received by the external data interface, and at 344, due to the routing of the external TSV pattern, the write data bypasses the data I / O circuitry 202 of the first memory die 102 1 . Then, at 346, the data is fed to the data I / O circuitry 202 of the second memory die 104 2 . Then, at 348, the data I / O circuitry 202 2 drives the write data to the data configuration circuitry 206 of the second die 104 2 . Then, at 350, the data configuration circuitry 206 of the second die 104 2 forwards the write data to the memory core 204 2 , and at 352, forwards the write data to the data configuration circuitry 206 of the third memory die 106 3 . At 354, further vertical transfer occurs between the data configuration circuitry 206 of the third memory die 106 3 and the data configuration circuitry 206 of the fourth memory die 108 4 . At 356, the data configuration circuitry 206 of the fourth die 108 4 then feeds the write data to the memory core 204 4 . The memory cores activated by the chip select signal (i.e., memory cores 204 2 or 204 4 ) receive the write data, and a write operation is performed in the accessed memory core. The read operation is similar but follows the signal path opposite to that of the write operation.

[0038] Figure 4 Illustrates another embodiment of a stacked memory device generally designated by 400. Although Figure 1 the stacked memory device 100 of Figure 4 is configured as a dual-channel, dual-rank device, Figure 4The data width presented by the stacked memory device is, in one embodiment, twice the data width of the stacked memory device 100 described above. For one embodiment, the stacked memory device 400 includes a plurality of configurable memory dies 402, 404, 406, and 408 that are vertically stacked and in the form of dynamic random access memory (DRAM) integrated circuit (IC) dies or chips, which are structurally identical to Figure 1 - the dies 102, 104, 106, and 108 of FIG. 3.

[0039] Further referring to Figure 4 , for one embodiment, the bottommost first DRAM die 402 of the stacked memory device 400 is configured as a first primary main memory die, which forms at least a part of the first data width of the first memory channel CH0. The first primary DRAM die 402 interfaces directly with an external memory controller (not shown) and serves as a part of the first column memory of the first memory channel CH0. For one embodiment, the first main memory die 402 is formed with an external data interface DATA 414, which includes a first set of data contacts "L0" and a second set of data contacts "U0" for the first memory channel CH0, and a third set of data contacts "L1" and a fourth set of data contacts "U1" for the second memory channel CH1. The internal data interface of the first primary main die 402 at 418 directly couples the memory core of the first primary main memory die 402 to the first set of contacts L0. The first primary main die 402 also includes an external C / A interface C / A 416, which includes a first set of C / A contacts CH0ca for the first memory channel CH0 and a second set of C / A contacts CH1ca for the second memory channel CH1. The internal C / A interface of the first primary main die 402 at 420 directly couples the memory core of the first primary main memory die 402 to the first set of C / A contacts CH0ca. The external data interface DATA 414 and the external C / A interface C / A 416 are coupled to an external memory controller (not shown) via respective data buses and C / A buses (not shown).

[0040] Continuing to refer to Figure 4, For one embodiment, the second DRAM die 404 of the stacked memory device 400 is directly stacked on the first DRAM die 402. The second DRAM die 404 is configured as a second primary main memory die that forms part of the first column of the second memory channel CH1. The second DRAM die 404 includes an internal data interface (at 422) and an internal C / A interface (at 424), the internal data interface coupling the memory core to a second set of data contacts L1 of the first DRAM die 402, and the external C / A interface coupling the memory core to a second set of C / A contacts CH1ca of the first main DRAM die 402. For one embodiment, the routing of data and C / A signals between the first primary die 402 and the second primary die 404 is performed through multiple sets of through-silicon vias (TSVs) as shown and described below with reference to Figure 5 as shown.

[0041] As described above, for one embodiment, the first primary main DRAM die 402 and the second primary main DRAM die 404 are configured as primary dies that form part of the first column of the respective first memory channel CH0 and second memory channel CH1. The separate channels CH0 and CH1 transmit data independently of each other in response to commands received independently of each other. This allows for finer-grained accesses that can be performed in parallel or substantially concurrently.

[0042] Further referring to Figure 4 , the third DRAM die 406 of the stacked memory device 400 is configured as a first secondary main memory die that extends the data width of the first memory channel CH0 by adding separate storage capacity and interface resources in parallel with the first primary die 402 in response to a given set of C / A signals. As a secondary main memory die, the third DRAM die 406 interfaces with an external memory controller (not shown) via a set of external interface contacts "U0". At 426, a set of internal data TSVs couples the contacts U0 to the memory core of the third die 406. At 428, a set of internal C / A TSVs couples the contacts CH0ca to the memory core of the third die 406 via the first die 402. Since the third DRAM die 406 transfers data with the memory controller, the data input / output (I / O) circuitry for the third DRAM die remains enabled.

[0043] Continuing to refer to Figure 4, the fourth DRAM die 408 of the stacked memory device 400 is configured as a second secondary main memory die that extends the data width of the second memory channel CH1 by adding separate memory capacity and interface resources in parallel with the second primary main die 404 in response to a given set of C / A signals. Similar to the third DRAM die 406, the fourth DRAM die 408 is interfaced to an external memory controller (not shown) via a set of external interface contacts "U1". At 430, a set of internal data TSVs couple the contacts U1 to the memory core of the fourth die 406. At 432, a set of internal C / A TSVs couple the contacts CH1ca to the memory core of the fourth die 408 via the second die 404. Since the fourth DRAM die 408 communicates with the memory controller, the data input / output (I / O) circuitry for the fourth DRAM die 408 remains enabled.

[0044] Although Figure 4 only four dies are shown to support a dual-channel device, it should be understood that the general architecture is scalable to support a greater number of channels and widths by including additional dies and modifying the external TSV pattern accordingly.

[0045] Figure 5 More particularly illustrated is Figure 4 an embodiment of the stacked memory device 400. Each of the four DRAM dies 402, 404, 406, and 408 includes selectively enabled data (DQ) I / O circuitry 502 coupled to a memory core 504 via data configuration circuitry 506. C / A I / O circuitry 508 is coupled to the memory core 504 by C / A configuration circuitry 510. For some embodiments, register storage 512 is included in each die to store configuration settings for a given die. At this time, each of the dies 402, 404, 406, and 408 has a construction similar to that of Figure 2 the dies 102, 104, 106, and 108.

[0046] For one embodiment, further referring to Figure 5 , each die includes an external data TSV field of TSVs at 514 and an internal data TSV field at 516. Although the internal data TSV field is similar to the field described in the die embodiments of Figure 2 , the size of the external data TSV field 514 is scaled to support an extended data width relative to the previously described embodiments. Thus, to support a stacked memory device 100 ( Figure 1) The number of TSVs and interface contacts employed for an embodiment of the external data TSV region 514 of the stacked memory device 400, which has a data width that is twice the data width, is twice that employed by the stacked memory device 100.

[0047] With further reference Figure 5 , the specific configuration settings of the data configuration circuitry and the C / A configuration circuitry 510 will be described for a specific embodiment to configure the memory device 400 as a dual-channel, dual-width memory device. The data configuration circuitry 506 for the first primary die 402 1 is configured such that the data I / O selector 222 ( Figure 2-1 ) is enabled, resulting in a direct signal flow between the data I / O circuitry 502 of the first die 402 1 and the memory core 504 of the first die 402 1 . The internal data selectors 224, 226, and 228 ( Figure 2 ) are disabled because there is no die beneath the first primary die 402 and thus no signals from the lower-level internal data TSV region. The C / A configuration circuitry 510 for the first primary die 402 1 is configured in a manner similar to the C / A configuration circuitry of the stacked memory device 100 for Figure 2 .

[0048] The second DRAM die 404 is configured similarly to the first die 402 as a primary die, but receives its external interface signals via an external TSV pattern and from the contact L1 of the first die 402. The data configuration circuitry 506 for the second primary die 404 2 is configured such that the data I / O selector 222 ( Figure 2-1 ) is enabled, resulting in a direct signal flow between the data I / O circuitry 502 of the second die 404 2 and the memory core 504 of the second die 404 2 . The C / A configuration circuitry 510 of the second die 404 2 is configured in the same manner as the C / A configuration circuitry of the stacked memory device 100 for Figure 2 .

[0049] Continuing with reference Figure 5 , the third DRAM die 406 is configured such that the data I / O circuitry 502 3 is enabled and the C / A I / O circuitry 508 3 is disabled. The data configuration circuitry 506 3 is configured to provide to the memory core 504 3The direct connection. The C / A configuration circuitry 510 of the third die 406 is configured in a manner similar to the C / A configuration circuitry of the stacked memory device 100 for Figure 2 The fourth DRAM die 408 is not involved in any data or C / A signal routing of the first memory channel CH0.

[0050] Now referring to Figure 6A , in which the first die 402, the second die 404, the third die 406, and the fourth die 408 are configured as described above, shows the data and C / A signal flow for data transfer involving the first memory channel CH0. For a given transaction on the first channel CH0, at 602, various command and address signals are received at the external C / A interface contact of the first DRAM die 402 for the first channel CH0. At 604, the C / A signal is fed to the C / A I / O circuitry 508 1 , and then at 606 it is forwarded to the C / A configuration logic 510 of the first DRAM die 402 1 . The C / A signal is fed from the C / A configuration circuitry 510 of the first die 402 1 to both: at 607 to the memory core 504 1 , and at 608 to the C / A configuration circuitry 510 of the second die 404 via the internal C / ATSV pattern 2 . Then, at 610, the C / A configuration circuitry 510 of the second die 404 2 passes the C / A signal to the C / A configuration circuitry 510 of the third die 406 via the internal C / A TSV pattern 3 . At 612, the C / A signal is fed by the C / A configuration circuitry 510 of the third memory die 406 3 to the memory core 504 of the third memory die 406 3 . For one embodiment, the common chip select control signal (or other control signal) in the C / A signal flow accesses the memory cores 504 of both the first die 402 1 and the third die 406 3 for transfer operations.

[0051] Further referring to Figure 6A , depending on whether the transaction involves a write operation or a read operation, the data involved in the transaction specified by the C / A signal travels across the die in the signal direction. For a write operation, at 614 and 615, the first and second parts of the write data are received by separate contact groups L0 and H0 of the external data interface, and at 616 are passed to the data I / O circuitry 502 of the first memory die 402 1, and the data I / O circuitry 502 of the third memory die 406 that is passed at 617 3 , which passes through the external data TSV pattern of the first die 402 and the second die 404. Then, at 618, the data I / O circuitry 502 of the first die 402 1 drives the first portion of the write data to the data configuration circuitry 506 of the first die 402 1 . At 620, in parallel with the data I / O circuitry 502 of the first die 402 1 , the data I / O circuitry 502 of the third die 406 3 drives the second portion of the write data to the data configuration circuitry 506 of the third die 406 3 . Then, at 622, the data configuration circuitry 506 of the first die 402 1 forwards the first portion of the write data to the memory core 504 1 , while at 624, the data configuration circuitry 506 of the third die 406 3 forwards the second portion of the write data to the memory core 504 3 . Since both memory cores 504 1 and 504 3 are activated by a common chip select signal and multiple data paths are configured from the external interface to each memory core, each memory core receives the corresponding portion of the write data during at least partially overlapping corresponding time intervals, commonly referred to as concurrent occurrence, and performs a write operation. The read operation is similar but follows a signal path opposite to that of the write operation.

[0052] Figure 6B illustrates Figure 4 the signal flow of the stacked memory device 400 for the second memory channel CH1 during a data transfer operation mode. Although only the second DRAM die 404 and the fourth DRAM die 408 are used for the second memory channel CH1, the first DRAM die 102 and the third DRAM die 406 are still involved in the internal TSV signal routing between the second DRAM die 404 and the fourth DRAM die 408. The first DRAM die 402 and the third DRAM die 406 are configured accordingly to perform signal routing support. It should also be understood that all of the configuration settings described above for the first memory channel CH0 remain configured for each die in addition to the settings used to configure each die to support the second memory channel CH1.

[0053] Further referring to Figure 6B , the external data TSV domain 214 and the external C / A TSV domain 218 ( Figure 2)Connect to the external interface contact portions assigned to the second memory channel CH1, such as at 644 and 645, and shift the corresponding data and C / A path TSV positions of the second DRAM die 404. The data configuration circuitry 506 for the first DRAM die 402 1 and the C / A configuration circuitry 510 1 are not configured to support the second channel CH1 and thus do not require further description.

[0054] Continuing to refer to Figure 6B , the data configuration circuitry 506 for the second DRAM die 404, the third DRAM die 406, and the fourth DRAM die 408 2 、506 3 and 506 4 are generally configured in a manner similar to that of the first DRAM die 402, the second DRAM die 404, and the third DRAM die 406 for the first memory channel CH0 for the second memory channel CH1, except that the enabled internal data TSV selector is shifted in the TSV position. The C / A configuration circuitry 510 for the second DRAM die 404, the third DRAM die 406, and the fourth DRAM die 408 2 、510 3 and 510 4 presents a similar configuration scheme.

[0055] Further referring to Figure 6B , in the case of configuring a stack of DRAM dies as described above, the data and C / A signal flows related to data transmission for the second memory channel CH1 are shown. For a given transaction for the second channel CH1, at 630, various command and address signals are received at the external C / A interface contact portion of the first DRAM die 402 for the second channel CH1. Then, at 632, the C / A signal is fed to the C / A I / O circuitry 508 2 , and then at 634, it is forwarded to the C / A configuration logic 510 of the second DRAM die 404 2 . The C / A signal is fed from the C / A configuration circuitry 510 of the second die 404 2 to the memory core 504 2 , and at 638, it is fed to the C / A configuration circuitry 510 of the third die 406 via the internal C / A TSV pattern 3 . Then, at 640, the C / A configuration circuitry 510 of the third die 406 3 passes the C / A signal to the C / A configuration circuitry 510 of the fourth die 408 via the internal C / A TSV pattern 4. At 642, the C / A signal is fed by the C / A configuration circuitry 510 of the fourth memory die 408 4 to the memory core 504 of the fourth memory die 408 4 . For one embodiment, a common chip select control signal (or multiple (encoded) chip select signals) in the C / A signal stream accesses the memory cores 504 2 of both the second die 404 and the fourth die 408 to perform transfer operations during a common time interval.

[0056] Continuing with reference Figure 6B , for a write operation, at 644 and 645, the first and second parts of the write data are received by separate contact groups L1 and H1 of the external data interface and are passed at 646 to the data I / O circuitry 502 of the second memory die 404 2 and are passed at 647 to the data I / O circuitry 502 of the fourth memory die 408 4 , which traverses the external data TSV pattern of the second die 404 and the third die 406. Then, at 648, the data I / O circuitry 502 of the second die 404 2 drives the first part of the write data to the data configuration circuitry 506 of the second die 404 2 . At 650, in parallel with the data I / O circuitry 502 of the second die 404 2 , the data I / O circuitry 502 of the fourth die 408 4 drives the second part of the write data to the data configuration circuitry 506 of the fourth die 408 4 . Then, at 652, the data configuration circuitry 506 of the second die 404 2 forwards the first part of the write data to the memory core 504 2 , while at 654, the data configuration circuitry 506 of the fourth die 408 4 forwards the second part of the write data to the memory core 504 4 . Since both memory cores 504 2 and 504 4 are activated by a common chip select signal and multiple data paths are configured from the external interface to each memory core, each memory core receives the corresponding part of the write data during corresponding time intervals that are at least partially temporally overlapping, commonly referred to as concurrent occurrence, and performs the write operation. The read operation is similar but follows a signal path opposite to that of the write operation.

[0057] Figure 7Illustrated is a dual-channel, two-column, extended-width stacked die memory device generally designated 700, which incorporates features from Figure 1 and Figure 4 as shown and in the above two embodiments. The stacked die memory device 700 includes eight memory dies 702, 704, 706, 708, 710, 712, 714, and 716 stacked vertically. Generally, the bottom-most dies 702, 704, 706, and 708 are configured similar to the Figure 4 extended-width embodiment and are thus configured as two primary master dies 702 and 704 (to form respective portions of a first channel CH0 and a second channel CH1), and two secondary master dies 706 and 708. To provide additional capacity, four responder dies 710, 712, 714, and 716 are added to form two columns for each of the two channels. When forming the multi-column stacked die device 700, the top-most dies 710, 712, 714, and 716 are configured similar to the Figure 1 embodiment, where the internal TSV pattern is scaled accordingly to support additional die tiers. Similar to the Figure 1 and Figure 4 embodiments, depending on the application, the Figure 7 embodiment can be further scaled to support any number of channels, widths, and / or columns.

[0058] The above-described embodiments regarding Figures 1-7 relate to stacked die devices with multiple channels, multiple columns, and extended width that are configurable and scalable while maintaining a minimum horizontal footprint. Other configurable features provided by some embodiments relate to enabling and / or disabling serialization and deserialization circuitry, depending on whether a given die is configured as a master die, a secondary master die, or a responder die. In some cases, having this capability can save power. For flexibility, the above embodiments utilize through-silicon via (TSV) technology, which can be scaled directly to support different die stack heights while improving signal integrity. In some cases, when cost considerations may require sacrificing flexibility and signal integrity, wire-bonded stacked dies can provide an acceptable alternative to TSV-based embodiments.

[0059] Figure 8FIG. illustrates an embodiment of a stacked die device 800 that interconnects multiple dies 802, 804, 806, and 808 in a staggered manner to implement a dual-channel two-column stacked die device using a wire bonding connection scheme. The base die 802 is mounted on a substrate 810 and is configured as the main die and the first column of the first channel, and includes external data interface pads at 812, which are connected to data pads DQ0 formed on the substrate 810 via wire bonding connections. The base die 802 also includes external C / A interface pads at 814, which are wire bonded to the first C / A pad CA0 formed on the substrate 810. The second die 804 is directly disposed above the base die 802 and is configured as a responder die, thus forming the second column of the first channel. The second die 804 includes internal data interface pads at 816, which are connected to the second data interface pads of the first die 802 via wire bonding connections at 818. The second die 804 also includes internal C / A interface pads at 820, which are wire bonded to the second C / A pads formed on the first die 802 at 822.

[0060] Further referring to Figure 8 , the third die 806 is mounted above the second die 804 and is configured as the second main die and the first column of the second channel. The third die 806 includes external data interface pads at 824, which are connected to data pads DQ1 formed on the substrate 810. The third die 806 also includes external C / A interface pads at 826, which are connected to the second C / A pad CA1 formed on the substrate 810. The fourth die 808 is directly disposed above the third die 806 and is configured as a responder die, thus forming the second column of the second channel. The fourth die 808 includes internal data interface pads at 828, which are wire bonded to the second data interface pads of the third die 806 at 830. The fourth die 808 also includes internal C / A interface pads at 832, which are wire bonded to the second C / A pads formed on the third die 806 at 834.

[0061] Continuing to refer to Figure 8, each die includes a data interface configuration circuit device 840 and a C / A interface configuration circuit device 850. Magnified annotation 8-1 shows an embodiment of the data interface configuration circuit device 840, which includes a selector 842 for selecting one of two I / O pad paths 843 or 845 to interface with the memory core 844. This selection is based on the I / O pads connected to another die or the substrate 810. Magnified annotation 8-2 shows an embodiment of the C / A interface configuration circuit device 850, which includes a selector 848 for selecting between one of two I / O pad paths 850 or 852 to interface with the memory core 844. This selection is based on whether the C / A I / O pads are connected to another die or the substrate 810.

[0062] Figure 9 Illustrated is an embodiment of a stacked die device 900 similar to that described above with respect to Figure 8 which includes a plurality of dies 902, 904, 906, and 908, and the plurality of dies 902, 904, 906, and 908 are interconnected in a non-staggered manner to implement a dual-channel two-column stacked die device using a wire bonding connection scheme. Most of the structure of the stacked die device 900 corresponds to Figure 8 the structure 800, although the bottom-most dies 902 and 904 are configured as master dies, and the top-most dies 906 and 908 are configured as responder dies.

[0063] The above and Figures 1-9 the embodiments shown should be understood to be conceptual in nature and should not be construed as illustrating and / or describing the exact location or layout of paths and / or connections.

[0064] When received within a computer system via one or more computer-readable media, such data- and / or instruction-based representations of the above circuits can be processed by processing entities (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs (including but not limited to netlist generation programs, layout and routing programs, etc.) to generate a representation or image of the physical manifestation of such circuits. Thereafter, such a representation or image can be used for device fabrication, e.g., by enabling the generation of one or more masks that are used to form the various components of the circuit during the device fabrication process.

[0065] Although the embodiments are described as stacked bodies of DRAM devices, the embodiments can also include other memory types, such as: NAND FLASH, MRAM, RRAM, SRAM, etc.

[0066] In the foregoing description and drawings, specific terms and reference numerals have been set forth to provide a thorough understanding of the present invention. In some instances, the terms and notations may imply specific details that are not required to practice the present invention. For example, any particular number of bits, signal path widths, signaling or operating frequencies, component circuits or devices, etc. may be different from those described in the alternative embodiments above. Additionally, the interconnection between circuit elements or circuit blocks shown or described as a multi-conductor signal link may also be a single-conductor signal link, and a single-conductor signal link may also be a multi-conductor signal link. Signals and signaling paths shown or described as single-ended may also be differential, and vice versa. Similarly, in alternative embodiments, signals described or depicted as having an active-high or active-low logic level may have the opposite logic level. Component circuit devices within an integrated circuit device may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology, or any other technology in which logic and analog circuits may be implemented. Regarding terms, when a signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition, the signal is said to be "asserted". Conversely, a signal is said to be "deasserted" to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or a floating state that may occur when the signal driving circuit transitions to a high impedance state, such as an open-drain or open-collector state). When a signal driving circuit "asserts" (or deasserts, if the context clearly states or indicates) a signal on a signal line coupled between the signal driving circuit and a signal receiving circuit, the signal driving circuit is said to "output" the signal to the signal receiving circuit. When a signal is asserted on a signal line, the signal line is said to be "activated", and when the signal is deasserted, the signal line is said to be "deactivated". Additionally, the prefix symbol " / " appended to a signal name indicates that the signal is a low-level signal (i.e., the asserted state is a logic low state). A bar over a signal name (e.g., ) is also used to indicate an active-low signal. The term "coupled" is used herein to denote both a direct connection and a connection through one or more intermediate circuits or structures. "Programming" an integrated circuit device may include, for example, but is not limited to, loading control values into registers or other storage circuits within the device in response to host instructions (e.g., via a mode register set command "MRS") to control aspects of the operation of the device, establishing the device configuration or controlling aspects of the operation of the device through a one-time programming operation (e.g., blowing a fuse within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also referred to as tying) to establish a particular device configuration or aspect of the operation of the device. The term "exemplary" is used to denote an example, rather than a preference or requirement.

[0067] Although the present invention has been described with reference to specific embodiments thereof, it will be apparent that various modifications and changes can be made to the invention without departing from its broader spirit and scope. For example, at least where practicable, the features or aspects of any embodiment can be applied in combination with, or in place of, the corresponding features or aspects of any other embodiment. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A stacked die device, comprising: A first active dynamic random access memory (DRAM) die having a first command interface for receiving a first command and a first data interface for transmitting first data, the first main DRAM die being configured to form at least a portion of a first memory channel and buffer signals transmitted between an external integrated circuit (IC) device and other portions of the first memory channel; A second main DRAM die stacked with the first main DRAM die and having a second command interface and a second data interface, the second command interface being configured to receive a second command independent of the first command, the second data interface being configured to transmit second data independent of the first data, the second main DRAM die being configured to form at least a portion of a second memory channel and buffer signals transmitted between the external IC device and other portions of the second memory channel; A third DRAM die stacked with the first main DRAM die and the second main DRAM die, the third DRAM die including a first selectively enabled data input / output (I / O) circuit coupled to the first main DRAM die; and A fourth DRAM die stacked with the first main DRAM die, the second main DRAM die, and the third DRAM die, the fourth DRAM die including a second selectively enabled data input / output (I / O) circuit coupled to the second main DRAM die.

2. The stacked die device of claim 1, wherein for a first operation mode: The third DRAM die is configured such that the first selectively enabled I / O circuit is disabled to define a first responder die, and the fourth DRAM die is configured such that the second selectively enabled I / O circuit is disabled to define a second responder die; Wherein the first main DRAM die and the first responder die cooperate to form a respective first column and second column of the first memory channel, the first memory channel presenting a first data width; and Wherein the second main DRAM die and the second responder die cooperate to form a respective first column and second column of the second memory channel, the second memory channel presenting the first data width.

3. The stacked die device of claim 2, wherein for a second operation mode: The third DRAM die is configured such that the first selectively enabled I / O circuit is enabled to define a first master die, and the fourth DRAM die is configured such that the second selectively enabled I / O circuit is enabled to define a second master die; Wherein the first main DRAM die and the first master die cooperate to form the first memory channel having a second data width greater than the first data width; and Wherein the second main DRAM die and the second master die cooperate to form the second memory channel having the second data width.

4. The stacked die device according to claim 3, wherein each DRAM die among the first main DRAM die, the second main DRAM die, the third DRAM die, and the fourth DRAM die further comprises: register storage means for storing configuration information specifying a main die configuration, a responder die configuration, or a secondary main die configuration.

5. The stacked die device according to claim 1, wherein: each DRAM die among the first main DRAM die, the second main DRAM die, the third DRAM die, and the fourth DRAM die is interconnected by through-silicon vias (TSVs).

6. The stacked die device according to claim 5, wherein the TSVs for each DRAM die among the first main DRAM die, the second main DRAM die, the third DRAM die, and the fourth DRAM die comprise: an external data TSV region directly coupled to an external interface of the DRAM device; an internal data TSV region directly coupled to memory core circuitry for each DRAM die among the first main DRAM die, the second main DRAM die, the third DRAM die, and the fourth DRAM die; and wherein a given data I / O circuit of the first main DRAM die, the second main DRAM die, the third DRAM die, or the fourth DRAM die is disposed between the external data TSV region and the internal data TSV region.

7. The stacked die device according to claim 5, wherein the TSVs for each DRAM die among the first main DRAM die, the second main DRAM die, the third DRAM die, and the fourth DRAM die further comprise: an external command address (CA) region directly coupled to an external interface of the DRAM device; an internal CA TSV region directly coupled to memory core circuitry for each DRAM die among the first main DRAM die, the second main DRAM die, the third DRAM die, and the fourth DRAM die; and wherein a given CA I / O circuit of the first main DRAM die, the second main DRAM die, the third DRAM die, or the fourth DRAM die is disposed between the external CA TSV region and the internal CA TSV region.

8. The stacked die device according to claim 1, wherein: the first main DRAM die and the third DRAM die are interconnected by a first set of wire bonds; and the second main DRAM die and the fourth DRAM die are interconnected by a second set of wire bonds.

9. A stacked die device, comprising: a package substrate; a plurality of stacked dynamic random access memory (DRAM) dies disposed on the package substrate, the plurality of stacked DRAM dies including: At least two main DRAM dies, forming a respective first column of a first memory channel and a respective first column of a second memory channel, each of the at least two main DRAM dies being configured to buffer signals transmitted between an external integrated circuit (IC) device and other portions of the first and second memory channels; A third DRAM die, including a first selectively enabled data input / output (I / O) circuit coupled to a first main DRAM die of the at least two main DRAM dies; and A fourth DRAM die, including a second selectively enabled data input / output (I / O) circuit coupled to a second main DRAM die of the at least two main DRAM dies.

10. The stacked die device according to claim 9, wherein: The third DRAM die is configured such that the first selectively enabled I / O circuit is disabled to define a first responder die forming a second column for the first memory channel, the first memory channel presenting a first data width, and the fourth DRAM die is configured such that the second selectively enabled I / O circuit is disabled to define a second responder die forming a second column for the second memory channel, the second memory channel presenting the first data width.

11. The stacked die device according to claim 9, wherein: The third DRAM die is configured such that the first selectively enabled I / O circuit is enabled to define a first main die, the first memory channel presenting a second data width that is twice the first data width, and the fourth DRAM die is configured such that the second selectively enabled I / O circuit is enabled to define a second main die, the second memory channel presenting the second data width.

12. The stacked die device according to claim 9, wherein each of the at least two main DRAM dies, the third DRAM die, and the fourth DRAM die further comprises: Register storage means for storing configuration information specifying a main die configuration, a responder die configuration, or a sub-main die configuration.

13. The stacked die device according to claim 9, wherein: Each of the at least two main DRAM dies, the third DRAM die, and the fourth DRAM die is interconnected by through-silicon vias (TSVs).

14. The stacked die device according to claim 13, wherein the TSVs for each of the at least two main DRAM dies, the third DRAM die, and the fourth DRAM die comprise: An external data TSV region directly coupled to an external interface of the DRAM device; An internal data TSV region directly coupled to memory core circuitry for each of the at least two main DRAM dies, the third DRAM die, and the fourth DRAM die; and The given data I / O circuit of at least two of the main DRAM dies, the third DRAM die, or the fourth DRAM die is disposed between the external data TSV region and the internal data TSV region.

15. The stacked die device according to claim 13, wherein the TSVs for each of the at least two main DRAM dies, the third DRAM die, and the fourth DRAM die further comprise: An external command address (CA) region directly coupled to the external interface of the DRAM device; An internal CA TSV region directly coupled to the memory core circuitry for each of the at least two main DRAM dies, the third DRAM die, and the fourth DRAM die; and wherein the given CA I / O circuit of the first main DRAM die, the second main DRAM die, the third DRAM die, or the fourth DRAM die is disposed between the external CA TSV region and the internal CA TSV region.

16. The stacked die device according to claim 9, wherein: The first main DRAM die and the third DRAM die among the at least two main DRAM dies are interconnected by a first set of wire bonds; and The second main DRAM die and the fourth DRAM die among the at least two main DRAM dies are interconnected by a second set of wire bonds.

17. A stacked die device, comprising: A plurality of dynamic random access memory (DRAM) dies disposed in a stack; Configuration circuitry for configuring the plurality of DRAM dies to: At least two main DRAM dies forming a respective first column of a first memory channel and a respective first column of a second memory channel, each of the at least two main DRAM dies for buffering signals transmitted between an external integrated circuit (IC) device and other portions of the first memory channel and the second memory channel; A third DRAM die including a first selectively enabled data input / output (I / O) circuit coupled to the first main DRAM die of the at least two main DRAM dies; and A fourth DRAM die including a second selectively enabled data input / output (I / O) circuit coupled to the second main DRAM die of the at least two main DRAM dies.

18. The stacked die device according to claim 17, wherein: The third DRAM die is configured by the configuration circuitry such that the first selectively enabled I / O circuit is disabled to define a first responder die forming a second column of the first memory channel, the first memory channel presenting a first data width, and the fourth DRAM die is configured by the configuration circuitry such that the second selectively enabled I / O circuit is disabled to define a second responder die forming a second column of the second memory channel, the second memory channel presenting the first data width.

19. The stacked die device according to claim 17, wherein: the third DRAM die is configured by the configuration circuit means for the first selectively enabled I / O circuit to be enabled to define a first master die, the first memory channel presenting a second data width that is twice the first data width, and the fourth DRAM die is configured by the configuration circuit means for the second selectively enabled I / O circuit to be enabled to define a second master die, the second memory channel presenting the second data width.

20. The stacked die device according to claim 17, wherein the configuration circuit means further comprises: register storage means for storing configuration information specifying master die configuration, responder die configuration, or sub-master die configuration.

21. The stacked die device according to claim 17, wherein: each DRAM die of the at least two main DRAM dies, the third DRAM die, and the fourth DRAM die is interconnected by through-silicon vias (TSVs).

22. The stacked die device according to claim 17, wherein: the first main DRAM die of the at least two main DRAM dies and the third DRAM die are interconnected by a first set of wire bonds; and the second main DRAM die of the at least two main DRAM dies and the fourth DRAM die are interconnected by a second set of wire bonds.

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