Hydrogen reduction of silicon nitride passivation layers by formation and treatment of passivation sub-layers

Abstract

A method for forming a passivation film having less than 10 atomic% hydrogen on a substrate includes providing the substrate within a processing station of a substrate processing system. A resulting passivation film having less than 10 atomic% of hydrogen is formed on the substrate by performing: depositing a passivation film sub-layer on the substrate, wherein the passivation film sub-layer is located on a semiconductor device layer or directly on a previously deposited passivation film sub-layer; and after depositing the passivation film sub-layer, performing a post plasma treatment on the passivation film sub-layer with at least one of nitrogen and argon to reduce a hydrogen content within the passivation film sub-layer.

Description

Cross - Reference to Related Applications

[0001] This application is a PCT international application and claims the benefit of U.S. Provisional Application No. 63 / 412,717, filed on October 3, 2022. The entire disclosure of the above application is incorporated herein by reference. Technical Field

[0002] This disclosure relates to the formation of a passivation layer, and more particularly, to reducing the hydrogen content in a silicon nitride passivation layer. Background Art

[0003] The background description provided herein is for the purpose of generally presenting the background of the disclosure. The work of the currently named inventors within the scope described in this background art section and aspects of the specification that were not prior art at the time of filing the application are neither expressly nor impliedly admitted to be prior art against the disclosure.

[0004] A substrate processing system can be used to perform etching, deposition, and / or other processing of substrates such as semiconductor wafers. As an example, a substrate can be disposed on an electrostatic chuck (ESC) in the substrate processing system. Multiple device layers can be formed on the substrate. After forming the device layers, a silicon nitride (SiN) passivation layer can be formed on the device layers using a plasma - enhanced chemical vapor deposition (PECVD) process. Summary of the Invention

[0005] Disclosed is a method for forming a passivation film having less than 10 atomic % hydrogen on a substrate. The method includes: providing the substrate in a processing station of a substrate processing system, and forming a resulting passivation film having less than 10 atomic % hydrogen on the substrate by performing the following steps: depositing a passivation film sub - layer on the substrate, where the passivation film sub - layer is on a semiconductor device layer or directly on a previously deposited passivation film sub - layer, and after depositing the passivation film sub - layer, performing a post - plasma treatment on the passivation film sub - layer with at least one of nitrogen and argon to reduce the hydrogen content within the passivation film sub - layer.

[0006] In other features, the method includes: the substrate includes a stack of layers, the stack of layers includes the semiconductor device layer and other semiconductor device layers, the stack includes at least one III - V semiconductor material; and the step of depositing the passivation film sub - layer includes depositing the passivation film sub - layer on the stack of layers.

[0007] In other features, the top layer of the stack of layers includes the at least one III - V semiconductor material. In other features, the post - plasma treatment of the passivation film sub - layer is performed to reduce the hydrogen content within the passivation film sub - layer to less than or equal to 10.0 atomic %.

[0008] Among other features, the post-plasma treatment of the passivation film sublayer is performed to reduce the hydrogen content in the passivation film sublayer to less than 10.0 atomic %. Among other features, the post-plasma treatment of the passivation film sublayer is performed to reduce the hydrogen content in the passivation film sublayer to less than 7.5 atomic %.

[0009] Among other features, the step of depositing the passivation film sublayer includes depositing the passivation film sublayer to have a thickness less than Among other features, the step of depositing the passivation film sublayer includes depositing the passivation film sublayer to have a thickness less than Among other features, the step of depositing the passivation film sublayer includes depositing the passivation film sublayer to have a thickness less than Among other features, the step of depositing the passivation film sublayer includes depositing the passivation film sublayer to have a thickness of

[0010] Among other features, the method further includes introducing at least one of nitrogen and argon for more than 30 seconds. Among other features, the method further includes introducing at least one of nitrogen and argon for less than or equal to 60 seconds. Among other features, the method further includes forming a plurality of passivation film sublayers on the substrate in the processing station.

[0011] Among other features, the method further includes forming a plurality of passivation film sublayers on the substrate in a plurality of processing stations such that each of the plurality of passivation film sublayers is formed in one of the plurality of processing stations and not all of the plurality of passivation film sublayers are formed in the same processing station.

[0012] Among other features, a semiconductor device is disclosed and includes: a bottom layer; a stack of semiconductor device layers disposed on the bottom layer; and a plurality of passivation film sublayers disposed on the stack of semiconductor device layers. The overall hydrogen content level of the plurality of passivation film sublayers is less than or equal to 10.0 atomic %.

[0013] Among other features, the stack of semiconductor device layers includes at least one III-V semiconductor material. Among other features, the top layer of the stack of semiconductor device layers includes at least one III-V semiconductor material.

[0014] Among other features, the plurality of passivation film sublayers are stacked as a single passivation layer. Among other features, the WER of the single passivation layer is Among other features, each of the plurality of passivation film sublayers is an ammonia-free silicon nitride layer. Among other features, the hydrogen content level of each of the plurality of passivation film sublayers is less than or equal to 10.0 atomic %. ​

[0015] Among other features, the hydrogen content level of each of the plurality of passivation film sub-layers is less than 10.0 atomic %. Among other features, each of the plurality of passivation film sub-layers has a hydrogen content level of less than 7.5 atomic %.

[0016] Among other features, the thickness of each of the plurality of passivation film sub-layers is less than Among other features, the thickness of each of the plurality of passivation film sub-layers is less than Among other features, the thickness of each of the plurality of passivation film sub-layers is less than Among other features, the thickness of each of the plurality of passivation film sub-layers is

[0017] A method for passivating a semiconductor device within a substrate processing system is disclosed. The method includes: providing a substrate including the semiconductor device within a processing station of the substrate processing system; and iteratively performing a passivation process to form a passivation film sub-layer on the semiconductor device. The passivation process includes: depositing a current passivation film sub-layer on a semiconductor device layer of the semiconductor device or on one of the previously deposited passivation film sub-layers; and post-plasma treating the current passivation film sub-layer with at least one of nitrogen and argon to reduce the hydrogen content within the current passivation film sub-layer.

[0018] Among other features, the semiconductor device includes a stack of layers, the stack of layers including the semiconductor device layer and other semiconductor device layers. The stack includes at least one III-V semiconductor material. The plurality of passivation film sub-layers are deposited on the stack of layers. Among other features, the top layer of the stack of layers includes at least one III-V semiconductor material.

[0019] Among other features, the plurality of passivation film sub-layers are stacked to provide a single resulting passivation layer. Among other features, the post-plasma treatment of the current passivation film sub-layer is performed to reduce the hydrogen content within the current passivation film sub-layer to less than or equal to 10.0 atomic %.

[0020] Among other features, the post-plasma treatment of the current passivation film sub-layer is performed to reduce the hydrogen content within the current passivation film sub-layer to less than 10.0 atomic %. Among other features, the post-plasma treatment of the current passivation film sub-layer is performed to reduce the hydrogen content within the current passivation film sub-layer to less than 7.5 atomic %.

[0021] Among other features, the current passivation film sub-layer is deposited to have a thickness less than Among other features, the current passivation film sub-layer is deposited to have a thickness less than The thickness. Among other features, the present passivation film sublayer is deposited to have a thickness less than The thickness. Among other features, the present passivation film sublayer is deposited to have a thickness less than The thickness.

[0022] Among other features, the method further includes introducing at least one of nitrogen and argon for more than 30 seconds. Among other features, the method further includes introducing at least one of nitrogen and argon for less than or equal to 60 seconds.

[0023] Among other features, the method further includes forming the plurality of passivation film sublayers in the processing station. Among other features, the method further includes forming the plurality of passivation film sublayers in a plurality of processing stations such that each of the plurality of passivation film sublayers is formed in one of the plurality of processing stations and not all of the plurality of passivation film sublayers are formed in the same processing station.

[0024] Among other features, a semiconductor device is provided and includes: a bottom layer; a stack of semiconductor device layers disposed on the bottom layer; and a plurality of passivation film sublayers disposed on the stack of semiconductor device layers, wherein at least one of the following is satisfied: i) the overall hydrogen content level of the plurality of passivation film sublayers is less than or equal to 10.0 atomic %, and ii) each of the plurality of passivation film sublayers has a hydrogen content of less than or equal to 10.0 atomic %.

[0025] Among other features, the stack of semiconductor device layers includes at least one III-V semiconductor material. Among other features, the top layer of the stack of semiconductor device layers includes at least one III-V semiconductor material.

[0026] Among other features, the plurality of passivation film sublayers are stacked as a single passivation layer. Among other features, the WER of the single passivation layer is Among other features, each of the plurality of passivation film sublayers is an ammonia-free silicon nitride layer.

[0027] Among other features, the hydrogen content level of each of the plurality of passivation film sublayers is less than or equal to 10.0 atomic %. Among other features, the hydrogen content level of each of the plurality of passivation film sublayers is less than 10.0 atomic %. Among other features, each of the plurality of passivation film sublayers has a hydrogen content level of less than 7.5 atomic %.

[0028] Among other features, the thickness of each of the plurality of passivation film sublayers is less than Among other features, the thickness of each of the plurality of passivation film sublayers is less than Among other features, the thickness of each of the plurality of passivation film sublayers is less than Among other features, the thickness of each of the plurality of passivation film sub-layers is

[0029] According to the detailed description, the claims, and the drawings, a further scope of applicability of the present disclosure will become apparent. The detailed description and specific examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present disclosure will be more fully understood from the detailed description and the drawings, in which:

[0031] Figure 1 is a functional block diagram of an example of a substrate processing system for implementing a passivation method according to an embodiment of the present disclosure;

[0032] Figure 2 is according to an embodiment of the present disclosure Figure 1 a top view cross-sectional view of a processing chamber of, which includes a plurality of processing stations for depositing a passivation film sub-layer and performing post-plasma processing;

[0033] Figure 3 is a cross-sectional side view of a layer of a semiconductor device according to the present disclosure, which includes a semiconductor device layer and a resulting passivation layer formed by stacking and processing each of the plurality of passivation film sub-layers;

[0034] Figure 4 depicts a passivation method for forming Figure 3 the resulting passivation layer; and

[0035] Figure 5 is a functional block diagram of an example of another substrate processing system for implementing a passivation method according to an embodiment of the present disclosure.

[0036] In the drawings, reference numerals may be reused to identify similar and / or identical elements. DETAILED DESCRIPTION

[0037] Devices such as radio frequency (RF) power devices, micro light-emitting diodes, wide bandgap power devices, etc. contain nitride materials known as "III-V" semiconductor materials. The III-V semiconductor materials have a wurtzite structure and include gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and corresponding alloys. Compared with traditional silicon- and silicon carbide (SiC)-based devices, III-V semiconductor-based devices have improved optical and electrical properties. Process integration of III-V semiconductor-based devices generally requires deposition of a relatively thin passivation layer that directly contacts the III-V semiconductor-based device. As an example, depending on the purpose of passivation and the device structure, the passivation layer can be 20 - 300 nanometers (nm) thick. An increase in thickness (e.g., exceeding 300 nm) can cause degradation of the device's electrical properties, such as a reduction in breakdown voltage. The purpose of the passivation layer is not only to provide protection against chemical-based degradation, but also to eliminate the possibility of the existence of charge trapping sources by introducing silicon (Si) or nickel (Ni) onto the surface of the III-V semiconductor-based device. This places strict requirements on the processing and physical properties of the passivation film layer, such as requirements for hydrogen content, deposition temperature, reactant species, and conformality. To meet some of these requirements, atomic layer deposition (ALD) can be implemented to form the passivation film layer. However, ALD is a slow process, resulting in reduced yield and increased cost.

[0038] For applications that require a passivation film layer, reducing the molecular hydrogen content of the passivation film layer prevents hydrogen atoms from moving around and having a negative impact on the parts and operation of the semiconductor device, which can lead to semiconductor device failure. Therefore, in specific applications, it is desirable to have a very low hydrogen concentration in the passivation film layer.

[0039] Examples described herein include forming a resulting passivation film layer with a low hydrogen concentration (e.g., less than 10 atomic % hydrogen). Certain processes may be able to reduce the hydrogen atom concentration to 20 atomic %, but consistently forming a passivation film layer with a hydrogen content below 12 atomic % has always been challenging. The atomic % of hydrogen represents the total number of hydrogen (H) atoms in the passivation layer divided by the total number of atoms in the passivation layer. In some examples, an iterative process of forming multiple thin passivation film sub-layers is performed. Then, each thin passivation film sub-layer is post-plasma treated to remove the hydrogen content. In some examples, the passivation film sub-layers are formed using a silicon nitride deposition process without NH 3 and subsequently post-treated with nitrogen and / or argon. The post-treatment with nitrogen and / or argon removes hydrogen from the passivation film sub-layers. Additionally, by forming multiple thin passivation film sub-layers instead of depositing a single thick passivation film, the effectiveness of the post-plasma treatment is increased to further minimize the total hydrogen content.

[0040] Figure 1 shows an exemplary substrate processing system (or tool) 100 that includes a system controller 101 that implements a passivation method to form different passivation film sub-layers and perform post-plasma processing on the passivation film sub-layers, as further described below. The substrate processing system 100 includes a processing chamber 102 having a plurality of processing stations 104 ( Figure 1 shows two processing stations), however, the processing chamber 102 can have four processing stations as Figure 2 shown.

[0041] In one embodiment, each of the processing stations 104 can be used to complete the resulting passivation layer on a corresponding substrate, including depositing a plurality of passivation film sub-layers on the corresponding substrate. Each substrate can include a plurality of semiconductor devices on which the passivation film sub-layers are formed. Post-plasma processing is performed on each passivation film sub-layer. As an example, 20 passivation film sub-layers can be deposited on a substrate within a processing station, and post-plasma processing is performed on each passivation film sub-layer before depositing the next passivation film sub-layer and / or completing the formation of the resulting passivation layer. This is also referred to as a non-sequential operation mode of film formation.

[0042] In another embodiment, each processing station 104 deposits one or more passivation film sub-layers of the resulting passivation layer on each of a plurality of substrates. Each substrate can include a plurality of semiconductor devices on which the passivation film sub-layers are formed. In this exemplary embodiment, each substrate is moved from one processing station to another to form the passivation film sub-layers. In one embodiment, a single passivation film sub-layer is formed in the first processing station and then the corresponding substrate is moved to the next processing station to form the next passivation film sub-layer. This continues until all of the passivation film sub-layers are formed on the substrate. After depositing a passivation film sub-layer and performing post-plasma processing on that passivation film sub-layer, each substrate is moved between adjacent processing stations. This is also referred to as a sequential operation mode of film formation.

[0043] As an example, 20 passivation film sub-layers of the resulting passivation layer can be formed on each of 4 substrates, where for each of the 4 substrates, 5 passivation film sub-layers are formed in each of the four processing stations. Post-plasma processing is performed on each passivation film sub-layer. The post-plasma processing of each passivation film sub-layer is performed in the processing station where that passivation film sub-layer is deposited. The sequential operation mode improves the uniformity of the passivation film sub-layers and the resulting passivation layer between substrates (substrate-to-substrate).

[0044] Each of the processing stations 104 includes a respective substrate support (e.g., substrate support 106), such as an electrostatic chuck, and a showerhead (e.g., showerhead 108). The substrate support includes a respective lift pin actuator assembly (e.g., lift pin actuator assembly 110). The lift pin actuator assembly includes lift pins (e.g., lift pins 112) that are actuated to lift a substrate (e.g., substrate 114) onto and off of the substrate support and the substrate transfer paddle 111.

[0045] Each of the processing stations 104 includes upper and lower electrodes. The showerhead may be implemented as the upper electrode or include the upper electrode. The substrate support may be implemented as the lower electrode or include the lower electrode. The upper and lower electrodes may be implemented as radio frequency (RF) electrodes, bias electrodes, clamping electrodes, and / or heating electrodes. For example, the upper electrode may be implemented as a showerhead that introduces and distributes gas in the processing station. The showerhead may include a stem 116 that includes an end connected to the top surface of the processing chamber 102. The showerhead is typically cylindrical and extends radially outward from the opposite end of the stem 116 at a position spaced from the top surface of the processing chamber. The surface of the showerhead facing the substrate includes holes through which processing gas or purge gas flows. Alternatively, the showerhead may include a conductive plate and may introduce gas in another manner.

[0046] The RF generation system 120 generates and outputs an RF voltage to the upper and lower electrodes. For each of the processing stations, one of the upper and lower electrodes may be DC grounded, AC grounded, or at a floating potential. For example, the RF generation system 120 may be controlled by the system controller 101 and includes one or more RF generators 122 (e.g., capacitive coupled plasma RF power generators, bias power generators, and / or other RF power generators) that generate an RF voltage, and the RF voltage is fed to the upper electrode and / or the lower electrode by one or more matching and distribution networks 124. The system controller 101 sets and adjusts the frequency of the RF signals output from the RF generators 123, 125. The frequency may be adjusted to adjust the power distribution within and across the substrate support. The substrate controller 101 may be connected to and / or include a memory 126 that may store passivation instructions 130 for implementing the passivation methods disclosed herein.

[0047] As an example, a first RF generator 123, a second RF generator 125, a first RF matching network 127, and a second RF matching network 129 are shown. The first RF generator 123 and the first RF matching network 127 may provide an RF voltage or may simply connect the showerhead to a ground reference. The second RF generator 125 and the second RF matching network 129 may be referred to individually or collectively as a power supply and provide RF / bias to the substrate support. In one embodiment, the first RF generator 123 and the first RF matching network 127 provide the power to ionize the gas and drive the plasma. In another embodiment, the second RF generator 125 and the second RF matching network 129 provide the power to ionize the gas and drive the plasma. One of the RF generators 123, 125 may be a high-power RF generator that generates, for example, 6 - 10 kilowatts (kW) or more of power.

[0048] The gas delivery system 131 includes one or more gas sources 132-1, 132-2, …, and 132-N (collectively referred to as gas sources 132), where N is an integer greater than zero. The gas sources 132 supply one or more precursors and their gas mixtures. The gas sources 132 may also supply etch gases, carrier gases, and / or purge gases. During the formation of the passivation film sublayer, silane and nitrogen may be supplied from the gas sources 132 to the processing chamber 102. During the post-plasma treatment of the passivation film sublayer, nitrogen and / or argon may be supplied from the gas sources 132 to the processing chamber 102. Vaporized precursors may also be used. The gas sources 132 are connected to a manifold 140 through valves 134-1, 134-2, …, and 134-N (collectively referred to as valves 134) and mass flow controllers 136-1, 136-2, …, and 136-N (collectively referred to as mass flow controllers 136). The output of the manifold 140 is fed to the processing chamber 102. For example, the output of the manifold 140 is fed to the showerhead.

[0049] Valves 156 and pumps 158 may be used to evacuate reactants from the processing chamber 102. The system controller 101 may control the components of the substrate processing system 100, including controlling the supply of RF power levels, the pressure and flow rate of the supplied gases, RF matching, etc. The system controller 101 controls the states of the valves 156 and pumps 158. A robot 164 may be used to transfer substrates into and out of the processing station 104. For example, the robot 164 may transfer substrates between the substrate support 106 and the load lock 166. The robot 164 may be controlled by the system controller 101. The system controller 101 may control the operation of the load lock 166. Valves, gas, and / or coolant pumps, power supplies, RF generators, etc. may be referred to as actuators.

[0050] The substrate processing system 100 further includes a power supply 170 that can supply power to the system processor 101, the lift pin actuator assembly 110, and the motor 172. The motor 172 rotates the mandrel 174. The power supply 170 can be controlled by the system controller 101. The system controller 101 can control the power supply from the power supply 170 to the motor 172 and / or to the RF generation system 120.

[0051] The lift pin actuator assembly 110 raises and lowers the lift pins 112. The lift pin actuator assembly 110 can include electric and / or pneumatic actuators for adjusting the position of the lift pins 112. The motor 172 rotates the mandrel 174 that is connected to a hub 176. The hub 176 is connected to the hub portion of the substrate transfer paddle 111. The hub portion can be held by the hub 176 using a number of techniques. In one embodiment, the hub portion is clamped in the hub 176 and is thus held by the hub 176. In another embodiment, the hub portion is inserted into the hub 176 and is supported (or held) by the hub 176. The substrate transfer paddle 111 can extend laterally and / or horizontally from the hub 176. The top and / or bottom planar surfaces of the substrate transfer paddle 111 can be parallel to the top and / or bottom planar surfaces of the substrate support 106.

[0052] During operation, the substrate transfer paddle 111 is rotated to position the substrate 114 above the substrate support 106. The lift pins 112 are raised to lift the substrate 114 off the substrate transfer paddle 111, and the substrate transfer paddle 111 is rotated to a retracted position. The lift pins 112 are then lowered to set the substrate 114 on the substrate support 106. Then, one or more processing operations (e.g., etching, deposition, or cleaning operations) are performed on the substrate 114. Subsequently, the lift pins 112 are raised to lift the substrate off the substrate support 106, and the substrate transfer paddle 111 is rotated to be positioned between the substrate support 106 and the substrate 114. Then the lift pins 112 are lowered to place the substrate 114 back on the substrate transfer paddle 111. This process can be repeated and the substrate can be moved from processing station to processing station in this manner. Each processing station can perform a different set of processing operations.

[0053] The lift pin 112 can also be used to transfer and remove the substrate 114 from the processing chamber 102 using the robotic arm of the robot 164. When the lift pin 112 is retracted, the upper end of the lift pin 112 can be positioned flush with or below the upper surface of the substrate support 106. During substrate transfer, removal, and / or conveyance, the lift pin is raised relative to the upper surface of the substrate support 106 to raise the substrate 114 and provide a gap between the substrate 114 and the substrate support 106. The gap between the substrate 114 and the substrate support 106 allows (i) the end effector of the robotic arm to be inserted or removed, and (ii) the substrate transfer paddle to move between the substrate 114 and the substrate support 106.

[0054] Figure 2 The processing chamber 102 including the processing station 104 is shown. The processing station 104 is used to deposit a passivation film sublayer and perform post-plasma processing on the passivation film sublayer. The processing chamber 102 is shown with the substrate transfer paddle 111 in the retracted state, but can be rotated on the substrate support 106 to the deployed state.

[0055] The substrate transfer paddle 111 is held by and extends from the hub 176. In the retracted state, the substrate transfer paddle 111 is set between the processing stations 104. When deployed, the substrate transfer paddle 111 is set at a position between the retracted positions. Rotation of the hub 176 causes the substrate transfer paddle 111 to rotate from the current processing station to the retracted position and then rotate clockwise or counterclockwise from the retracted position to the next processing station.

[0056] As an example, the substrate transfer paddle 111 is shown as including support pins. The support pins on one of the substrate transfer paddles 111 are designated as 210 and 212. The support pins on the other of the substrate transfer paddles 111 can be configured similarly to the support pins 210, 212. The support pin 210 is located radially inside the support pin 212. For each substrate transfer paddle 111, the support pin 210 is located along the substrate transfer paddle between the hub 176 and the support pin 212.

[0057] Figure 3Shows a substrate 300 including a bottom layer 302, a semiconductor device layer 304, and a resulting passivation layer 306. The resulting passivation layer 306 includes a stack of passivation film sub-layers 308, each of which is post-plasma treated. The passivation film sub-layers 308 can be referred to as post-plasma treated passivation layers. The semiconductor device layer 304 can include semiconductor devices, such as one or more micro light-emitting diodes (LEDs), one or more wide-bandgap power devices, one or more memory devices, or other known semiconductor devices. The semiconductor devices 310 are shown as dashed boxes and can each be incorporated into some or all of the semiconductor device layer 304. In some cases, the semiconductor device layer 304 contains multiple semiconductor devices. The semiconductor device layer 304 can include, for example, metal layers, dielectric layers, intermediate coupling layers, P-type, I-type, and / or N-type doped layers, etc. The semiconductor device layer 304 can include III-V semiconductor materials, such as GaN, AlN, InN, and / or other nitride materials and / or corresponding alloys. The semiconductor device layer 304 can include semiconductor devices that require a passivation layer with a low atomic % hydrogen to be formed thereon. The bottom-most passivation film sub-layer 308 can be in contact with one or more of the semiconductor devices 310, or can be separated from the semiconductor devices by one or more other layers.

[0058] Each of the passivation film sub-layers 308 can be formed of SiN and / or ultraviolet (UV) light transparent SiN (UV-SiN). In one embodiment, the passivation film sub-layers 308 are formed without using ammonia (NH 3 ), which is called an NH-free 3 process. In one embodiment, silane (SiH 4 ) and nitrogen are introduced to form each of the passivation film sub-layers 308. This is done to provide an NH-free 3 silicon nitride film sub-layer. As an example, if the passivation film sub-layer 308 is formed by introducing SiH 4 and NH 3 , the resulting passivation film sub-layer can have a hydrogen content of 20 to 30 atomic %. The introduction of NH 3 increases the hydrogen content level of the passivation layer. In some cases, by using an NH-free 3 process, the hydrogen content can be reduced to 11 - 15 atomic %. Each of the passivation film sub-layers 308 has a set thickness and / or a thickness within a set range, Figure 3 and an exemplary thickness T P is shown in Figure 4 . The passivation film sub-layers 308 can have the same thickness or can have different thicknesses. In one embodiment, the passivation film sub-layers 308 have the same thickness. Exemplary thicknesses and ranges for the

[0059] Figure 4 method are disclosed below.Figure 3 Method for forming the resulting passivation layer 306, which can use Figure 1 substrate processing system 100 or Figure 5 substrate processing system 500 to implement. Although the following operations are described for a single processing station operating in a non-sequential operation mode, these operations can be modified for a sequential operation mode. The following operations are mainly described for Figure 1 substrate processing system, but are also applicable to Figure 5 substrate processing system. As an example, the operation can be implemented by system controller 101 executing passivation instruction 130.

[0060] The method can start at 400. At 402, if the substrate (or semiconductor wafer) is not yet in the processing station, the substrate (or semiconductor wafer) can be introduced into the processing station and placed on the substrate support. The substrate can include a bottom layer and one or more semiconductor device layers, such as bottom layer 302 and semiconductor device layer 304, which includes semiconductor device 310.

[0061] At 403, system controller 101 can adjust the temperature in the processing station and / or of the substrate support to adjust the temperature of the substrate to a predetermined range. As an example, the temperature of the substrate can be adjusted to 400 - 450 °C. In one embodiment, the temperature of the substrate is adjusted to 425 °C. Figure 5 Shows an example including temperature controller 514 that can be used to adjust the temperature. Similar temperature control systems can be implemented for each processing station that is an example of Figure 1 the example.

[0062] The following operations 404 and 406 are performed in at least one iteration to form a low hydrogen concentration film. In some embodiments, operations 404 and 406 are iteratively performed until a desired resulting layer thickness is met or until a predetermined number of sub-layers are formed. Each iteration can be referred to as a passivation sub-layer cycle. During each cycle, SiN and / or UV-SiN passivation film sub-layers are formed with a minimum hydrogen content. As an example, more than 20 cycles can be performed to form more than 20 passivation film sub-layers. In one embodiment, 20 - 40 passivation film sub-layers are formed.

[0063] At 404, a deposition step is performed, including SiH 4and nitrogen is introduced into the processing station to deposit a passivation film sub-layer on the top surface of the stack of semiconductor device layers or on the top surface of the last deposited passivation film sub-layer. In some cases, the deposition step is a PECVD process. In some embodiments, the deposition step may utilize a dual radio frequency (RF) process, including providing dual frequencies, such as 13.56 MHz and 400 kHz. Other RF frequencies may be used. The dual frequencies can be used to adjust the passivation layer film stress to a target level. The passivation layer may require a mild compressive stress for better adhesion to the semiconductor device layer. The use of dual frequencies provides a greater processing space to adjust the film stress. However, in some cases, the deposition step may utilize a single radio frequency.

[0064] In some examples, an NH-free 3 silicon nitride PECVD deposition process is used to form the passivation film sub-layer. In one embodiment, operation 404 is performed for 1 - 2 seconds. In another embodiment, the PECVD time is 1 second. In another embodiment, the PECVD time is less than 1 second but greater than 0.5 second. The passivation film sub-layer is thin, for example less than thick. In one embodiment, the thickness of the passivation film sub-layer is less than In another embodiment, the thickness is less than of the thickness. In another embodiment, the thickness is thick. The thickness of the passivation film sub-layer depends in part on the time of the deposition process / step, where a longer deposition time may correspond to a thicker sub-layer. Generally, when the passivation film sub-layer is thinner, subsequent post-plasma treatment can more effectively remove H atoms.

[0065] At 406, the passivation film sub-layer is post-plasma treated using at least one of nitrogen and argon. During the post-plasma treatment, nitrogen and / or argon is introduced into chamber 102. Nitrogen and / or argon can be injected into the processing chamber in the range of 8000 - 13000 standard cubic centimeters per minute (sccm) and the pressure in the processing chamber can be 4 - 8.5 Torr (T). In one embodiment, nitrogen is introduced without introducing argon. In another embodiment, argon is introduced without introducing nitrogen. In yet another embodiment, both nitrogen and argon are introduced. The post-plasma treatment helps to release the hydrogen content in the film sub-layer, thereby reducing the film hydrogen concentration level. The post-plasma treatment reduces hydrogen by breaking silicon-hydrogen (SiH) bonds and releasing hydrogen from the film. In some embodiments, the post-plasma treatment includes exposing the passivation film sub-layer to nitrogen and / or argon. As an example, the exposure can last for 10 - 60 seconds. In one embodiment, the exposure is performed for at least 30 seconds. In another embodiment, the exposure is performed for less than or equal to 60 seconds. In another embodiment, the exposure is performed for less than or equal to 40 seconds. In another embodiment, the exposure time is 60 seconds. When the exposure lasts for 30 - 60 seconds, the effectiveness of the post-plasma treatment in removing hydrogen may be the greatest. After the exposure is performed for 40 seconds, the effectiveness of removing hydrogen may decrease. Effectiveness refers to the amount and rate of hydrogen removal. In some cases, the amount of hydrogen removed in the 40 - 60 second period is lower compared to the hydrogen removal effectiveness in the 10 - 40 second period. In some cases, the effectiveness of hydrogen removal significantly decreases after 60 seconds, such that the benefits of the post-plasma treatment are negligible.

[0066] In one embodiment, the post-plasma treatment is performed for a period of time to reduce the hydrogen atom % to less than 10 atomic %. In another embodiment, the post-plasma treatment is performed for a period of time to reduce the hydrogen atom % to between 7 - 10 atomic %. In another embodiment, the post-plasma treatment is performed for a period of time to reduce the hydrogen atom % to between 7 - 8 atomic %. In another embodiment, the hydrogen atom % is less than 7.5%.

[0067] In one embodiment, no RF power is provided during the post-plasma treatment. In another embodiment, RF power is provided. The post-plasma treatment can be a dual-frequency process and includes supplying RF power at the same or different frequency as the frequency introduced during the deposition process used to form the processed passivation film sub-layer.

[0068] At 408, the system controller decides whether to form another passivation film sub-layer. If so, operations 404 and 406 are performed again, otherwise the method can end at 410.

[0069] By repeating the deposition - plasma treatment cycles - operations 404 and 406, the H content within the resulting passivation layer is reduced. As an example, the H content within the film can be reduced from up to 20 atomic % to less than 8 atomic %, for example 7.3 atomic %. Quantitative analysis of the hydrogen content to determine the atomic % can be accomplished, for example, using hydrogen forward scattering spectroscopy (HFSS). This can be performed after depositing a predetermined number of passivation film sub - layers and / or after forming the resulting passivation layer.

[0070] HFSS is an ion - scattering technique that is used to quantitatively determine the vertical distribution of hydrogen in thin films. During the HFSS process, He 2+ ions impinge on the sample surface at a grazing angle, knocking hydrogen atoms out of the sample, which can then be analyzed using a solid - state detector. The ability to perform measurements of the composition and vertical distribution of the hydrogen content within the thin film is obtained to gain an understanding of the physical and / or electrical properties of the thin film. The higher the hydrogen concentration level, the greater the impact on the physical and / or electrical properties of the film. Other techniques such as Auger electron spectroscopy (AES), energy - dispersive X - ray spectroscopy (EDS), and X - ray photoelectron spectroscopy (XPS) cannot detect hydrogen concentration; while secondary ion mass spectrometry (SIMS) can measure hydrogen, quantifying hydrogen by SIMS can be difficult and requires standards. HFSS provides a non - destructive method for measuring hydrogen content. The entire wafer can be analyzed using HFSS. Conductors and insulators can be analyzed. The depth resolution of HFSS is

[0071] As a comparative example of using HFSS, a SiN passivation layer without NH 3 formed at a temperature of 400 °C using a dual - RF PECVD process without post - plasma treatment can have a hydrogen content of 17 atomic %. A SiN passivation layer without NH 3 formed at a temperature of 425 °C using a dual - RF PECVD process without post - plasma treatment can have a hydrogen content of 11 atomic %. A SiN passivation layer without NH 3 formed at a temperature of 425 °C using a dual - RF PECVD process with post - plasma treatment can have a hydrogen content of 8 atomic %. Prior to using the processes disclosed above, forming a SiN passivation layer with a hydrogen content below 10 atomic % has been a challenge.

[0072] Another technique that can be used to indirectly estimate the hydrogen content is to determine, for example, the wet - etching rate (WER) of the resulting passivation layer. The lower the hydrogen content (or atomic % of hydrogen), the slower the WER. In some embodiments, the resulting passivation layer formed using the above - described processes has a low WER (e.g., using nitrogen in the post - plasma treatment with dual - RF power at 425 °C), for example, at 6.2 - 6.4 angstroms per minute Immerse for 5 m in 100:1 dilute hydrofluoric acid (dHF). There is an inverse relationship between the WER and the duration of post-plasma treatment. When the duration of post-plasma treatment increases from 40 seconds to 60 seconds, the change in WER is minimal. This shows that the benefits of post-plasma treatment for more than 60 seconds are negligible.

[0073] As another comparative example, a SiN passivation layer without NH formed using a dual RF PECVD process without post-plasma treatment 3 may have a WER of 17 angstroms per minute A SiN passivation layer without NH formed using a dual RF PECVD process and a post-plasma treatment without RF power 3 may have A SiN passivation layer without NH formed using a dual RF PECVD process and a dual RF post-plasma treatment including the introduction of argon (Ar) 3 may have A SiN passivation layer without NH formed using a dual RF PECVD process and a dual RF post-plasma treatment including the introduction of nitrogen (N 2 ) 3 may have As the thickness of the passivation film sub-layer decreases, the WER decreases. A low WER indicates a low level of hydrogen content.

[0074] Figure 5 An example substrate processing system 500 is shown, which includes a substrate support 501 shown as an electrostatic chuck. In the example shown, the substrate support 501 includes a body 502. The body 502 may be formed of different materials and / or different ceramic compositions. The body 502 may include, for example, aluminum alloy, aluminum nitride (AlN 3 )), aluminum oxide (Al 2 O 3 )), and / or aluminum oxynitride (AlON).

[0075] The substrate processing system 500 includes a processing chamber 504. A substrate support 501 is enclosed within the processing chamber 504. The processing chamber 504 also encloses other components, such as an upper electrode 505, and contains an RF plasma. During operation, a substrate 507 is configured on the substrate support 501 and electrostatically clamped to the substrate support 501. For example, the upper electrode 505 may include a showerhead 509 for introducing and distributing gas. The showerhead 509 may include a stem 511 that includes an end connected to the top surface of the processing chamber 504. The showerhead 509 is generally cylindrical and extends radially outward from the opposite end of the stem 511 at a position spaced from the top surface of the processing chamber 504. The substrate-facing surface of the showerhead 509 includes holes through which a processing gas or a purge gas flows. Alternatively, the upper electrode 505 may include a conductive plate and may introduce gas in another manner. In one embodiment, the substrate support 501 may include one or more gas channels 512 for flowing backside gas to the backside of the substrate 507.

[0076] The substrate support 501 may include one or more coolant channels 510 that receive coolant from a pump 513. A temperature controller 514 may control the operation of the pump 513 to control the flow rate and temperature of the coolant flowing into and out of the coolant channels 510. The pump 513 may circulate the coolant between a reservoir 515 and the coolant channels 510. Although a single pump 513 is shown, two or more pumps may be included. A valve assembly 517 may be disposed between the pump 513 and the coolant channels 510 and controlled by the temperature controller 514. Supply and return lines may be connected between (i) one or more pumps and the coolant channels 510, and / or (ii) the valve assembly 517 and the coolant channels 510.

[0077] An RF generation system 520 generates and outputs an RF voltage to one or more lower electrodes 519 in the upper electrode 505 and the substrate support 501. One of the upper electrode 505 and the substrate support 501 may be DC grounded, AC grounded, or at a floating potential. For example, the RF generation system 520 may include one or more RF generators 522 (e.g., a capacitively coupled plasma RF power generator, a bias power generator, and / or other RF power generators) that generate an RF voltage, and the RF voltage is fed to the upper electrode 505 and / or the substrate support 501 by one or more matching and distribution networks 524. An electrode that receives an RF signal, an RF voltage, and / or RF power is referred to as an RF electrode. As an example, a plasma RF generator 523, a bias RF generator 525, a plasma RF matching network 527, and a bias RF matching network 529 are shown. The plasma RF generator 523 may be a high-power RF generator that generates, for example, 6 - 10 kilowatts (kW) or more of power. The bias RF matching network supplies power to an RF electrode (e.g., the RF electrode 519).

[0078] The gas delivery system 530 includes one or more gas sources 532-1, 532-2, …, and 532-N (collectively referred to as gas sources 532), where N is an integer greater than zero. The gas sources 532 supply one or more precursors and their gas mixtures. The gas sources 532 can supply silane, nitrogen, and / or argon as described above to form a passivation film sublayer and perform post-plasma treatment thereon. The gas sources 532 can also supply etching gases, carrier gases, and / or purge gases. Vaporized precursors can also be used. The gas sources 532 are connected to the manifold 540 through valves 534-1, 534-2, …, and 534-N (collectively referred to as valves 534), and mass flow controllers 536-1, 536-2, …, and 536-N (collectively referred to as mass flow controllers 536). The output of the manifold 540 is fed to the processing chamber 504. For example, the output of the manifold 540 is fed to the showerhead 509.

[0079] Although shown as separate from the system controller 560, the temperature controller 514 can be implemented as part of the system controller 560. The substrate support 501 can include a plurality of temperature control zones, each of which includes a temperature sensor and a set of microchannels. The temperature controller 514 can monitor the temperature indicated by the temperature sensor and adjust the flow rate and / or temperature of the coolant circulating through one or more sets of microchannels to adjust the temperature to a target temperature.

[0080] The substrate processing system 500 can also include a power supply 544 that provides power including a high voltage to the chucking electrode 531 to electrostatically chuck the substrate 507 to the substrate support 501. The chucking electrode receives power to electrostatically chuck the substrate 507 to the substrate support 501 and can receive an RF signal, RF voltage, and / or RF power. The power supply 544 can be controlled by the system controller 560.

[0081] The substrate processing system 500 can also include a backside vacuum controller 552. The backside vacuum controller 552 can receive gas from the manifold 540 and supply the gas to the channels 512 and / or the pump 558. This improves the heat transfer between the substrate support 501 and the substrate 507. Backside gas can also be provided to improve substrate peripheral edge cleaning and vacuum tracking of the substrate position. The channels 512 can be fed by one or more injection ports. In one embodiment, multiple injection ports are included to improve cooling. As an example, the backside gas can include helium.

[0082] The temperature controller 514 can control the operation of the pump 513 and / or other coolant circulation pumps and / or valve assemblies 517 based on parameters detected by the temperature sensor 543 within the processing chamber 504. The backside vacuum controller 552 controls the flow rate of the backside gas (e.g., helium) flowing into the channel 512 for cooling the substrate 507 by controlling the flow rate from one or more gas sources 532 to the channel 512. The backside vacuum controller 552 controls the pressure and flow rate of the gas supplied to the channel 512 based on the detected parameters from the temperature sensor 543. In one embodiment, the temperature controller 514 and the backside vacuum controller 552 are implemented as a combined single controller.

[0083] The temperature sensor 543 can include a resistance temperature device, a thermocouple, a digital temperature sensor, and / or other suitable temperature sensors. One or more temperature sensors 543 can be disposed in the substrate support 501 and used to detect the temperature of the substrate support 501. During the deposition process, the substrate 507 can be heated in the presence of high-power plasma. The gas flow through the channel 512 can reduce the temperature of the substrate 507.

[0084] The valve 556 and the pump 558 can be used to exhaust reactants from the processing chamber 504. The system controller 560 can control the components of the substrate processing system 500, including controlling the supplied RF power level, the pressure and flow rate of the supplied gas, RF matching, etc. The system controller 560 controls the states of the valve 556 and the pump 558. The system controller 560 can be configured and / or operate similarly to the system controller 101 of Figure 1 and vice versa. The robot 564 can be used to transfer the substrate onto the substrate support 501 and remove the substrate from the substrate support 501. For example, the robot 564 can transfer the substrate between the substrate support 501 and the load lock 566. The robot 564 can be controlled by the system controller 560. The system controller 560 can control the operation of the load lock 566.

[0085] The valves, gas pumps, power supplies, RF generators, etc. mentioned herein can be referred to as actuators. The coolant channels, gas channels, etc. mentioned herein can be referred to as temperature adjustment elements. Other temperature control elements, such as heating elements, can also be included in the substrate support. In the illustrated example, the electrodes 519, 531 are disposed in the uppermost one of the layers of the substrate support 501. The coolant channel 510 is disposed in another or more of the layers.

[0086] The foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. The broad teachings of the disclosure can be implemented in a variety of forms. Thus, while the disclosure includes specific examples, the true scope of the disclosure should not be so limited since other modifications will become apparent upon study of the drawings, the specification, and the appended claims. It should be understood that one or more steps in a method can be performed in a different order (or concurrently) without changing the principles of the disclosure. Further, while each embodiment has been described above as having certain features, any one or more of those features described with respect to any embodiment of the disclosure can be implemented in and / or combined with the features of any other embodiment, even if the combination is not explicitly described. In other words, the described embodiments are not mutually exclusive, and permutations of one or more of the embodiments with each other remain within the scope of the disclosure.

[0087] Various terms are used to describe spatial and functional relationships between elements (e.g., between modules, between circuit elements, between semiconductor layers, etc.), and the various terms include "connected," "engaged," "coupled," "adjacent," "next to," "on top of," "above," "over," "under," and "disposed." Unless a relationship between a first and a second element is explicitly described as "direct" or "directly," when such a relationship is described in the foregoing disclosure, the relationship can be a direct relationship in which no other intervening elements exist between the first and second elements, but can also be an indirect relationship in which one or more intervening elements exist (spatially or functionally) between the first and second elements. As an example, a first layer disposed on a second layer indicates that the first layer is above a portion of the second layer. The first layer can be in direct contact with the second layer or can be separated from the second layer by one or more intervening (or intermediate) layers. As used herein, the phrase "at least one of A, B, and C" should be interpreted to mean a logical (A or B or C) using a non-exclusive logical OR and should not be interpreted to mean "at least one of A, at least one of B, and at least one of C."

[0088] In some implementations, the controller is part of a system, which can be part of the above examples. Such systems can include semiconductor processing equipment, which includes one or more processing tools, one or more chambers, one or more platforms for processing, and / or specific processing components (wafer pedestal, gas flow system, etc.). These systems can be integrated with electronics for controlling their operations before, during, and after the processing of semiconductor wafers or substrates. The electronics can be referred to as a "controller", which can control various components or sub-components of one or more systems. Depending on the processing requirements and / or system type, the controller can be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer in and out of tools and other transfer tools and / or load locks connected or docked to a particular system.

[0089] Broadly speaking, a controller can be defined as electronics that has various integrated circuits, logic, memory, and / or software for receiving instructions, issuing instructions, controlling operations, enabling cleaning operations, enabling endpoint measurements, etc. The integrated circuits can include chips in the form of firmware that stores program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). The program instructions can be instructions sent to the controller in the form of various individual settings (or program files), which define operating parameters for performing a specific process on or for a semiconductor wafer or system. In some embodiments, the operating parameters can be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or die of a wafer.

[0090] In some implementations, the controller can be part of or coupled to a computer that is integrated with, coupled to, otherwise networked to the system, or a combination thereof. For example, the controller can be in the "cloud" or be all or part of a wafer fab host system, which can permit remote access to wafer processing. The computer can implement remote access to the system to monitor the current progress of a manufacturing operation, review the history of past manufacturing operations, review trends or performance criteria for multiple manufacturing operations, change parameters of the current process, set processing steps to follow the current process, or initiate a new process. In some examples, a remote computer (such as a server) can provide a process recipe to the system via a network, which can include a local network or the Internet. The remote computer can include a user interface that enables the input or programming of parameters and / or settings, which are then sent from the remote computer to the system. In some examples, the controller receives instructions in the form of data that specify the parameters for each processing step to be performed during one or more operations. It should be understood that the parameters can be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller can be distributed, for example, by including one or more discrete controllers that are networked together and work towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that communicate with one or more integrated circuits that are remote (such as at the platform level or as part of a remote computer), which are combined to control the process on the chamber.

[0091] Example systems can include, but are not limited to, a plasma etch chamber or module, a deposition chamber or module, a spin rinse chamber or module, a metal plating chamber or module, a cleaning chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, an orbit chamber or module, and any other semiconductor processing system that can be associated with or used for the manufacture and / or preparation of semiconductor wafers.

[0092] As described above, depending on the one or more processing steps to be performed by the tool, the controller can communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the factory, a host computer, another controller, or tools used in the material transport that shuttles the wafer container to and from the tool locations and / or load ports in a semiconductor manufacturing facility.

Claims

1. A method for forming a passivation film having less than 10 atomic % hydrogen on a substrate, the method comprising: providing the substrate in a processing station of a substrate processing system, and forming a resultant passivation film having less than 10 atomic % hydrogen on the substrate by performing the following steps: depositing a passivation film sub-layer on the substrate, wherein the passivation film sub-layer is on a semiconductor device layer or directly on a previously deposited passivation film sub-layer, and after depositing the passivation film sub-layer, performing a post-plasma treatment on the passivation film sub-layer with at least one of nitrogen and argon to reduce the hydrogen content within the passivation film sub-layer.

2. The method according to claim 1, wherein: the substrate comprises a stack of layers, the stack of layers including the semiconductor device layer and other semiconductor device layers, the stack including at least one III-V semiconductor material; and the step of depositing the passivation film sub-layer comprises depositing the passivation film sub-layer on the stack of layers.

3. The method according to claim 2, wherein the top layer of the stack of layers comprises the at least one III-V semiconductor material.

4. The method according to claim 1, wherein the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content within the passivation film sub-layer to less than or equal to 10.0 atomic %.

5. The method according to claim 1, wherein the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content within the passivation film sub-layer to less than 10.0 atomic %.

6. The method according to claim 1, wherein the post-plasma treatment of the passivation film sub-layer is performed to reduce the hydrogen content within the passivation film sub-layer to less than 7.5 atomic %.

7. The method according to claim 1, wherein the step of depositing the passivation film sub-layer comprises depositing the passivation film sub-layer to have a thickness less than .

8. The method according to claim 1, wherein the step of depositing the passivation film sub-layer comprises depositing the passivation film sub-layer to have a thickness less than .

9. The method according to claim 1, wherein the step of depositing the passivation film sub-layer comprises depositing the passivation film sub-layer to have a thickness less than .

10. The method according to claim 1, wherein the step of depositing the passivation film sub-layer comprises depositing the passivation film sub-layer to have a thickness of.

11. The method according to claim 1, further comprising introducing the at least one of nitrogen and argon for more than 30 seconds.

12. The method according to claim 1, further comprising introducing the at least one of nitrogen and argon for less than or equal to 60 seconds.

13. The method according to claim 1, further comprising forming a plurality of passivation film sub-layers on the substrate in the processing station.

14. The method according to claim 1, further comprising forming a plurality of passivation film sub-layers on the substrate in a plurality of processing stations such that each of the plurality of passivation film sub-layers is formed in one of the plurality of processing stations and not all of the plurality of passivation film sub-layers are formed in the same processing station.

15. A semiconductor device, comprising: a bottom layer; a stack of semiconductor device layers disposed on the bottom layer; and a plurality of passivation film sub-layers disposed on the stack of semiconductor device layers, wherein the overall hydrogen content level of the plurality of passivation film sub-layers is less than or equal to 10.0 atomic %.

16. The semiconductor device according to claim 15, wherein the stack of semiconductor device layers comprises at least one III-V semiconductor material.

17. The semiconductor device according to claim 15, wherein a top layer of the stack of semiconductor device layers comprises at least one III-V semiconductor material.

18. The semiconductor device according to claim 15, wherein the plurality of passivation film sub-layers are stacked as a single passivation layer.

19. The semiconductor device according to claim 18, wherein the WER of the single passivation layer is / m.

20. The semiconductor device according to claim 15, wherein each of the plurality of passivation film sub-layers is an ammonia-free silicon nitride layer.

21. The semiconductor device according to claim 15, wherein a hydrogen content level of each of the plurality of passivation film sub-layers is less than or equal to 10.0 atomic %.

22. The semiconductor device according to claim 15, wherein a hydrogen content level of each of the plurality of passivation film sub-layers is less than 10.0 atomic %.

23. The semiconductor device according to claim 15, wherein each of the plurality of passivation film sub-layers has a hydrogen content level of less than 7.5 atomic %.

24. The semiconductor device according to claim 15, wherein the thickness of each of the plurality of passivation film sub-layers is less than 25. The semiconductor device according to claim 15, wherein the thickness of each of the plurality of passivation film sub-layers is less than 26. The semiconductor device according to claim 15, wherein the thickness of each of the plurality of passivation film sub-layers is less than 27. The semiconductor device according to claim 15, wherein the thickness of each of the plurality of passivation film sub-layers is

Images