Etching method and plasma processing apparatus

Abstract

The etching method includes: a step (a) of providing a substrate including a laminated film including a silicon oxide film and a silicon nitride film; (b) etching the silicon nitride film with a first plasma generated from a first processing gas including a hydrofluorocarbon gas while applying a first bias voltage to the substrate support part; and (c) etching the silicon oxide film using a second plasma generated from a second processing gas containing a fluorocarbon gas while applying a second bias voltage, the absolute value of the voltage value of the second bias voltage being greater than the absolute value of the voltage value of the first bias voltage. Each of the first bias voltage and the second bias voltage is a pulse wave in which ON and OFF of a pulse of a DC voltage are periodically repeated, and the ON time of the pulse is 0.5 microsecond or less.

Description

Technical Field

[0001] Exemplary embodiments of the present invention relate to an etching method and a plasma processing apparatus. Background Art

[0002] In the manufacture of electronic devices, in order to form recesses in a film on a substrate, the film is sometimes subjected to plasma etching. Patent Document 1 discloses that in a plasma processing apparatus for plasma etching, an electric bias for attracting ions to the substrate is applied to a substrate holder. In the plasma processing apparatus disclosed in Patent Document 1, as an example of the electric bias, a pulsed voltage continuous pulse wave is disclosed.

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: International Publication No. 2022 / 234643 Summary of the Invention

[0006] Technical Problem to be Solved by the Invention

[0007] The present invention provides a technique capable of suppressing abnormal shapes of recesses formed by etching.

[0008] Means for Solving the Technical Problem

[0009] In one exemplary embodiment, an etching method is provided. The etching method includes: step (a) of providing a substrate including a stacked film including a silicon oxide film and a silicon nitride film; step (b) of etching the silicon nitride film with a first plasma generated from a first processing gas containing a hydrofluorocarbon gas while applying a first bias voltage to a substrate support portion supporting the substrate; and step (c) of etching the silicon oxide film with a second plasma generated from a second processing gas containing a fluorocarbon gas while applying a second bias voltage to the substrate support portion, the absolute value of the voltage value of the second bias voltage being greater than the absolute value of the voltage value of the first bias voltage, the first bias voltage and the second bias voltage each being a pulse wave in which ON and OFF of a DC voltage are periodically repeated, and the ON time of the pulse being 0.5 microseconds or less.

[0010] Advantageous Effects of the Invention

[0011] By adopting one exemplary embodiment of the present invention, abnormal shapes of recesses formed by etching can be suppressed. Brief Description of the Drawings

[0012] Figure 1 is a diagram schematically showing a plasma processing apparatus according to an exemplary embodiment.

[0013] Figure 2 is a diagram schematically showing a plasma processing apparatus of an exemplary embodiment.

[0014] Figure 3 is a flowchart of an etching method of an exemplary embodiment.

[0015] Figure 4 is applicable to Figure 3 a cross-sectional view of a substrate which is an example of the method.

[0016] Figure 5 is a cross-sectional view showing one step of an etching method of an exemplary embodiment.

[0017] Figure 6 is a cross-sectional view showing another step of an etching method of an exemplary embodiment.

[0018] Figure 7 is an example of a timing chart showing the time variations of the source electric power and the bias voltage.

[0019] Figure 8 is to Figure 7 a diagram enlarging a part of the timing chart.

[0020] Figure 9 In (a) of , it is a diagram for explaining an example of the first bias voltage and the potential of the substrate when the ON time exceeds 0.5 microseconds. Figure 9 In (b) of , it is a diagram for explaining an example of the first bias voltage and the potential of the substrate when the ON time is 0.5 microseconds or less.

[0021] Figure 10 is a diagram showing the experimental results of etching using the etching method of an exemplary embodiment. Detailed Embodiments

[0022] Hereinafter, various exemplary embodiments will be described in detail with reference to the accompanying drawings. In addition, in each of the drawings, the same or corresponding parts are denoted by the same reference numerals.

[0023] Figure 1FIG. 0 schematically shows a plasma processing apparatus according to an exemplary embodiment. In one embodiment, the plasma processing system includes a plasma processing apparatus 1 and a control unit 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support portion 11, and a plasma generation portion 12. The plasma processing chamber 10 has a plasma processing space. In addition, the plasma processing chamber 10 has at least one gas supply port for supplying at least one processing gas to the plasma processing space, and at least one gas discharge port for discharging gas from the plasma processing space. The gas supply port is connected to a gas supply portion 20 described later, and the gas discharge port is connected to an exhaust system 40 described later. The substrate support portion 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0024] The plasma generation portion 12 can generate plasma from at least one processing gas supplied into the plasma processing space. The plasma formed in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), ECR plasma (Electron-Cyclotron-Resonance Plasma), helicon wave plasma (HWP), surface wave plasma (SWP), or the like. In addition, various types of plasma generation portions including an AC (Alternating Current) plasma generation portion and a DC (Direct Current) plasma generation portion may be used. In one embodiment, the AC signal (AC electric power) used in the AC plasma generation portion has a frequency in the range of 100 kHz to 10 GHz. Therefore, the AC signal includes an RF (Radio Frequency) signal and a microwave signal. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0025] The control unit 2 can process computer-executable commands for causing the plasma processing apparatus 1 to execute various processes described in the present invention. The control unit 2 can control each element of the plasma processing apparatus 1 to execute various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 is implemented by a computer 2a, for example. The processing unit 2a1 can read a program from the storage unit 2a2 and execute various control actions by executing the read program. The program may be pre-stored in the storage unit 2a2 or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read and executed by the processing unit 2a1 from the storage unit 2a2. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a RAM (Random Access Memory), a ROM (Read Only Memory), an HDD (Hard Disk Drive), an SSD (Solid State Drive), or a combination thereof. The communication interface 2a3 can communicate with the plasma processing apparatus 1 via a communication line such as a LAN (Local Area Network).

[0026] Next, a structural example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1 will be described. Figure 2 FIG. schematically shows a plasma processing apparatus according to an exemplary embodiment.

[0027] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply unit 20, a power supply 30, and an exhaust system 40. In addition, the plasma processing apparatus 1 includes a substrate support unit 11 and a gas introduction unit. The gas introduction unit can introduce at least one processing gas into the plasma processing chamber 10. The gas introduction unit includes a showerhead 13. The substrate support unit 11 is disposed in the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support unit 11. In one embodiment, the showerhead 13 constitutes at least a part of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, the side wall 10a of the plasma processing chamber 10, and the substrate support unit 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support unit 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0028] The substrate support portion 11 includes a main body portion 111 and a ring assembly 112. The main body portion 111 has: a central region 111a for supporting the substrate W; and an annular region 111b for supporting the ring assembly 112. A wafer is an example of the substrate W. The annular region 111b of the main body portion 111 surrounds the central region 111a of the main body portion 111 in a top view. The substrate W is disposed on the central region 111a of the main body portion 111, and the ring assembly 112 is disposed on the annular region 111b of the main body portion 111 so as to surround the substrate W on the central region 111a of the main body portion 111. Therefore, the central region 111a is also referred to as a substrate support surface for supporting the substrate W, and the annular region 111b is also referred to as a ring support surface for supporting the ring assembly 112.

[0029] In one embodiment, the main body portion 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. In addition, other members surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member, may have the annular region 111b. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Additionally, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32 described later may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode can function as a lower electrode. When a bias RF signal and / or a DC signal described later is supplied to the at least one RF / DC electrode, the RF / DC electrode is also referred to as a bias electrode. In addition, the conductive member of the base 1110 and the at least one RF / DC electrode may function as a plurality of lower electrodes. In addition, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support portion 11 includes at least one lower electrode.

[0030] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge ring is formed of a conductive material or an insulating material, and the cover ring is formed of an insulating material.

[0031] In addition, the substrate support portion 11 may include a temperature adjustment module for adjusting at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow path 1110a, or a combination thereof. A heat transfer fluid such as brine or gas may flow in the flow path 1110a. In one embodiment, the flow path 1110a is formed in the base 1110, and one or more heaters are disposed within the ceramic member 1111a of the electrostatic chuck 1111. In addition, the substrate support portion 11 may include a heat transfer gas supply portion for supplying a heat transfer gas to a gap between the back surface of the substrate W and the central region 111a.

[0032] The showerhead 13 is capable of introducing at least one processing gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and a plurality of gas introduction ports 13c. The processing gas supplied to the gas supply port 13a can be introduced into the plasma processing space 10s from the plurality of gas introduction ports 13c through the gas diffusion chamber 13b. In addition, the showerhead 13 includes at least one upper electrode. Further, the gas introduction unit may include, in addition to the showerhead 13, one or more side gas injectors (SGIs) mounted in one or more openings formed in the side wall 10a.

[0033] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is capable of supplying at least one processing gas from the respective corresponding gas source 21 to the showerhead 13 via the respective corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Moreover, the gas supply unit 20 may include at least one flow modulation device for modulating or pulsing the flow rate of at least one processing gas.

[0034] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is capable of supplying at least one RF signal (RF electric power) to at least one lower electrode and / or at least one upper electrode. Thereby, a plasma can be formed from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. In addition, by supplying a bias RF signal to at least one lower electrode, a bias potential can be generated on the substrate W to attract the ion component in the formed plasma to the substrate W.

[0035] In one embodiment, the RF power supply 31 includes a first RF generation unit 31a and a second RF generation unit 31b. The first RF generation unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is capable of generating a source RF signal (source RF electric power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, it may be that the first RF generation unit 31a is capable of generating a plurality of source RF signals having different frequencies. The one or more generated source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0036] The second RF generation unit 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is capable of generating a bias RF signal (bias RF electric power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, it may be that the second RF generation unit 31b is capable of generating a plurality of bias RF signals having different frequencies. The one or more generated bias RF signals are supplied to at least one lower electrode. Further, in various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0037] In addition, the power supply 30 may include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generation unit 32a and a second DC generation unit 32b. In one embodiment, the first DC generation unit 32a is connected to at least one lower electrode and is capable of generating a first DC signal. The generated first DC signal is applied to at least one lower electrode. In one embodiment, the second DC generation unit 32b is connected to at least one upper electrode and is capable of generating a second DC signal. The generated second DC signal is applied to at least one upper electrode.

[0038] In various embodiments, the first DC signal and the second DC signal may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a pulse waveform in the shape of a rectangle, trapezoid, triangle, or a combination thereof. In one embodiment, a waveform generation unit for generating a sequence of voltage pulses from a DC signal is connected between the first DC generation unit 32a and at least one lower electrode. Accordingly, the first DC generation unit 32a and the waveform generation unit constitute a voltage pulse generation unit. In the case where the second DC generation unit 32b and the waveform generation unit constitute a voltage pulse generation unit, the voltage pulse generation unit is connected to at least one upper electrode. The voltage pulses may have a positive polarity or a negative polarity. Further, the sequence of voltage pulses may include one or more positive-polarity voltage pulses and one or more negative-polarity voltage pulses within one cycle. Further, the first DC generation unit 32a and the second DC generation unit 32b may be provided in addition to the RF power supply 31, or the first DC generation unit 32a may be provided in place of the second RF generation unit 31b.

[0039] The exhaust system 40 can be connected to, for example, a gas discharge port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s can be adjusted using the pressure regulating valve. The vacuum pump may include a turbo molecular pump, a dry pump, or a combination thereof.

[0040] Figure 3 It is a flowchart of an etching method of an exemplary embodiment. Figure 3 The illustrated etching method MT (hereinafter referred to as “method MT”) can be executed by the plasma processing apparatus 1 of the above embodiment. The method MT can be applied to the substrate W.

[0041] Figure 4 It is a cross-sectional view of a substrate W which is an example to which the method MT can be applied. Figure 4 The illustrated substrate W can be used for manufacturing semiconductor devices. The semiconductor devices may include, for example, memory devices such as DRAM and 3D-NAND, and logic devices. The substrate W has a silicon-containing film EF. The substrate W may further have a base film UF. The silicon-containing film EF may be provided on the base film UF. The base film UF may include a material different from the material included in the silicon-containing film EF. The base film UF may include silicon.

[0042] The silicon-containing film EF includes a stacked film, and the stacked film includes a silicon oxide film (SiO x )EF2 and a silicon nitride film (SiN x )EF1. x is a positive real number. In Figure 4In the example, a silicon oxide film EF2 is provided on the base film UF. A silicon nitride film EF1 is provided on the silicon oxide film EF2. The thickness of the silicon nitride film EF1 may be the same as that of the silicon oxide film EF2, or may be different from that of the silicon oxide film EF2. In the case of different thicknesses, the thickness of the silicon nitride film EF1 may be thicker than that of the silicon oxide film EF2, or may be thinner than that of the silicon oxide film EF2.

[0043] In Figure 4 the example, the silicon-containing film EF is a bilayer structure of a silicon oxide film EF2 and a silicon nitride film EF1. The silicon-containing film EF may also be, for example, a multilayer film including one or more silicon oxide films and one or more silicon nitride films alternately stacked. The silicon-containing film EF may be, for example, a multilayer film including a plurality of silicon oxide films and a plurality of silicon nitride films alternately stacked.

[0044] The substrate W may further include a mask MF having an opening OP. The opening OP may have a hole pattern or a line pattern. The mask MF may be provided on the silicon-containing film EF. The mask MF may include at least one selected from a carbon-containing film and a metal-containing film. The carbon-containing film may include an amorphous carbon film. The metal-containing film may include at least one metal selected from tungsten (W), titanium (Ti), and ruthenium (Ru).

[0045] Hereinafter, taking the case where the method MT is applied to the substrate W using the plasma processing apparatus 1 of the above-described embodiment as an example, reference is made to Figures 3 to 8 to describe the method MT. Figure 5 and Figure 6 are cross-sectional views of one process of an etching method showing one exemplary embodiment, respectively. In the case of using the plasma processing apparatus 1, by controlling each part of the plasma processing apparatus 1 by the control unit 2, the method MT can be executed in the plasma processing apparatus 1. In the method MT, as Figure 2 shown, the substrate W disposed on the substrate support portion 11 in the plasma processing chamber 10 is processed.

[0046] As Figure 3 shown, the method MT may include a process ST1, a process ST2, and a process ST3. The processes ST1, ST2, and ST3 may be executed in sequence. It is also possible to repeat the processes ST2 and ST3 after the process ST3.

[0047] (Process ST1)

[0048] In the process ST1, the Figure 4 shown substrate W is provided. The substrate W can be supported by the substrate support portion 11 in the plasma processing chamber 10.

[0049] (Process ST2)

[0050] In process ST2, a first plasma PM1 is generated from a first process gas, and the silicon nitride film EF1 is etched using the first plasma PM1. As Figure 5 shown, in the silicon nitride film EF1, a recess RE1 is formed by etching. The recess RE1 corresponds to the opening OP. At the bottom BT1 of the recess RE1, the upper surface of the silicon oxide film EF2 may be exposed. That is, the etching of the silicon nitride film EF1 can be carried out until the bottom BT1 of the recess RE1 reaches the silicon oxide film EF2.

[0051] The first process gas contains a hydrofluorocarbon gas (C x H y F z gas). x, y, and z are each natural numbers. The hydrofluorocarbon gas can be selected from CHF 3 gas, CH 2 F 2 gas, CH 3 F gas, C 2 HF 5 gas, C 2 H 2 F 4 gas, C 2 H 3 F 3 gas, C 2 H 4 F 2 gas, C 3 HF 7 gas, C 3 H 2 F 2 gas, C 3 H 2 F 4 gas, C 3 H 2 F 6 gas, C 3 H 3 F 5 gas, C 4 H 2 F 6 gas, C 4 H 5 F 5 gas, C 4 H 2 F 8 gas, C 5 H 2 F 6 gas, C 5 H 2 F 10 gas and C 5 H 3 F7 At least one in the gas. The first processing gas may further contain a fluorocarbon gas (C x F y gas). x and y are each natural numbers. The fluorocarbon gas may be selected from C 4 F 6 gas and C 4 F 8 gas. The first processing gas may further contain nitrogen trifluoride gas (NF 3 gas). The first processing gas may further contain oxygen (O 2 gas).

[0052] In step ST2, the temperature of the substrate support portion 11 that supports the substrate W can be, for example, 50°C. The temperature of the substrate support portion 11 can be set to 100°C or lower, can also be set to 80°C or lower, and can further be set to 60°C or lower.

[0053] In step ST2, the pressure inside the plasma processing chamber 10 can be, for example, 10 mTorr (1.3 Pa). The pressure inside the plasma processing chamber 10 can be set to 50 mTorr (6.5 Pa) or lower, and can also be set to 30 mTorr (3.9 Pa) or lower.

[0054] (Step ST3)

[0055] In step ST3, a second plasma PM2 is generated from the second processing gas, and the silicon oxide film EF2 is etched using the second plasma PM2. As Figure 6 shown, in the silicon oxide film EF2, a recess RE2 is formed by etching. The recess RE2 corresponds to the recess RE1. The recess RE2 can be formed continuously from the recess RE1. At the bottom BT2 of the recess RE2, the upper surface of the base film UF can be exposed. That is, the etching of the silicon oxide film EF2 can be carried out until the bottom BT2 of the recess RE2 reaches the base film UF.

[0056] The second processing gas contains a fluorocarbon gas (C x F y gas). The fluorocarbon gas may be selected from C 2 F 2 gas, C 2 F 4 gas, C 3 F 6 gas, C 3 F 8 gas, C 4 F 6 gas, C 4 F 8 gas and C 5 F8 At least one of the gases. The second processing gas may further contain a hydrofluorocarbon gas (C x H y F z gas). Examples of the C x H y F z gas contained in the second processing gas may be the same as the examples of the C x H y F z gas contained in the first processing gas. The second processing gas may further contain nitrogen trifluoride gas. The second processing gas may further contain oxygen.

[0057] In step ST3, the temperature of the substrate support portion 11 that supports the substrate W can be, for example, 70°C. The temperature of the substrate support portion 11 can be set to 100°C or lower, or can be set to 80°C or lower.

[0058] In step ST3, the pressure inside the plasma processing chamber 10 can be, for example, 10 mTorr (1.3 Pa). The pressure inside the plasma processing chamber 10 can be set to 50 mTorr (6.5 Pa) or lower, or can be set to 30 mTorr (3.9 Pa) or lower.

[0059] Next, referring to Figure 7 and Figure 8 , the source RF electric power (hereinafter also referred to as source power) and the bias voltage supplied to the plasma processing apparatus 1 in steps ST2 and ST3 will be described. The source electric power can be generated by the first RF generation unit 31a and supplied to at least one lower electrode and / or at least one upper electrode. The bias voltage can be generated by the voltage pulse generation unit and supplied to the substrate support portion 11. Figure 7 is an example of a timing chart showing the time variation of the source electric power WS and the bias voltage VB. Figure 7 The horizontal axis of Figure 7 represents time. Figure 7 The vertical axis of

[0060] The source electric power WS includes a first source electric power WS1 supplied in process ST2 and a second source electric power WS2 supplied in process ST3. The first source electric power WS1 may include a first power level PL1 and a second power level PL2 lower than the first power level PL1. The first power level PL1 and the second power level PL2 may be periodically repeated. The second power level PL2 may be a state where the first source electric power WS1 is OFF (0 W). It may be that during the period when the first source electric power WS1 is at the first power level PL1, the first source electric power WS1 promotes the generation of the first plasma PM1. During the period when the first source electric power WS1 is at the second power level PL2, the generation of the first plasma PM1 may be stopped, or a plasma with a plasma density lower than that of the first plasma PM1 may be generated.

[0061] The second source electric power WS2 may include a third power level PL3 and a fourth power level PL4 lower than the third power level PL3. The third power level PL3 and the fourth power level PL4 may be periodically repeated. The third power level PL3 may be higher than the first power level PL1. The fourth power level PL4 may be a state where the second source electric power WS2 is OFF (0 W). The fourth power level PL4 may be the same as or different from the second power level PL2. In Figure 7 the example of, the fourth power level PL4 is the same as the second power level PL2. It may be that during the period when the second source electric power WS2 is at the third power level PL3, the second source electric power WS2 promotes the generation of the second plasma PM2. During the period when the second source electric power WS2 is at the fourth power level PL4, the generation of the second plasma PM2 may be stopped, or a plasma with a plasma density lower than that of the second plasma PM2 may be generated.

[0062] The bias voltage VB includes: a first bias voltage VB1 applied to the substrate support portion 11 in process ST2; and a second bias voltage VB2 applied to the substrate support portion 11 in process ST3. In process ST2, a first time period T1 and a second time period T2 following the first time period T1 are periodically repeated. In the first time period T1, the first bias voltage VB1 is applied. The first bias voltage VB1 may also be a negative voltage. It may be that by applying the first bias voltage VB1, the ions contained in the first plasma PM1 are attracted to the bottom BT1 of the recess RE1 formed in the silicon nitride film EF1, and the etching of the silicon nitride film EF1 proceeds. On the other hand, in the second time period T2, the first bias voltage VB1 is not applied. Thus, in the second time period T2, the etching of the silicon nitride film EF1 can be suppressed.

[0063] In process ST3, the third time period T3 and the fourth time period T4 following the third time period T3 are repeatedly performed cyclically. In the present embodiment, the third time period T3 follows the second time period T2 in process ST2. In the third time period T3, a second bias voltage VB2 is applied. The second bias voltage VB2 can also be a negative voltage. It can be that by applying the second bias voltage VB2, the ions contained in the second plasma PM2 are attracted to the bottom BT2 of the recess RE2 formed in the silicon oxide film EF2, and the etching of the silicon oxide film EF2 proceeds. On the other hand, in the fourth time period T4, the second bias voltage VB2 is not applied. Thus, in the fourth time period T4, the etching of the silicon oxide film EF2 can be suppressed.

[0064] As Figure 7 shown, in process ST2, it can be that in the first time period T1, the first source power WS1 has a first power level PL1. That is, it can be that the time period in which the first source power WS1 has the first power level PL1 is synchronized with the time period in which the first bias voltage VB1 is applied, in the first time period T1. In this case, in the first time period T1, the generation of the first plasma PM1 can be promoted, and thus, the etching of the silicon nitride film EF1 can be promoted. In process ST2, it can be that in the second time period T2, the first source power WS1 has a second power level PL2. That is, it can be that the time period in which the first source power WS1 has the second power level PL2 is synchronized with the time period in which the first bias voltage VB1 is not applied, in the second time period T2. In this case, in the second time period T2, the generation of the second plasma PM2 can be stopped, or the plasma density can be reduced, and thus, the etching of the silicon nitride film EF1 can be suppressed.

[0065] As Figure 7 shown, in process ST3, it can be that in the third time period T3, the second source power WS2 has a third power level PL3. That is, it can be that the time period in which the second source power WS2 has the third power level PL3 is synchronized with the time period in which the second bias voltage VB2 is applied, in the third time period T3. In this case, in the third time period T3, the generation of the second plasma PM2 can be promoted, and thus, the etching of the silicon oxide film EF2 can be promoted. In process ST2, it can be that in the fourth time period T4, the second source power WS2 has a fourth power level PL4. That is, it can be that the time period in which the second source power WS2 has the fourth power level PL4 is synchronized with the time period in which the second bias voltage VB2 is not applied, in the fourth time period T4. In this case, in the fourth time period T4, the generation of the second plasma PM2 can be stopped, or the plasma density can be reduced, and thus, the etching of the silicon oxide film EF2 can be suppressed.

[0066] Next, referring to Figure 8A more detailed description of the first bias voltage VB1 and the second bias voltage VB2 is given. Figure 8 is a diagram that magnifies a part of the timing diagram of Figure 7 . Figure 8 The horizontal axis of represents time. Figure 8 The vertical axis of represents voltage values. The first bias voltage VB1 is a pulse wave in which the ON and OFF of the pulse PS1 of a DC voltage are periodically repeated. In the present embodiment, since the first bias voltage VB1 is a negative voltage, the voltage value of the pulse PS1 becomes a negative first DC voltage value (-V1) at the ON time T ON 1 and becomes a voltage value of 0 V at the OFF time T OF 1. The second bias voltage VB2 is a pulse wave in which the ON and OFF of the pulse PS2 of a DC voltage are periodically repeated. In the present embodiment, since the second bias voltage VB2 is a negative voltage, the voltage value of the pulse PS2 becomes a negative second DC voltage value (-V2) at the ON time T ON 2 and becomes a voltage value of 0 V at the OFF time T OF 2.

[0067] The absolute value V2 of the second DC voltage value (-V2) as the voltage value of the second bias voltage VB2 is greater than the absolute value V1 of the first DC voltage value (-V1) as the voltage value of the first bias voltage VB1. The absolute value V1 of the first DC voltage value (-V1) can be 1 kV or more and 5 kV or less. The absolute value V2 of the second DC voltage value (-V2) can be 5 kV or more and 20 kV or less.

[0068] It can be that the frequency FR2 of the period CY2 of the pulse PS2 that defines the second bias voltage VB2 is higher than the frequency FR1 of the period CY1 of the pulse PS1 that defines the first bias voltage VB1. Alternatively, it can be that the frequency FR2 of the period CY2 of the pulse PS2 that defines the second bias voltage VB2 is equal to or higher than the frequency FR1 of the period CY1 of the pulse PS1 that defines the first bias voltage VB1. Here, the period CY1 is the total period of the ON time T ON 1 and the OFF time T OF 1. Similarly, CY2 is the total period of the ON time T ON 2 and the OFF time T OF 2. The frequency FR1 can be 200 kHz or more and 400 kHz or less, or can be 300 kHz or more and 500 kHz or less. The frequency FR2 can be 200 kHz or more and 500 kHz or less, or can be 300 kHz or more and 600 kHz or less.

[0069] The ON time T of the pulse PS1 of the first bias voltage VB1 ON1 can be the same as the ON time T of the pulse PS2 of the second bias voltage VB2. ON 2. The ON time T ON 1 and the ON time T ON 2 can each be 0.5 microseconds (μs) or less, can also be 0.4 microseconds or less, and can be 0.2 microseconds or more. As described above, when the frequency FR2 is higher than the frequency FR1, the ON time T ON 1 is the same as the ON time T ON 2, so that the OFF time T of the pulse PS1 OF 1 is longer than the OFF time T of the pulse PS2 OF 2.

[0070] The duty ratio of each of the first bias voltage VB1 and the second bias voltage VB2 can be 5% or more, can also be 10% or more, can be 25% or less, and can also be 20% or less. Here, the duty ratio under the first bias voltage VB1 is the value obtained by expressing the ratio of the ON time T ON 1 to the period CY1 as a percentage. The duty ratio under the second bias voltage VB2 is the value obtained by expressing the ratio of the ON time T ON 2 to the period CY2 as a percentage.

[0071] The ON time T ON 1 starts simultaneously with the moment when the power supply 30 of the plasma processing apparatus 1 starts outputting the first bias voltage VB1, and ends simultaneously with the moment when the power supply 30 stops outputting the first bias voltage VB1. Due to the impedance of the wiring path from the voltage pulse generation unit to the substrate support unit 11, etc., it may be that after a time has elapsed since the start of the ON time T ON 1, the first bias voltage VB1 supplied to the substrate support unit 11 reaches the peak voltage value. Similarly, the ON time T ON 2 starts simultaneously with the moment when the power supply 30 of the plasma processing apparatus 1 starts outputting the second bias voltage VB2, and ends simultaneously with the moment when the power supply 30 stops outputting the second bias voltage VB2. Due to the impedance of the wiring path from the voltage pulse generation unit to the substrate support unit 11, etc., it may be that after a time has elapsed since the start of the ON time T ON 2, the second bias voltage VB2 supplied to the substrate support unit 11 reaches the peak voltage value.

[0072] Next, with reference to Figure 9 and Figure 10 the effects of the short time when the ON time T ON 1 and the ON time T ON 2 are 0.5 microseconds or less will be described. In addition, the effects described here are merely examples and are not limited thereto. Figure 9 (a) of is for the ON time T ONFigure for explaining an example of the first bias voltage VB1 and the potential WV1 of the substrate W when it exceeds 0.5 microseconds. Figure 9 (b) is for the ON time T ON Figure for explaining an example of the first bias voltage VB1 and the potential WV2 of the substrate W when T1 is 0.5 microseconds or less. In addition, in Figure 9 T1 of the first bias voltage VB1 is taken as an example for explanation, but ON the explanation Figure 9 also applies to the ON time T ON 2 of the second bias voltage VB2.

[0073] As Figure 9 shown, in the ON time T ON 1, after the potential WV1 and the potential WV2 reach the first DC voltage value (-V1), they gradually change to 0V. Specifically, the potentials WV1 and WV2 of the substrate W change in the direction of decreasing the absolute values of the potentials WV1 and WV2 of the substrate W. When the first bias voltage VB1 switches from the ON time T ON 1 to the OFF time T OF 1, the potentials WV1 and WV2 of the substrate W change sharply to 0V. Compared with the change amount ΔV of the potential WV1 shown in Figure 9 (a), Figure 9 the change amount ΔV of the potential WV2 shown in (b) is smaller. The change amount ΔV of the potential WV1 is, for example, within 10% of the absolute value of the first DC voltage value (-V1). The change amount ΔV of the potential WV2 is, for example, within 5% of the absolute value of the first DC voltage value (-V1). The smaller the change amount ΔV, the easier it is to maintain the absolute value of the potential of the substrate W at a large value. As a result, it is easy to attract the ions contained in the first plasma PM1 to the bottom BT1 of the recess RE1 formed in the silicon nitride film EF1 by etching. As a result, the reduction of the pattern width at the bottom BT1 of the recess RE1 can be suppressed. Similarly, the reduction of the pattern width at the bottom BT2 of the recess RE2 formed in the silicon oxide film EF2 by etching can be suppressed.

[0074] As Figure 9 (b) shows, in the potential WV2 of the substrate W, the period T5, which is a period with a large change amount starting from the first DC voltage value (-V1), is removed. In the period T5, since the absolute value of the potential is less than the absolute value of the first DC voltage value (-V1), the ions contained in the first plasma PM1 are difficult to reach the bottom BT1, and the ions are likely to collide with the upper part of the recess RE1. In the ON time T ONWhen T1 is 0.5 microseconds or less, it is easy to suppress the collision of such ions with the upper part, and thus it is easy to suppress the expansion of the pattern width of the upper part of the recess RE1. As described above, in the ON time T ON When T1 is 0.5 microseconds or less, it is possible to suppress the reduction of the pattern width of the bottom BT1 of the recess RE1, and on the other hand, it is possible to suppress the expansion of the pattern width of the upper part of the recess RE1. Thus, the shape abnormality of the recess RE1 can be suppressed. Similarly, the shape abnormality of the recess RE2 can be suppressed.

[0075] It can be as Figure 8 shown, the frequency FR2 of the period CY2 of the pulse PS2 that defines the second bias voltage VB2 is higher than the frequency FR1 of the period CY1 of the pulse PS1 that defines the first bias voltage VB1. Moreover, the ON time T ON 1 of the pulse PS1 of the first bias voltage VB1 can be the same as the ON time T ON 2 of the pulse PS2 of the second bias voltage VB2. In this case, the OFF time T OF 1 of the pulse PS1 of the first bias voltage VB1 is longer than the OFF time T OF 2 of the pulse PS2 of the second bias voltage VB2. During the OFF times T OF 1, T OF 2 of the pulses PS1, PS2, it is possible to suppress the attraction of ions to the silicon oxide film EF2 or the silicon nitride film EF1, and there is a tendency for deposits to easily adhere to the side walls of the recesses RE1, RE2. Therefore, when the OFF time T OF 1 is longer than the OFF time T OF 2, in the etching of the silicon nitride film EF1, it is easier to protect the side walls than in the etching of the silicon oxide film EF2.

[0076] Above, various exemplary embodiments have been described, but it is not limited to the above exemplary embodiments, and various additions, omissions, substitutions, and changes can be made. In the silicon-containing film EF, a silicon nitride film EF1 can be provided on the base film UF, and a silicon oxide film EF2 can be provided on the silicon nitride film EF1. In the method MT, it can also be that the process ST3 is performed before the process ST2. In this case, it can be that after the process ST1, in the process ST3, the third period T3 and the fourth period T4 following the third period T3 are periodically repeated. After that, it can be that in the process ST2, the first period T1 follows the last fourth period T4 in the process ST3. In the process ST2, the first period T1 and the second period T2 following the first period T1 can be periodically repeated.

[0077] Next, the experiments conducted for the evaluation of the method MT will be described. The experiments described below do not limit the present invention.

[0078] Figure 10 It is a diagram showing the experimental results of etching using an etching method of an exemplary embodiment. In the experiment, a substrate was prepared, which included a silicon oxide film as the film to be etched and a mask on the silicon oxide film. The mask had openings with a hole pattern. After the substrate was introduced into the plasma processing chamber, while applying a bias voltage to the substrate support portion, the film to be etched was etched using the plasma generated from a processing gas containing a fluorocarbon gas. The bias voltage was a pulse wave in which the ON and OFF of the DC voltage pulse were periodically repeated. The voltage value of the bias voltage was 7 kV. The frequency defining the period of the bias voltage pulse was 400 kHz or 500 kHz. At each frequency, the ON time of the bias voltage pulse was varied between 0.4 μs and 0.6 μs. After etching, in the cross-section of the substrate, the pattern width (CD: Critical Dimension) at the bottom of the recess formed in the silicon oxide film was measured. In addition, the pattern width at the upper part of the recess (the pattern width of the recess at the interface between the silicon oxide film and the mask) was also measured.

[0079] As Figure 10 shown, at a frequency of 500 kHz, the pattern width at the bottom when the ON time of the pulse was 0.5 μs was approximately 2.1% wider than the pattern width at the bottom when the ON time of the pulse was 0.6 μs. At a frequency of 500 kHz, the pattern width at the bottom when the ON time of the pulse was 0.4 μs was approximately 2.5% wider than the pattern width at the bottom when the ON time of the pulse was 0.5 μs. At a frequency of 400 kHz, the pattern width at the bottom when the ON time of the pulse was 0.5 μs was approximately 2.1% wider than the pattern width at the bottom when the ON time of the pulse was 0.6 μs. The pattern width at the bottom when the ON time of the pulse was 0.4 μs was approximately 1.5% wider than the pattern width at the bottom when the ON time of the pulse was 0.5 μs. From the above results, it can be seen that when the ON time of the bias voltage pulse becomes smaller, the pattern width at the bottom of the recess formed in the silicon oxide film becomes wider. In addition, at all frequencies and ON times, the pattern width at the upper part of the recess was approximately 25.5 nm. Therefore, it can be seen that even when the ON time of the bias voltage pulse becomes smaller, an increase in the pattern width at the upper part of the recess can be suppressed.

[0080] Here, various exemplary embodiments included in the present invention are described in the following [E1] to [E11].

[0081] [E1]

[0082] An etching method, characterized by comprising:

[0083] Step (a): Provide a substrate including a stacked film having a silicon oxide film and a silicon nitride film.

[0084] Step (b): While applying a first bias voltage to a substrate support portion supporting the substrate, etch the silicon nitride film using a first plasma generated from a first processing gas containing a hydrofluorocarbon gas; and

[0085] Step (c): While applying a second bias voltage to the substrate support portion, etch the silicon oxide film using a second plasma generated from a second processing gas containing a fluorocarbon gas, the absolute value of the voltage value of the second bias voltage being greater than the absolute value of the voltage value of the first bias voltage,

[0086] The first bias voltage and the second bias voltage are each a pulse wave in which ON and OFF of a direct current voltage pulse are periodically repeated, and the ON time of the pulse is 0.5 microseconds or less.

[0087] [E2]

[0088] The etching method according to [E1], characterized in that the duty ratio of each of the first bias voltage and the second bias voltage is 20% or less.

[0089] [E3]

[0090] The etching method according to [E1] or [E2], characterized in that the duty ratio of each of the first bias voltage and the second bias voltage is 5% or more.

[0091] [E4]

[0092] The etching method according to any one of [E1] to [E3], characterized in that the frequency of the period of the pulse defining the second bias voltage is equal to or higher than the frequency of the period of the pulse defining the first bias voltage.

[0093] [E5]

[0094] The etching method according to any one of [E1] to [E3], characterized in that the frequency of the period of the pulse defining the second bias voltage is higher than the frequency of the period of the pulse defining the first bias voltage.

[0095] [E6]

[0096] The etching method according to [E5], characterized in that the ON time of the pulse of the first bias voltage is the same as the ON time of the pulse of the second bias voltage.

[0097] [E7]

[0098] The etching method according to any one of [E1] to [E6], characterized in that:

[0099] The frequency of the period of the pulse that defines the first bias voltage is 200 kHz or more and 400 kHz or less,

[0100] The frequency of the period of the pulse that defines the second bias voltage is 200 kHz or more and 500 kHz or less.

[0101] [E8]

[0102] The etching method according to any one of [E1] to [E7], characterized in that:

[0103] The absolute value of the voltage value of the first bias voltage is 1 kV or more and 5 kV or less,

[0104] The absolute value of the voltage value of the second bias voltage is 5 kV or more and 20 kV or less.

[0105] [E9]

[0106] The etching method according to any one of [E1] to [E8], characterized in that:

[0107] In the step (b), a first period and a second period following the first period are periodically repeated. The first bias voltage is applied in the first period, and the first bias voltage is not applied to the substrate support portion in the second period.

[0108] In the step (c), a third period and a fourth period following the third period are repeated. The second bias voltage is applied in the third period, and the second bias voltage is not applied to the substrate support portion in the fourth period.

[0109] [E10]

[0110] The etching method according to [E9], characterized in that:

[0111] In the step (b), a first source RF electric power for generating the first plasma is supplied.

[0112] The first source RF electric power has a first power level and a second power level lower than the first power level, and the first power level and the second power level are periodically repeated.

[0113] The period when the first source RF electric power is at the first power level is synchronized with the first period when the first bias voltage is applied.

[0114] In the process (c), a second source RF electric power for generating the second plasma is supplied.

[0115] The second source RF electric power has a third power level and a fourth power level lower than the third power level, and the third power level and the fourth power level are periodically repeated.

[0116] The period during which the second source RF electric power is at the third power level is synchronized with the third period during which the second bias voltage is applied.

[0117] [E11]

[0118] A plasma processing apparatus, comprising:

[0119] A chamber;

[0120] A substrate support unit for supporting a substrate in the chamber, the substrate including a stacked film, the stacked film including a silicon oxide film and a silicon nitride film;

[0121] A gas supply unit capable of supplying a first processing gas containing a hydrofluorocarbon gas and a second processing gas containing a fluorocarbon gas into the chamber;

[0122] A plasma generation unit capable of generating a first plasma from the first processing gas and generating a second plasma from the second processing gas; and

[0123] A control unit

[0124] The control unit can control the gas supply unit and the plasma generation unit such that: while applying a first bias voltage to the substrate support unit, etching the silicon nitride film with the first plasma; while applying a second bias voltage to the substrate support unit, etching the silicon oxide film with the second plasma.

[0125] The absolute value of the voltage value of the second bias voltage is greater than the absolute value of the voltage value of the first bias voltage.

[0126] Each of the first bias voltage and the second bias voltage is a pulse wave in which ON and OFF of the pulse are periodically repeated.

[0127] The ON time of the pulse is 0.5 microseconds or less.

[0128] Description of reference numerals

[0129] 1… Plasma processing apparatus, 10… Plasma processing chamber, 11… Substrate support portion, 12… Plasma generation portion, 2… Control portion, 20… Gas supply portion, EF1… Silicon nitride film, EF2… Silicon oxide film, PS1… Pulse of first bias voltage, PS2… Pulse of second bias voltage, PM1… First plasma, PM2… Second plasma, T ON 1… ON time of pulse of first bias voltage, T ON 2… ON time of pulse of second bias voltage, VB1… First bias voltage, VB2… Second bias voltage, W… Substrate.

Claims

1. An etching method, characterized in that: include: Step (a), providing a substrate, wherein the substrate includes a stacked film, and the stacked film includes a silicon oxide film and a silicon nitride film; Step (b), etching the silicon nitride film using a first plasma generated from a first processing gas containing a hydrofluorocarbon gas while applying a first bias voltage to a substrate support portion supporting the substrate; and step (c), etching the silicon oxide film using a second plasma generated from a second processing gas containing a fluorocarbon gas while applying a second bias voltage to the substrate support portion, wherein an absolute value of a voltage value of the second bias voltage is greater than an absolute value of a voltage value of the first bias voltage, Each of the first bias voltage and the second bias voltage is a pulse wave in which ON and OFF of a pulse of a DC voltage are periodically repeated, and the ON time of the pulse is 0.5 microseconds or less.

2. The etching method according to claim 1, characterized in that: The first bias voltage and the second bias voltage each have a duty ratio of 20% or less.

3. The etching method according to claim 1 or 2, characterized in that: The first bias voltage and the second bias voltage each have a duty ratio of 5% or more.

4. The etching method according to claim 1 or 2, characterized in that: A frequency defining a cycle of the pulse of the second bias voltage is equal to or higher than a frequency defining a cycle of the pulse of the first bias voltage.

5. The etching method according to claim 1 or 2, characterized in that: A frequency defining a cycle of the pulses of the second bias voltage is higher than a frequency defining a cycle of the pulses of the first bias voltage.

6. The etching method according to claim 5, characterized in that: The ON time of the pulse of the first bias voltage is the same as the ON time of the pulse of the second bias voltage.

7. The etching method according to claim 1 or 2, characterized in that: The frequency of the cycle of the pulse of the first bias voltage is set to be not less than 200 kHz and not more than 400 kHz, The frequency of the cycle of the pulse of the second bias voltage is defined to be greater than or equal to 200 kHz and less than or equal to 500 kHz.

8. The etching method according to claim 1 or 2, characterized in that: The absolute value of the voltage value of the first bias voltage is greater than or equal to 1 kV and less than or equal to 5 kV. An absolute value of the voltage value of the second bias voltage is greater than or equal to 5 kV and less than or equal to 20 kV.

9. The etching method according to claim 1 or 2, characterized in that: In the step (b), a first period and a second period following the first period are periodically repeated, the first bias voltage is applied during the first period, and the first bias voltage is not applied to the substrate support portion during the second period. In the step (c), a third period and a fourth period following the third period are repeated, wherein the second bias voltage is applied during the third period and the second bias voltage is not applied to the substrate supporting portion during the fourth period.

10. The etching method according to claim 9, characterized in that: In the step (b), a first source RF electric power is supplied for generating the first plasma. The first source RF electric power has a first power level and a second power level lower than the first power level, the first power level and the second power level are repeated periodically, The period during which the first source RF electric power is at the first power level is synchronized with the first period during which the first bias voltage is applied, In the step (c), a second source RF electric power is supplied for generating the second plasma. The second source RF electric power has a third power level and a fourth power level lower than the third power level, the third power level and the fourth power level are repeated periodically, A period during which the second source RF electric power is at the third power level is synchronized with the third period during which the second bias voltage is applied.

11. A plasma processing device, characterized in that: include: Chamber; a substrate supporting portion for supporting a substrate in the chamber, wherein the substrate includes a stacked film including a silicon oxide film and a silicon nitride film; a gas supply unit capable of supplying a first process gas containing a hydrofluorocarbon gas and a second process gas containing a fluorocarbon gas into the chamber; a plasma generating unit capable of generating a first plasma from the first process gas and generating a second plasma from the second process gas; and Control Department, The control unit is capable of controlling the gas supply unit and the plasma generation unit so that: while applying a first bias voltage to the substrate support unit, the silicon nitride film is etched using the first plasma; while applying a second bias voltage to the substrate support unit, the silicon oxide film is etched using the second plasma. The absolute value of the voltage value of the second bias voltage is greater than the absolute value of the voltage value of the first bias voltage, The first bias voltage and the second bias voltage are each a pulse wave in which ON and OFF of a pulse are periodically repeated. The ON time of the pulse is less than 0.5 microseconds.

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