Current mirror circuit and imaging device

Abstract

Provided is a current mirror circuit capable of adjusting noise characteristics of the entire circuit while adjusting output impedance. The current mirror circuit includes: a signal line connected to the plurality of circuits; a first current source; a first transistor; a second current source; a second transistor; and an adjustment mechanism. The first transistor has a gate connected to a signal line. A first current source is connected to the drain of the first transistor. The second transistor has a gate connected to the first current source and a source connected to the signal line. The second current source is connected to the signal line. The adjustment mechanism adjusts an output impedance applied to the signal line.

Description

Technical Field

[0001] The technology according to the present disclosure (this technology) relates to a current mirror circuit and an imaging device including the current mirror circuit. Background Art

[0002] In an imaging device, a pixel signal read from a pixel is generally converted from an analog signal into a digital signal by a column analog-to-digital converter and subjected to signal processing by a digital signal processor (DSP). A current mirror circuit is used for the column analog-to-digital converter.

[0003] The current mirror circuit includes a reference current source that supplies a driving current, and supplies the current supplied from the reference current source to the column analog-to-digital converter (for example, Patent Document 1).

[0004] Incidentally, the column analog-to-digital converter includes a plurality of circuits for converting a pixel signal from an analog signal into a digital signal for each pixel. In the case of sending a current to the plurality of circuits through the current mirror circuit, there are cases where it is desired to reduce and adjust the output impedance on the transmission side, which is the side of the plurality of circuits.

[0005] Citation List

[0006] Patent Document

[0007] Patent Document 1: Japanese Patent Application Laid-Open No. 2009-21685 Summary of the Invention

[0008] Technical Problem to be Solved by the Invention

[0009] However, in the current mirror circuit described in Patent Document 1, the output impedance cannot be adjusted.

[0010] In view of this situation, the present disclosure has been made, and an object thereof is to provide a current mirror circuit and an imaging device capable of adjusting the noise characteristics of the entire circuit while adjusting the output impedance.

[0011] Technical Solution to the Technical Problem

[0012] One aspect of the present disclosure is a current mirror circuit, including: a signal line connected to a plurality of circuits; a first transistor having a gate connected to the signal line; a first current source connected to a drain of the first transistor; a second transistor having a gate connected to the first current source and including a source connected to the signal line; a second current source connected to the signal line; and an adjustment mechanism that adjusts an output impedance applied to the signal line.

[0013] Another aspect of the present disclosure is an imaging device including a current mirror circuit, comprising: a signal line connected to a plurality of circuits; a first transistor having a gate connected to the signal line; a first current source connected to a drain of the first transistor; a second transistor having a gate connected to the first current source and a source connected to the signal line; a second current source connected to the signal line; and an adjustment mechanism for adjusting an output impedance applied to the signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing an example of a schematic configuration of an imaging device according to a first embodiment of the present disclosure.

[0015] Figure 2 is a block diagram for explaining an example of an image signal reading mechanism in an imaging device according to a first embodiment of the present invention.

[0016] Figure 3 is a circuit diagram for explaining an example of a current mirror circuit according to a first comparative example of a first embodiment.

[0017] Figure 4 is a circuit diagram for explaining an example of a current mirror circuit according to a second comparative example of a first embodiment.

[0018] Figure 5 is a circuit diagram for explaining an example of a current mirror circuit according to a first embodiment of the present disclosure.

[0019] Figure 6 is a circuit diagram for explaining an example of a current mirror circuit according to a second embodiment of the present disclosure.

[0020] Figure 7 is a circuit diagram for explaining an example of a current mirror circuit according to a third embodiment of the present disclosure.

[0021] Figure 8 is a circuit diagram for explaining an example of a current mirror circuit according to a fourth embodiment of the present disclosure.

[0022] Figure 9 is a circuit diagram for explaining an example of a current mirror circuit according to a fifth embodiment of the present disclosure.

[0023] Figure 10 is a circuit diagram for explaining an example of a current mirror circuit according to a sixth embodiment of the present disclosure.

[0024] Figure 11 is a block diagram showing an example of a configuration of an imaging system as an electronic device to which the present technology is applied. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the description of the accompanying drawings mentioned below, the same or similar parts are denoted by the same or similar reference numerals to avoid redundant description.

[0026] It should be noted that the effects described in this specification are merely examples and are not limited, and other effects may be provided.

[0027] <First Embodiment>

[0028] (Overall Configuration of Imaging Device)

[0029] Figure 1 is a block diagram showing an example of a schematic configuration of an imaging device according to a first embodiment of the present disclosure. The imaging device 1 is a semiconductor device that converts the amount of electric charge corresponding to the intensity of light formed as an image on each pixel into an electric signal using a photoelectric conversion element (such as a photodiode constituting each pixel), and outputs the electric signal as image data, and is configured as, for example, a CMOS image sensor. The imaging device 1 may be configured as an on-chip system (SoC) as a whole, such as a CMOS LSI. However, for example, some of the components described below may be configured as separate LSIs.

[0030] As shown in the figure, the imaging device 1 includes components such as a pixel array unit 11, a vertical drive unit 12, a column processing unit 13, a horizontal drive unit 14, a system control unit 15, a signal processing unit 16, and a data storage unit 17.

[0031] The pixel array unit 11 includes a group of photoelectric conversion elements, such as photodiodes forming pixels 110 arranged in a horizontal direction (row direction) and a vertical direction (column direction). The pixel array unit 11 converts the amount of electric charge corresponding to the intensity of incident light formed as an image on each pixel 110 into an electric signal and outputs the electric signal as a pixel signal.

[0032] The vertical drive unit 12 includes a shift register, an address decoder, etc. The vertical drive unit 12 supplies drive signals and the like to each pixel 110 via a plurality of pixel drive lines 18, thereby driving each pixel 110 of the pixel array unit 11, for example, simultaneously or row by row.

[0033] The column processing unit 13 reads pixel signals from each pixel via vertical signal lines (VSL) 19 for each pixel column of the pixel array unit 11, and performs noise removal processing, correlated double sampling (CDS) processing, analog-to-digital (A / D) conversion processing, etc. The pixel signals processed by the column processing unit 13 are output to the signal processing unit 16.

[0034] The horizontal driving unit 14 includes a shift register, an address decoder, etc. The horizontal driving unit 14 sequentially selects the pixels 110 corresponding to the pixel columns of the column processing unit 13. When selective scanning is thus performed by the horizontal driving unit 14, the pixel signals that have undergone signal processing for each pixel 110 in the column processing unit 13 are sequentially output to the signal processing unit 16.

[0035] The system control unit 15 includes a timing generator that generates various timing signals, etc. The system control unit 15 performs drive control of the vertical driving unit 12, the column processing unit 13, and the horizontal driving unit 14 based on timing signals generated by, for example, a timing generator (not shown).

[0036] The signal processing unit 16 performs signal processing such as arithmetic processing on the pixel signals provided from the column processing unit 13 while temporarily storing data in the data storage unit 17 as needed, and outputs an image signal based on each pixel signal.

[0037] It should be noted that the imaging device 1 to which the present technology is applied is not limited to the above configuration. For example, the imaging device 1 may be configured such that the data storage unit 17 is arranged at the subsequent stage of the column processing unit 13, and the pixel signals output from the column processing unit 13 are provided to the signal processing unit 16 via the data storage unit 17. Alternatively, the imaging device 1 may be configured such that the cascaded column processing unit 13, the data storage unit 17, and the signal processing unit 16 process each pixel signal in parallel.

[0038] Figure 2 It is a block diagram for explaining an example of an image signal reading mechanism in an imaging device according to a first embodiment of the present invention. In this figure, an image signal reading mechanism 20 starting from one pixel 110 in two pixel columns is exemplarily shown.

[0039] This figure shows a current mirror circuit 30 and a comparator 131 used in an analog-to-digital converter (hereinafter referred to as an AD converter) as the configuration of the column processing unit 13.

[0040] As shown in this figure, the pixel 110 includes a photoelectric conversion unit 1101, a transfer transistor 1102, a floating diffusion unit (hereinafter referred to as an FD unit) 1103, an amplification transistor 1104, a selection transistor 1105, and a reset transistor 1106. In this example, each transistor in the pixel 110 is an N-type metal oxide semiconductor (MOS) transistor (hereinafter referred to as an NMOS transistor), but it is not limited thereto.

[0041] In addition, for example, multiple driving lines for supplying various driving signals TGL, RST, SEL, etc. to the pixel 110 are wired for each pixel row, asFigure 1 The pixel driving line 18 shown in []. These driving signals are, for example, pulse signals that turn on (conduct) the NMOS transistor at a high potential level and turn off (non-conduct) the NMOS transistor at a low potential level.

[0042] The photoelectric conversion unit 1101 is, for example, a PN junction photodiode. The photoelectric conversion unit 1101 generates and accumulates charges corresponding to the amount of received light. The transfer transistor 1102 is an NMOS transistor provided between the photoelectric conversion unit 1101 and the FD unit 1103. The driving signal TGL is applied to the gate of the transfer transistor 1102. That is, when the driving signal TGL reaches a high potential level, the transfer transistor 1102 enters the conducting state, and the charges accumulated in the photoelectric conversion unit 1101 are transferred to the FD unit 1103 via the transfer transistor 1102.

[0043] The reset transistor 1106 is an NMOS transistor provided between the constant potential VDD and the FD unit 1103. The driving signal RST is applied to the gate of the reset transistor 1106. When the driving signal RST reaches a high potential level, the reset transistor 1106 enters the conducting state, and the potential of the FD unit 1103 is reset to the level of the constant potential VDD.

[0044] The FD unit 1103 is a floating diffusion region capable of holding a predetermined amount of charge. The charges accumulated in the FD unit 1103 undergo charge-voltage conversion through the amplifying transistor 1104 to become voltage signals and are read out.

[0045] The amplifying transistor 1104 is an NMOS transistor having a gate connected to the FD unit 1103 and a drain connected to the constant potential VDD. The amplifying transistor 1104 serves as an input unit of a reading circuit (i.e., a source follower circuit) for reading the charges held in the FD unit 1103. That is, the source of the amplifying transistor 1104 connected to the vertical signal line 19 through the selection transistor 1105 and the current source 191 connected to the vertical signal line 19 together form a source follower circuit.

[0046] The selection transistor 1105 is an NMOS transistor provided between the source of the amplifying transistor 1104 and the vertical signal line 19. The driving signal SEL is applied to the gate of the selection transistor 1105. When the driving signal SEL reaches a high potential level, the selection transistor 1105 enters the conducting state, and the pixel 110 enters the selected state. Therefore, the pixel signal output from the amplifying transistor 1104 is read out to the vertical signal line 19 via the selection transistor 1105.

[0047] (Configuration of the comparator)

[0048] In contrast, the comparator 131 is provided in parallel for each vertical signal line 19 corresponding to a pixel column. The comparator 131 is a differential amplifier including a first input unit 1311, a second input unit 1312, and a third input unit 1313. The first input unit 1311, the second input unit 1312, and the third input unit 1313 are NMOS transistors. The first input unit 1311 has a gate connected to the vertical signal line 19 and a source connected to the source of the second input unit 1312 and the drain of the third input unit 1313. The pixel signal is applied to the gate of the first input unit 1311. That is, when the voltage of the pixel signal exceeds the threshold voltage between the gate and the drain of the first input unit 1311, the first input unit 1311 enters the conducting state, and the pixel signal is output from the drain of the first input unit 1311.

[0049] The second input unit 1312 has a gate connected to a reference signal circuit (not shown) and a source connected to the source of the first input unit 1311 and the drain of the third input unit 1313. The reference signal is applied to the gate of the second input unit 1312. That is, when the voltage of the reference signal exceeds the threshold voltage between the gate and the drain of the second input unit 1312, the second input unit 1312 enters the conducting state, and the reference signal is output from the drain of the second input unit 1312.

[0050] The third input unit 1313 has a gate connected to the signal line 31 of the current mirror circuit 30, a source grounded, and a drain connected to the source of the first input unit 1311 and the source of the second input unit 1312. When a drive current is provided from the current mirror circuit 30, the comparator 131 operates. Then, a current signal is applied from the current mirror circuit 30 to the gate of the third input unit 1313. When the voltage of the current signal exceeds the threshold voltage between the gate and the drain of the third input unit 1313, the third input unit 1313 enters the conducting state, and the current signal is output from the drain of the third input unit 1313.

[0051] The comparator 131 compares the pixel signal with the reference signal and outputs a signal according to the comparison result to a counter (not shown). The counter counts the input signal according to a predetermined clock and outputs the count value as a pixel signal in digital form.

[0052] <Comparative Example of the Embodiment>

[0053] Figure 3This is a circuit diagram illustrating an example of a current mirror circuit according to a first comparative example of the first embodiment. In this figure, the current mirror circuit B30-1 includes a first transistor 32 and a first current source 33. In this example, the first transistor 32 is an NMOS transistor, but the present invention is not limited thereto. A signal line 31 is connected to the gate of the first transistor 32. The source of the first transistor 32 is connected to the ground potential GND. The first current source 33 is provided between the drain of the first transistor 32 and the power supply line 34 (constant potential VDD). The first current source 33 is connected to the drain of the first transistor 32 and directly connected to the signal line 31.

[0054] The current from the first current source 33 is converted into a voltage signal by the first transistor 32 and output to a plurality of third input units 1313-1 to 1313-i (i is an integer) via the signal line 31.

[0055] Incidentally, when the voltage signal is sent to the plurality of third input units 1313-1 to 1313-i through the current mirror circuit B30-1, the output impedance on the transmission side increases.

[0056] Therefore, a current mirror circuit for reducing the output impedance has been proposed.

[0057] Figure 4 This is a circuit diagram illustrating an example of a current mirror circuit according to a second comparative example of the first embodiment. In Figure 4 the parts that are the same as those in the above Figure 3 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0058] The current mirror circuit B30-2 further includes a second current source 35 and a second transistor 36. In this example, the second transistor 36 is an NMOS transistor, but the present invention is not limited thereto.

[0059] The gate of the second transistor 36 is connected to the first current source 33, and it has a source connected to the signal line 31 and a drain connected to the power supply line 34 (constant potential VDD). The second current source 35 is provided between the signal line 31 and the ground potential GND. The second transistor 36 amplifies the potential applied to the gate of the first transistor 32 according to the current value output from the first current source 33. Then, when the potential applied to the gate of the first transistor 32 exceeds the threshold voltage between the gate and the source of the first transistor 32, the first transistor 32 enters the conduction state, the current output from the first current source 33 is converted into a voltage signal by the first transistor 32, and the voltage signal is provided to the plurality of third input units 1313-1 to 1313-i via the signal line 31.

[0060] Incidentally, according to the current mirror circuit B30-2, the output impedance on the transmission side can be reduced, but the output impedance cannot be adjusted when it is excessively reduced.

[0061] <Solutions of the First Embodiment>

[0062] Therefore, in the first embodiment of the present disclosure, the current mirror circuit 30 includes an impedance adjustment mechanism that adjusts the output impedance applied to the signal line 31 by adjusting the loop gain frequency band of the feedback loop FB1 formed by the first transistor 32, the signal line 31, and the second transistor 36.

[0063] Figure 5 is a circuit diagram for explaining an example of the current mirror circuit 30 according to the first embodiment of the present disclosure. In Figure 5 , parts that are the same as those in the above Figure 4 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0064] In the first embodiment of the present invention, the current regulator 37 is provided as an impedance adjustment mechanism that regulates the current flow from the second current source 35 to the signal line (VGCM) 31. That is, in the first embodiment of the present invention, the current regulator 37 is used to change the frequency band of the source follower configured by the second transistor 36 and the second current source 35, and to adjust the loop gain frequency band of the feedback loop FB1.

[0065] In the first embodiment of the present invention, the source of the first transistor 32 is connected to the constant potential VDD. The first current source 33 is provided between the drain of the first transistor 32 and the ground potential GND. The drain of the second transistor 36 is connected to the ground potential GND. The second current source 35 is provided between the signal line 31 and the constant potential VDD.

[0066] The current output from the first current source 33 is converted into a voltage signal by the first transistor 32 and the second transistor 36, and is output to the plurality of third input units 1313-1 to 1313-i via the signal line 31. The error signal (noise) propagated from the circuit driven by the plurality of third input units 1313-1 to 1313-i via the signal line 31 is superimposed on the voltage signal output to the source of the second transistor 36. This error signal (noise) is output in an inverted phase to the drain of the first transistor 32, is superimposed on the signal line 31 through the second transistor 36, and attempts to eliminate the noise propagated to the signal line 31.

[0067] In order to adjust the degree of cancellation, the current regulator 37 is used to change the frequency band of the source follower configured by the second transistor 36 and the second current source 35. For example, the current regulator 37 is adjusted in the direction of decreasing current, so that the frequency band of the feedback loop FB1 configured by the first transistor 32 and the second transistor 36 becomes narrower, and the effect of noise cancellation is weakened.

[0068] <Effects produced by the first embodiment>

[0069] As described above, according to the first embodiment, the loop gain frequency band of the feedback loop FB1 formed by the first transistor 32, the signal line 31, and the second transistor 36 can be adjusted by the current regulator 37, so that the output impedance can be adjusted at a low level, and thus the noise characteristics of the entire circuit can be adjusted.

[0070] <Second embodiment>

[0071] Figure 6 is a circuit diagram for illustrating an example of the current mirror circuit 30A according to the second embodiment of the present disclosure. In Figure 6 , the same parts as those in the above Figure 5 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0072] In the second embodiment of the present disclosure, a varactor 41 is connected between the signal line 31 and the drain of the first transistor 32 to form a low-pass filter in the feedback loop FB1. Then, the capacitance ratio of the capacitor 41 is adjusted to adjust the loop gain frequency band of the feedback loop FB1.

[0073] The error signals (noises) transmitted from the plurality of third input units 1313-1 to 1313-i via the signal line 31 pass between the source and the gate of the second transistor 36 and are attenuated by the low-pass filter.

[0074] <Effects produced by the second embodiment>

[0075] As described above, according to the second embodiment, by connecting the varactor 41 between the signal line 31 and the drain of the first transistor 32 to form a low-pass filter, the loop gain frequency band of the feedback loop FB1 can be made narrower, and the effect of canceling the error signals (noises) propagated from the plurality of third input units 1313-1 to 1313-i via the signal line 31 can be weakened. In addition, by adjusting the capacitance ratio of the capacitor 41, the output impedance on the transmission side can be adjusted, and thus the noise characteristics of the entire circuit can be adjusted.

[0076] <Third embodiment>

[0077] Figure 7This is a circuit diagram for illustrating an example of the current mirror circuit 30B according to the third embodiment of the present disclosure. In Figure 7 those parts that are the same as the above Figure 5 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0078] In the third embodiment of the present disclosure, a varactor 42 is connected between the drain of the first transistor 32 and the constant potential VDD to form a low-pass filter in the feedback loop FB1. Then, the capacitance ratio of the capacitor 42 is adjusted to adjust the loop gain bandwidth of the feedback loop FB1.

[0079] The error signal (noise) transmitted from the plurality of third input units 1313-1 to 1313-i via the signal line 31 passes between the source and the gate of the second transistor 36 and is attenuated by the low-pass filter.

[0080] <Effects produced by the third embodiment>

[0081] As described above, according to the third embodiment, by connecting the capacitor 42 between the drain of the first transistor 32 and the constant potential VDD to form a low-pass filter, the loop gain bandwidth of the feedback loop FB1 can be narrowed, and the effect of eliminating the error signal (noise) propagated from the plurality of third input units 1313-1 to 1313-i via the signal line 31 can be weakened. In addition, by adjusting the capacitance ratio of the capacitor 42, the output impedance on the transmission side can be adjusted, and thus the noise characteristics of the entire circuit can be adjusted.

[0082] <Fourth embodiment>

[0083] Figure 8 This is a circuit diagram for illustrating an example of the current mirror circuit 30C according to the fourth embodiment of the present disclosure. In Figure 8 those parts that are the same as the above Figure 5 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0084] In the fourth embodiment of the present disclosure, one end of a resistor 52 is connected to the drain of the first transistor 32. The other end of the resistor 52 is connected to a replica circuit 60, which includes the same components as those of the current mirror circuit 30C. The resistor 52 is divided into two resistors 521 and 522 by a signal line extending from the gate of the second transistor 36. The resistance values of the respective resistors 521 and 522 for voltage division can be adjusted.

[0085] The replication circuit 60 includes a signal line 61, a first transistor 62, a first current source 63, a second current source 64, and a second transistor 65. The signal line 61 is connected to the gate of the first transistor 62. The source of the first transistor 62 is connected to the constant potential VDD. The first current source 63 is provided between the drain of the first transistor 62 and the ground potential GND. Note that, unlike the signal line 31, the plurality of third input units 1313-1 to 1313-i are not connected to the signal line 61.

[0086] The gate of the second transistor 65 is connected to the first current source 63, and it has a source connected to the signal line 61 and a drain connected to the ground potential GND. The second current source 64 is provided between the signal line 61 and the constant potential VDD. The other end of the resistor 52 is connected to the drain of the first transistor 62.

[0087] In the fourth embodiment of the present disclosure, the feedback loop FB2 is formed by the first transistor 32, the signal line 31, the second transistor 36, and the resistor 522. The error signal (noise) transmitted from the plurality of third input units 1313-1 to 1313-i via the signal line 31 passes between the source and the gate of the second transistor 36 and is output to the resistor 522. In addition, the low-frequency (DC) voltage fluctuation (power supply noise) generated at the constant potential VDD passes between the source and the gate of the second transistor 36 and is output to the resistor 522.

[0088] Then, based on the bias voltage output from the replication circuit 60, the error signal (noise) and the power supply noise are divided by the resistor 52 and output to the drain of the first transistor 32. Therefore, the error signal (noise) and the power supply noise are attenuated. In addition, by adjusting the resistance values of the respective resistors 521 and 522 for voltage division, the output impedance on the transmission side can be adjusted, and thus the noise characteristics of the entire circuit can be adjusted.

[0089] <Effects produced by the fourth embodiment>

[0090] As described above, according to the fourth embodiment, by using the bias voltage output from the replication circuit 60 as a reference, the error signal (noise) output from the plurality of third input units 1313-1 to 1313-i to the feedback loop FB2 is divided by the resistor 52, the output impedance can be adjusted, and in addition, the fourth embodiment is resistant to power supply noise.

[0091] Note that, in the fourth embodiment, the bias voltage output from the replication circuit 60 is used as a reference, but a reference signal other than the bias voltage output from the replication circuit 60 can be used as a reference.

[0092] <Fifth embodiment>

[0093] Figure 9It is a circuit diagram for explaining an example of the current mirror circuit 30D according to the fifth embodiment of the present disclosure. In Figure 9 the same parts as those in the above Figure 5 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0094] The fifth embodiment of the present disclosure includes a first capacitor 71, a varactor second capacitor 72, and an auto-zero (AZ) switch 73. The first capacitor 71 is connected between the first current source 33 and the drain of the first transistor 32 and the gate of the second transistor 36. The second capacitor 72 is connected between the ground potential GND and the gate of the second transistor 36. The AZ switch 73 is connected in parallel to the first capacitor 71 to turn on and off the short circuit.

[0095] In the fifth embodiment of the present disclosure, the feedback loop FB3 is formed by the first transistor 32, the signal line 31, the second transistor 36, and the first capacitor 71.

[0096] During the auto-zero operation, the AZ switch 73 is switched to the on state to short-circuit the first capacitor 71. Then, the voltage signals sent to the plurality of third input units 1313-1 to 1313-i pass between the source and the gate of the second transistor 36 and are fed back to the first transistor 32.

[0097] During driving, the AZ switch 73 is switched to the off state. Then, the voltage signals sent to the plurality of third input units 1313-1 to 1313-i and the error signals (noise) sent from the plurality of third input units 1313-1 to 1313-i via the signal line 31 pass between the source and the gate of the second transistor 36 and accumulate in the first capacitor 71. In addition, the power supply noise generated at the constant potential VDD passes between the source and the gate of the second transistor 36 and accumulates in the first capacitor 71.

[0098] Then, the error signals (noise) of the power supply voltage and the power supply noise are divided by the first capacitor 71 and the second capacitor 72 and output to the drain of the first transistor 32. Therefore, the error signals (noise) and the power supply noise of the power supply voltage are attenuated. In addition, by adjusting the capacitance ratio of the second capacitor 72, the output impedance on the transmission side can be adjusted, and thus the noise characteristics of the entire circuit can be adjusted.

[0099] <Effects produced by the fifth embodiment>

[0100] As described above, according to the fifth embodiment, the output impedance can be adjusted by dividing the error signals sent from the plurality of third input units 1313-1 to 1313-i via the signal line 31 by the first capacitor 71 and the second capacitor 72.

[0101] <Sixth Embodiment>

[0102] Figure 10 It is a circuit diagram for explaining an example of the current mirror circuit 30E according to the sixth embodiment of the present disclosure. In Figure 10 the parts identical to those in the above Figure 9 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0103] In the sixth embodiment of the present disclosure, the second capacitor 74 is connected between the gate of the second transistor 36 and the constant potential VDD. In this example, the first transistor 32 and the second transistor 36 are P-type MOS transistors (PMOS transistors) having polarities opposite to those of NMOS transistors.

[0104] During the auto-zero operation, the AZ switch 73 is switched to the on state to short-circuit the first capacitor 71. Then, the voltage signals sent to the plurality of third input units 1313-1 to 1313-i pass between the source and the gate of the second transistor 36 and are fed back to the first transistor 32.

[0105] During driving, the AZ switch 73 is switched to the off state. Then, the voltage signals sent to the plurality of third input units 1313-1 to 1313-i and the error signals (noises) sent from the plurality of third input units 1313-1 to 1313-i via the signal line 31 pass between the source and the gate of the second transistor 36 and accumulate in the first capacitor 71. In addition, the power supply noise generated at the constant potential VDD passes between the source and the gate of the second transistor 36 and accumulates in the first capacitor 71.

[0106] Then, the error signals (noises) and the power supply noise are divided by the first capacitor 71 and the second capacitor 74 and output to the drain of the first transistor 32. Therefore, the error signals (noises) and the power supply noise are attenuated. In addition, by adjusting the capacitance ratio of the second capacitor 74, the output impedance on the transmission side can be adjusted, and thus the noise characteristics of the entire circuit can be adjusted.

[0107] <Effects Produced by the Sixth Embodiment>

[0108] As described above, the sixth embodiment produces effects similar to those produced by the above-described fifth embodiment, and in addition, has higher power supply noise tolerance.

[0109] <Other Embodiments>

[0110] The present technology has been described above according to the first to sixth embodiments, but it should not be understood that the description and the drawings forming part of the present disclosure limit the present technology. It will be apparent to those skilled in the art that various alternative embodiments, examples, and operation techniques can be included in the present technology when understanding the spirit of the technical content disclosed in the above first to sixth embodiments. In addition, within the range where there is no contradiction, the configurations disclosed in the first to sixth embodiments can be appropriately combined. For example, the configurations disclosed in multiple different embodiments can be combined, or the configurations disclosed in multiple different variations of the same embodiment can be combined.

[0111] <Application Examples of Electronic Devices>

[0112] The above light detection device can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with an imaging function, or other devices with an imaging function.

[0113] Figure 11 is a block diagram showing a configuration example of an imaging system as an electronic device to which the present technology is applied.

[0114] Figure 11 The imaging system 2201 shown in includes an optical system 2202, a shutter device 2203, a solid-state imaging element 2204 as an imaging device, a control circuit 2205, a signal processing circuit 2206, a monitor 2207, and two memories 2208, and can capture still images and moving images.

[0115] The optical system 2202 includes one or more lenses and guides light (incident light) from a subject to the solid-state imaging element 2204 to form an image on the light receiving surface of the solid-state imaging element 2204.

[0116] The shutter device 2203 is arranged between the optical system 2202 and the solid-state imaging element 2204 and controls the light irradiation period and the light shielding period of the solid-state imaging element 2204 under the control of the control circuit 2205.

[0117] The solid-state imaging element 2204 includes a package containing the above solid-state imaging element. The solid-state imaging element 2204 accumulates signal charges for a certain period according to the light that forms an image on the light receiving surface via the optical system 2202 and the shutter device 2203. According to the drive signal (timing signal) provided from the control circuit 2205, the signal charges accumulated in the solid-state imaging element 2204 are transferred.

[0118] The control circuit 2205 outputs drive signals for controlling the transfer operation of the solid-state imaging element 2204 and the shutter operation of the shutter device 2203 to drive the solid-state imaging element 2204 and the shutter device 2203.

[0119] The signal processing circuit 2206 performs various types of signal processing on the signal charges output from the solid-state imaging element 2204. The image (image data) obtained by performing signal processing by the signal processing circuit 2206 is provided to the monitor 2207 for display or provided to the memory 2208 for storage (recording).

[0120] Similarly, in the imaging system 2201 configured as described above, the imaging device 1 can be applied in place of the above-mentioned solid-state imaging element 2204.

[0121] Note that the present disclosure may also have the following configurations. (1)

[0123] A current mirror circuit, comprising:

[0124] A signal line connected to a plurality of circuits;

[0125] A first transistor having a gate connected to the signal line;

[0126] A first current source connected to the drain of the first transistor;

[0127] A second transistor having a gate connected to the first current source and a source connected to the signal line;

[0128] A second current source connected to the signal line; and

[0129] An adjustment mechanism for adjusting the output impedance applied to the signal line. (2)

[0131] The current mirror circuit according to (1), wherein the adjustment mechanism adjusts the output impedance by adjusting the current flowing from the first current source to the signal line. (3)

[0133] The current mirror circuit according to (1), wherein the adjustment mechanism includes a capacitor connected between the signal line and the drain of the first transistor, and adjusts the output impedance by adjusting the capacitance ratio of the capacitor. (4)

[0135] The current mirror circuit according to (1), wherein the adjustment mechanism includes a capacitor connected between the drain of the first transistor and the power supply potential, and adjusts the output impedance by adjusting the capacitance ratio of the capacitor. (5)

[0137] The current mirror circuit according to (1), wherein the adjusting mechanism includes a resistor having one end connected to the drain of the first transistor, and the output impedance is adjusted by dividing the error signal propagated from a plurality of circuits via the signal line by the resistor based on the signal input to the other end of the resistor. (6)

[0139] The current mirror circuit according to (5) further includes:

[0140] A copying circuit including components identical to those of the first current source, the first transistor, the second current source, and the second transistor,

[0141] wherein the copying circuit is connected to the other end of the resistor, and

[0142] the adjusting mechanism adjusts the output impedance by dividing the error signal propagated from a plurality of circuits via the signal line by the resistor based on the bias voltage output from the copying circuit. (7)

[0144] The current mirror circuit according to (1), wherein the adjusting mechanism includes a first capacitor connected between the first current source and the gate of the second transistor and a second capacitor connected between the gate of the second transistor and the power supply potential, and the output impedance is adjusted by dividing the error signal propagated from a plurality of circuits via the signal line by the first capacitor and the second capacitor. (8)

[0146] The current mirror circuit according to (7), wherein the second capacitor is a varactor type. (9)

[0148] The current mirror circuit according to (7) further includes a switch unit that is connected in parallel to the first capacitor and switches the on / off of the short circuit. (10)

[0150] The current mirror circuit according to (1), wherein the adjusting mechanism includes a first capacitor connected between the first current source and the gate of the second transistor and a second capacitor connected between the gate of the second transistor and the ground potential, and the output impedance is adjusted by dividing the error signal propagated from a plurality of circuits via the signal line by the first capacitor and the second capacitor. (11)

[0152] The current mirror circuit according to (10), wherein the second capacitor is a varactor type. (12)

[0154] The current mirror circuit according to (10) further includes a switch unit that is connected in parallel to the first capacitor and switches the on / off of the short circuit. (13)

[0156] An imaging device includes a current mirror circuit, which includes:

[0157] A signal line connected to a plurality of circuits;

[0158] A first transistor with its gate connected to the signal line;

[0159] A first current source connected to the drain of the first transistor;

[0160] A second transistor with its gate connected to the first current source and including a source connected to the signal line;

[0161] A second current source connected to the signal line; and

[0162] An adjustment mechanism for adjusting the output impedance applied to the signal line.

[0163] List of reference numerals

[0164] 1 Imaging device

[0165] 11 Pixel array unit

[0166] 12 Vertical drive unit

[0167] 13 Column processing unit

[0168] 14 Horizontal drive unit

[0169] 15 System control unit

[0170] 16 Signal processing unit

[0171] 17 Data storage unit

[0172] 18 Pixel drive line

[0173] 19 Vertical signal line

[0174] 20 Pixel signal reading mechanism

[0175] 30, 30A, 30B, 30C, 30D, 30E Current mirror circuit

[0176] 31, 61 Signal line

[0177] 32, 62 First transistor

[0178] 33, 63 First current source

[0179] 34 Power supply line

[0180] 35, 64 Second current source

[0181] 36, 65 Second transistor

[0182] 37 Current regulator

[0183] 41, 42 Capacitor

[0184] 52 Resistor

[0185] 60 Duplication circuit

[0186] 71 First capacitor

[0187] 72, 74 Second capacitor

[0188] 73 Auto-zero (AZ) switch

[0189] 110 Pixel

[0190] 131 Comparator

[0191] 191 Current source

[0192] 521, 522 Resistor

[0193] 1101 Photoelectric conversion unit

[0194] 1102 Transfer transistor

[0195] 1103 FD unit

[0196] 1104 Amplification transistor

[0197] 1105 Selection transistor

[0198] 1106 Reset transistor

[0199] 1311 First input unit

[0200] 1312 Second input unit

[0201] 1313 (1313-1 to 1313-i) Third input unit

[0202] 2201 Imaging system

[0203] 2202 Optical system

[0204] 2203 Shutter device

[0205] 2204 Solid-state imaging element

[0206] 2205 Control circuit

[0207] 2206 Signal processing circuit

[0208] 2207 Monitor

[0209] 2208 Memory

[0210] FB1, FB2, FB3 Feedback Loops

[0211] VDD Constant Potential

[0212] GND Ground Potential.

Claims

1. A current mirror circuit, comprising: a signal line connected to a plurality of circuits; a first transistor having a gate connected to the signal line; a first current source connected to the drain of the first transistor; a second transistor having a gate connected to the first current source and a source connected to the signal line; a second current source connected to the signal line; and an adjustment mechanism for adjusting an output impedance applied to the signal line.

2. The current mirror circuit according to claim 1, wherein the adjustment mechanism adjusts the output impedance by adjusting a current flowing from the second current source to the signal line.

3. The current mirror circuit according to claim 1, wherein the adjustment mechanism includes a capacitor connected between the signal line and the drain of the first transistor, and adjusts the output impedance by adjusting a capacitance ratio of the capacitor.

4. The current mirror circuit according to claim 1, wherein the adjustment mechanism includes a capacitor connected between the drain of the first transistor and a power supply potential, and adjusts the output impedance by adjusting a capacitance ratio of the capacitor.

5. The current mirror circuit according to claim 1, wherein the adjustment mechanism includes a resistor having one end connected to the drain of the first transistor, and adjusts the output impedance by dividing a voltage of an error signal propagated from the plurality of circuits via the signal line by the resistor with a signal input to the other end of the resistor as a reference.

6. The current mirror circuit according to claim 5, further comprising: a replication circuit including components identical to the first current source, the first transistor, the second current source, and the second transistor, wherein the replication circuit is connected to the other end of the resistor, and the adjustment mechanism adjusts the output impedance by dividing a voltage of an error signal propagated from the plurality of circuits via the signal line by the resistor with a bias voltage output from the replication circuit as a reference.

7. The current mirror circuit according to claim 1, wherein the adjustment mechanism includes a first capacitor connected between the first current source and the gate of the second transistor and a second capacitor connected between the gate of the second transistor and a power supply potential, and adjusts the output impedance by dividing a voltage of an error signal propagated from the plurality of circuits via the signal line by the first capacitor and the second capacitor.

8. The current mirror circuit according to claim 7, wherein the second capacitor is a varactor type.

9. The current mirror circuit according to claim 7, further comprising a switch unit connected in parallel to the first capacitor and switching on and off a short circuit.

10. The current mirror circuit according to claim 1, wherein The adjustment mechanism includes a first capacitor connected between the first current source and the gate of the second transistor and a second capacitor connected between the gate of the second transistor and the ground potential, and adjusts the output impedance by dividing the error signal propagated from the plurality of circuits via the signal line by the first capacitor and the second capacitor.

11. The current mirror circuit according to claim 10, wherein, the second capacitor is a varactor type.

12. The current mirror circuit according to claim 10, further comprising a switch unit, the switch unit being connected in parallel to the first capacitor and switching the on / off of the short circuit.

13. An imaging device, comprising a current mirror circuit, the current mirror circuit comprising: a signal line connected to a plurality of circuits; a first transistor having a gate connected to the signal line; a first current source connected to the drain of the first transistor; a second transistor having a gate connected to the first current source and a source connected to the signal line; a second current source connected to the signal line; and an adjustment mechanism that adjusts the output impedance applied to the signal line.

Images