Substrate for electronic component, method for manufacturing substrate for electronic component, display device including same, and semiconductor device

Abstract

The present invention relates to a substrate for an electronic component, a method for manufacturing the substrate, and a display device and a semiconductor device including the substrate for an electronic component, the substrate for an electronic component comprising: a substrate including one or more through-core through-holes; and an adhesion enhancing layer provided on the surface of the substrate and the through-core through-hole, one or more of the upper surface and the lower surface of the through-core through-hole having a larger pore diameter than a point inside the through-core through-hole. According to the present invention, by including the adhesion enhancing layer, the adhesion force of the gold-plated metal layer can be improved, the occurrence of defects can be prevented, and the manufacturing process can be simplified compared to conventional substrates for electronic components.

Description

Technical Field

[0001] The present invention relates to a substrate for electronic components including a substrate having a through-core via hole, a method of manufacturing the substrate for electronic components, a display device including the substrate for electronic components, and a semiconductor device. Background Art

[0002] As a substrate, which is a basic material for various electronic devices represented by semiconductor devices, display devices, etc., aims to stack multiple chips on a small area using 2.5D or 3D integrated circuit technology. Therefore, a method for realizing miniaturization of semiconductor devices, simplification of processes, and systematization is required.

[0003] Through-core via holes (substrate-through vias, via holes, etc.) provide electrical connections between layers in physical electronic circuits or chips. For example, in a three-dimensional stacked integrated circuit, through-core via holes can integrate electronic components in the vertical and horizontal directions. Generally, through-core via holes are used in silicon substrates. Korean Patent Publication No. 10-1459597 discloses a method for manufacturing a through-silicon via (TSV) substrate. However, from an economic perspective, since glass is cheaper than silicon, glass substrates have recently been more widely used in electronic devices. Glass substrates can also provide improved electromagnetic loss characteristics, improved dielectric characteristics, a customized coefficient of thermal expansion, and the ability to achieve a scalable form factor.

[0004] Korean Patent Publication No. 10-1685578 provides an electroless palladium gold plating method, including: a step of providing an electroless palladium gold plating solution; a step of introducing an inert gas into the electroless palladium gold plating solution; a step of immersing a substrate in the electroless palladium gold plating solution; and a step of performing electroless gold plating on the substrate using the plating solution. However, even when applying the plating method, there may be a problem that it is impossible to ensure sufficient adhesion and reliability of the gold plating film. This can affect the transmission of electrical signals and power, and ultimately may be directly related to the performance of the device. Therefore, there is a need to develop a substrate for electronic components and a method of manufacturing the same, which can not only reduce the incidence of defects in the process to improve the yield, but also prevent electrode lifting even under harsh conditions, and simplify the manufacturing process. Summary of the Invention

[0005] Technical Problem

[0006] In order to solve the above problems, an object of the present invention is to provide a substrate for electronic components and a method of manufacturing the same, in which the adhesion of gold plating is improved in the process of gold plating a substrate having a through-core via hole.

[0007] An object of the present invention is to provide a substrate for electronic components and a manufacturing method thereof. The substrate for electronic components can not only adjust the thickness of the gold plating layer and prevent electrode warping even under severe conditions, but also simplify the manufacturing process compared with the existing substrates for electronic components.

[0008] In addition, an object of the present invention is to provide a display device and a semiconductor device including the substrate for electronic components.

[0009] However, the problems to be solved by the present invention are not limited to the above-mentioned problems, and those skilled in the art will clearly understand other problems not mentioned from the following description.

[0010] Technical Solution

[0011] The present invention relates to a substrate for electronic components, including: a substrate including one or more through-core via holes; and a close adhesion promoting layer provided on the surface of the substrate and the through-core via holes, wherein the aperture of one or more of the upper and lower surfaces of the through-core via hole is larger than the aperture at a point inside the hole.

[0012] In the present invention, in the vertical cross-section of the through-core via hole, the angle between the line connecting a point of the core via hole on the upper or lower surface and the point with the smallest aperture inside the via hole and the line connecting a point of the core via hole on the upper or lower surface in the vertical direction can be 1° to 25° or less.

[0013] In the present invention, the vertical cross-section of the through-core via hole can be symmetric or asymmetric.

[0014] In the present invention, the inner wall surface of the through-core via hole can be in a form including irregularities.

[0015] The present invention can be characterized in that the substrate is glass or quartz.

[0016] In the present invention, the close adhesion promoting layer can be one or more selected from the group consisting of a UV curable resin having an acrylic group and a polyimide-based thermosetting resin, or a film coated with a metal, an oxide, or a ceramic oxide.

[0017] In the present invention, the thickness of the close adhesion promoting layer can be 250 to

[0018] In the present invention, the average of the apertures of one or more of the upper and lower surfaces of each through-type via hole of the substrate can be 5 to 190 μm.

[0019] The present invention relates to a method for manufacturing a substrate for electronic components, comprising: (a) forming a bonding promotion layer on the surface of a substrate including one or more through-core through holes; and (b) plating gold metal on the surface of the substrate on which the bonding promotion layer is formed, wherein the hole diameter of one or more of the upper and lower surfaces of the through-core through holes is larger than the hole diameter of a point inside the hole, and the gold plating step of (b) is performed by one or more methods selected from electrolytic gold plating and electroless gold plating.

[0020] In the present invention, the above step (a) may also include a surface modification process.

[0021] In the present invention, the surface modification may be performed by one or more methods selected from the group consisting of saponification treatment, plasma treatment, corona treatment, and primer treatment.

[0022] In the present invention, before the above step (a), it can also include a process of manufacturing a through-core through hole in which one or more apertures on the top and bottom sides are larger than the aperture of a point inside the hole by adjusting the etching speed on the top and bottom sides of the substrate.

[0023] In the present invention, the above step (b) may be further performed more than once.

[0024] Furthermore, the present invention may relate to a display device and a semiconductor device including the electronic component substrate.

[0025] Effects of the Invention

[0026] According to the electronic component substrate and the manufacturing method thereof of the present invention, when manufacturing a substrate having a through-core through hole, it includes a adhesion enhancement layer formed by a wet coating method, thereby improving the adhesion of the metal gold-plated layer and preventing the occurrence of defects, thereby being able to provide a high-quality electronic component substrate.

[0027] Furthermore, according to the electronic component substrate and the method for manufacturing the same of the present invention, the thickness of the gold plating layer can be adjusted by an additional process, and the manufacturing process can be simplified compared to conventional electronic component substrates.

[0028] According to the electronic component substrate and the manufacturing method thereof of the present invention, the diameter of at least one of the upper and lower surfaces of the through-core through hole can be larger than the diameter of a point inside the hole. In addition, when the volume of the internal metal of the through-core through hole expands / contracts accordingly, the metal plated inside the core through hole can be prevented from being impacted and concentrated in any one direction of the upper or lower surface of the hole, thereby preventing the electrode from warping under severe conditions.

[0029] By using the electronic component substrate of the present invention, a display device and a semiconductor device having excellent reliability can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 FIG. is a cross-sectional view of a substrate including a through-core via hole according to an embodiment of the present invention (a hourglass-shaped through-core via hole is not shown).

[0031] Figure 2 FIG. is a cross-sectional view of a substrate having a close contact promoting layer formed thereon in the substrate for an electronic component of the present invention (a hourglass-shaped through-core via hole is not shown).

[0032] Figure 3 FIG. is a cross-sectional view of a substrate having a close contact promoting layer and a metal electrode layer formed thereon in the substrate for an electronic component of the present invention (a hourglass-shaped through-core via hole is not shown).

[0033] Figure 4 FIG. is a cross-sectional view of a substrate including a through-core via hole according to an embodiment of the present invention (a hourglass-shaped through-core via hole is shown).

[0034] Figure 5 FIG. is a cross-sectional view of a substrate having a close contact promoting layer formed thereon in the substrate for an electronic component of the present invention (a hourglass-shaped through-core via hole is shown).

[0035] Figure 6 FIG. is a cross-sectional view of a substrate having a close contact promoting layer and a metal electrode layer formed thereon in the substrate for an electronic component of the present invention (a hourglass-shaped through-core via hole is shown).

[0036] Figure 7 FIG. is a view showing a vertical cross-section of a through-core via hole of the present invention, in which the upper aperture diameter, the aperture diameter at a point inside the hole, and the lower aperture diameter are respectively shown.

[0037] Figure 8 FIG. is a view showing a vertical cross-section of a through-core via hole of the present invention, in which the angle between a line connecting a point on the upper or lower core via hole and the point having the smallest aperture diameter inside the via hole and a line connecting a point on the upper or lower core via hole in the vertical direction is shown.

[0038] Figure 9 FIG. is a view showing a vertical cross-section of a through-core via hole of the present invention, in which the inner wall surface of the through-core via hole is shown to have a concavo-convex shape.

[0039] Figure 10 FIG. is a picture of a vertical cross-section of a through-core via hole of the present invention in Example 1.

[0040] Figure 11 FIG. is a picture of a vertical cross-section of a through-core via hole of the present invention in Example 1 and an enlarged view of the inner wall surface.

[0041] Figure 12a and Figure 12bThis is a vertical cross-sectional picture of a through-core through hole of the present invention in Example 3.

[0042] Figure 13 This is a vertical cross-sectional picture of a through-core through hole of Example 4 of the present invention.

[0043] Figure 14 This is a vertical cross-sectional picture of the through-core through hole of the present invention in Example 1.

[0044] The reference numerals in the above-mentioned figures are as follows.

[0045] 10: substrate, 20: adhesion promotion layer, 30: metal electrode layer. DETAILED DESCRIPTION

[0046] The present invention relates to a substrate for electronic components, a method for manufacturing the substrate for electronic components, a display device and a semiconductor device including the substrate for electronic components, wherein the substrate for electronic components comprises: a substrate including one or more through-core through holes; and a close contact enhancement layer provided on the surface of the substrate and the through-core through holes, wherein the aperture of one or more of the upper and lower surfaces of the through-core through holes is larger than the aperture of a point inside the hole.

[0047] In more detail, it relates to a method for manufacturing a substrate for electronic components that improves the adhesion of gold plating, comprising: (a) forming a adhesion-enhancing layer on the surface of a substrate including one or more through-core through holes; and (b) plating gold metal on the surface of the substrate on which the adhesion-enhancing layer is formed, wherein the aperture of one or more of the upper and lower surfaces of the through-core through holes is larger than the aperture of a point inside the hole, and the gold plating step of (b) is performed by one or more methods selected from electrolytic gold plating and electroless gold plating. According to the present invention, the adhesion-enhancing layer can be formed by a wet coating method. In addition, accordingly, compared with a general sputtering method, a more uniform thin film can be formed inside the core through hole, the incidence of defects can be reduced when forming metal wiring, and there are advantages such as being able to reduce manufacturing costs and maintenance costs.

[0048] According to the substrate for electronic components and the manufacturing method thereof of the present invention, the through-core through hole can have a shape in which the hole diameter of one or more of the upper and lower surfaces is larger than the hole diameter of a point inside the hole. Accordingly, when the volume of the metal inside the hole of the through-core through hole expands / contracts, the impact concentration on the metal plated inside the core through hole in any side direction of the upper or lower surface of the hole can be prevented, thereby preventing the electrode from warping under harsh conditions.

[0049] Although the display device and the semiconductor device including the substrate for electronic components have been described by one or more embodiments of the present invention, the present invention is not limited thereto and can be used without limitation in a plurality of fields to which the substrate for electronic components and its manufacturing method can be applied.

[0050] Hereinafter, embodiments of the present invention will be described more specifically with reference to the accompanying drawings. However, the following drawings attached to this specification only illustrate preferred embodiments of the present invention and, together with the foregoing description of the invention, serve to better understand the technical idea of the present invention. Therefore, the present invention should not be construed as limited to the matters described in such drawings.

[0051] As used in this specification, the terms "comprises", "comprising", and "having" are used in a sense that does not exclude the presence or addition of one or more other elements, steps, acts, and / or components other than those recited. Throughout the specification, the same reference numerals refer to the same components.

[0052] Spatially relative terms, such as "below", "bottom surface", "lower part", "above", "top surface", "upper part", etc., may be used to facilitate the description of the relative relationship between one element or component and another element or component as shown in the figures. Spatially relative terms should be understood to include terms that describe different directions of elements relative to each other when in use or operation, in addition to the directions shown in the figures. For example, when an element shown in the figures is flipped, an element described as "below" or "lower part" of another element may be located "above" the other element. Therefore, the exemplary term "below" can include both the below and above directions. The element may also face another direction, and accordingly, the spatially relative terms may be interpreted according to the orientation.

[0053] In addition, the described "surface" includes not only the upper and lower sides of an object in space but also all outwardly exposed outer portions. For example, the "surface of a substrate including a through-core via hole" may be interpreted as a term that includes the upper and lower surfaces of the substrate and the inner (or internal) wall surface of the core via hole.

[0054] As used in this specification, "substantially" can be interpreted to include not only physically identical or consistent cases but also cases within the error range in measurement or manufacturing processes, for example, it can be interpreted as an error range of 0.1% or less.

[0055] <Substrate for Electronic Components>

[0056] The present invention relates to a substrate for electronic components, comprising: a substrate including one or more through-core through holes; and a close contact promotion layer, which is arranged on the surface of the substrate and the through-core through holes. In particular, the substrate can be selected from glass or quartz. According to the adhesion test based on the international standard ASTM D3359, the gold plating close contact of the electronic component substrate manufactured according to one embodiment of the present invention can be 4B or more, but is not limited thereto. The electronic component substrate of the present invention can further include a metal gold plating layer on the close contact promotion layer.

[0057] The through-core through hole of the present invention can have a shape in which the aperture of one or more of the top and bottom surfaces can be larger than the aperture of a point inside the hole. Accordingly, when the volume of the metal inside the hole of the through-core through hole expands / contracts, the impact concentration on the metal plated inside the core through hole in any side direction of the top or bottom of the hole can be prevented, thereby preventing the electrode from warping under harsh conditions.

[0058] Preferably, the electronic component substrate of the present invention can be produced by the method described in “the method for producing the electronic component substrate” to be described later.

[0059] substrate

[0060] The electronic component substrate of the present invention can be made of a material with low conductivity such as glass, quartz, polyimide, etc. In particular, from the perspective of excellent chemical durability and optical properties, it is preferred to use a glass or quartz material as the substrate. From the same perspective, it is more preferred to select a glass material than quartz.

[0061] Figure 1 1 is a cross-sectional view showing a substrate including a through-core through hole according to an embodiment of the present invention. Figure 2 This is a cross-sectional view showing a substrate having an adhesion promoting layer formed thereon, among the electronic component substrates of the present invention. Figure 3 2 is a cross-sectional view of a substrate having a close adhesion promoting layer and a metal electrode layer formed thereon in the electronic component substrate of the present invention. Figures 1 to 3 , the hourglass-shaped through-core through hole described later is not shown)

[0062] According to one embodiment of the present invention, the substrate is preferably as follows Figure 1 The glass substrate 10 includes one or more through-core through holes. The glass substrate has excellent characteristics in terms of versatility and durability. The composition used to manufacture the glass substrate is not particularly limited and can be selected according to the desired use. For example, the glass substrate can be made of a material including Corning Glass, Eagle XG TMGlass formation suitable for electronic devices such as glass, NSG soda-lime glass, NEG glass, or Code 2318 glass. However, the present invention is not limited thereto, and other types of ion-exchangeable glass or fused quartz can also be used to form the glass substrate.

[0063] In addition, processes commonly used in the art can be applied to manufacture a substrate with a through-core via hole by drilling a through-core via hole in the substrate. The shape and size of the substrate are not limited and can be quadrilateral, circular, etc., but a quadrilateral may be advantageous from a process perspective. In addition, the average thickness of the substrate can be selectively used without limitation as needed, but for UTG (Ultra thin glass), its thickness can be 30 μm or more and 100 μm or less, while for substrates for communication, display devices, and semiconductors, its thickness can be up to 1100 μm, and preferably can be 250 to 700 μm. When the thickness of the substrate satisfies the above range, it is preferred from the perspective of durability.

[0064] The through-core via hole can be a through type with holes formed on both the upper and lower surfaces and having side walls, and its horizontal cross-section can be circular, elliptical, or polygonal, but is not limited thereto. In addition, the shape of the horizontal cross-section of the upper and / or lower surface can be the same as or different from the horizontal cross-section inside the hole. Preferably, the horizontal cross-sections of the upper surface, lower surface, and inside of the hole of the through-core via hole can be circular. In addition, the through-core via hole of the present invention can be used to enable filling with a conductive material such as copper or other metals through the hole of the core via hole without inserting components to maintain electrical characteristics. The through-core via hole can be formed on the substrate by any suitable method, for example, drilling can be performed on the substrate using a pulsed laser. The average of the diameters of one or more of the upper and lower surfaces of each through-core via hole can be 5 to 190 μm, and most preferably 20 to 50 μm. When the above range is satisfied, a gold plating layer can be uniformly formed, and electrical interference can be prevented. In the present invention, for the "hole diameter" of the through-core via hole, when the through-hole of the horizontal cross-section is circular, it refers to the diameter; when it is not circular, it can be the length of the longest line segment connecting any two points of the horizontal cross-section of the through-hole. In the present invention, the "cross-sectional area" of the through-core via hole can refer to the area of the horizontal cross-section of the through-hole.

[0065] Figure 4 It is a cross-sectional view of a substrate including a through-core via hole showing an embodiment of the present invention. Figure 5 It is a cross-sectional view of a substrate with a close contact enhancing layer formed in the substrate for electronic components of the present invention. Figure 6 It is a cross-sectional view of a substrate with a close contact enhancing layer and a metal electrode layer formed in the substrate for electronic components of the present invention (showing an hourglass-shaped through-core via hole).Figure 7 This is a diagram showing a vertical cross-section of the through-core via hole of the present invention, which respectively shows the aperture diameter at the top, the aperture diameter at a point inside the hole, and the aperture diameter at the bottom. The core via hole of the present invention can be composed of the top, the bottom, and the hole interior (synonymous with "inner side") connecting the top and the bottom. In an example of the present invention, referring to Figures 4 to 7 , the diameter of the hole of the core via hole at a point inside the through-core via hole can be smaller than the diameter of the hole of the core via hole at the top and the diameter of the hole of the core via hole at the bottom. Alternatively, in an example of the present invention, the cross-sectional area of the core via hole at the top and the bottom can be larger than the cross-sectional area at a point inside the hole. More specifically, it can be a form in which the cross-sectional area or aperture diameter of the hole of the core via hole becomes smaller from the top and the bottom towards the hole interior. Thus, since there is a point with a smaller cross-sectional area or aperture diameter inside the hole, when the substrate of the present invention is subjected to an external physical impact, or when the volume of the metal inside the through-core via hole expands / contracts due to temperature / humidity, it is possible to prevent the impact concentration from occurring in any one side direction of the top or the bottom of the hole for the metal plated inside the core via hole, thereby preventing the metal from detaching from the core via hole. Specifically, when the substrate is subjected to an external physical impact, or when the volume of the metal inside the hole expands / contracts due to temperature / humidity, electrode detachment will occur in the case of a conventional structure where the force will concentrate on one side direction of the top and the bottom, while the substrate of the present invention disperses the impact in two directions of the top and the bottom with a point having a smaller cross-sectional area or aperture diameter inside the hole as the center, thereby preventing the metal from detaching from the core via hole.

[0066] In an embodiment of the present invention, the vertical cross-section of the through-core via hole of the present invention can be symmetric or asymmetric. In an embodiment of the present invention, the vertical cross-section of the through-core via hole of the present invention can be in the shape of an hourglass, and the hourglass can be symmetric or asymmetric.

[0067] When the core via hole of the present invention is symmetric, in the present invention, when the top of the line connecting the top and the bottom of the core via hole is 0% and the bottom is 100%, the point with the smallest cross-sectional area or hole diameter of the hole of the core via hole can be located at the point of 40 to 60%, but it is not limited thereto. When the core via hole of the present invention is asymmetric, in the present invention, when the top of the line connecting the top and the bottom of the core via hole is 0% and the bottom is 100%, the point with the smallest cross-sectional area or hole diameter of the hole of the core via hole can be located at the point of 15 to 35% or 65% to 75%, but it is not limited thereto.

[0068] More specifically, Figure 8 This is a diagram showing a vertical cross-section of the through-core via hole of the present invention, which shows the angle between the line connecting a point of the core via hole at the top or the bottom and the point with the smallest aperture diameter inside the via hole and the line connecting a point of the core via hole at the top or the bottom in the vertical direction. Referring to Figure 8, the through-core via hole of the present invention may include a form in which the angle between the line connecting a point on the upper or lower core via hole and the point with the smallest aperture inside the via hole in the vertical section and the line connecting a point on the upper or lower core via hole in the vertical direction is 1° to 25°, preferably 3° to 20°, and most preferably 5° to 18°. In this case, it is most conducive to achieving the object of the present invention.

[0069] In the present invention, as described above, the symmetric / asymmetric through-core via hole with a point having a smaller cross-sectional area or aperture inside the hole can be formed by adjusting the etching speed or ratio of the upper and lower surfaces when manufacturing the core via hole. For example, when etching the upper and lower surfaces of the substrate to form a through-core via hole, if etching is performed simultaneously from both the upper and lower surfaces, the etching exposure intensity weakens from the upper and lower sides toward the inside of the substrate, and accordingly, a symmetric hourglass-shaped core via hole can be formed. At this time, for etching, a well-known etching solution for etching the substrate can be used. For example, an etching solution composition containing hydrofluoric acid can be used, but it is not particularly limited. For example, the etching solution composition may include hydrofluoric acid, nitric acid, sulfuric acid, a surfactant as an additive, an antifoaming property control additive, and / or distilled water.

[0070] In addition, in another example of the present invention, if the etching time of one of the upper and lower surfaces is extended, an asymmetric hourglass-shaped core via hole can be formed.

[0071] The etching time varies depending on the thickness of the substrate. Taking the substrate from to as a reference, the etching can be performed for about 3 to 4 hours, but it is not limited thereto.

[0072] Regarding the formation of symmetric or asymmetric hourglass-shaped core via holes corresponding to the etching time, according to an example of the present invention, when performing etching that exposes both the upper and lower surfaces simultaneously, a symmetric hourglass-shaped core via hole can be formed.

[0073] In addition, in order to form an asymmetric hourglass-shaped core via hole, the degree of exposure of the upper and lower surfaces of the substrate to the etching solution composition can be adjusted. For example, a method of horizontally opposing the substrate to the etching solution composition on the surface where the distance to the interval with the smallest aperture is set shorter among the upper and lower surfaces can be used to adjust the asymmetric ratio of the hourglass shape. That is, a method of floating the substrate on the etching solution composition and adjusting it to be horizontally opposed to the etching solution composition can be adopted.

[0074] In addition, although not particularly limited, in order to adjust the degree of exposure of the upper and lower surfaces of the substrate to the etching solution composition to be different from each other, a fixture with acid resistance (such as polytetrafluoroethylene, etc.) can be used on one of the upper and lower surfaces to physically block the exposure of the etching solution composition.

[0075] The aperture diameter of the core through-hole on the upper surface of the core through-hole of the present invention and the aperture diameter of the core through-hole on the lower surface may be the same as or different from each other. In addition, when the substrate of the present invention includes a plurality of core through-holes, the shape or aperture diameter of each core through-hole may be the same as or different from each other. For example, design can be carried out by considering the contact area of elements or wirings located on the upper side and / or the lower side of the substrate of the present invention, components connected to RDL (redistribution layer) or PAD (pad), connection terminals, etc. For example, when a wider upper electrical contact area is required or the lower electrical contact area is small, the shape of the core through-hole can be adjusted accordingly.

[0076] Figure 9 FIG. shows a vertical cross-section of the through-core through-hole of the present invention, in which the inner wall surface of the through-core through-hole is shown in a form including irregularities. Specifically, the inner wall surface of the through-core through-hole of the present invention can be in a form with a wider surface area, for example, it can include repeated or non-repeated irregularities. Accordingly, by generating a three-dimensional anchoring effect on the metal plated inside the through-core through-hole of the present invention, the adhesion can be improved. That is, in the present invention, by increasing the roughness inside the through-core through-hole, the specific surface area is increased, and an effect of increasing the contact area when forming a metal electrode at the interface of the area increased (generated) due to the irregularities is imparted. The anchoring effect of the waviness of the surface irregularities and the lay also contribute to the improvement of the adhesion force aimed at by the present invention.

[0077] More preferably, compared with the inner wall surface of a conventional core through-hole that does not include irregularities, the specific surface area of the inner wall surface of the through-core through-hole of the present invention can be increased by 10 to 300%, preferably 50 to 300%, thereby providing a closely adherable interface for the metal formed inside the core. When the specific surface area exceeds the above range and increases excessively, the surface of the substrate will be porous, which may reduce the mechanical strength of the substrate.

[0078] In order to form the above-mentioned irregularities on the inner wall surface of the through-core through-hole of the present invention, a known method can be used. For example, by adjusting the etching rate using an ultrasonic cleaning method, the roughness of the inner wall surface of the through-core through-hole can be adjusted.

[0079] More specifically, in order to form the unevenness on the inner wall surface of the through-core via hole of the present invention as described above, ultrasonic vibration can be applied to the sample at a certain time interval by using the ultrasonic cleaning method to increase the etched shape adjustment and surface roughness as process variables. The ultrasonic cleaning is performed in a form of repeating on / off at a time interval, and this can adjust the time to reach the balance of the composition by adjusting the circulation of the internal etching solution composition to adjust the concentration. Immediately perform etching corresponding to this concentration. When the concentration decreases, it can help the circulation of the solution outside the etching part where the high-concentration etching solution composition is located to adjust so that the concentration of the etching solution composition increases in a certain proportion. By using it as a process factor in such a way that the time point for removing the residues after etching is appropriately adjusted to the time point of ultrasonic on / off, the unevenness as described above can be formed on the inner wall surface of the through-core via hole.

[0080] Specifically, the higher the aspect ratio of the average thickness of the substrate relative to the aperture diameter of the core via hole, the more the integrated circuit performance of the semiconductor device can be improved, and the packaging size and stress effect can be reduced. However, the higher the aspect ratio, the more difficult it is to metallize the side walls of the core via hole. When the aperture diameter of the core via hole is too small, there is a disadvantage that voids may be caused during the process of filling the core via hole with a conductive material. Therefore, in an embodiment of the present invention, the aspect ratio of 1:10 to a maximum of 1:30 is most preferable in terms of the easiness of the process and the performance of the semiconductor device.

[0081] Regarding the number of the core via holes used, it is preferably 1 to 5,000 per square centimeter of the substrate for an electronic component substrate that is suitable for maintaining low resistance while having sufficient conductivity, but it is not limited thereto, and the substrate formed with the core via holes can be used without limitation according to needs. For example, when the density of the core via holes is low, the number can be more than 1 and less than 400 per square centimeter of the substrate.

[0082] adhesion promoting layer

[0083] Figure 2 An embodiment of the substrate of the present invention formed with the adhesion promoting layer is shown. As Figure 2As shown, the intimate adhesion promoting layer 20 can be formed by directly contacting the surface of the substrate 10, and can be used to improve the adhesion force of the metal plating layer formed by a subsequent gold plating process. The intimate adhesion promoting layer may include one or more selected from the group consisting of UV curable resins having an acrylic group and polyimide-based thermosetting resins as polymer substances, which can be polymerized by appropriate light or heat. The intimate adhesion promoting layer of the present invention includes a film coated with metal, oxide, and / or ceramic oxide. In this case, the substances included in the intimate adhesion promoting layer are not limited to specific substances such as organic substances, inorganic substances, metals, and oxides, but can be configured in a form of continuously laminated organic and / or inorganic substances. In addition, the intimate adhesion promoting layer of the present invention can be a thin film coated (deposited) by methods such as sputtering or chemical vapor deposition (CVD), and the thin film may include ITO, IZO, AZO, IGZO, CuO, and / or TiO 2 .

[0084] The UV curable resin can be used without limitation a substance known in the industry as being usable for negative photoresists, but a UV curable resin having an acrylic group is more preferable in terms of excellent adhesion to the substrate surface and ensuring the interfacial adhesion force with the metal included in the metal plating layer, and thus having excellent adhesion of the upper and lower coatings based on the intimate adhesion promoting layer.

[0085] The polyimide-based thermosetting resin is more preferably used for forming the intimate adhesion promoting layer of the substrate for electronic components because its cured product has good heat resistance, solvent resistance, chemical resistance, mechanical properties, electrical insulation properties, etc. There is no strict limitation on the weight average molecular weight (measured by GPC) of the polyimide, but for example, it can be 1,000 g / mol or more and 200,000 g / mol or less, or 10,000 g / mol or more and 200,000 g / mol or less.

[0086] In addition, the intimate adhesion promoting layer can be made by curing after coating a composition further including a photopolymerizable compound, a photopolymerization initiator, a thermosetting agent, a solvent, and / or an additive, etc. in the polymer substance.

[0087] The photopolymerizable compound is a compound that can be polymerized by the action of the following photopolymerization initiator, and a monofunctional monomer or a monomer having two or more functional groups can be used, and preferably a polyfunctional monomer having two or more functional groups can be used.

[0088] Specific examples of the monofunctional monomer include, but are not limited to, nonylphenoxy carbitol acrylate, 2-hydroxy-3-phenoxy acrylate, 2-ethylhexyl acrylate, 2-hydroxyethyl acrylate, N-vinylpyrrolidone, etc.

[0089] Specific examples of the monomer having two or more functional groups include, as a bifunctional monomer, 1,6-hexanediol di(meth)acrylate, ethylene glycol di(meth)acrylate, neopentyl glycol di(meth)acrylate, triethylene glycol di(meth)acrylate, bisphenol A bis(acryloyloxyethyl) ether, 3-methylpentanediol di(meth)acrylate, etc., and as a monomer having three or more functional groups, trimethylolpropane tri(meth)acrylate, ethoxylated trimethylolpropane tri(meth)acrylate, propoxylated trimethylolpropane tri(meth)acrylate, pentaerythritol tri(meth)acrylate, pentaerythritol tetra(meth)acrylate, dipentaerythritol penta(meth)acrylate, ethoxylated pentaerythritol hexa(meth)acrylate, propoxylated pentaerythritol hexa(meth)acrylate, pentaerythritol hexa(meth)acrylate, etc., but are not limited to these.

[0090] The photopolymerizable compound may be contained in an amount of more than 30% by weight but less than 95% by weight based on 100% by weight of the entire composition. Preferably, when the content is in the range of more than 40% by weight but not more than 90% by weight, the photoconversion efficiency, curing degree, and dispersion stability are improved, so that there are preferable advantages in terms of the strength or smoothness of the pixel portion. If the content of the photopolymerizable compound is lower than the above range, it is difficult to ensure the fluidity for inkjet; if the content exceeds the above range, problems such as a decrease in the adhesion force may occur, so the content is preferably within the above range.

[0091] The photopolymerization initiator can be used without particular limitation in terms of type as long as it can polymerize the photopolymerizable compound. For example, considering polymerization characteristics, initiation efficiency, absorption wavelength, solubility, price, etc., it is preferable to use the photopolymerization initiator as one or more compounds selected from the group consisting of acetylacetone compounds, benzophenone compounds, triazine compounds, imidazole compounds, oxime compounds, thione compounds, and phosphorus oxide compounds.

[0092] For example, using an oxime compound or a phosphorus oxide compound can ensure more excellent physical properties in terms of the curing density and surface roughness of the cured film. Specific examples of the oxime compound can include o-ethoxycarbonyl-α-oximino-1-phenylpropan-1-one, etc., and representative commercially available products include Irgacure OXE 01 and OXE 02 from BASF Corporation.

[0093] Specific examples of the representative phosphorus oxide compounds include trimethylbenzoyl phenylphosphine oxide, such as Darocur TPO of BASF Corporation, Lucirin TPO, diphenyl(2,4,6-trimethylbenzoyl)phosphine oxide of TCI Corporation, and the like.

[0094] The photopolymerization initiator may be contained in an amount of 0.1 to 10% by weight, preferably 0.5 to 8% by weight, based on 100% by weight of the entire composition. When the content of the photopolymerization initiator is within the above range, sufficient curing can be achieved by light or heat, thereby forming an adhesion promoting layer having excellent physical properties such as hardness. Moreover, since the composition is highly sensitized, the exposure time is shortened, and thus the productivity can be improved. Therefore, it is preferred.

[0095] The photopolymerization initiator may further include a photopolymerization initiator assistant to improve the sensitivity of the composition of the present invention. When the photopolymerization initiator assistant is included, the sensitivity is further improved, thereby having the advantage of improved productivity. The photopolymerization initiator assistant may preferably be used, for example, one or more compounds selected from the group consisting of amine compounds, carboxylic acid compounds, and organic sulfides containing mercaptan, but is not limited thereto. The photopolymerization initiator assistant may be appropriately added within the range that does not impair the effects of the present invention.

[0096] The heat curing agent can be activated by heat, and examples include phenolic resins such as phenol-formaldehyde resin, trifunctional phenol-formaldehyde resin, cresol-formaldehyde resin, bisphenol A phenol-formaldehyde resin, xylenol-formaldehyde resin, triphenyl phenol-formaldehyde resin, non-phenyl phenolic resin, dicyclopentadiene phenol-formaldehyde resin, naphthalene phenolic resin, phenol-p-xylene resin, phenol-4,4'-dimethylbiphenyl resin, phenolic dicyclopentadiene novolac resin, dicyclopentadiene-phenol resin (DCPD-phenol), new phenolic resin (xylok, p-xylene modified), triazine compounds, dihydroxynaphthalene, dihydroxybenzene and other phenolic resin curing agents; aliphatic anhydrides such as dodecenyl succinic anhydride (DDSA), poly azelaic poly anhydride; alicyclic anhydrides such as hexahydrophthalic anhydride (HHPA), methyltetrahydrophthalic anhydride (MeTHPA), methylnadic anhydride (MNA); aromatic anhydrides such as Trimellitic Anhydride (TMA), pyromellitic acid dianhydride (PMDA), benzophenonetetracarboxylic dianhydride (BTDA) and other anhydride curing agents; amine curing agents such as 4,4'-dimethylaniline (diamino diphenyl methane, DAM or DDM), diaminodiphenyl sulfone (DDS), dicyandiamide (DICY), etc., but are not limited thereto. The content of the heat curing agent can be appropriately selected and used according to the amounts commonly used in the technical field, and no special limitation is imposed thereon.

[0097] No special limitation is imposed on the solvent, as long as it can make the cured resin have appropriate viscosity, can easily dissolve the remaining components, and will not damage the substrate. Various organic solvents used in the field of manufacturing substrates for electronic components can be used.

[0098] Specific examples of the solvent may include ethylene glycol monoalkyl ethers such as ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol monopropyl ether, and ethylene glycol monobutyl ether; diethylene glycol dialkyl ethers such as diethylene glycol dimethyl ether, diethylene glycol diethyl ether, diethylene glycol dipropyl ether, and diethylene glycol dibutyl ether; ethylene glycol alkyl ether acetates such as ethylene glycol methyl ether acetate and ethylene glycol ethyl ether acetate; propylene glycol dialkyl ethers such as propylene glycol monomethyl ether; alkylene glycol alkyl ether acetates such as propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, propylene glycol monopropyl ether acetate, methoxybutyl acetate, and methoxypentyl acetate; aromatic hydrocarbons such as benzene, toluene, xylene, and mesitylene; ketones such as methyl ethyl ketone, acetone, methyl amyl ketone, methyl isobutyl ketone, and cyclohexanone; alcohols such as ethanol, propanol, butanol, hexanol, cyclohexanol, ethylene glycol, and glycerol; esters such as ethyl 3-ethoxypropionate and methyl 3-methoxypropionate; cyclic esters such as γ-butyrolactone, etc.

[0099] Among the above solvents, from the viewpoints of coatability and drying property, preferably, organic solvents having a boiling point of 100 to 200 °C can be mentioned. More preferably, alkylene glycol alkyl ether acetates, ketones, esters such as ethyl 3-ethoxypropionate or methyl 3-methoxypropionate can be mentioned. More preferably, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate, propylene glycol monoethyl ether acetate, cyclohexanone, ethyl 3-ethoxypropionate, methyl 3-methoxypropionate, etc. can be mentioned.

[0100] In addition, the above solvent may include an aprotic solvent. For example, it preferably includes one or more polar aprotic solvents selected from acetone, acetonitrile, m-cresol, tetrahydrofuran (THF), N-methyl-2-pyrrolidone (NMP), N,N-dimethylformamide (DMF), N,N-dimethylacetamide (DMAc), dimethyl sulfoxide (DMSO), and ethyl acetate.

[0101] The above solvents can be used alone or in combination of two or more. When they are contained in an amount of 30 to 70% by weight based on 100% by weight of the composition, when coating is performed using a coating device such as a roll coater, a spin coater, a slot spin coater, a dip coater, a slot coater (sometimes also called a slot die coater), or an inkjet printer, it will provide an effect of improved coatability, and thus is preferred.

[0102] In addition, in order to improve the flatness or close contact property of the close contact promoting layer, additives commonly used in the art may further be included within the scope not departing from the object of the present invention. Specifically, a leveling agent, an antifoaming agent, a surfactant, a close contact promoting agent, an ultraviolet absorber, an anti-aggregation agent, and / or a dispersing agent, etc. may further be included. These additives may also be appropriately added by those skilled in the art within the scope not impairing the effects of the present invention.

[0103] As the above-mentioned surfactant, a fluorine-based surfactant, etc. may further be included. When the above-mentioned surfactant is included, it has the advantage of being able to improve the flatness of the coating film. In addition, when two or more surfactants having different particle sizes and structures are used in combination, it has the advantage of being able to be uniformly ejected during inkjet ejection, and is more advantageous in terms of the effect of protecting in a manner that can prevent oxygen or moisture from penetrating into the substrate during the process. For example, the above-mentioned fluorine-based surfactant may be BM-1000, BM-1100 (BM Chemie), fluorad FC-135 / FC-170C / FC-430 (Sumitomo 3M Co., Ltd.), SH-28PA / -190 / -8400 / SZ-6032 (Dow Corning), Megaface F-554 / Megaface F-559 / Megaface F-563 (DIC Corporation), etc., but is not limited thereto.

[0104] The above-mentioned dispersing agent is a kind of surfactant, which is used to uniformly disperse the solid components in the solvent, so as to obtain high-density fluidity to ensure the best dispersibility in the process. As long as it is a dispersing agent commonly used in the art, it may be included without limitation.

[0105] The above-mentioned close contact promoting agent can be added to improve the close contact property with the substrate, and it may include a silane coupling agent having a reactive substituent selected from the group consisting of a carboxyl group, a methacryloyl group, an isocyanate group, an epoxy group, and combinations thereof, but is not limited thereto. Specifically, vinyltrimethoxysilane, vinyltriethoxysilane, vinyltris(2-methoxyethoxy)silane, N-(2-aminoethyl)-3-aminopropylmethyldimethoxysilane, N-(2-aminoethyl)-3-aminopropyltrimethoxysilane, 3-aminopropyltriethoxysilane, 3-glycidoxypropyltrimethoxysilane, 3-glycidoxypropylmethyldimethoxysilane, 2-(3,4-epoxycyclohexyl)ethyltrimethoxysilane, 3-chloropropylmethyldimethoxysilane, 3-chloropropyltrimethoxysilane, 3-methacryloxypropyltrimethoxysilane, 3-mercaptopropyltrimethoxysilane, etc. may be used, but is not limited thereto.

[0106] The above additives can be used in an amount of 0.01 to 10% by weight, specifically 0.02 to 8% by weight, more specifically 0.03 to 5% by weight, but not limited thereto, based on 100% by weight of the entire composition. When the above additives are included within the above range, the coatability, flatness, adhesion, etc. of the above composition can be improved, and thus it is preferred.

[0107] In one embodiment, the thickness of the adhesion promoting layer 20 can be 250 to Preferably 500 to More preferably it can be 1000 to From the aspect of improving the adhesion of the gold plating layer provided on the adhesion promoting layer, it is preferred that the thickness of the adhesion promoting layer satisfies the above range.

[0108] By coating the adhesion promoting layer between the metal gold plating layer and the glass substrate, the adhesion of the metal gold plating layer to the glass substrate can be improved. This is because when forming an electrode using a substrate including a through-hole type via hole, improving the adhesion between the electrode and the glass substrate has the effect of preventing warping and substrate deformation caused by thermal shock and / or thermal deformation during the process, thereby ensuring the reliability of the electrode, and is effective in improving the durability of the substrate, such as increasing physical adhesion and preventing corrosion caused by moisture and / or gas, etc. The gold plating adhesion of the substrate for electronic components of the present invention is preferably 4B or more. When the gold plating adhesion of the metal gold plating layer is lower than the above range, problems may occur in the durability of the substrate for electronic components and the semiconductor package including the same. The gold plating adhesion can be 4B or more, and more preferably 5B from the aspect of durability. This can be evaluated according to the standard of ASTM D3359 which is an international standard method. According to the evaluation standard of the above international standard, the adhesion of the metal gold plating layer in one embodiment of the present invention can be such that no peeling phenomenon is observed during evaluation, or a peeling phenomenon is observed in an area of less than 5% of the target area.

[0109] metal plating layer

[0110] Referring to Figure 3 , a substrate for electronic components in one embodiment of the present invention may have a metal gold plating layer formed on the surface of the adhesion promoting layer.

[0111] Regarding the gold plating layer, as long as it includes a conductive metal, there is no special limitation. However, from the aspects of low cost, productivity, ease of maintenance and management, etc., in terms of process ease, it is preferred that the gold plating layer is made of metal ink. Specifically, when forming the metal gold plating layer including the metal ink, the production time can be shortened compared with the case of including ordinary metals when forming a sufficient gold plating layer thickness, low resistance can be achieved, and it is suitable for forming a metal layer on a complex structure such as a core via hole where it is difficult to adopt the ordinary photolithography method. The metal ink is composed of metal nanoparticles with consistent size and shape dispersed in alcohol and / or hydrocarbon series solvents, and preferably the metal nanoparticles contain 3 to 50 wt% relative to the total weight of the dispersion liquid. The metal nanoparticles can be conductive silver, gold, nickel, copper or their combinations, etc. In terms of copper, it is advantageous from an economic aspect, and its conductivity is excellent compared with other metals, so it is more preferred. The particle size of the metal nanoparticles can be 100 nm or less, and preferably 30 to 60 nm from the aspect of process ease. The solvent can include the usual solvents used in the art. More preferably, alcohol compounds such as methanol, ethanol, isopropyl alcohol, butanol, propylene glycol methyl ether, etc.; and hydrocarbon compounds such as hexane, heptane, benzene, toluene, xylene, ethylenes, acetate esters, etc. can be used alone or in combination of two or more.

[0112] <Method for manufacturing a substrate for electronic components>

[0113] The method for manufacturing a substrate for electronic components according to the present invention is characterized by including: (a) a step of forming an adhesion promoting layer on the surface of a substrate including one or more through-type vias; and (b) a step of plating a metal on the surface of the adhesion promoting layer, and the plating step in (b) is performed by one or more methods selected from electrolytic plating and electroless plating.

[0114] In addition, in the method for manufacturing a substrate for electronic components according to the present invention, after the above step (b), it may further include: a photolithography process for realizing a circuit (step (c)), and the above step (b) may be further performed one or more times.

[0115] The manufacturing method of a substrate for electronic components according to one or more embodiments of the present invention includes: (a) a step of forming an adhesion promoting layer on the surface of a substrate including one or more through-core vias; and (b) a step of plating a metal on the surface of the substrate on which the adhesion promoting layer is formed, whereby the adhesion of the metal plating layer can be improved, and the aperture diameter of one or more of the upper and lower surfaces of the through-core via can be larger than the aperture diameter at a point inside the hole. In addition, after the above steps (a) and (b), as an additional process, it may further include step (c), that is, a subsequent step including a photolithography process; and before performing the above steps (a), (b), and (c) of the present invention, a step of drilling through-core vias on the substrate by improving the preparation process can be added. In particular, before the above step (a), it may further include a process of manufacturing a through-core via in which the aperture diameter of one or more of the upper and lower surfaces is larger than the aperture diameter at a point inside the hole by adjusting the etching rates of the upper and lower surfaces of the substrate. The preparation process can be applied as it is to the content described for the substrate of the above <substrate for electronic components>, so it will not be elaborated.

[0116] (a) Step of forming an adhesion promoting layer on the surface of a substrate including one or more through-core via holes

[0117] The step of forming the adhesion promoting layer of the present invention can be performed by coating a composition for forming the adhesion promoting layer.

[0118] The composition for forming the adhesion promoting layer of the present invention can be a composition including the resin and solvent described in the above <adhesion promoting layer> item.

[0119] According to one or more embodiments of the present invention, as described in <substrate for electronic components>, the substrate on which the adhesion promoting layer is formed can use a material selected from glass or quartz, and glass material is preferably selected in terms of coatability, optical properties, chemical durability, etc.

[0120] In addition, the above coating methods include coating processes such as spin coating, roll coating, bar coating, dip coating, gravure coating, curtain coating, die coating, spray coating, knife coating, kneading coating, etc.; printing processes such as screen printing, spray printing, inkjet printing, letterpress printing, gravure printing, lithographic printing, etc.; IML (In-Mold Labeling) injection molding method, and deposition processes such as CVD (chemical vapor deposition), PVD (physical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), etc. According to an embodiment of the present invention, when coating a coating liquid to form a uniform coating film to form an adhesion enhancement layer, various wet coating methods such as slot die coating, spin coating, dip coating, bar coating, spray coating, etc. in the above methods can be used without limitation. From the aspects of coatability and processability, it is preferably carried out especially by the slot die coating or spin coating method. Thus, by using wet coating to form the adhesion enhancement layer, the production speed is increased compared with the conventional sputtering method, thereby ensuring productivity, and having the advantages of realizing a low-cost and high-efficiency process.

[0121] According to an embodiment of the present invention, before coating the adhesion enhancement layer, a surface modification process for pretreatment purposes may further be included. Preferably, the surface modification includes saponification treatment, plasma treatment, corona treatment, primer treatment, etc. From the aspect of process easiness, it is preferred to perform the corona treatment method. Thereafter, the coating film is heated and dried at a temperature of 50°C or higher and 150°C or lower, or 50°C or higher and 100°C or lower by heating means such as a hot plate, a hot air circulation furnace, an infrared furnace, etc. to volatilize the solvent. In order to cure the dried coating film by heat treatment, heat or light may be appropriately applied according to the type of the polymer substance contained, that is, the UV curable resin or the thermosetting resin. The light treatment may use g-line (wavelength: 436 nm), h-line, i-line (wavelength: 365 nm), etc. The irradiation amount of ultraviolet rays can be appropriately selected as needed, and no limitation is made thereto in the present invention. The heat treatment can be carried out by heating means such as a hot plate, a hot air circulation furnace, an infrared furnace, etc., and the temperature can be appropriately selected as needed within the range of 200°C or higher, preferably 200°C or higher and 300°C or lower, and no limitation is made thereto in the present invention.

[0122] (b) Step of plating a metal on the surface of the substrate on which the adhesion promoting layer is formed

[0123] The gold plating step of the present invention can be performed in a wet coating manner. In an embodiment of the present invention, this step can be a step performed using a metal ink. The metal ink can be applied without limitation to the content described in the above <metal gold plating layer> item.

[0124] According to an embodiment of the present invention, after forming a seed layer through the coating and sintering processes of the metal ink commonly used in the art, an electrolytic gold plating and electroless gold plating method to be described later can be used to form a metal gold plating layer. By gradually performing the above processes, in addition to the upper and lower surfaces of the glass substrate having a through-core via hole, a uniform and excellent adhesion metal gold plating layer can be formed on the inner wall of the core via hole.

[0125] Specifically, this step can be performed by one or more methods selected from electrolytic gold plating and electroless gold plating. In particular, since the present invention includes an adhesion enhancement layer in the substrate, even when no current is applied in the gold plating step and only a metal ink is used, a metal gold plating with a high adhesion can be uniformly performed on the through-core via hole portion of the substrate. In addition, of course, an electrolytic gold plating method with current application can also be applied in the present invention.

[0126] The electrolytic gold plating is not particularly limited as long as it is a method of electrolytic gold plating known in the art such as in the fields of electrical and electronic circuits, semiconductors, and / or communications. Specifically, the electrolytic gold plating step can be performed by applying a current after wet coating the metal ink on the surface of the substrate formed with the adhesion enhancement layer. When the metal ink is wet coated on the surface of the substrate formed with the adhesion enhancement layer, metal seeds can be formed on the adhesion enhancement layer. The metal ink can be coated by spin coating or the like.

[0127] The substrate on which metal seeds are formed by the above metal ink coating can be added to an electrolytic solution, and gold plating can be performed by applying a current. The electrolytic solution is not particularly limited as long as it includes electrolyte substances such as chloride ions, lithium ions, CuSO 4 , H 2 SO 4 etc. The current is preferably 0.5 to 20 ASD (amps / dm 2 ). When it is lower than the above range, the gold plating grains will become coarser, resulting in poor adhesion of the metal gold plating layer; when it exceeds the above range, an edge burning phenomenon will occur when the excess gold plating current concentrates on the edge portion, and there is a possibility that the operation cannot proceed smoothly.

[0128] The electroless gold plating method can coat the metal ink on the surface of the substrate formed with the adhesion promoting layer by a wet coating method, and can be carried out without further electrolyte treatment and / or without applying current. In the case of a substrate without an adhesion promoting layer, due to the low adhesion force, it is impossible to ensure the adhesion force and uniformity of gold plating on the glass substrate only by the electroless gold plating method. However, in the present invention, since the adhesion promoting layer is introduced on the substrate, it is possible to achieve uniform and highly adherent gold plating only by electroless wet gold plating without applying current.

[0129] In the present invention, the above step (b) can be repeated one or more times. When the above step (b) is repeated multiple times, a multi-layer laminate can be formed. In this case, an insulating film can be further included between the multi-layer laminates. Regarding the multi-layer laminate and / or the insulating film, the common structures or techniques in the art can be applied to the present invention without limitation. Accordingly, the film thickness of the metal gold plating layer can be adjusted as desired. Specifically, by further performing the above step (b) more than once, a metal gold plating layer with a thickness of about 10 μm can be manufactured. The above number of times and the final thickness of the metal gold plating layer may vary depending on the content of the metal ink and / or the coating method, etc.

[0130] (c) Subsequent steps

[0131] The manufacturing method of the substrate for electronic components of the present invention may further include a lithography process for implementing a circuit after the above step (b). The lithography process may apply known methods for forming patterns on a metal gold plating layer. For example, it may include PCB (Printed Circuit Board), COG (chip on Glass) for micro LEDs, or FEM (Front end module) substrates for high-frequency radio frequency (RF), etc. And sputtering processes such as PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), direct printing processes such as screen printing, gravure, gravure offset, or inkjet printing, coating processes, wet or dry gold plating processes, etc. may be applied. In particular, in order to achieve a desired pattern shape, a lithography etching method is preferably applied.

[0132] The lithography etching method is a method of forming a pattern through a series of processes known in the art, in which a photoresist is coated on a layer to be patterned, the coated photoresist is selectively cured using a mask, the uncured photoresist is developed and removed, then etching is performed to form a pattern, and the cured photoresist is removed. Photoresists can be classified into positive photoresists and negative photoresists. A positive photoresist is a photoresist that is soluble in a developer during UV (ultraviolet) exposure, and a negative photoresist is a photoresist that is insoluble in a developer during UV exposure. Therefore, when using a positive photoresist, the part exposed to UV can be developed and a pattern can be formed through subsequent processes; when using a negative photoresist, the part not exposed to UV can be developed and a pattern can be formed through subsequent processes. The conditions for curing the photoresist are not particularly limited. For example, it can be irradiated with UV of 0.01 to 10 J / cm 2 for 1 second to 500 seconds, and preferably it can be irradiated with UV of 0.05 to 1 J / cm 2 for 1 second to 120 seconds.

[0133] <Display devices and semiconductor devices including the substrate for electronic components>

[0134] In addition to the substrate for electronic components described above, the present invention also includes a display device and / or a semiconductor device manufactured by a post-process including known processes for manufacturing a display device and / or a semiconductor device. The display device and the semiconductor device are not particularly limited as long as they are executed by known methods used in the art. In addition, display devices including the substrate for electronic components include, for example, LCD (Liquid Crystal Display), PDP (Plasma Display Panel), FED (Field Emission Display), ELD (Electro-Luminescent Display), OLED (Organic LightEmitting Diode), etc. However, it includes not only ordinary liquid crystal display devices but also various image display devices such as field emission display devices, plasma display devices, and field emission display devices. The semiconductor package, semiconductor device, and display device including the substrate for electronic components have excellent integration and excellent electrical characteristics, can be applied to various devices commonly used in the art, and can exhibit excellent performance.

[0135] Embodiments of the Invention

[0136] Hereinafter, embodiments of the present invention will be specifically described. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms. In addition, these embodiments are provided only to complete the disclosure of the present invention and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the present invention. The present invention is defined only by the scope of the claims. Unless otherwise noted, "%" and "parts" in the examples are mass % and mass parts, respectively.

[0137] <Manufacture of Substrate for Electronic Components>

[0138] Example 1 Angle 5 to 10°, hourglass shape, three-dimensional effect (specific surface area increasing type)

[0139] (1) Preparation process - manufacturing process of a substrate having through-core via holes

[0140] Prepare a glass substrate (BDA-E, thickness 0.5 mm, Nippon Electric Glass Co., Ltd.) with a flat surface. The substrate is cleaned in an ultrasonic bath for 8 minutes at 70 °C using 2.5 vol% PK-LCG225X-1 detergent. Then it is rinsed with deionized water to remove organic residues, and in order to form core through-holes, defects are formed at predetermined positions on the glass surface. Specifically, the manufacturing of the core through-holes on the glass substrate is carried out as follows. The core through-hole etching position on the glass substrate is selectively irradiated with a 30 W-class laser with a wavelength of 904 to 1065 nm in the IR region. After that, in an immersion (deeping) method, the glass substrate is etched in a hydrofluoric acid etching solution, washed with ultrapure water, and dried, thereby fabricating a glass substrate with through-core through-holes formed therein.

[0141] Let the number of the core through-holes be 2 4,000 per 1 cm. The maximum outer diameter of the core through-holes is 87.3 μm, and the smallest part of the diameter inside the through-hole is 45 μm. In addition, for the substrate with core through-holes fabricated in this way, scribing is performed on the glass using a numerically controlled (CNC) laser device or a diamond glass cutter, and then breaking is carried out to expose the vertical cross-section. Then, it is observed using a microscope with the manufacturer being OLYMPUS and the model being STM7-MFA, and the results are as Figure 10 、 Figure 11 and Figure 14 shown. It is confirmed that the angle of the hourglass shape inside the core through-holes is 5 to 10°, and the inner wall with an increased specific surface area is confirmed.

[0142] (2) Formation of the adhesion promoting layer (step (a): wet coating)

[0143] Next, for the glass substrate with through-core through-holes formed, in order to perform surface modification, the surface is corona-treated using a corona treatment device (CTW series, WEDGE CO., LTD). Specifically, one treatment is carried out under the conditions of an output (treatment intensity) of 0.3 kW and a treatment speed of 3 m / minute.

[0144] After that, in order to make the final film thickness 1.5 μm, a close adhesion promoting layer material containing palladium (Pd) filler particles and a polyimide resin is used, and spin coating is carried out on the glass substrate at 2000 RPM for 20 seconds (1H-DX2, MIKASA). And it is cured on a hot plate at a temperature of 120 °C for 30 minutes. The thickness of the formed close adhesion promoting layer is measured using a field emission scanning electron microscope (FE-SEM, HITACHI, SU-8010), and the thickness of the close adhesion promoting layer formed on the upper and lower surfaces of the glass substrate is measured to be on average

[0145] (3) Metal plating process (step (b): electroplating)

[0146] After adding copper nanoparticles (average particle size 50 nm) at 40 wt% in an acetate solvent containing a part of Butyl Carbitol Acetate and dispersing them, a copper ink mixture was prepared. Then, the copper ink mixture was spin-coated on the glass substrate with the through-holes formed thereon at 2000 RPM for 20 seconds using a spin coater (1H-DX2, MIKASA), and then heated and dried (baked) in an oven at 80 °C for 5 minutes. Next, the dried copper ink pattern was irradiated with light using a xenon lamp (PulseForge 1300, NovaCentrix) to sinter it. At this time, the driving voltage of the light source was set to 650 V, and the intensity was about 8.91 J / cm 2 , and the irradiation pulse time was 1000 μsec.

[0147] The substrate was cleaned with a cleaning agent composed of EVP 221C (Dupont, 5 vol%) and 47% H 2 SO 4 (14.0 vol%) at room temperature for 10 seconds. Then, it was cleaned with deionized water (D.I. water) at room temperature for about 2 minutes, and pickled with 47% H 2 SO 4 (28.0 vol%) for 10 seconds. Then, gold plating was performed to form a copper-gold plating film on the surface of the glass substrate and inside the core through-holes. Specifically, the gold plating solution contained CuSO 4. 5H 2 O (75 g / L), H 2 SO 4 (190 g / L), Cl- (50 mg / L), ST-901C (0.5 vol%), and gold plating was performed at 2 ASD (Amps / dm 2 ) at room temperature for 35 minutes.

[0148] The sample after gold plating was cleaned with deionized water (D.I. water) at room temperature for about 2 minutes, and treated with OXIBAN 60 (0.5 vol%) for 30 seconds for rust prevention. Then, it was cleaned again with deionized water (D.I. water) at room temperature for about 1 minute, dried, and then annealed in a convection oven at 120 °C for 30 minutes.

[0149] Example 2 Angle 12 - 18°, hourglass shape, three-dimensional effect (specific surface area increasing type)

[0150] Let the number of the core through-holes be 4,000 per 1 cm 2 The outer diameter of the core through-holes is at most 80 μm, and the diameter of the smallest part inside the through-hole is 56 μm. By the above method, it was confirmed that the angle of the hourglass shape inside the core through-hole was 12 to 18°, and the inner wall with an increased specific surface area was confirmed.

[0151] Example 3 Angle 10 - 15°, asymmetric hourglass type, three-dimensional effect (specific surface area increasing type)

[0152] Let the number of the core through-holes be 4,000 per 1 cm 2 The diameter of the upper part of the core through-hole is 190 μm, the diameter of the lower part is 49 μm, and the diameter of the smallest part inside the through-hole is 35 μm. In addition, the substrate with core through-holes formed in this way was cut in the same method as above to expose the vertical cross-section, and then observed by the above method. The results are as Figure 12a and Figure 12b shown. It was confirmed that the angle of the hourglass shape inside the core through-hole was an asymmetric type of 10 - 15°, and the inner wall with an increased specific surface area was confirmed.

[0153] Example 4 Angle 25°, without adjusting the specific surface area

[0154] Let the number of the core through-holes be 4,000 per 1 cm 2 The outer diameter of the core through-holes is at most 80 μm, and the diameter of the smallest part inside the through-hole is 56 μm.

[0155] After exposing the vertical cross-section of the substrate with core through-holes formed in this way by the above method, it was observed by the above method. The results are as Figure 13 shown. It was confirmed that the angle of the hourglass shape inside the core through-hole was a symmetric type of 25°, and the inner wall with no increased specific surface area was confirmed.

[0156] Comparative Example 1

[0157] Except for omitting step (a) of the formation process of the close contact promoting layer, the electronic component substrate of Comparative Example 1 was manufactured by the same method as the manufacturing method of the electronic component substrate of Example 1 above.

[0158] Comparative Example 2

[0159] Except for omitting step (a) of the formation process of the close contact promoting layer and applying the following sputtering method (step (b')) instead of step (b), the electronic component substrate of Comparative Example 2 was manufactured by the same method as the manufacturing method of the electronic component substrate of Example 1 above.

[0160] Step (b'): plating process - sputtering method

[0161] After cleaning a glass substrate with a formed close contact enhancement layer using a standard cleaning process, titanium (Ti) is sputtered twice on the front and back of the glass substrate respectively using a DC Magnetron Sputter to form a film layer. Then, a voltage with an argon (Ar) partial pressure of 10 sccm, a sputtering pressure of 3 mTorr, and a DC power of 100 W is applied to form a film with a thickness of . The film thickness was confirmed by a scanning electron microscope (SEM). After the titanium (Ti) film layer is completed, copper (Cu) is sputtered in the same manner as above to form a film layer with a thickness of .

[0162] The substrate is cleaned with a cleaning agent composed of EVP 221C (Dupont, 5 vol%) and 47% H 2 SO 4 (14.0 vol%) at room temperature for 10 seconds. Then, it is cleaned with deionized water (D.I. water) at room temperature for about 2 minutes, and pickled with 47% H 2 SO 4 (28.0 vol%) for 10 seconds.

[0163] Then, gold plating is performed to form a copper-gold plating film on the surface of the glass substrate and inside the holes of the core through-holes. Specifically, the gold plating solution contains CuSO 4.5 H 2 O (75 g / L), H 2 SO 4 (190 g / L), Cl- (50 mg / L), ST-901C (0.5 vol%), and gold plating is performed at 2 ASD (Amps / dm 2 ) at room temperature for 35 minutes.

[0164] The sample after gold plating is cleaned with deionized water (D.I. water) at room temperature for about 2 minutes, and treated with OXIBAN 60 (0.5 vol%) for 30 seconds for rust prevention. Then, it is cleaned again with deionized water (D.I. water) at room temperature for about 1 minute, dried, and then annealed in a convection oven at 120 °C for 30 minutes.

[0165] Comparative Example 3 Angle 0 - Cylindrical

[0166] Let the number of the core through-holes be per 1 cm 24,000 were formed, and the outer diameter of the upper / lower surface of the core through-hole and the diameter inside the through-hole were 56 μm.

[0167] Experimental example

[0168] (1) Gold plating adhesion evaluation

[0169] An adhesion test was conducted on the surface of the substrates for electronic components manufactured according to the above-described examples and comparative examples in accordance with the ASTM D3359 standard, which is the CrossCut international standard method. Specifically, in 100 1 mm * 1 mm grid scales formed on the surface of the substrate for electronic components, the degree of the peeled part after the tape adhesion test was observed, and the adhesion degree was evaluated with values from 0B to 5B. The results are shown in Table 1 below.

[0170] <Evaluation criteria>

[0171] 5B: No peeling occurred in the entire area of the test piece.

[0172] 4B: A state where peeling occurred in less than 5% of the entire area of the test piece.

[0173] 3B: A state where peeling occurred in more than 5% and less than 15% of the entire area of the test piece.

[0174] 2B: A state where peeling occurred in more than 15% and less than 35% of the entire area of the test piece.

[0175] 1B: A state where peeling occurred in more than 35% and less than 65% of the entire area of the test piece.

[0176] 0B: A state where peeling occurred in more than 65% of the entire area of the test piece.

[0177] In addition, the above results were judged according to the following criteria and are recorded in Table 1 below.

[0178] <Judgment criteria>

[0179] OK (qualified): Gold plating adhesion is 4B or more

[0180] NG (unqualified): Gold plating adhesion is less than 4B

[0181] (2) Average thickness of the gold plating layer

[0182] The average thickness of the gold plating layer confirmed by scanning electron microscope (SEM) was measured and is recorded in Table 1 below.

[0183]

Table 1

[0184]

[0185] (3) Reliability assessment

[0186] The reliability of the examples and comparative examples was evaluated according to the following Korean industry standard (KS) test methods, and the results are shown in Table 2.

[0187] When electrode floating and / or electrode corrosion was confirmed, "NG (not qualified)" was recorded; otherwise, "qualified (OK)" was recorded.

[0188] <Korean industry standard (KS) test methods>

[0189] High temperature and high humidity for 500 HR at 60 / 93: IEC60068-2-3 (high temperature and high humidity test), KS C 0222 (high temperature and high humidity test)

[0190] Low temperature test for 240 HR: IEC60068-2-1 (low temperature test), KS C 0220 (low temperature test); High temperature test for 240 HR: IEC60068-2-2 (high temperature test), KS C 0221 (high temperature test)

[0191] Temperature and humidity cycle test from -20 to 60 °C for 72 HR: IEC60068-2-30 (temperature and humidity cycle test), Ks C 0227 (temperature and humidity cycle test)

[0192] Salt spray: IEC600682.11 (salt spray test), KS C 0223 (salt spray test)

[0193]

Table 2

[0194]

[0195]

[0196] According to the experimental data in Table 1 above, it can be confirmed that the gold plating adhesion of the electronic component substrate manufactured according to the embodiment of the present invention is excellent, while in the case of Comparative Example 1 in which the copper ink is gold plated by ordinary sputtering method of non-wet coating method and Comparative Example 2 in which the adhesion promotion layer is not applied, the gold plating adhesion is less than the judgment standard, and peeling is observed on a larger area. In addition, according to the experimental data in Table 2, the electronic component substrates including through-type core through holes with a larger aperture than the aperture of a point inside the hole manufactured according to Examples 1 to 4 of the present invention do not show the phenomenon of electrode warping under the harsh conditions of high temperature and low temperature. In particular, the electronic component substrates of Examples 1 to 3, which increase the specific surface area of ​​the inner wall while making the inner side of the core through hole in an hourglass shape, do not show the phenomenon of electrode warping under all harsh conditions such as high temperature / high humidity, high temperature, low temperature, and salt water, confirming that it has a more excellent effect. In contrast, the electronic substrate of Comparative Example 3 including a cylindrical core through hole shows poor results of electrode warping under all conditions.

[0197] [Industrial Applicability]

[0198] According to the electronic component substrate and the manufacturing method thereof of the present invention, when manufacturing a substrate having a through-core through hole, it includes a adhesion enhancement layer formed by a wet coating method, thereby being able to improve the adhesion of the metal gold-plated layer and prevent defects, thereby being able to provide a high-quality electronic component substrate.

Claims

1. A substrate for an electronic component, characterized in that, comprising: a substrate including one or more through-core via holes; and a close contact promoting layer provided on the surface of the substrate and the surface of the through-core via holes, wherein the aperture of one or more of the upper and lower surfaces of the through-core via hole is larger than the aperture of a point inside the hole.

2. The substrate for an electronic component according to claim 1, characterized in that, in the vertical cross-section of the through-core via hole, the angle between the line connecting a point of the core via hole on the upper or lower surface and the point with the smallest aperture inside the via hole and the line connecting a point of the core via hole on the upper or lower surface in the vertical direction is 1° to 25° or less.

3. The substrate for an electronic component according to claim 1, characterized in that, the vertical cross-section of the through-core via hole is symmetric or asymmetric.

4. The substrate for an electronic component according to claim 1, characterized in that, the inner wall surface of the through-core via hole has a concavo-convex shape.

5. The substrate for an electronic component according to claim 1, characterized in that, the substrate is glass or quartz.

6. The substrate for an electronic component according to claim 1, characterized in that, the close contact promoting layer includes one or more selected from the group consisting of a UV curable resin having an acrylic group and a polyimide-based thermosetting resin, or is a film coated with a metal, an oxide, or a ceramic oxide.

7. The substrate for an electronic component according to claim 1, characterized in that, The thickness of the intimate enhancement layer is 250 to 8. The substrate for an electronic component according to claim 1, characterized in that, the average of the apertures of one or more of the upper and lower surfaces of each through-core via hole of the substrate is 5 to 190 μm.

9. A method for manufacturing a substrate for an electronic component, characterized in that, comprising: (a) a step of forming a close contact promoting layer on the surface of a substrate including one or more through-core via holes; and (b) a step of plating a gold metal on the surface of the substrate on which the close contact promoting layer is formed, wherein the aperture of one or more of the upper and lower surfaces of the through-core via hole is larger than the aperture of a point inside the hole, and the gold plating step in (b) is performed by one or more methods selected from electrolytic gold plating and electroless gold plating.

10. The method for manufacturing a substrate for an electronic component according to claim 9, characterized in that, the above step (a) further includes a surface modification process.

11. The method for manufacturing a substrate for an electronic component according to claim 10, characterized in that, the surface modification is performed by one or more methods selected from the group consisting of saponification treatment, plasma treatment, corona treatment, and primer treatment methods.

12. The method for manufacturing a substrate for an electronic component according to claim 9, characterized in that, before the above step (a), there is further included a process of manufacturing a through-core via hole in which the aperture of one or more of the upper and lower surfaces is larger than the aperture of a point inside the hole by adjusting the etching rate of the upper and lower surfaces of the substrate.

13. The method for manufacturing a substrate for an electronic component according to claim 9, characterized in that, the above step (b) is further performed one or more times.

14. A display device, characterized in that, Comprising a substrate for electronic components according to any one of claims 1 to 8.

15. A semiconductor device, characterized in that it comprises a substrate for electronic components according to any one of claims 1 to 8.

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