Semiconductor package assembly

Abstract

A semiconductor package assembly is provided that includes a semiconductor structure (e.g., an IC chip) and a package substrate electrically connected to the semiconductor structure. The assembly also includes a ceramic capacitor comprising alternating dielectric layers and internal electrode layers, the internal electrode layers including a first internal electrode layer and a second internal electrode layer. The capacitor also includes an external terminal disposed on a first surface of the capacitor and electrically connected to the semiconductor structure, and an external terminal disposed on a second surface of the capacitor and electrically connected to the package substrate.

Description

[0001] Related Applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 420,761, filed on Oct. 31, 2022, which is incorporated herein by reference. BACKGROUND OF THE INVENTION

[0003] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density has come from the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area. As the demand for miniaturized electronic devices grows, semiconductor chip packaging technology needs to be smaller and more creative. To assist in the high-density implementation of semiconductor chips, an interposer formed of an organic material, an inorganic material (e.g., glass), or a silicon material is typically employed. When the interposer is formed of a semiconductor material (e.g., silicon), such a component is commonly referred to as a Chip-on-Interposer structure or a Chip-On-Wafer (COW) structure. The CoW structure can then be attached to a stacked packaging substrate to form a CoWoS structure, and the resulting packaged component can ultimately be connected to a printed circuit board. As part of a system that powers a chip, one or more ceramic capacitors are also typically employed so that the voltage can be kept constant or nearly constant when the chip requires instantaneous current. However, unfortunately, the increase in the switching speed in the chip has led to an increase in parasitic inductance. Accordingly, there is a need for improvement in semiconductor packaged components that employ ceramic capacitors. SUMMARY OF THE INVENTION

[0004] According to one embodiment of the present invention, a semiconductor package assembly is disclosed. The semiconductor package assembly includes a semiconductor structure and a package substrate electrically connected to the semiconductor structure. The assembly further includes a ceramic capacitor having a first surface and an opposite second surface. The ceramic capacitor includes alternating dielectric layers and internal electrode layers. These internal electrode layers include a first internal electrode layer and a second internal electrode layer. The capacitor further includes a first external terminal, a second external terminal, a third external terminal, and a fourth external terminal. The first external terminal is electrically connected to these first internal electrode layers and is disposed on the first surface of the capacitor. The second external terminal is electrically connected to these first internal electrode layers and is disposed on the second surface of the capacitor. The third external terminal is electrically connected to these second internal electrode layers and is disposed on the first surface of the capacitor. The fourth external terminal is electrically connected to these second internal electrode layers and is disposed on the second surface of the capacitor. The first external terminal and the third external terminal (e.g., optionally through an interposer) are electrically connected to the semiconductor structure, and the second external terminal and the fourth external terminal of the ceramic capacitor are electrically connected to the package substrate.

[0005] Other features and aspects of the present invention are set forth in more detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The complete and enabling disclosure of the present invention, including the best mode thereof for one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying drawings, in which:

[0007] Figure 1 is a cross-sectional view of one embodiment of a semiconductor package assembly of the present invention attached to a circuit board;

[0008] Figure 2 is a cross-sectional view of another embodiment of the semiconductor package assembly of the present invention;

[0009] Figure 3A shows a perspective view of one embodiment of a ceramic capacitor that can be employed in the present invention;

[0010] Figure 3B shows Figure 3A a side view of the internal electrode layers of the capacitor;

[0011] Figure 4A shows a perspective view of another embodiment of a ceramic capacitor that can be employed in the present invention;

[0012] Figure 4B shows Figure 4A an end view of the capacitor;

[0013] Figure 4C shows Figure 4ASide view of the capacitor;

[0014] Figure 5A Perspective view showing another embodiment of the ceramic capacitor that can be adopted in the present invention;

[0015] Figure 5B Shows Figure 5A Side view of the internal electrode layer of the capacitor;

[0016] Figure 6A Perspective view showing another embodiment of the ceramic capacitor that can be adopted in the present invention;

[0017] Figure 6B Shows Figure 6A Side view of the internal electrode layer of the capacitor;

[0018] Figure 6C Shows Figure 6A Perspective view of the internal electrode layer of the capacitor;

[0019] Figure 6D Shows Figure 6A Cut-away perspective view of the capacitor;

[0020] Figure 7A Perspective view showing another embodiment of the ceramic capacitor that can be adopted in the present invention;

[0021] Figure 7B Shows Figure 7A Side view of the internal electrode layer of the capacitor;

[0022] Figure 7C Shows Figure 7A Perspective view of the internal electrode layer of the capacitor;

[0023] Figure 7D Shows Figure 7A Cut-away perspective view of the capacitor;

[0024] Figure 8A Perspective view showing another embodiment of the ceramic capacitor that can be adopted in the present invention;

[0025] Figure 8B Shows Figure 8A Cut-away perspective view of the capacitor;

[0026] Figure 9A Perspective view showing yet another embodiment of the ceramic capacitor that can be adopted in the present invention;

[0027] Figure 9B Shows Figure 9A Side cut-away perspective view of a configuration of the internal electrode layer of the capacitor; and

[0028] Figure 9CShows Figure 9A A side perspective view of another configuration of the internal electrode layer of the capacitor of Figure 9A .

[0029] In this specification and the drawings, repeated reference to reference numerals is intended to represent the same or similar features or elements of the present invention. Detailed Description

[0030] Those of ordinary skill in the art will understand that this discussion is only a description of exemplary embodiments and is not intended to limit the broader aspects of the present invention.

[0031] Generally, the present invention relates to a semiconductor package assembly that includes a semiconductor structure, a package substrate electrically connected to the semiconductor structure, and optionally an interposer positioned between the semiconductor structure and the package substrate and electrically connected to the semiconductor structure and the package substrate. The assembly also includes a ceramic capacitor having a first surface and an opposite second surface. The ceramic capacitor includes alternating dielectric layers and internal electrode layers, where the internal electrode layers include a first internal electrode layer and a second internal electrode layer. A first external terminal is electrically connected to the first internal electrode layer and is disposed on the first surface of the capacitor, and a second external terminal is electrically connected to the first internal electrode layer and is disposed on the second surface of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and is disposed on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layer and is disposed on the second surface of the capacitor. Generally, the first external terminal and the second external terminal have the same polarity (e.g., positive), and the third external terminal and the fourth external terminal have the same polarity (e.g., negative). In any case, the first external terminal and the third external terminal of the ceramic capacitor are electrically connected to the semiconductor structure, and the second external terminal and the fourth external terminal of the ceramic capacitor are electrically connected to the package substrate.

[0032] The various embodiments of the present invention will be described in more detail below.

[0033] I. Semiconductor Structure

[0034] One or more semiconductor structures (e.g., dies, wafers, integrated circuit devices, etc.) can generally be used in semiconductor package assemblies. Generally speaking, a semiconductor structure can include an insulating material (e.g., dielectric materials formed in multiple layers, as known in the art) and a plurality of conductive paths formed through the insulating material. The insulating material can include dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, polyimide materials, glass-reinforced epoxy matrix materials, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). The insulating material can also include semiconductor materials such as silicon, germanium, or III-V materials (e.g., gallium nitride), as well as one or more additional materials. For example, the insulating material can include silicon oxide or silicon nitride. The conductive paths of the die can include conductive traces and / or conductive vias, and can connect to any conductive contacts in the die in any suitable manner. The semiconductor structure can include a mixed-pitch die (in the sense that the die has multiple sets of conductive contacts with different pitches), e.g., the die can have "rougher" conductive contacts for coupling to an interposer of the semiconductor package assembly. The structure can also include a single-sided die (having conductive contacts only on a single surface) and / or a double-sided die (having conductive contacts on a first surface and an opposite second surface). The conductive paths in the die can be adjacent to a pad material such as a suitable adhesion pad and / or a barrier pad. The semiconductor structure can also include a wafer. In some embodiments, the semiconductor structure includes a monolithic silicon, fan-out or fan-in packaged die, or a die stack (e.g., wafer-stacked, die-stacked, or multi-layer die-stacked).

[0035] The semiconductor structure may also have an integrated circuit (“IC”) structure such that it is in the form of a discrete IC device or “chip”. Such an IC device may include one or more device layers disposed on a die substrate. The die substrate may be a semiconductor substrate composed of a semiconductor material system, which includes, for example, an n-type or p-type material system (or a combination of both). The die substrate may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, alternative materials may be used to form the die substrate, which may or may not be combined with silicon, and these alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The die substrate may also be formed of other materials classified as Group II-VI, Group III-V, or Group IV. The device layer may include one or more transistors (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)), support circuits for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other IC components. The device layer may include, for example, one or more source and / or drain (S / D) regions, a gate for controlling the current flow between the S / D regions in the transistor, and one or more S / D contacts for routing electrical signals to or from the S / D regions. Each transistor may include a gate formed of at least two layers (a gate dielectric and a gate electrode). The gate dielectric may include a stack of one or more layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that can be used in the gate dielectric include, but are not limited to: hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, an annealing process may be performed on the gate dielectric to improve its quality.

[0036] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some embodiments, the gate electrode may consist of a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the various metals discussed below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the various metals discussed above with reference to PMOS transistors (e.g., for work function tuning). Electrical signals (e.g., power and / or input / output (I / O) signals) may be routed to devices (e.g., transistors) of the device layer and / or routed from devices (e.g., transistors) of the device layer via one or more interconnect layers disposed on the device layer. For example, conductive features (e.g., gates and S / D contacts) of the device layer may be electrically coupled to interconnect structures that may optionally form the metallization stack (also referred to as the "ILD stack") of the IC device. The interconnect structures may include lines and / or vias filled with a conductive material such as metal. These lines may be arranged to route electrical signals in a direction in a plane substantially parallel to the surface of the die substrate on which the device layer is formed. These vias may be arranged to route electrical signals in a direction in a plane substantially perpendicular to the surface of the die substrate on which the device layer is formed.

[0037] IC devices can include, for example, memory devices (e.g., random access memory (RAM) devices, such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridging RAM (CBRAM) devices; erasable-programmable read-only memory (EPROM) chips; non-volatile memory (e.g., 3D XPoint); volatile memory (e.g., high-bandwidth memory); stacked memories, etc.); logic devices (e.g., AND gates, OR gates, NAND gates, or NOR gates, programmable logic devices, etc.); processor devices (e.g., central processing unit (CPU), graphics processing unit (GPU), etc.); application-specific integrated circuit (ASIC), field programmable gate array (FPGA), platform controller hub (PCH), etc., and any other suitable memory, logic, and / or processor devices. Multiple devices can be combined on a single structure. For example, a memory array formed by multiple memory devices can be formed on the same die as a processor device or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0038] A semiconductor structure can also be a "chiplet", which is a small integrated circuit (IC) containing a well-defined subset of functions that is part of a processing module that makes up a larger integrated circuit such as a computer processor. In some embodiments, one or more chiplets are coupled to a host chip in different ways, where each of the one or more chiplets includes its own cache memory - for example, including a last level cache (LLC) accessible to one or more cores of the host chip. The host chip can include one or more processor cores, each of which can operate as a consumer of memory resources, and the chiplet can include one or more memory arrays, each of which is coupled to be accessible by a corresponding processor core of the host chip. In this particular context, the terms "memory", "memory array", "memory resource" and related terms generally refer to cache memory or non-cache memory (e.g., system memory). Similarly, the term "memory controller" generally refers to controller circuitry that provides access to one of cache memory or non-cache memory. The host chip can contain a processor core that operates as a consumer of memory resources. For example, the host chip can execute an operating system, a binary input / output system (BIOS), and / or any of various other software processes. To facilitate the execution of such software, the chiplet can include one or more memory arrays coupled to be accessible by the processor core through a hardware interface. In one embodiment, the memory array includes static random access memory (SRAM) cells or dynamic random access memory (DRAM) cells. Additionally or alternatively, the processor core can be coupled to cache data into the memory array - for example, where the processor core is coupled to access the last level cache (LLC) of the memory array. In various other embodiments, the memory array can contain non-volatile memory (NVM) cells. The chiplet can also contain a memory controller coupled between the hardware interface and the memory array, which controls memory access on behalf of the processes executed by the core. By providing the memory array in the chiplet disposed between the hardware interface and the host chip, data locality can be improved for use by one or more cores of the packaged device. This improved data locality makes access to memory resources relatively more space-efficient, time-efficient, and / or power-efficient.

[0039] One or more semiconductor structures may be arranged or stacked into a 3D configuration in a two-dimensional configuration or array known in the art (e.g., 2D, 2.1D, 2.3D, or 2.5D heterogeneous integration). When a stacked configuration is employed, the semiconductor structures may include two or more semiconductor substrates (e.g., chips, interposers, etc.) mounted on a circuit board. If implemented as semiconductor chips, the substrates may be any of numerous different types of circuit devices used in an electronic device, such as a microprocessor, a graphics processor, a combined microprocessor / graphics processor, an application specific integrated circuit, or a memory device, etc., and may be single-core or multi-core. The substrate may be composed of bulk semiconductor (e.g., silicon or germanium) or semiconductor-on-insulator material (e.g., silicon-on-insulator material). The circuit board may be a semiconductor chip package substrate, a circuit card, or virtually any other type of printed circuit board. Although a more typical configuration will utilize a build-up design, a monolithic structure may be used for the circuit board. In this regard, the circuit board may consist of a central core, on which one or more build-up layers are formed, and additional one or more build-up layers are formed below the central core. The core itself may consist of a stack of one or more layers. The circuit paths between the substrate and the circuit board and between any substrates may be provided by an interconnect structure.

[0040] II. Encapsulation Substrate

[0041] A semiconductor package assembly includes, in addition to the semiconductor structure, a package substrate to assist in bridging high-density interconnects and functions. Generally, the package substrate includes an insulating material and one or more conductive paths (e.g., as shown, including conductive traces and / or conductive vias) passing through the insulating material. For example, the insulating material may be an organic material, such as a bismaleimide triazine (“BT”) resin material (e.g., BT, BT-epoxy, etc.), an epoxy resin material (e.g., glass fiber-reinforced epoxy (e.g., FR4)), a polyimide material, a low-k and ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, and organic polymer dielectric). The insulating material may also be an inorganic material, such as an inorganic material formed from a ceramic material (e.g., glass) and a semiconductor material (e.g., silicon, germanium, and other Group III-V (e.g., gallium nitride) and Group IV materials).

[0042] Depending on the specific configuration of the semiconductor package assembly, the conductive paths of the package substrate can be used for various different purposes. For example, in embodiments where the package substrate is directly connected to the semiconductor structure, the conductive paths can assist in coupling the semiconductor structure to the circuit board. In embodiments employing an interposer, the conductive paths can assist in coupling the interposer to the circuit board. Any suitable conductive path arrangement passing through any suitable number of insulating layers can generally be employed. The conductive paths can be made of any suitable conductive material (e.g., copper). The conductive paths can be adjacent to a pad material, such as a suitable adhesion pad and / or barrier pad. In some embodiments, the package substrate can be a lower density dielectric, while the semiconductor structure and / or optional interposer can be a higher density dielectric. As used herein, the terms "lower density" and "higher density" are relative terms indicating that the conductive paths (e.g., including wires and conductive vias) in the lower density dielectric are larger and / or have a greater pitch than those in the higher density dielectric. The higher density dielectric can be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (having small vertical interconnect features formed by an advanced laser or lithography process), while the lower density dielectric can be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using an etching chemistry to remove unwanted copper regions and having rough vertical interconnect features formed by a standard laser process).

[0043] As described above, one or more semiconductor structures may optionally be electrically connected to one or more interposers, such that the resulting semiconductor package assembly is considered a "chip-on-interposer" structure. Herein, the interposer may provide an intermediate substrate to assist in extending connections to wider pitches or rerouting connections to different connections. In such embodiments, the semiconductor structure may be electrically connected to the interposer by one or more coupling components. The coupling components may electrically and mechanically couple the chip-on-interposer structure to the package substrate and may include, for example, solder bumps, solder balls, male and female portions of a socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures. The underfill material may be an insulating material, such as a suitable epoxy material. When an underfill material is employed, the underfill material may include capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material may include an epoxy flux that aids in soldering the semiconductor structure and then polymerizing and encapsulating the interconnects within the interposer. The interposer generally includes an insulating material as described above and one or more conductive paths (e.g., including conductive traces and / or conductive vias as shown) passing through the insulating material. As is known in the art, such paths may include one or more metal interconnects and vias. For example, in one embodiment, the interposer may be formed of silicon, and vias may be formed in the interposer, which may be referred to as "through-silicon vias (TSVs)".

[0044] When an interposer is employed, depending on the particular embodiment, the interposer can be passive or active. "Passive" generally means that the interposer typically has no embedded electronic components. On the other hand, an "active" interposer generally includes one or more electronic components embedded within an insulating material. Examples of such electronic components can include, for example, capacitors (e.g., the capacitors described herein), resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices can also be formed in the interposer, such as radio frequency devices, power amplifiers, power management devices, antennas, and microelectromechanical system (MEMS) devices. For example, an active interposer can include an active layer and a bulk semiconductor layer. In this document, the front surface of the active layer can be referred to as the "active side", while the opposite surface of the bulk semiconductor layer can be referred to as the "back side". In one embodiment, the active layer can include one or more electronic components formed on the active side, such as a level 1 (L1) memory element that serves as a memory cache for storing a configuration bit stream, and the configuration bit stream is used to configure logical sectors in a coprocessor. The active layer can optionally include decryption / decompression circuitry for processing encrypted and / or compressed configuration bit streams. The semiconductor layer can include through-silicon vias (TSVs) that connect the electronic components (e.g., L1 memory elements) in the active layer to coupling elements (e.g., solder balls). For example, an L1 cache can receive a configuration bit stream from a host processor through solder balls and TSVs. In this way, the energy efficiency of transmitting signals and power between the active layer of the interposer and the package substrate can be improved.

[0045] III. Ceramic Capacitor

[0046] As described above, at least one ceramic capacitor is electrically connected to the semiconductor structure and the package substrate such that the assembly can achieve "package-level decoupling". For example, in one embodiment, the ceramic capacitor can be directly connected to the semiconductor structure and the package substrate. However, in other embodiments, an interposer can be employed between the semiconductor structure and the package substrate. In such an embodiment, the ceramic capacitor can be positioned between the semiconductor structure and the interposer such that the capacitor is electrically connected to the package substrate through the interposer. In another embodiment, the ceramic capacitor can be positioned between the interposer and the package substrate such that the capacitor is electrically connected to the semiconductor structure through the interposer.

[0047] Regardless of the specific construction of the component, a ceramic capacitor includes a body that includes alternating dielectric layers and internal electrode layers. The internal electrode layers include at least a first internal electrode layer and a second internal electrode layer. The capacitor can include, for example, at least two sets (e.g., at least three sets, e.g., at least four sets) of internal electrode layers. Of course, it should be understood that the capacitor can include any number of sets of alternating dielectric layers and internal electrode layers and need not be limited. Generally, the capacitor includes an upper surface (e.g., a first surface) and a lower surface (e.g., a second surface) opposite the upper surface. The capacitor further includes at least one side surface, particularly at least two side surfaces, extending between the upper surface and the lower surface. The capacitor can include at least one end surface, particularly at least two end surfaces, extending between the upper surface and the lower surface. The side surfaces can extend in the length (L) direction and have a generally longer dimension than the end surfaces that extend in the width (W) direction and have a generally shorter dimension. In one embodiment, the capacitor can have a parallelepiped shape, such as a rectangular parallelepiped shape. The overall dimensions of the capacitor can depend on the specific application. However, generally, the height or thickness of the capacitor is from about 10 micrometers (μm) to about 5000 μm, in some embodiments from about 20 μm to about 2500 μm, in some embodiments from about 50 μm to about 1500 μm, and in some embodiments from about 100 μm to about 1000 μm. When the capacitor is surrounded by a ball grid array, the height of the capacitor can be within 10% of the height (or diameter) of the balls of the ball grid array, e.g., within 7%, e.g., within 5%, e.g., within 3%, e.g., within 2%, e.g., within 1%. For example, such a height can be the original height before any reflow. The length of the capacitor in the "L" direction can likewise be from about 50 μm to about 10000 μm, in some embodiments from about 100 μm to about 7500 μm, and in some embodiments from about 1000 μm to about 5000 μm, and the width of the capacitor in the "W" direction can be from about 25 μm to about 5000 μm, in some embodiments from about 50 μm to about 3500 μm, and in some embodiments from about 500 μm to about 2500 μm.

[0048] The first internal electrode layer and the second internal electrode layer may be interleaved in a relative and spaced-apart relationship, wherein a dielectric layer is located between each internal electrode layer. Each set of alternating dielectric layers and internal electrode layers may be spaced apart from an adjacent set by a certain distance. For example, this distance may be greater than the thickness of a single dielectric layer in the set, such as the distance is at least 2 times the thickness of the dielectric layer in the set, in some embodiments, the distance is at least 3 times the thickness of the dielectric layer in the set, in some embodiments, the distance is at least 5 times the thickness of the dielectric layer in the set, and in some embodiments, the distance is at least 10 times the thickness of the dielectric layer in the set. Each set of internal electrode layers and / or the entire capacitor may include from about 10 to about 4000 internal electrode layers, in some embodiments, including from about 50 to about 2000 internal electrode layers, and in some embodiments, including from about 100 to about 1000 internal electrode layers. The thickness of the dielectric layer and / or the internal electrode layer is not limited and may be any desired thickness depending on the performance characteristics. For example, the thickness range of the internal electrode layer and / or a single dielectric layer may be from about 100 nanometers (nm) to about 10 μm, in some embodiments, from about 500 nm to about 8 μm, in some embodiments, from about 1 μm to about 5 μm. In certain embodiments, if the capacitor includes a second set of alternating dielectric layers and internal electrode layers, the distance between the first internal electrode layer of one set and the last internal electrode layer of another set may be greater than the distance between adjacent internal electrode layers within a given set. For example, the distance between the first internal electrode layer of the first set and the last internal electrode layer of the second set may be greater than the distance between the first internal electrode layer and the second internal electrode layer of the first set.

[0049] Although not required at all, the dielectric region of a ceramic capacitor can also include one or more voids. In this regard, the dielectric region can be a region that includes dielectric material but does not include internal electrode material. The dielectric region can thus constitute a region that does not include alternately arranged dielectric layers and internal electrode layers. Thus, the dielectric region can include dielectric material between respective groups of alternating dielectric layers and internal electrode layers along the "W" direction. Additionally, the dielectric region can include dielectric material between the lateral edges of each electrode in a given group of alternating dielectric layers and internal electrode layers and an end surface adjacent in the longitudinal direction, provided, for example, that such internal electrode layers do not extend to the end surface such that they are offset relative to the end surface. It should be understood that although such a dielectric region can be formed from a green sheet of alternating dielectric layers and internal electrode layers, such a region does not include any internal electrode material or corresponding layers. Thus, air voids can be provided in these regions. Additionally, the dielectric region can include dielectric material present between the first internal electrode layer of each group and an adjacent side surface of the capacitor. The dielectric region can also include dielectric material present between the last internal electrode layer of each group and an adjacent side surface of the capacitor. The dielectric region can also include dielectric material between the lateral edges of adjacent lead tabs extending from the body of the internal electrode layer. In a particular embodiment, the dielectric region can include the region within the capacitor that exists between two external terminals. Additionally, it should be understood that the dielectric region can include any combination of the above regions.

[0050] As indicated above, the dielectric region includes regions that include dielectric material but do not include internal electrode material. Thus, disregarding pores, the dielectric region can include 90 vol.% or more of dielectric material, such as 93 vol.% or more of dielectric material, such as 95 vol.% or more of dielectric material, such as 97 vol.% or more of dielectric material, such as 98 vol.% or more of dielectric material, such as 99 vol.% or more of dielectric material, such as 100 vol.% of dielectric material. Such pores can be void of any material, in particular any dielectric material or internal electrode material. In one embodiment, the pores can be (partially or completely) enclosed by the housing material. In one embodiment, the pores can be partially enclosed by the housing material. By partially enclosing, the housing material is only partially present around the inside of the pores, thereby separating the housing material from the dielectric material partially. In this regard, at least some perimeter of the pores can be in direct contact with the dielectric material of the dielectric region. In another embodiment, the pores can be completely or fully enclosed by the housing material. By fully enclosing, the housing material is present around the inside of the pores such that the pores are completely separated from the dielectric material. In any case, the housing material can serve as a barrier between the inside of the pores and the dielectric material of the dielectric region. In one embodiment, the housing material can be a non-conductive material. However, it should be understood that in one embodiment, the pores can be not enclosed by the housing material, or even not partially enclosed by the housing material.

[0051] These holes can be arranged such that there is no barrier between the air holes and the dielectric material of the dielectric region. The air holes can have any shape and need not be restricted. For example, the shape can be spherical, cylindrical, etc. In one embodiment, the shape can be spherical. The air holes can have a maximum size (e.g., length, width, diameter, etc.) that is from about 5 μm to about 5000 μm, in some embodiments from about 50 μm to about 2500 μm, and in some embodiments from about 100 μm to about 1000 μm. Any known technique can be used to form these holes, such as by printing a specific pattern on a green ceramic sheet and then laminating and firing the stacked laminates to form these holes. Alternatively, various drilling techniques can be used to form these holes so as to provide any desired shape within the dielectric material of the dielectric region. One or more vias (e.g., through vias) can be used to allow the air holes to exist. These vias can be unfilled with material (e.g., any conductive or non-conductive material) such that air exists inside. Additionally, in one embodiment, the vias can be arranged such that they only exist within the dielectric region. In this regard, the vias can be arranged such that they do not contact any internal electrode layer. In one embodiment, the vias can extend from the upper surface of the capacitor to the lower surface of the capacitor. In this regard, the vias can be columnar and extend through the thickness of the capacitor. Thus, the vias can be through-conductive vias. In another embodiment, the vias can only partially extend through the thickness of the capacitor. For example, the vias can only partially extend through the thickness of the capacitor, such as extending through about 10% to about 90% of the capacitor thickness, and in some embodiments, extending through about 20% to about 80% of the capacitor thickness.

[0052] In addition to the alternating internal electrode layers and dielectric layers, the ceramic capacitor further includes a first external terminal and a second external terminal. The first external terminal is electrically connected to the first internal electrode layer and is disposed on the first surface (e.g., the upper surface) of the capacitor. The second external terminal is electrically connected to the first internal electrode layer and is disposed on the second surface (e.g., the lower surface) of the capacitor. Similarly, a third external terminal is electrically connected to the second internal electrode layer and is disposed on the first surface of the capacitor, and a fourth external terminal is electrically connected to the second internal electrode layer and is disposed on the second surface of the capacitor. Generally, the first external terminal and the second external terminal have the same polarity (e.g., positive), and the third external terminal and the fourth external terminal have the same polarity (e.g., negative). In any case, the first external terminal and the third external terminal of the ceramic capacitor can be electrically connected to a semiconductor structure, and the second external terminal and the fourth external terminal of the ceramic capacitor can be electrically connected to a package substrate.

[0053] The capacitor further includes external terminals located on opposite end surfaces. For example, one or more of these external terminals may extend from a first surface (e.g., the upper surface) and / or a second surface (e.g., the lower surface) to the end surface. When present on the end surface, the external terminal may only partially be present on the end surface such that the external terminal does not cover the entire end surface. In another embodiment, the capacitor may not include any external terminals located on opposite end surfaces. In a particular embodiment, no external terminals may be present on the side surface of the capacitor. In any case, the external terminals generally include at least one first-polarity terminal and at least one second opposite-polarity terminal. The capacitor may include on the upper surface of the capacitor the following number of first-polarity terminals and / or second opposite-polarity terminals: at least one, e.g., at least two, e.g., at least four, e.g., at least six, e.g., at least eight. Additionally, the capacitor may include on the lower surface of the capacitor the above-mentioned number of terminals.

[0054] The capacitor may include an equal number of first-polarity terminals and / or second-polarity terminals on the upper surface and the lower surface of the capacitor. On the upper surface of the capacitor, the number of first-polarity terminals may be equal to the number of second opposite-polarity terminals. On the lower surface of the capacitor, the number of first-polarity terminals may be equal to the number of second opposite-polarity terminals. The total number of terminals present on the upper surface of the capacitor may be equal to the total number of terminals present on the lower surface of the capacitor. The total number of first-polarity terminals present on the upper and lower surfaces of the capacitor may be equal to the total number of second opposite-polarity terminals present on the upper and lower surfaces of the capacitor. Generally, similar-polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers on the lower surface of the capacitor are electrically connected to similar-polarity terminals on the upper surface of the capacitor. The similar-polarity terminals located on the upper and lower surfaces of the capacitor may not be staggered. In this regard, the corresponding similar-polarity terminals on the top surface and the lower surface may not be offset in terms of terminal position, but may be located directly above or below another similar-polarity terminal on the opposite top surface or lower surface. In other words, the corresponding similar-polarity terminals corresponding to a particular set of alternating dielectric layers and internal electrode layers, and in particular the corresponding lead tabs of this set, may be substantially aligned. Substantially aligned means that the deviation from a lateral edge of a polarity terminal on the upper surface is within + / - 10% of the deviation from the lateral edge of the corresponding polarity terminal on the lower surface, e.g., within + / - 5%, e.g., within + / - 4%, e.g., within + / - 3%, e.g., within + / - 2%, e.g., within + / - 1%, e.g., within + / - 0.5%.

[0055] The pitch of each external terminal (i.e., the nominal distance between each center, also referred to as the center-to-center spacing) can be determined by a specific package substrate configuration. The pitch of each external terminal in one direction (i.e., the x-direction or the y-direction) can be the same as the pitch of adjacent external terminals in the other direction (i.e., the y-direction or the x-direction, respectively). That is to say, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals. The range of this pitch can be, for example, from about 0.1 mm to about 2 mm, in some embodiments, from about 0.2 mm to about 1.5 mm, and in some embodiments, from about 0.4 mm to about 1.4 mm.

[0056] If desired, the external terminals can be arranged in a configuration similar to a ball grid array. For example, the external terminals can be arranged to form contacts typically used in a ball grid array (especially a peripheral ball grid array). In this regard, the pitch of each external terminal can be the same as the pitch of the peripheral ball grid array. That is to say, this pitch can be within 10% of the pitch of the peripheral ball grid array, for example, within 5%, for example, within 2%, for example, within 1%, for example, within 0.5%, for example, within 0.1%. Additionally, like a ball grid array, each external terminal can be arranged in multiple rows and multiple columns. That is to say, each external terminal can be arranged such that they exist in at least one row and at least two columns. For example, each external terminal can exist in at least two rows, for example, in at least three rows, for example, in at least four rows. The number of rows can be determined by the number of different sets of alternating dielectric layers and internal electrode layers. Additionally, each external terminal can exist in at least two columns, for example, in at least three columns, for example, in at least four columns. The number of columns can be determined by the number of different columnar tabs of the internal electrodes.

[0057] The length of the external terminal extending along the upper surface (i.e., extending from one end surface to the other end surface in the longitudinal direction) may be the same as the length of the corresponding external terminal extending along the lower surface. For example, the length of the external terminal may be from about 0.3 mm to about 1.1 mm, in some embodiments, from about 0.4 mm to about 1 mm, and in some embodiments, from about 0.5 mm to about 0.9 mm. The length of the external terminal may also be less than the length of the capacitor, for example, 50% or less of the length of the capacitor, for example, 40% or less of the length of the capacitor, for example, 30% or less of the length of the capacitor, for example, 25% or less of the length of the capacitor, for example, 20% or less of the length of the capacitor, for example, 15% or less of the length of the capacitor. If desired, each external terminal may have a different length. For example, the length of the external terminal adjacent to the end surface may be greater than the length of the external terminal deviated from the end surface. In this regard, the ratio of the length of the external terminal adjacent to the end surface to the length of the external terminal deviated from the end surface may be from about 0.3 to about 5, in some embodiments, the ratio may be from about 0.5 to about 4, and in some embodiments, the ratio may be from about 0.7 to about 3. On the upper surface and the lower surface, the width of the external terminal extending from one side surface to the opposite side surface may be the same. For example, the range of this width may be from about 0.3 mm to about 1.1 mm, in some embodiments, from about 0.4 mm to about 1 mm, and in some embodiments, from about 0.5 mm to about 0.9 mm.

[0058] Reference Figure 3A and Figure 3B FIG. shows, in more detail, a specific embodiment of the ceramic capacitor 10 that can be used in the semiconductor package assembly of the present invention. The capacitor 10 generally has the thickness "T", width "W", and length "L" as described above. In addition, as shown, the capacitor 10 has a 1×2 configuration because it includes two external terminals along one dimension of the upper surface and the lower surface. That is, the capacitor 10 includes a first external terminal 12 and a second external terminal 14 on the upper surface, and corresponding third and fourth external terminals (not shown) on the lower surface, respectively. The first external terminal 12 and the third external terminal (not shown) may have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) may also have the same polarity (i.e., negative). The width "BW" and length "BL" of the external terminals 12 and / or 14 may be within the above ranges. Although not required, as described above, a hole 1350 may also be formed between the terminals 12 and 14 in the capacitor 10.

[0059] The capacitor 10 further includes a dielectric layer (not shown) and an internal electrode layer 110, as Figure 3BAs shown. That is, the internal electrode layer 110 includes a first internal electrode layer 105 and a second set of internal electrode layers 115. In the particular embodiment shown, the internal electrode layers 105, 115 include at least one lead tab 120, 130, 140, 150 extending from the top and bottom edges of the body of the internal electrode layer. The lead tabs 120, 130, 140, 150 of the internal electrode layers 105, 115 can extend to the upper and lower surfaces of the capacitor and assist in forming external terminals. In this regard, the lead tabs 120, 130, 140, 150 can be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 120, 130, 140, 150 can include front edges 123, 133, 143, 153 that extend to the edge of the dielectric layer and allow the formation of external terminals. The length of the lead tabs 120, 130, 140, 150 can vary as needed, but is typically from about 0.3 mm to about 1.2 mm, in some embodiments from about 0.4 mm to about 1.1 mm, and in some embodiments from about 0.5 mm to about 1 mm. When there is more than one lead tab along an edge, the individual lead tabs can have the same length. In another embodiment, the individual lead tabs can have different lengths. For example, a lead tab that is generally aligned with the side edge of the internal electrode layer can have a greater length than a lead tab that is offset from the side edge of the internal electrode layer. In this regard, the ratio of the length of the lead tab that is aligned with the side edge of the internal electrode layer to the length of the lead tab that is offset from the side edge of the internal electrode layer can be from about 0.3 to about 5, in some embodiments from about 0.5 to about 4, and in some embodiments from about 0.7 to about 3. Generally aligned typically means that the deviation from the side edge of one of the first and / or second lead tabs on the top edge is within + / - 10% of the deviation from the corresponding side edge of the first and / or second lead tabs on the bottom edge, such as within + / - 5%, such as within + / - 4%, such as within + / - 3%, such as within + / - 2%, such as within + / - 1%, such as within + / - 0.5%.

[0060] As Figure 3BAs shown, the first internal electrode layer 105 includes a lead tab 120 extending along the top edge 105c and from the body 135 and a lead tab 130 extending along the bottom edge 105d and from the body 135. The second internal electrode layer 115 includes a lead tab 140 extending along the top edge and from the body 145 and a lead tab 150 extending along the bottom edge and from the body 145. The lead tabs 120, 130 on the top and bottom edges of the first internal electrode layer 105 may be aligned in the vertical direction. That is, the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c. Additionally, these lateral edges 121, 131 may be aligned with the side edge 105a of the internal electrode layer 105. However, it should be understood that the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c may be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite the top edge 105c. In other words, the two lateral edges 122, 132 may be aligned and deviate from the side edges 105a and 105b by the same distance along the bottom edge 105d and the top edge 105c. Similarly, the lead tabs 140, 150 on the top and bottom edges of the second internal electrode layer 115 may be aligned in the vertical direction. That is, the lateral edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite the top edge. In one embodiment, the two lateral edges 141, 142 of the first lead tab 140 along the top edge may be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 105 may also apply to the internal electrode layer 115. With this arrangement, a gap may be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. Similarly, a gap may be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The sizes of the respective corresponding gaps may be substantially the same.

[0061] The lead tabs 120 and 140 can be arranged parallel to the lead tabs 130 and 150 respectively, extending from the internal electrode layers 105 and 115 such that the respective lead tabs extending from the alternating electrode layers 105 and 115 can be aligned in corresponding columns. For example, the lead tabs 120 and 130 of the internal electrode layer 105 can be arranged in a corresponding stacked configuration, while the lead tabs 140 and 150 of the internal electrode layer 115 can be arranged in a corresponding stacked configuration.

[0062] It will be appreciated that the lead tab 120 is connected to the external terminal 12, and the lead tab 140 is connected to the external terminal 14. Thus, each lead tab 120 will be staggered with the corresponding lead tab 140 in a manner similar to the external terminals 12 and 14. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0063] The distance between each adjacent exposed lead tab of the internal electrode layer in a given column can be specifically designed to help ensure the guiding and shaping of each termination. The distance between each exposed lead tab of the internal electrode layer in a given column can range, for example, from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 5 μm, and in some embodiments from about 1 μm to about 4 μm. Additionally, the distance between adjacent columnar stacks of the electrode tabs can (but is not limited to) be at least twice as large as the distance between each adjacent lead tab in a given column to ensure that different terminations do not connect together. In some embodiments, the distance between adjacent columnar stacks of the exposed metallization is about four times the distance between each adjacent exposed electrode tab in a particular stack. However, this distance can vary depending on the desired capacitance performance and the package substrate configuration. For example, the distance can be from about 0.1 mm to about 1.5 mm, in some embodiments from about 0.2 mm to about 1.3 mm, and in some embodiments from about 0.3 mm to about 1 mm, which is determined based on the center points of the respective lead tabs or based on the distance between adjacent lateral edges of the lead tabs. Additionally, this distance can correspond to the spacing distance of the balls on a ball grid array.

[0064] In Figure 3A and Figure 3B the illustrated embodiment, the capacitor includes two external terminals that extend to the ends of the capacitor. However, this is by no means necessary. Referring to FIGS. 4A through Figure 4C, for example, shows an embodiment of a capacitor 10, in which a first external terminal 12, a second external terminal 14, and a third and a fourth external terminal (not shown) do not extend to the ends of the capacitor. To help achieve such a configuration in this particular embodiment, the capacitor 10 includes an internal electrode layer 110, which includes a first internal electrode layer 105 and a second internal electrode layer 115. The first internal electrode layer 105 may extend to the upper surface of the capacitor 10, and the second internal electrode layer 115 extends to the lower surface of the capacitor. These extensions help to form the external terminals. In this regard, the internal electrode layer may be exposed on the upper and lower surfaces of the capacitor and allow a connection between the body of the internal electrode layer and the external terminals. For example, the internal electrode layers 105, 115 extend to the edges of the dielectric layer and allow the formation of external terminals. The lateral edges or side edges of the internal electrode layers 105, 115 may be aligned in the vertical direction. That is, the lateral edge of the first internal electrode layer 105 may be aligned with the lateral edge of the second internal electrode layer 115. In one embodiment, the two lateral edges may be aligned. In another embodiment, the contact point of the first internal electrode layer 105 with the external terminal may be aligned with the contact point of the second internal electrode layer 115 with the external terminal. Additionally, Figure 4A the capacitor 10 includes at least one first polarity terminal and at least one second opposite polarity terminal on the upper surface. Although not shown, the lower surface includes at least a first polarity terminal and a second opposite terminal.

[0065] In Figure 3A and Figure 3B as well as Figures 4A to 4C the embodiment shown, the capacitor includes two external terminals on each surface. However, as indicated above, the present invention is not limited by the number of external terminals and / or the number of lead tabs extending from the top edge and / or the bottom edge. Referring to Figure 5A and Figure 5B, for example, the illustrated capacitor 20 has a 1×4 array configuration and thus includes four external terminals on each surface. That is, the capacitor includes four terminals in two dimensions along the upper and lower surfaces. In this regard, the capacitor includes a total of four external terminals located on the upper surface (i.e., the first external terminals 22a and 22b and the second external terminals 24a and 24b), and a corresponding set of third and fourth external terminals (not shown) located on the lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). The capacitor 20 generally also has a thickness "T", a width "W", and a length "L" as described above, and the widths "BW" and lengths "BLA" and "BLB" of the external terminals 22a, 22b and / or 24a, 24b can be within the ranges described above. Although not at all necessary, holes 1350 can also be formed between the external terminals 22a, 24b, 22b and / or 24a in the capacitor 20 as described above.

[0066] The capacitor 20 further includes an internal electrode layer 210, and the internal electrode layer 210 includes a first internal electrode layer 205 and a second internal electrode layer 215 which are alternately arranged. The internal electrode layers 205, 215 include at least one lead tab 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b extending from the top edge and the bottom edge of the main body of the internal electrode layer. The lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b of the internal electrode layers 205, 215 extend to the upper surface and the lower surface of the capacitor and contribute to forming external terminals. In this regard, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b may be exposed on the upper surface and the lower surface of the capacitor and allow connection between the main body of the internal electrode layer and the external terminals. For example, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b may include front edges 223a and 223b, 233a and 233b, 243a and 243b, 253a and 253b that extend to the edge of the dielectric layer and allow formation of the external terminals. The internal electrode layers 205, 215 include at least two lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b along the top edge and the bottom edge. The first internal electrode layer 205 includes two lead tabs 220a and 220b respectively extending from the main body 235 along the top edge 205c, and two lead tabs 230a and 230b respectively extending from the main body 235 along the bottom edge 205d. The second internal electrode layer 215 includes two lead tabs 240a and 240b respectively extending from the main body 245 along the top edge, and two lead tabs 250a and 250b respectively extending from the main body 245 along the bottom edge.

[0067] The lead tabs 220a and 220b, 230a and 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 can be aligned in the vertical direction. That is, the lateral edges 221a, 222a of the first lead tab 220a along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230a along the bottom edge 205d opposite to the top edge 205c. Additionally, such lateral edges 221a, 231a can be aligned with the side edge 205a of the internal electrode layer 205. However, it should be understood that the two lateral edges 221a, 222a of the first lead tab 220a along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230a along the bottom edge 205d opposite to the top edge 205c. In other words, the two lateral edges 222a, 232a can deviate from the side edges 205a and 205b by the same distance along the bottom edge 205d and the top edge 205c. When the top edge 205c and the bottom edge 205d include at least two lead tabs 220a and 220b, 230a and 230b, at least one lateral edge of each lead tab on the top edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. Moreover, the two lateral edges of each lead tab on the top edge 205c can be aligned with the corresponding lateral edges of the lead tabs on the bottom edge 205d. Similarly, the lead tabs 240a and 240b, 250a and 250b on the top edge and the bottom edge of the second internal electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite to the top edge.

[0068] The two lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 205 can also apply to the internal electrode layer 215. With this arrangement, a gap can be formed between the lead tabs along the top edge 205c of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 220a and 220b, 240a and 240b extending from the top edge of each internal electrode layer. Additionally, a gap can be formed between the lead tabs along the top edge 205d of the first internal electrode layer 205, the lead tabs along the bottom edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 230a and 230b, 250a and 250b extending from the top edge of each internal electrode layer. Furthermore, whether from the same internal electrode layer or from adjacent internal electrode layers, the size of the gap between two corresponding tabs extending from the top edge can be substantially the same as the size of the gap between the corresponding two tabs extending from the bottom edge. For example, the gap between the lead tabs 220a and 220b can be substantially the same as the gap between the lead tabs 230a and 230b. Similarly, the gap between the lead tabs 220a and 240a can be substantially the same as the gap between the lead tabs 230 and 250a.

[0069] Any one or all of the lead tabs 220a and 220b, 240a and 240b can be arranged parallel to the lead tabs 230a and 230b, 250a and 250b respectively, extending from the layers 205 and 215 such that the leads extending from the alternating electrode layers 205 and 215 can be aligned in corresponding columns. For example, the lead tabs 220a and 220b and 230a and 230b of the internal electrode layer 205 can be arranged in corresponding stacked configurations, while the lead tabs 240a and 240b and 250a and 250b of the internal electrode layer 215 can be arranged in corresponding stacked configurations. It will be appreciated that the lead tabs 220a and 220b are respectively connected to the external terminals 22a and 22b, while the lead tabs 240a and 240b are respectively connected to the external terminals 24a and 24b. Accordingly, the corresponding lead tabs 220a and 220b will be staggered with the corresponding lead tabs 240a and 240b respectively, in a manner similar to the external terminals 22a and 22b and 24a and 24b. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portions.

[0070] In the above embodiment, the external terminals are arranged in a single dimension in a linear manner (e.g., 1×2 or 1×4 configuration). Of course, it should be understood that a multi-dimensional array of external terminals can also be employed. Referring Figures 6A to 6D , for example, a particular embodiment of the capacitor 10 having a 2×2 array configuration is shown. In such a configuration, the capacitor includes a total of four external terminals (a first external terminal 12 and a second external terminal 14) located on the upper surface, and a corresponding number of external terminals (a third external terminal and a fourth external terminal, not shown) located on the lower surface. The first external terminal 12 and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminal 14 and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). Although by no means necessary, as described above, a hole 1350 can also be formed between the external terminals 12 and 14 in the capacitor 10.

[0071] The capacitor 10 includes alternating dielectric layers and internal electrode layers 110, and the internal electrode layers 110 include a first internal electrode layer 105 and a second internal electrode layer 115 arranged alternately. Similar to the embodiments discussed above with respect to Figure 3A and Figure 3B , the internal electrode layers 105, 115 also include at least one lead tab 120, 130, 140, 150 extending from the top and bottom edges of the body of the internal electrode layer. However, compared with Figure 3A and Figure 3BContrary to the internal electrodes, the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the distances by which the lateral edges 121, 122 of the first lead tab 120 along the top edge 105c deviate from (indicated by "O") the side edges 105a and 105b can be the same as the distances by which the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c deviate from the side edges 105a and 105b. However, it should be understood that the two lateral edges 121, 122 of the first lead tab 120 along the top edge 105c can be aligned with the lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c. In other words, the distances by which the two side edges 121, 122 of the first lead tab 120 along the top edge 105c deviate from the side edges 105a and 105b can be the same as the distances by which the two lateral edges 131, 132 of the first lead tab 130 along the bottom edge 105d opposite to the top edge 105c deviate from the side edges 105a and 105b.

[0072] Similarly, the lead tabs 140, 150 on the top and bottom edges of the second internal electrode layer 115 can be aligned in the vertical direction. That is, the lateral edges 141, 142 of the first lead tab 140 along the top edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. In one embodiment, the two lateral edges 141, 142 of the first lead tab 140 along the top edge can be aligned with the lateral edges 151, 152 of the first lead tab 150 along the bottom edge opposite to the top edge. The relationship between each lateral edge of the first lead tab on the top edge and each lateral edge of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 105 can also apply to the internal electrode layer 115. With this arrangement, a gap can be formed between the lead tab 120 of the first internal electrode layer 105 and the lead tab 140 of the second internal electrode layer 115. A gap can be formed between the lead tab 130 of the first internal electrode layer 105 and the lead tab 150 of the second internal electrode layer 115. The sizes of the respective gaps can be substantially the same.

[0073] The lead tabs 120 and 140 can be arranged parallel to the lead tabs 130 and 150 respectively, extending from the internal electrode layers 105 and 115, such that the respective lead tabs extending from the alternating electrode layers 105 and 115 can be aligned in corresponding columns. For example, the lead tabs 120 and 130 of the internal electrode layer 105 can be arranged in a corresponding stacked configuration, while the lead tabs 140 and 150 of the internal electrode layer 115 can be arranged in a corresponding stacked configuration. It will be appreciated that the lead tab 120 is connected to the external terminal 12, and the lead tab 140 is connected to the external terminal 14. Thus, each lead tab 120 will be staggered with the corresponding lead tab 140 in a manner similar to the external terminals 12 and 14. The staggered lead tabs can provide multiple adjacent current injection points on the associated main electrode portion.

[0074] As Figure 6D shown, multiple sets 110a and 110b of internal electrode layers 110 can be used to form Figure 6A the external terminal array shown. Generally, the distance "t" between the set 110a and the set 110b is from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distance "t" can be but is not limited to at least 2 times the distance between adjacent lead tabs in a given column, in some embodiments the distance "t" can be but is not limited to at least about 3 times the distance between adjacent lead tabs in a given column, and in embodiments the distance "t" can be but is not limited to from about 4 times to about 8 times the distance between adjacent lead tabs in a given column to ensure that different termination portions do not connect together.

[0075] Referring to FIGS. 7A through Figure 7D 7C, an embodiment of a capacitor 20 having a 2×4 array configuration is shown. In this configuration, the capacitor includes a total of eight external terminals (first external terminals 22a, 22b and second external terminals 24a, 24b) located on the upper surface, and a corresponding number of external terminals (third external terminal and fourth external terminal, not shown) located on the lower surface. The first external terminals 22a, 22b and the third external terminal (not shown) generally have the same polarity (i.e., positive), and the second external terminals 24a, 24b and the fourth external terminal (not shown) generally also have the same polarity (i.e., negative). Although not at all necessary, holes 1350 can also be formed between the external terminals 22a, 22b, 24a and / or 24b in the capacitor 20 as described above.

[0076] The capacitor 20 further includes two sets 210a and 210b of alternating internal electrode layers 210, as Figure 7D shown. As Figure 7B and Figure 7CAs shown, each set of alternating dielectric layers and internal electrode layers 210 includes a first internal electrode layer 205 and a second internal electrode layer 215 arranged alternately. The internal electrode layers 205, 215 include at least one lead tab 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b extending from the top and bottom edges of the body of the internal electrode layer. The lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b of the internal electrode layers 205, 215 extend to the upper and lower surfaces of the capacitor and contribute to forming external terminals. In this regard, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b may be exposed on the upper and lower surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b may include front edges 223a and 223b, 233a and 233b, 243a and 243b, 253a and 253b that extend to the edges of the dielectric layer and allow formation of the external terminals. The internal electrode layers 205, 215 include at least two lead tabs 220a and 220b, 230a and 230b, 240a and 240b, 250a and 250b along the top and bottom edges. The first internal electrode layer 205 includes two lead tabs 220a and 220b each extending from the body 235 along the top edge 205c, and two lead tabs 230a and 230b each extending from the body 235 along the bottom edge 205d. The second internal electrode layer 215 includes two lead tabs 240a and 240b each extending from the body 245 along the top edge, and two lead tabs 250a and 250b each extending from the body 245 along the bottom edge.

[0077] The lead tabs 220a and 220b, 230a and 230b on the top edge 205c and the bottom edge 205d of the first internal electrode layer 205 can be aligned in the vertical direction. That is, the lateral edges 221a, 222a of the first lead tab 220a along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230a along the bottom edge 205d opposite to the top edge 205c. In other words, the distances by which the lateral edges 221a, 222a of the first lead tab 220 along the top edge 205c deviate from (indicated by "O") the side edges 205a and 205b can be the same as the distances by which the lateral edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c deviate from the side edges 205a and 205b. In addition, the two lateral edges 221a, 222a of the first lead tab 220 along the top edge 205c can be aligned with the lateral edges 231a, 232a of the first lead tab 230 along the bottom edge 205d opposite to the top edge 205c. That is, the two side edges can deviate from the side edges 205a and 205b by the same distance. When the top edge 205c and the bottom edge 205d include at least two lead tabs 220a and 220b, 230a and 230b, at least one lateral edge of each lead tab on the top edge 205c can be aligned with the corresponding lateral edge of the lead tab on the bottom edge 205d. In addition, the two lateral edges of each lead tab on the top edge 205c can be aligned with the corresponding lateral edges of the lead tab on the bottom edge 205d.

[0078] Similarly, the lead tabs 240a and 240b, 250a and 250b on the top and bottom edges of the second internal electrode layer 215 can be aligned in the vertical direction. That is, the lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. The two lateral edges 241a, 242a of the first lead tab 240 along the top edge can be aligned with the lateral edges 251a, 252a of the first lead tab 250 along the bottom edge opposite the top edge. The relationship between the respective lateral edges of the first lead tab on the top edge and the respective lateral edges of the first lead tab on the bottom edge as mentioned with respect to the internal electrode layer 205 can also apply to the internal electrode layer 215. With this arrangement, a gap can be formed between the lead tabs along the top edge 205c of the first internal electrode layer 205, the lead tabs along the top edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 220a and 220b, 240a and 240b extending from the top edges of the respective internal electrode layers. Additionally, a gap can be formed between the lead tabs along the top edge 205d of the first internal electrode layer 205, the lead tabs along the bottom edge of the second internal electrode layer 215, or any of the lead tabs in both. For example, a gap can be formed between any of the lead tabs 230a and 230b, 250a and 250b extending from the top edges of the respective internal electrode layers. Furthermore, whether from the same internal electrode layer or from adjacent internal electrode layers, the size of the gap between two corresponding tabs extending from the top edge can be substantially the same as the size of the gap between the corresponding two tabs extending from the bottom edge. For example, the gap between lead tabs 220a and 220b can be substantially the same as the gap between lead tabs 230a and 230b. Similarly, the gap between lead tabs 220a and 240a can be substantially the same as the gap between lead tabs 230a and 250a.

[0079] Any one or all of the lead tabs 220a and 220b, 240a and 240b may be arranged parallel to the lead tabs 230a and 230b, 250a and 250b, respectively, and extend from the layers 205 and 215 such that the leads extending from the alternating electrode layers 205 and 215 may be aligned in corresponding columns. For example, the lead tabs 220a and 220b and 230a and 230b of the internal electrode layer 205 may be arranged in corresponding stacked configurations, while the lead tabs 240a and 240b and 250a and 250b of the internal electrode layer 215 may be arranged in corresponding stacked configurations. It will be appreciated that the lead tabs 220a and 220b are connected to the external terminals 22a and 22b, respectively, while the lead tabs 240a and 240b are connected to the external terminals 24a and 24b, respectively. Thus, the respective lead tabs 220a and 220b will be staggered with the respective lead tabs 240a and 240b in a manner similar to the external terminals 22a and 22b and 24a and 24b. The staggered lead tabs may provide multiple adjacent current injection points on the associated main electrode portions.

[0080] As Figure 7D shown, multiple sets of the internal electrode layers 110 of 210a and 210b may be used to form Figure 7A the external terminal array shown. Generally, the distance "t" between the set 110a and the set 110b is from about 0.2 μm to about 10 μm, in some embodiments from about 0.5 μm to about 8 μm, and in some embodiments from about 1 μm to about 5 μm. Additionally, the distance "t" may be, but is not limited to, at least 2 times the distance between adjacent lead tabs in a given column, in some embodiments the distance "t" may be, but is not limited to, at least about 3 times the distance between adjacent lead tabs in a given column, and in embodiments the distance "t" may be, but is not limited to, from about 4 times to about 8 times the distance between adjacent lead tabs in a given column to ensure that different termination portions do not connect together.

[0081] Referring Figure 8A and Figure 8B, shows an embodiment of a capacitor 20 having a 4×4 array configuration. In such a configuration, the capacitor includes a total of 16 external terminals (first external terminals 32a, 32b and second external terminals 34a, 34b) located on the upper surface, and a corresponding number of external terminals (third external terminals and fourth external terminals, not shown) located on the lower surface. The first external terminals 32a, 32b and the third external terminals (not shown) generally have the same polarity (i.e., positive), and the second external terminals 34a, 34b and the fourth external terminals (not shown) generally also have the same polarity (i.e., negative). Although not at all necessary, holes 1350 may also be formed between the external terminals 32a, 32b, 34a and / or 34b in the capacitor 20 as described above. As Figure 8B shown, the capacitor 30 also includes internal electrode layers 210 arranged in four groups 210a, 210b, 210c and 210d. Similar to the embodiments discussed above, the distance "t 1 ", "t 2 " and / or "t 3 " can be from about 0.2 μm to about 10 μm, in some embodiments, from about 0.5 μm to about 8 μm, and in some embodiments, from about 1 μm to about 5 μm. Additionally, the distance "t 1 ", "t 2 " and / or "t 3 " can be but is not limited to at least 2 times the distance between adjacent lead tabs in a given column. In some embodiments, the distance "t 1” , "t 2 " and / or "t 3 " can be but is not limited to at least about 3 times the distance between adjacent lead tabs in a given column, and in embodiments, the distance "t 1 ", "t 2 " and / or "t 3 " can be but is not limited to about 4 times to about 8 times the distance between adjacent lead tabs in a given column to ensure that different terminations do not connect together.

[0082] In the above embodiments, the internal electrode layers are generally oriented in a vertical configuration. Of course, this is by no means necessary, and other geometric configurations, such as a horizontal configuration, are equally suitable. Referring to Figures 9A to 9C , for example, shows the capacitor 20, similar to Figure 8A and Figure 8B , the capacitor 20 has a 4×4 configuration of external terminals 32 and 34, but employs a horizontal internal electrode configuration. That is, as Figure 9B and Figure 9CAs shown, the capacitor 20 includes a plurality of internal electrode layers 205 and 215 arranged alternately and a plurality of dielectric layers, wherein the electrode layers are staggered in a relative and spaced-apart relationship, and the dielectric layers are located between each adjacent electrode layer. The internal electrode layers are electrically connected to external terminals through conductive vias (e.g., the first conductive via 225 and the second conductive via 285). The conductive vias extend to the upper surface 235 and the lower surface 245 of the capacitor. In this regard, the conductive vias can be exposed on the upper surface 235 and the lower surface 245 of the capacitor. This exposure can contribute to the formation of external terminals on the upper surface 235 and the lower surface 245 of the capacitor. In addition, the internal electrode layers 205 and 215 have a rectangular configuration and are arranged such that they do not extend to the side surface of the capacitor.

[0083] If desired, the capacitor 20 may further include a first shielding region 255 and a second shielding region 265, and each shielding region may include one or more shielding electrode layers 275. As shown, the shielding regions are provided above and below the active electrode region and the active electrode layers 205, 215. Figure 9C The use of a first anchor electrode 305 and a second anchor electrode 295 is also shown. The first anchor electrode 305 is provided in the first active electrode layer 205 having a first active electrode. In this regard, the first active electrode is electrically connected to the first conductive via 225, while the first anchor electrode is connected to the second conductive via 285. Similarly, the second anchor electrode 295 is provided in the second active electrode layer 215 having a second active electrode. In this regard, the second active electrode is electrically connected to the second conductive via 285, while the second anchor electrode is connected to the first conductive via 225.

[0084] The first conductive via 225 extends through and is in electrical contact with the first plurality of internal electrode layers 205. However, the first conductive via 225 extends through the non-contact via 105, wherein a gap 105 is formed between the first conductive via 225 and the electrodes of the second plurality of internal electrode layers 215. Such a gap 105 allows the second plurality of internal electrode layers 215 to be insulated from the first conductive via 225. Similarly, the second conductive via 285 extends through and is in electrical contact with the second plurality of internal electrode layers 215. However, the second conductive via 285 extends through the non-contact via 115, wherein a gap 115 is formed between the second conductive via 285 and the electrodes of the first plurality of internal electrode layers 205. Such a gap 115 allows the first plurality of internal electrode layers 205 to be insulated from the second conductive via 285. When there are anchor (or dummy) electrodes as shown in FIG. 10C, these layers also include gaps 125 and 135. The first conductive via 225 extends through and is in electrical contact with the first plurality of internal electrode layers 205 and contacts the second anchor tab 295. However, the second anchor tab 295 is isolated from the active electrodes of the second plurality of internal electrode layers 215 by a gap 125 formed between the anchor tab 295 and the active electrodes 215. Such a gap 125 allows the second plurality of internal electrode layers 215 to be insulated from the second anchor tab 295 and the first conductive via 225.

[0085] The dielectric layer of the ceramic capacitor described herein is generally formed of a ceramic material. The dielectric material may have a relatively high dielectric constant. For example, the dielectric constant may be 3 or greater, in some embodiments, from about 10 to about 20000, in some embodiments, from about 50 to about 10000, in some embodiments, from about 60 to about 9000, in some embodiments, from about 80 to about 8000. Particularly suitable examples of ceramic materials having a high dielectric constant are ceramic materials designated as NPO (COG) (up to about 100), X7R (from about 3000 to about 7000), X7S, Z5U, and / or Y5V based on the standard classification established by the Electronic Industries Alliance (EIA). Such materials may include perovskites, such as barium titanate ceramic materials (e.g., barium titanate, barium strontium titanate, calcium barium titanate, barium zirconate titanate, strontium barium zirconate titanate, calcium barium zirconate titanate, etc.), lead titanate ceramic materials (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), bismuth sodium titanate, etc. In one particular embodiment, for example, a chemical formula of Ba x Sr 1-x TiO 3barium strontium titanate (“BSTO”), where x ranges from 0 to 1, and in some embodiments, x ranges from about 0.15 to about 0.65, and in some embodiments, x ranges from about 0.25 to about 0.6. Other suitable barium titanate ceramic materials can include, for example: Ba x Ca 1-x TiO 3 , where x ranges from about 0.2 to about 0.8, and in some embodiments, ranges from about 0.4 to about 0.6; barium calcium zirconium titanate (BaCaZrTiO 3 ); A[B1 1 / 3 B2 2 / 3 O 3 materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1), B1 is Mg y Zn 1-y (y can be a value from 0 to 1), B2 is Ta z Nb 1-z (z can be a value from 0 to 1); and so on. Other suitable ceramic materials can include, for example, Pb x Zr 1-x TiO 3 (“PZT”), where the range of x is from about 0.05 to about 0.4; lanthanum lead zirconate titanate (“PLZT”); lead titanate (PbTiO 3 ); and so on.

[0086] The internal electrode layer can be formed of any of a variety of different metals known in the art. The internal electrode layer can be made of a metal (e.g., a conductive metal). These materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys, as well as respective sputtered layers of chromium, nickel, and gold, may also be suitable. In a particular embodiment, the internal electrode layer can include nickel or an alloy thereof. Similarly, the external terminals can be formed of any of a variety of different metals known in the art. The external terminals can be made of a metal (e.g., a conductive metal). These materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and the like, as well as various combinations thereof. In a particular embodiment, the external terminals can include copper or an alloy thereof. The average thickness of the external terminals can be about 100 μm or less, and in some embodiments, the average thickness of the external terminals can be about 1 μm to about 70 μm, and in some embodiments, the average thickness of the external terminals can be about 5 μm to about 50 μm.

[0087] Any method known in the art can be used to form the external terminals. The external terminals can be formed using techniques such as sputtering, spraying, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spraying / air brushing, etc. The external terminals can be formed such that the external terminals are thin film coatings of metal. Such thin film coatings can be formed by depositing a conductive material (e.g., a conductive metal) on the exposed portion of the internal electrode layer. For example, the front edge of the internal electrode layer can be exposed such that the front edge can permit the formation of plated terminals. The plated terminals can be formed by techniques known in the art, such as electroless plating, electroplating, or combinations thereof. When multiple layers are used to form the external terminals, the external terminals can include an electroplated layer and an electroless plated layer. For example, electroless plating can be first used to deposit an initial material layer. Then the plating technique can be switched to an electroplating system, which can allow for faster material buildup. When forming the plated terminals using either plating method, the front edge of the lead tab of the internal electrode layer that is exposed from the body of the capacitor is subjected to the plating solution. In one embodiment, by subjecting, the capacitor is immersed in the plating solution.

[0088] The plating solution used during the plating process can include a conductive material, such as a conductive metal. For example, the plating solution can be a nickel sulfamate bath solution or other nickel solution such that the coating and the external terminals include nickel. Alternatively, the plating solution can be a copper acid bath or other suitable copper solution such that the coating and the external terminals include copper. Additionally, it should be understood that the plating solution can include other additives known in the art. For example, the additives can include other organic additives and media that can assist the plating process. Additionally, additives can be used in order to use the plating solution at a desired pH level. In one embodiment, a resistance reducing additive can be employed in the solution to aid in complete coating coverage and bonding of the plating material to the exposed front edge of the lead tab of the capacitor and the internal electrode layer. The capacitor can be exposed, submerged, or immersed in the plating solution for a predetermined amount of time. The exposure time need not be limited, but can be for a sufficient amount of time to allow for the deposition of sufficient plating material in order to form the plated terminals. In this regard, the time should be sufficient to allow for the formation of a continuous connection between the desired exposed adjacent front edges of the lead tabs of the respective internal electrode layers within a set of alternating dielectric layers and internal electrode layers.

[0089] The difference between electroplating and electroless plating is that electroplating employs an electrical bias, such as by using an external power source. The electroplating solution can typically be subjected to a high current density range, e.g., ten to fifteen amps per square foot (amp / ft 2)(The rated voltage is 9.4 volts). The following connection can be formed: in this connection, the negative electrode is connected to the capacitor where the plating terminal needs to be formed, and the positive electrode is connected to the solid material in the same plating solution (for example, copper in a copper plating solution). That is, the capacitor is biased to a polarity opposite to that of the plating solution. Using this method, the conductive material of the plating solution is attracted to the metal at the exposed front edge of the lead tab of the internal electrode layer.

[0090] Before immersing the capacitor in the plating solution or subjecting it to the plating solution, various pretreatment steps can be employed. Such steps can be carried out for a variety of purposes, including catalyzing, accelerating, and / or improving the adhesion of the plating material to the front edge of the lead tab. Additionally, an initial cleaning step can be employed before plating or any other pretreatment step. This step can be used to remove any oxide buildup formed on the exposed lead tab of the internal electrode layer. When the internal electrode or other conductive element is formed of nickel, this cleaning step may be particularly helpful in removing any buildup of nickel oxide. Component cleaning can be achieved by completely immersing in a pre-cleaning bath (for example, a pre-cleaning bath including an acidic cleaner). In one embodiment, the exposure can last for a predetermined time, for example, on the order of about 10 minutes. Cleaning can alternatively be achieved through a chemical polishing or harperizing step.

[0091] Additionally, a step of activating the exposed metal front edge of the lead tabs of the internal electrode layer can be performed to facilitate the deposition of the conductive material. The activation can be achieved by dipping in palladium salts, photopatterning palladium organometallic precursors (by mask or laser), screen printing or inkjet deposition of palladium compounds, or electrophoretic palladium deposition. It should be recognized that palladium-based activation is currently only disclosed as an example of an activation solution, which generally works well with the activation of the exposed tab portions formed of nickel or its alloys. However, it should be understood that other activation solutions can also be used, and thus other activation solutions need not be limited. Additionally, as an alternative to or in addition to the above activation step, an activation dopant can be introduced into the conductive material when forming the internal electrode layer of the capacitor. For example, when the internal electrode layer includes nickel and the activation dopant includes palladium, the palladium dopant can be introduced into the nickel ink or composition for forming the internal electrode layer. Doing so can eliminate the palladium activation step. It should be further recognized that some of the above activation methods (e.g., organometallic precursors) also contribute to the co-deposition of themselves with the glass former to increase the adhesion to the general ceramic body of the capacitor. When the activation step is used as described above, traces of the activator material may generally remain at the exposed conductive portions before and after the termination plating. Additionally, post-treatment steps after plating can also be employed as needed or necessary. Such steps can be performed for various purposes, including enhancing and / or improving the adhesion of the materials. For example, a heating (or annealing) step can be employed after the plating step. Such heating can be carried out by baking, laser irradiation, ultraviolet (UV) exposure, microwave exposure, arc welding, etc.

[0092] Thus, as described above, the external terminals used in the capacitor can include at least one plating layer. In one embodiment, the external terminal can include only one plating layer. However, it should be understood that the external terminal can include multiple plating layers. For example, the external terminal can include a first plating layer and a second plating layer. Additionally, the external terminal can further include a third plating layer. Moreover, the materials of these plating layers can be any of the above and known in the art. For example, one plating layer (e.g., the first plating layer) can include copper or its alloy. Another plating layer (e.g., the second plating layer) can include nickel or its alloy. Alternatively, another plating layer (e.g., the second plating layer) can include copper or its alloy. Another plating layer (e.g., the third plating layer) can include tin, lead, gold, or a combination, such as an alloy. Alternatively, the initial plating layer can include nickel, followed by a plating layer of tin or gold. In another embodiment, an initial plating layer of copper can be formed, followed by a nickel layer.

[0093] In one embodiment, the initial or first plating may be a conductive metal (e.g., copper). The area may then be covered with a second layer comprising a resistive polymeric material for sealing. The area may then be polished to selectively remove the resistive polymeric material and then plated again with a third layer comprising a conductive metal material (e.g., copper). The aforementioned second layer above the initial plating may correspond to a solder mask layer, such as a nickel solder mask layer. In some embodiments, the above layers may be formed by electroplating an additional metal (e.g., nickel or copper) layer on top of an initial electroless or electroplated layer (e.g., plated copper). Other exemplary layer materials for the solder mask layer include nickel-phosphorus, gold, and silver. In some embodiments, the third layer on the solder mask layer may correspond to a conductive layer, such as plated nickel (Ni), nickel / chromium (Ni / Cr), silver (Ag), palladium (Pd), tin (Sn), lead / tin (Pb / Sn), or other suitable plated solder. Additionally, a layer of metal plating may be formed and then an electroplating step may be performed to provide a resistive alloy or a higher resistivity metal alloy coating on such metal plating, such as electroless Ni-P alloy. However, it should be understood that any metal coating may be included, as would be understood by one of ordinary skill in the art from the entire disclosure herein. It should be recognized that any of the above steps may be performed as a batch process, such as a barrel plating process, a fluidized bed plating process, and / or a flow-through plating termination process, all of which are known in the art. Such batch processes are capable of processing multiple components simultaneously, thereby providing an efficient and rapid termination process. This is a particular advantage over conventional termination methods, such as printing on thick film terminations that require individual component handling).

[0094] IV. Semiconductor Encapsulation Component

[0095] As is known in the art, semiconductor package components may be electrically connected and / or mounted on a circuit board (e.g., a printed circuit board) to form a microelectronic assembly. Within the package component itself, semiconductor structures, package substrates, and ceramic capacitors may typically be arranged in various different configurations to connect to the circuit board. For example, referring to Figure 1, shows an embodiment of a semiconductor package assembly 600 that includes semiconductor structures 610, 620, and 630 electrically connected to an interposer 650 and a package substrate 680 electrically connected to the interposer 650. The semiconductor structures can be any type of structure as described above. For example, in one embodiment, structures 610 and 630 can be high bandwidth memory structures, field programmable gate arrays. As shown, semiconductor structures 610, 620, and 630 can be electrically connected to the interposer 650 via first level coupling components 611, 621, and 631, respectively. In the illustrated embodiment, coupling component 621 can be a solder ball or solder bump, while coupling components 611 and 631 can be a conductive adhesive or underfill material. Although not at all necessary, a molding compound 760 can also be employed. The molding compound can be, for example, an insulating material as described above (e.g., an epoxy resin material). Similarly, the interposer 650 includes conductive traces 652 formed within an insulating dielectric material 654. The conductive traces 652 allow the interposer 650 to be electrically connected to the package substrate 680 via second level coupling components 656 (e.g., solder balls or solder bumps). The package substrate 680 in turn includes conductive traces 682 (e.g., vias) within an insulating dielectric material 684. The conductive traces 682 allow the package assembly 800 to be electrically connected to a circuit board 800 (e.g., a printed circuit board) via third level coupling components 704 (e.g., solder balls) (via the package substrate 680).

[0096] It is noted that ceramic capacitor 10 (e.g., see Figure 3A and Figure 3B) is also electrically connected to at least one of the semiconductor structures 610, 620, and / or 630 and the package substrate 680. More particularly, in the illustrated embodiment, the ceramic capacitor 10 is positioned between at least a portion of the package interposer 650 and the package substrate 680. Of course, the ceramic capacitor 10 can also be positioned at various other locations within the package, such as between the semiconductor structures 610, 620, and / or 630 and the interposer 650. Although only one capacitor is shown, it should of course be understood that multiple ceramic capacitors can be employed. The external terminals of one or more ceramic capacitors can be in electrical communication with the current paths of the interposer and the package substrate, respectively, and can be electrically connected to the interposer and the package substrate using any method commonly known in the art. For example, in addition to the solder balls 656, the ceramic capacitor 10 can be directly electrically connected to the package substrate 680 and the interposer 650, or at least a coupling component 702 (e.g., a solder bump) having a size smaller than the coupling component 656 can be employed. The capacitor 10 can allow an alternating current (AC) signal to pass through or be transmitted while generally blocking a direct current (DC) signal. That is, the capacitor can be used to block low-frequency signals and transmit high-frequency signals. Additionally, by arranging the capacitor 10 as shown, certain conductive paths located directly above the capacitor can be eliminated, thereby further improving performance. Using a ceramic capacitor in this manner can also significantly reduce inductance. In particular, minimizing the distance or path to ground can help reduce inductance. For example, using a ceramic capacitor can result in an inductance of about 1 nanohenry (nH) or less, about 25 femtohenry (fH) to about 900 picohenry (pF) in some embodiments, about 100 fH to about 500 pF in some embodiments, and about 250 fH to about 100 pF in some embodiments. The ceramic capacitor can also exhibit a low equivalent series resistance, which is, for example, about 100 milliohms (mΩ) or less, about 0.01 mΩ to about 50 mΩ in some embodiments, about 0.1 mΩ to about 40 mΩ in some embodiments, and about 0.5 mΩ to about 30 mΩ in some embodiments. A low inductance and / or equivalent series resistance can be achieved while still exhibiting a customized capacitance value, for example, a capacitance value of about 1 picofarad (pF) to about 1000 microfarads (μF), about 500 pF to about 500 μF in some embodiments, and about 1 μF to about 100 μF in some embodiments.

[0097] In Figure 1 the illustrated embodiment, the interposer 650 is generally considered a “passive” interposer because it does not contain any integrated electronic components. However, it should be understood that an “active” interposer can also be appropriately used in the semiconductor package assembly of the present invention. For example, referring toFigure 2 shows an embodiment of a semiconductor package assembly 800 that includes an active interposer 802 also shown in FIG. 3. In this embodiment, the interposer 802 is electrically connected to a package substrate 832, and a semiconductor structure 310 (e.g., a coprocessor) is electrically connected to the interposer 802. The semiconductor structure 310 may include an active layer 392 and a bulk semiconductor layer 390 (sometimes referred to herein as a passive layer 390). The active layer 392 may include circuit elements and a register bank 394, and the register bank 394 may act as on-die memory for the structure 310. Similarly, the active interposer 802 may include an active layer 806 and a bulk semiconductor layer 804 (sometimes referred to as a passive layer 804). The passive layer 806 may include a plurality of level-1 (L1) memory elements 808 formed on the active side, and the plurality of L1 memory elements 808 may be used as a memory cache for storing configuration bitstreams for configuring logical sectors in the structure 310. The active interposer 802 may be electrically connected to the package substrate 832 through coupling components 822 (e.g., solder bumps or solder balls), and the passive layer 804 may include through-silicon vias (TSVs) 810 that may connect components (e.g., the L1 memory elements 808 in the active layer 806) to the coupling components 822. The active layer 806 may face the active layer 392 of the semiconductor structure 310 and may be electrically connected to components in the active layer 392 through coupling components 820 (e.g., solder bumps).

[0098] If desired, an additional semiconductor structure 812 (e.g., an auxiliary chip) may be directly electrically connected to the substrate 832. The structure 812 may include an active layer 816 and a bulk semiconductor layer 814 (sometimes referred to as a passive layer 814). The active layer 816 may include level-2 (L2) memory elements 809 formed on the active side, and the L2 memory elements 809 may be used as a memory cache for storing configuration bitstreams. For example, the configuration bitstreams stored in the L1 memory elements 808 on the interposer 802 may be transferred to the L2 memory elements 809 to make room on the L1 memory elements 808 for newly incoming configuration bitstreams (e.g., configuration bitstreams received from a host processor at the L1 memory elements 808). The active layer 816 may face the package substrate 832 and may be electrically connected to the package substrate 832 through coupling components 822 and 824 (e.g., solder balls or solder bumps). A bridge 826 may also be used to connect the semiconductor structure 812 to the interposer 802. The bridge 826 may include interconnects 828 formed in a silicon substrate that is embedded in the package substrate 832. The interconnects 828 may electrically connect the portion of the coupling component 824 connected to the semiconductor structure 812 to the portion of the coupling component 824 connected to the interposer 802. As is known in the art, a heat sink 830 may also be provided in contact with the semiconductor structures 310 and 812.

[0099] As shown, ceramic capacitor 20 (e.g., see Figure 5A and Figure 5B ) is also electrically connected to semiconductor structure 310 and package substrate 832 via an interposer 802. More particularly, in the illustrated embodiment, ceramic capacitor 20 is positioned between at least a portion of interposer 802 and package substrate 832. Via 810 can electrically connect ceramic capacitor 20 to semiconductor structure 310 via coupling component 820. Ceramic capacitor 20 can also be electrically connected to L1 memory element 808 in active layer 806. The external terminals of one or more ceramic capacitors can be in electrical communication with the current paths of the interposer and the package substrate, respectively, and can be electrically connected to the interposer and the package substrate using any method commonly known in the art. For example, in addition to solder balls 824 or 822, ceramic capacitor 20 can be directly electrically connected to package substrate 832 and interposer 802, or at least a coupling component 722 (e.g., solder bump) having a size smaller than coupling components 824 or 822 can be employed.

[0100] Those of ordinary skill in the art can practice these and other modifications and variations of the present invention without departing from the spirit and scope of the present invention. Additionally, it should be understood that aspects of the various embodiments can be interchanged, in whole or in part. Further, those of ordinary skill in the art will understand that the foregoing description is by way of example only and is not intended to limit the present invention as further described in the appended claims.

Claims

1. A semiconductor packaging component, the semiconductor packaging component comprises: a semiconductor structure; a packaging substrate electrically connected to the semiconductor structure; and a ceramic capacitor having a first surface and an opposite second surface, wherein the ceramic capacitor comprises alternating dielectric layers and internal electrode layers, the internal electrode layers comprising a first internal electrode layer and a second internal electrode layer, and wherein the capacitor further comprises a first external terminal, a second external terminal, a third external terminal and a fourth external terminal, the first external terminal being electrically connected to the first internal electrode layer and disposed on the first surface of the capacitor, the second external terminal being electrically connected to the first internal electrode layer and disposed on the second surface of the capacitor, the third external terminal being electrically connected to the second internal electrode layer and disposed on the first surface of the capacitor, the fourth external terminal being electrically connected to the second internal electrode layer and disposed on the second surface of the capacitor, and wherein the first external terminal and the third external terminal are electrically connected to the semiconductor structure, and the second external terminal and the fourth external terminal are electrically connected to the packaging substrate.

2. The semiconductor packaging component according to claim 1, wherein, the semiconductor structure is an integrated circuit device.

3. The semiconductor packaging component according to claim 2, wherein, the integrated circuit device comprises a memory device, a logic device, a processor device or a combination thereof.

4. The semiconductor packaging component according to claim 1, wherein, the component comprises a plurality of semiconductor structures.

5. The semiconductor packaging component according to claim 4, wherein, the plurality of semiconductor structures are arranged in an array.

6. The semiconductor packaging component according to claim 4, wherein, the plurality of semiconductor structures are stacked.

7. The semiconductor packaging component according to claim 1, wherein, the packaging substrate comprises an insulating material, and one or more conductive paths are formed through the insulating material, and wherein the conductive paths are electrically connected to the second external terminal and the fourth external terminal of the ceramic capacitor.

8. The semiconductor packaging component according to claim 7, wherein, the insulating material comprises an organic material, an inorganic material, a semiconductor material or a combination thereof.

9. The semiconductor packaging component according to claim 1, the semiconductor packaging component further comprises an interposer electrically connected to the semiconductor structure and the packaging substrate, wherein, the first external terminal and the third external terminal are electrically connected to the interposer.

10. The semiconductor packaging component according to claim 9, wherein, the interposer comprises an insulating material, and one or more conductive paths are formed through the insulating material, and wherein the conductive paths are electrically connected to the first external terminal and the third external terminal of the ceramic capacitor.

11. The semiconductor packaging component according to claim 9, wherein, the insulating material comprises an organic material, an inorganic material, a semiconductor material or a combination thereof.

12. The semiconductor packaging component according to claim 9, wherein, the electronic component is embedded in the interposer.

13. The semiconductor packaging component according to claim 12, wherein, the electronic component includes a capacitor, a resistor, an inductor, a fuse, a diode, a transformer, a sensor, an electrostatic discharge device, a memory device, a radio frequency device, a power amplifier, a power management device, an antenna, a microelectromechanical system, or a combination thereof.

14. The semiconductor packaging component according to claim 12, wherein, the ceramic capacitor is embedded in the interposer.

15. The semiconductor packaging component according to claim 1, wherein, the first external terminal and the second external terminal have a positive polarity, and the third external terminal and the fourth external terminal have a negative polarity.

16. The semiconductor packaging component according to claim 1, wherein, at least one of the first external terminal, the second external terminal, the third external terminal, or the fourth external terminal extends to an end surface of the capacitor.

17. The semiconductor packaging component according to claim 1, wherein, the first external terminal, the second external terminal, the third external terminal, or the fourth external terminal does not extend to an end surface of the capacitor.

18. The semiconductor packaging component according to claim 1, wherein, the ceramic capacitor includes only the first external terminal and the third external terminal on the first surface, and includes only the second external terminal and the fourth external terminal on the second surface.

19. The semiconductor packaging component according to claim 1, wherein, the capacitor includes at least four external terminals on the first surface and includes at least four external terminals on the second surface.

20. The semiconductor packaging component according to claim 19, wherein, the external terminals are arranged linearly on the first surface and the second surface.

21. The semiconductor packaging component according to claim 19, wherein, the external terminals are arranged in a multi-dimensional array on the first surface and the second surface.

22. The semiconductor packaging component according to claim 1, wherein, the first internal electrode layer and the second internal electrode layer are arranged vertically.

23. The semiconductor packaging component according to claim 22, wherein, the first internal electrode layer includes a lead tab extending to the first surface to contact the first external terminal and a lead tab extending to the second surface to contact the third external terminal, and further wherein the second internal electrode layer includes a lead tab extending to the first surface to contact the second external terminal and a lead tab extending to the second surface to contact the fourth external terminal.

24. The semiconductor packaging component according to claim 1, wherein, the first internal electrode layer and the second internal electrode layer are arranged horizontally.

25. The semiconductor packaging component according to claim 24, wherein, The first internal electrode layer and the second internal electrode layer are connected to the first external terminal, the second external terminal, the third external terminal, and the fourth external terminal through conductive vias.

26. The semiconductor package assembly according to claim 1, wherein, the dielectric layer of the ceramic capacitor comprises a ceramic material.

27. The semiconductor package assembly according to claim 26, wherein, the ceramic material is a barium titanate ceramic material.

28. The semiconductor package assembly according to claim 1, wherein, the first external terminal, the second external terminal, the third external terminal, and the fourth external terminal comprise at least one plating layer.

29. The semiconductor package assembly according to claim 28, wherein, the plating layer is formed by a process including electroless plating, electroplating, or a combination thereof.

30. The semiconductor package assembly according to claim 1, wherein, the circuit board is electrically connected to the package substrate through a coupling component.

31. The semiconductor package assembly according to claim 30, wherein, the coupling component comprises solder.

32. The semiconductor package assembly according to claim 1, wherein, the second external terminal and the fourth external terminal of the ceramic capacitor are electrically connected to the package substrate through a coupling component.

33. A microelectronic component, the microelectronic component comprising the semiconductor package assembly according to claim 1, and a circuit board, wherein, the package substrate is electrically connected to the circuit board.

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