Glare and occluded view compensation for automotive and other applications

Abstract

The invention discloses glare and occluded view compensation for automotive and other applications. Usually when glare is present on the display screen, a user may be able to mitigate glare by tilting or otherwise moving the screen or changing its view position. However, when driving an automobile, there are limited options to overcome glare on the dashboard, especially when you are driving longer distances in the same direction. Various embodiments relate to eliminating such glare. Other embodiments relate to mixed reality (MR) and filling occluded areas.

Description

This application is a divisional application of the invention patent application with the application date of April 16, 2018, the priority date of April 17, 2017, the application number of 201810338031.6, and the title of "Glare and Occluded View Compensation for Automotive and Other Applications". Technical Field

[0001] Embodiments generally relate to glare on instrument panels or windshields, and more particularly, to reducing the effects of such glare and blind spots. Background Art

[0002] Typically, when there is glare on a display screen, users may be able to reduce the glare by tilting or otherwise moving the screen or changing their viewing position. Also, they may be able to move the room or close the curtains on the window, etc. However, when driving a car, the options for overcoming glare on the instrument panel or windshield are limited, especially when you are driving a long distance in the same direction. Brief Description of the Drawings

[0003] The various advantages of the embodiments will become apparent to those skilled in the art by reading the following description and the appended claims and by referring to the following drawings, in which:

[0004] Figure 1 is a block diagram showing a computer system configured to implement one or more aspects of the embodiments described herein;

[0005] Figures 2A to 2D shows a parallel processor component according to an embodiment;

[0006] Figures 3A to 3B is a block diagram of a graphics multi-processor according to an embodiment;

[0007] Figures 4A to 4F shows an exemplary architecture in which multiple GPUs are communicatively coupled to multiple multi-core processors;

[0008] Figure 5 shows a graphics processing pipeline according to an embodiment;

[0009] Figure 6A and Figure 6B are examples of a block diagram and a flowchart showing the movement of gauges and instruments due to glare on the instrument panel, respectively;

[0010] Figures 7A to 7B are examples of a block diagram showing glare on the windshield and reducing such glare, respectively;

[0011] Figure 7C is an example flowchart showing the steps for reducing glare on the windshield;

[0012] Figures 8A to 8B is an example block diagram showing a system for reducing blind spots in front of a vehicle;

[0013] Figures 9A to 9B is an example block diagram showing mixed reality (MR) occluded regions and devices for filling these regions;

[0014] Figure 10 is an example flowchart showing steps for filling MR occluded regions;

[0015] Figure 11 is a block diagram of an example of a display having local backlight capabilities according to an embodiment;

[0016] Figure 12A is a block diagram of an example of a data processing device according to an embodiment;

[0017] Figure 12B is a display of an example of distance determination according to an embodiment;

[0018] Figure 13 is a block diagram of an example of a hierarchical display architecture according to an embodiment;

[0019] Figure 14 is a block diagram of an example of a display architecture according to an embodiment, the display architecture including a plurality of display units;

[0020] Figure 15 is a block diagram of an example of a cloud-assisted media delivery architecture according to an embodiment;

[0021] Figures 16 to 18 is a block diagram of an example of an overview of a data processing system according to an embodiment;

[0022] Figure 19 is a block diagram of an example of a graphics processing engine according to an embodiment;

[0023] Figures 20 to 22 is a block diagram of an example of an execution unit according to an embodiment;

[0024] Figure 23 is a block diagram of an example of a graphics pipeline according to an embodiment;

[0025] Figures 24A to 24B is a block diagram of an example of a graphics pipeline according to an embodiment;

[0026] Figure 25 is a block diagram of an example of a graphics software architecture according to an embodiment;

[0027] Figure 26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and

[0028] Figure 27 It is a block diagram of an example of a system-on-chip integrated circuit according to an embodiment. Detailed implementation

[0029] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features are not described to avoid obscuring the present invention.

[0030] System Overview

[0031] Figure 1 It is a block diagram showing a computing system 100 configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, and the processors communicate with the system memory via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component or may be integrated within one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, and the display controller may be included within one or more processors 102. In one embodiment, one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0032] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express bus), or can be a vendor-specific communication interface or communication fabric. In one embodiment, one or more parallel processors 112 form a computationally centralized parallel or vector processing system that includes a large number of processing cores and / or processing clusters (such as, many integrated core (MIC) processors). In one embodiment, one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of one or more display devices 110A coupled via the I / O hub 107. One or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0033] Within the I / O subsystem 111, the system storage unit 114 can be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. The I / O switch 116 can be used to provide an interface mechanism to enable connections between the I / O hub 107 and other components (such as, a network adapter 118 and / or a wireless network adapter 119 that can be integrated into the platform, and various other devices that can be added via one or more plug-in devices 120). The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or other network devices that include one or more radio devices.

[0034] The computing system 100 may include other components not explicitly shown, including USB or other port connectors, optical storage drives, video capture devices, etc., which can also be connected to the I / O hub 107. The communication paths interconnecting the various components within Figure 1 can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI Express bus) or any other bus or point-to-point communication interface and / or protocol (such as, NV-Link high-speed interconnect, or interconnect protocols known in the art).

[0035] In one embodiment, one or more parallel processors 112 include circuitry optimized for graphics and video processing (including, e.g., video output circuitry) and constitute a graphics processing unit (GPU). In another embodiment, one or more parallel processors 112 include circuitry optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, one or more parallel processors 112, the memory hub 105, the processor 102, and the I / O hub 107 may be integrated into a system-on-chip (SoC) integrated circuit. Alternatively, components of the computing system 100 may be integrated into a single package to form a system-in-package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0036] It will be appreciated that the computing system 100 shown herein is illustrative, and various variations and modifications are possible. The connection topology may be modified as needed, including the number and arrangement of bridges, the number of processors 102, and the number of parallel processors 112. For example, in some embodiments, the system memory 104 is connected directly to the processors 102 rather than through a bridge, while other devices communicate with the system memory 104 via the memory hub 105 and the processors 102. In other alternative topologies, the parallel processors 112 are connected to the I / O hub 107 or directly to one of the processors 102 rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more sets of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processors 112.

[0037] Some of the specific components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of plug-in cards or peripherals may be supported, or some components may be eliminated. Additionally, some architectures may use different terms for components similar to those shown Figure 1 herein. For example, in some architectures, the memory hub 105 may be referred to as a north bridge, while the I / O hub 107 may be referred to as a south bridge.

[0038] Figure 2AShows a parallel processor 200 according to an embodiment. Various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). According to an embodiment, the illustrated parallel processor 200 is Figure 1 a variant of one or more of the parallel processors 112 shown in

[0039] In one embodiment, the parallel processor 200 includes a parallel processing unit 202. The parallel processing unit includes an I / O unit 204 that enables communication with other devices, including other instances of the parallel processing unit 202. The I / O unit 204 may be directly connected to other devices. In one embodiment, the I / O unit 204 is connected to other devices via the use of a hub or switch interface, such as the memory hub 105. The connection between the memory hub 105 and the I / O unit 204 forms a communication link 113. Within the parallel processing unit 202, the I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, where the host interface 206 receives commands related to performing processing operations and the memory crossbar 216 receives commands related to performing memory operations.

[0040] When the host interface 206 receives command buffers via the I / O unit 204, the host interface 206 may direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled to a scheduler 210 that is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in an active state before tasks are distributed to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at both a coarse-grained and fine-grained level, enabling fast preemption and context switching of threads executing on the processing array 212. In one embodiment, the host software may demonstrate the workload via one of a plurality of image processing doorbells for scheduling on the processing array 212. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0041] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each of the clusters 214A - 214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or workload distribution algorithms to allocate work to the clusters 214A - 214N of the processing cluster array 212, and the various scheduling and / or workload distribution algorithms may vary depending on the workload generated for each type of program or computation. Scheduling may be handled dynamically by the scheduler 210, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the processing cluster array 212. In one embodiment, different clusters 214A - 214N of the processing cluster array 212 may be assigned to process different types of programs, or to perform different types of computations.

[0042] The processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, the processing cluster array 212 is configured to perform general - purpose parallel computing operations. For example, the processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physical operations), and performing data transformations.

[0043] In one embodiment, the processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where the parallel processor 200 is configured to perform graphics processing operations, the processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. Additionally, the processing cluster array 212 may be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 202 may pass data from the system memory via the I / O unit 204 for processing. During processing, the passed - through data may be stored in on - chip memory (e.g., parallel processor memory 222) during processing and then written back to the system memory.

[0044] In one embodiment, when the parallel processing unit 202 is used to perform graphics processing, the scheduler 210 may be configured to divide the processing workload into tasks of approximately equal size to better enable distribution of graphics processing operations across the plurality of clusters 214A through 214N in the processing cluster array 212. In some embodiments, multiple portions of the processing cluster array 212 may be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to produce a rendered image for display. Intermediate data produced by one or more of the clusters 214A through 214N may be stored in a buffer to allow transfer of the intermediate data between the clusters 214A through 214N for further processing.

[0045] During operation, the processing cluster array 212 may receive processing tasks to be executed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include indices of data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data) as well as status parameters and commands defining how to process the data (e.g., what program to execute). The scheduler 210 may be configured to obtain the indices corresponding to the tasks or may receive these indices from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured in an effective state before initiating the workload specified by incoming command buffers (e.g., batch buffers, push buffers, etc.).

[0046] Each of one or more instances of the parallel processing unit 202 can be coupled to the parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar 216, which can receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), each of which can be coupled to a portion (e.g., a memory cell) of the parallel processor memory 222. In one implementation, the number of partition units 220A - 220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A - 220N may not be equal to the number of memory devices.

[0047] In various embodiments, the memory cells 224A through 224N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory (such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory). In one embodiment, the memory cells 224A through 224N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory cells 224A through 224N can vary and can be selected from one of a variety of conventional designs. A render target (such as a frame buffer or a texture map) can be stored across the memory cells 224A through 224N, allowing the partition units 220A through 220N to write multiple portions of each render target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 222. In some embodiments, a local instance of the parallel processor memory 222 can be excluded to facilitate a unified memory design that leverages system memory in combination with local cache memory.

[0048] In one embodiment, any one of clusters 214A - 214N of processing cluster array 212 can process data to be written to any one of memory cells 224A - 224N within parallel processor memory 222. Memory crossbar 216 can be configured to pass the output of each of clusters 214A - 214N to any of partition units 220A - 220N or another one of clusters 214A - 214N that can perform additional processing operations on the output. Each of clusters 214A - 214N can communicate with memory interface 218 through memory crossbar 216 to read from or write to various external memory devices. In one embodiment, memory crossbar 216 has a connection to memory interface 218 to communicate with I / O unit 204 and has a connection to a local instance of parallel processor memory 222, enabling processing units within different processing clusters 214A - 214N to communicate with system memory or other memory not local to the parallel processing unit 202. In one embodiment, memory crossbar 216 can use virtual channels to separate the traffic flow between clusters 214A - 214N and partition units 220A - 220N.

[0049] Although a single instance of parallel processing unit 202 is shown within parallel processor 200, any number of instances of parallel processing unit 202 can be included. For example, multiple instances of parallel processing unit 202 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. Different instances of parallel processing unit 202 can be configured to interoperate even if these different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of parallel processing unit 202 can include higher precision floating point units relative to other instances. Systems including one or more instances of parallel processing unit 202 or parallel processor 200 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0050] Figure 2B is a block diagram of partition unit 220 according to an embodiment. In one embodiment, partition unit 220 is Figure 2AAn example of one of the partition units 220A through 220N. As shown, partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent write-back requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent to the frame buffer via the frame buffer interface 225 for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory, such as memory units 224A through 224N of FIG. 2 (e.g., within the parallel processor memory 222).

[0051] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. The ROP 226 then outputs the processed graphics data stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta-color compression is performed on depth and color data on a per-tile basis.

[0052] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A through 214N of FIG. 2) rather than within the partition unit 220. In such embodiments, read and write requests for pixel data, rather than pixel fragment data, are transmitted via the memory crossbar 216. The processed graphics data can be displayed on a display device (such as Figure 1 one of the one or more display devices 110), routed for further processing by the (multiple) processors 102, or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0053] Figure 2Cis a block diagram of a processing cluster 214 within a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A through 214N of FIG. 2. The processing cluster 214 may be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executing on a particular set of input data. In some embodiments, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In other embodiments, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronous threads using a common instruction unit configured to issue instructions to a set of processing engines within each of the processing clusters. Unlike SIMD execution regimes where all processing engines typically execute the same instruction, SIMT execution allows different threads to more easily follow divergent execution paths through a given thread program. Those skilled in the art will understand that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0054] The operation of the processing cluster 214 may be controlled via a pipeline manager 232 that distributes processing tasks to the SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of FIG. 2 and manages the execution of those instructions via the graphics multiprocessor 234 and / or the texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors with different architectures may be included within the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included within the processing cluster 214. The graphics multiprocessor 234 may process data, and a data crossbar 240 may be used to distribute the processed data to one of a number of possible destinations, including other shader units. The pipeline manager 232 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0055] Each graphics multiprocessor 234 within the processing cluster 214 may include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipeline manner in which new instructions can be issued before previous instructions are completed. The functional execution logic supports a wide variety of operations, including integer and floating-point arithmetic, comparison operations, boolean operations, bit shifts, and the calculation of various algebraic functions. In one embodiment, different operations may be performed using the same functional unit hardware, and any combination of functional units may exist.

[0056] Instructions transmitted to processing cluster 214 form threads. A set of threads executed across a group of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 234. A thread group can include fewer threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines can be idle during a cycle in which the thread group is being processed. A thread group can also include more threads than the number of processing engines within graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines within graphics multiprocessor 234, processing can be executed on consecutive clock cycles. In one embodiment, multiple thread groups can be executed concurrently on graphics multiprocessor 234.

[0057] In one embodiment, graphics multiprocessor 234 includes an internal cache memory to perform load and store operations. In one embodiment, graphics multiprocessor 234 can forgo the internal cache and use the cache memory (e.g., L1 cache 308) within processing cluster 214. Each graphics multiprocessor 234 also has access to an L2 cache within a partition unit (e.g., partition units 220A - 220N of FIG. 2) that is shared among all processing clusters 214 and can be used to transfer data between threads. Graphics multiprocessor 234 also has access to off - chip global memory, which can include one or more of local parallel processor memory and / or system memory. Any memory external to parallel processing unit 202 can be used as global memory. Multiple embodiments in which processing cluster 214 includes multiple instances of graphics multiprocessor 234 can share common instructions and data, which can be stored in L1 cache 308.

[0058] Each processing cluster 214 can include an MMU 245 (memory management unit) configured to map virtual addresses to physical addresses. In other embodiments, one or more instances of MMU 245 can reside within memory interface 218 of FIG. 2. MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more discussion on tiling) to physical addresses; and optionally a cache line index. MMU 245 can include an address translation lookaside buffer (TLB) or cache that can reside within graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality, allowing for efficient request interleaving among partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0059] In graphics and computing applications, the processing cluster 214 can be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. As needed, texture data is read from an internal texture L1 cache (not shown) or, in some embodiments, from an L1 cache within the graphics multiprocessor 234, and the texture data is obtained from an L2 cache, local parallel processor memory, or system memory. Each graphics multiprocessor 234 outputs the processed tasks to a data crossbar 240 to provide the processed tasks to another processing cluster 214 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. The preROP 242 (e.g., pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234 and direct the data to ROP units that may be co-located with partition units (e.g., partition units 220A - 220N of FIG. 2) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translation.

[0060] It will be recognized that the core architectures described herein are illustrative and that various variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessors 234, texture units 236, preROP 242, etc.) may be included within the processing cluster 214. Additionally, while only one processing cluster 214 is shown, the parallel processing units as described herein may include any number of instances of the processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0061] Figure 2D A graphics multiprocessor 234 according to one embodiment is shown. In such an embodiment, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of the processing cluster 214. The graphics multiprocessor 234 has an execution pipeline including, but not limited to: an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general-purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0062] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. These instructions are cached in the instruction cache 252 and dispatched by the instruction unit 254 for execution. The instruction unit 254 may dispatch instructions as thread groups (e.g., warps), where each thread of a thread group is assigned to a different execution unit within the GPGPU core 262. Instructions may access any of the local, shared, or global address spaces by specifying an address within a unified address space. The address mapping unit 256 may be used to translate an address in the unified address space into a distinct memory address that can be accessed by the load / store unit 266.

[0063] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for the operands of the data paths connected to the functional units (e.g., GPGPU core 262, load / store unit 266) of the graphics multiprocessor 324. In one embodiment, the register file 258 is partitioned among each of these functional units such that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is partitioned among different warps executed by the graphics multiprocessor 324.

[0064] The GPGPU cores 262 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing the instructions of the graphics multiprocessor 324. According to an embodiment, the GPGPU cores 262 may be architecturally similar or may be architecturally different. For example and in one embodiment, a first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or may implement variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (such as, copy rectangle or pixel blend operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0065] In one embodiment, the GPGPU core 262 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 262 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU core can be generated at compile time by a shader compiler or can be automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example, in one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel via a single SIMD8 logical unit.

[0066] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to perform load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, whereby data transfer between the GPGPU core 262 and the register file 258 is very low latency. The shared memory 270 can be used to implement communication between threads executing on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used as, for example, a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can also programmatically store data in the shared memory in addition to the automatically cached data stored in the cache memory 272.

[0067] Figures 3A to 3B Additional graphics multiprocessors according to embodiments are shown. The graphics multiprocessors 325, 350 shown are Figure 2C variants of the graphics multiprocessor 234. The graphics multiprocessors 325, 350 shown can be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0068] Figure 3A A graphics multiprocessor 325 according to an additional embodiment is shown. The graphics multiprocessor 325 relative to Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A to 332B, register banks 334A - 334B, and texture units 344A - 344B. The graphics multiprocessor 325 also includes multiple sets of graphics or compute execution units (e.g., GPGPU cores 336A to 336B, GPGPU cores 337A to 337B, GPGPU cores 338A to 338B) and multiple sets of load / store units 340A to 340B. In one embodiment, the execution resource units have a common instruction cache 330, a texture and / or data cache memory 342, and a shared memory 346.

[0069] The various components can communicate via an interconnect structure 327. In one embodiment, the interconnect structure 327 includes one or more crossbars to enable communication between the various components of the graphics multiprocessor 325. In one embodiment, the interconnect structure 327 is a separate high-speed network structure layer on which each component of the graphics multiprocessor 325 is stacked. The components of the graphics multiprocessor 325 communicate with remote components via the interconnect structure 327. For example, the GPGPU cores 336A - 336B, 337A - 337B, and 338A - 338B can each communicate with the shared memory 346 via the interconnect structure 327. The interconnect structure 327 can arbitrate communication within the graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0070] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is shown. The graphics processor includes multiple sets of execution resources 356A to 356D, where each set of execution resources includes multiple instruction units, register banks, GPGPU cores, and load / store units, as Figure 2D and Figure 3A shown. The execution resources 356A to 356D can work in concert with the texture units 360A to 360D for texture operations while sharing the instruction cache 354 and the shared memory 362. In one embodiment, the execution resources 356A to 356D can share the instruction cache 354 and the shared memory 362 as well as multiple instances of the texture and / or data cache memories 358A to 358B. The various components can communicate via an interconnect structure 352 similar to Figure 3A the interconnect structure 327.

[0071] Those skilled in the art will understand that Figure 1 、 Figures 2A to 2D and Figures 3A to 3BThe architectures described herein are descriptive and non - limiting with respect to the scope of this embodiment. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop computer or server central processing units (CPUs) (including multi - core CPUs), one or more parallel processing units (e.g., the parallel processing unit 202 of FIG. 2), and one or more graphics processors or specialized processing units.

[0072] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general - purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high - speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as these cores and communicatively coupled to these cores via an internal processor bus / interconnect (i.e., within the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0073] Techniques for GPU-to-Host Processor Interconnect

[0074] Figure 4A An exemplary architecture is shown where multiple GPUs 410 to 413 are communicatively coupled to multiple multi - core processors 405 to 406 via high - speed links 440 to 443 (e.g., buses, point - to - point interconnects, etc.). In one embodiment, depending on the implementation, the high - speed links 440 to 443 support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the basic principles of the present invention are not limited to any particular communication protocol or throughput.

[0075] Additionally, in one embodiment, two or more of the GPUs 410 to 413 are interconnected via high - speed links 444 to 445, which may be implemented using the same or different protocols / links as those used for the high - speed links 440 to 443. Similarly, two or more of the multi - core processors 405 to 406 may be connected via a high - speed link 433, which may be a symmetric multi - processor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communication between the various system components shown may be implemented using the same protocol / link (e.g., via a common interconnect structure). However, as mentioned, the basic principles of the present invention are not limited to any particular type of interconnect technology.

[0076] In one embodiment, each of the multi-core processors 405 to 406 is communicatively coupled to the processor memories 401 to 402 via the memory interconnects 430 to 431 respectively, and each of the GPUs 410 to 413 is communicatively coupled to the GPU memories 420 to 423 via the GPU memory interconnects 450 to 453 respectively. The memory interconnects 430 to 431 and 450 to 453 may utilize the same or different memory access technologies. By way of example and without limitation, the processor memories 401 to 402 and the GPU memories 420 to 423 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or nano random access memory. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0077] As described below, although the various processors 405 to 406 and GPUs 410 to 413 may be physically coupled to specific memories 401 to 402, 420 to 423 respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as the "effective address" space) is distributed among all the individual physical memories. For example, each of the processor memories 401 to 402 may include 64 GB of the system memory address space, and each of the GPU memories 420 to 423 may include 32 GB of the system memory address space (resulting in a total of 256 GB of addressable memory in this example).

[0078] Figure 4B Additional details of the interconnect between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment are shown. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card, and the line card is coupled to the processor 407 via a high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0079] The illustrated processor 407 includes multiple cores 460A through 460D, each core having a translation lookaside buffer 461A through 461D and one or more caches 462A through 462D. These cores may include various other components for executing instructions and processing data, which are not shown to avoid obscuring the basic principles of the present invention (e.g., instruction fetch units, branch prediction units, decoders, execution units, reorder buffers, etc.). The caches 462A through 462D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple sets of cores 460A through 460D. For example, one embodiment of processor 407 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. Processor 407 and graphics accelerator integration module 446 are connected to system memory 441, which may include processor memories 401 through 402.

[0080] Data and instructions stored in the various caches 462A through 462D, 456, and system memory 441 are kept consistent via inter-core communication over coherence bus 464. For example, each cache may have cache coherence logic / circuit associated therewith to communicate via coherence bus 464 in response to detected reads or writes to a particular cache line. In one implementation, a cache snooping protocol is implemented via coherence bus 464 to snoop on cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the basic principles of the present invention.

[0081] In one embodiment, proxy circuit 425 communicatively couples graphics acceleration module 446 to coherence bus 464, allowing graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the cores. Specifically, interface 435 provides connectivity to proxy circuit 425 via high-speed link 440 (e.g., PCIe bus, NVLink, etc.), and interface 437 connects graphics acceleration module 446 to link 440.

[0082] In one implementation, the accelerator integrated circuit 436 represents multiple graphics processing engines 431, 432, N of the graphics acceleration module 446 to provide cache management, memory access, context management, and interrupt management services. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In other words, the graphics acceleration module may be a GPU having multiple graphics processing engines 431 to 432, N, or the graphics processing engines 431 to 432, N may be individual GPUs integrated on a common package, line card, or chip.

[0083] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 to perform various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation) and a memory access protocol for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431 to 432, N. In one embodiment, the data stored in the cache 438 and the graphics memories 433 to 434, N is kept consistent with the core caches 462A to 462D, 456, and the system memory 411. As mentioned, this may be achieved via the proxy circuit 425, which participates in the cache coherence mechanism on behalf of the cache 438 and the memories 433 to 434, N (e.g., sending updates related to modifications / accesses to cache lines on the processor caches 462A to 462D, 456 to the cache 438, and receiving updates from the cache 438).

[0084] A set of registers 445 stores context data for threads executed by the graphics processing engines 431 to 432, N, and the context management circuit 448 manages the thread contexts. For example, the context management circuit 448 may perform save and restore operations during a context switch to save and restore the contexts of various threads (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, during a context switch, the context management circuit 448 may store the current register values in a specified area in memory (e.g., identified by a context pointer). Then, it may restore these register values when returning to the context. In one embodiment, the interrupt management circuit 447 receives and processes interrupts received from system devices.

[0085] In one implementation, the MMU 439 converts virtual / valid addresses from the graphics processing engine 431 into real / physical addresses in the system memory 411. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 can be dedicated to a single application executing on the processor 407 or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented, in which multiple applications or virtual machines (VMs) share the resources of the graphics processing engines 431 to 432, N. These resources can be further divided into "slices" that are allocated to these VMs and / or applications based on the processing requirements and priorities associated with different VMs and / or applications.

[0086] Thus, the accelerator integrated circuit acts as a bridge to the system of the graphics accelerator module 446 and provides address translation and system memory cache services. Additionally, the accelerator integrated circuit 436 can provide virtualization facilities to the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engine.

[0087] Since the hardware resources of the graphics processing engines 431 to 432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using valid address values. In one embodiment, one function of the accelerator integrated circuit 436 is to physically isolate the graphics processing engines 431 to 432, N such that they appear to the system as independent units.

[0088] As mentioned, in the illustrated embodiment, one or more graphics memories 433 to 434, M are respectively coupled to each of the graphics processing engines 431 to 432, N. The graphics memories 433 to 434, M store the instructions and data processed by each of the graphics processing engines 431 to 432, N. The graphics memories 433 to 434, M can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or nano random access memory (Nano-Ram).

[0089] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memories 433 to 434, M is the data that will be most frequently used by graphics processing engines 431 to 432, N and preferably not used (at least not frequently) by cores 460A to 460D. Similarly, the biasing mechanism attempts to keep the data required by the cores (and preferably not by graphics processing engines 431 to 432, N) in the caches 462A to 462D, 456 of these cores and in system memory 411.

[0090] Figure 4C Another embodiment is shown where accelerator integrated circuit 436 is integrated within processor 407. In this embodiment, graphics processing engines 431 to 432, N communicate directly to accelerator integrated circuit 436 via interface 437 and interface 435 (again, these interfaces can utilize any form of bus or interface protocol) over high-speed link 440. Accelerator integrated circuit 436 can perform the same operations as described with respect to Figure 4B but potentially at a higher throughput given its very close proximity to coherence bus 462 and caches 462A to 462D, 426.

[0091] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter can include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0092] In one embodiment of the dedicated process model, graphics processing engines 431 to 432, N are dedicated to a single application or process under a single operating system. A single application can funnel other application requests to graphics engines 431 to 432, N, thereby providing virtualization within a VM / partition.

[0093] In the dedicated process programming model, graphics processing engines 431 to 432, N can be shared by multiple VM / application partitions. The shared model requires the hypervisor to virtualize graphics processing engines 431 to 432, N to allow access by each operating system. For a non-hypervisor single partition system, graphics processing engines 431 to 432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431 to 432, N to provide access to each process or application.

[0094] For a shared programming model, the graphics acceleration module 446 or individual graphics processing engines 431 - 432, N use a process handle to select process elements. In one embodiment, the process elements are stored in the system memory 411 and can be addressed using the effective - to - real address translation techniques described herein. The process handle can be an implementation - specific value provided to the host process when it registers its context with the graphics processing engines 431 - 432, N (i.e., calls the system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0095] Figure 4D An exemplary accelerator integration slice 490 is shown. As used herein, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process elements 483 are stored in response to a GPU call 481 from an application 480 executing on the processor 407. The process elements 483 contain the process state of the corresponding application 480. The work descriptor (WD) 484 contained within the process element 483 can be a single job requested by the application or can contain a pointer to a job queue. In the latter case, the WD 484 is a pointer to the job request queue within the application's address space 482.

[0096] The graphics acceleration module 446 and / or individual graphics processing engines 431 - 432, N can be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting the process state and sending the WD 484 to the graphics acceleration module 446 to start a job in a virtualized environment.

[0097] In one implementation, the dedicated - process programming model is implementation - specific. In this model, a single process owns the graphics acceleration module 446 or an individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0098] In operation, the WD fetch unit 491 in the accelerator integrated slice 490 fetches the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines in the graphics acceleration module 446. Data from the WD 484 can be stored in the register 445 and used by the MMU 439, the interrupt management circuit 447, and / or the context management circuit 446 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuit for accessing the segment / page table 486 within the OS virtual address space 485. The interrupt management circuit 447 can process the interrupt events 492 received from the graphics acceleration module 446. When performing a graphics operation, the MMU 439 converts the effective address 493 generated by the graphics processing engines 431 to 432, N into a real address.

[0099] In one embodiment, a set of identical registers 445 is replicated for each of the graphics processing engines 431 to 432, N and / or the graphics acceleration module 446, and these registers can be initialized by a hypervisor or an operating system. Each of these replicated registers can be included in the accelerator integrated slice 490. Exemplary registers that can be initialized by the hypervisor are shown in Table 1. Table 1 - Registers Initialized by the Hypervisor

[0100] Exemplary registers that can be initialized by the operating system are shown in Table 2. Table 2 - Registers Initialized by the Operating System 1 Process and Thread Identification 2 Effective Address (EA) Context Save / Resume Pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Storage Segment Table Pointer 5 Permission Mask 6 Work Descriptor

[0101] In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engines 431 to 432, N. It contains all the information required for the graphics processing engines 431 to 432, N to complete their work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be completed.

[0102] Figure 4E Additional details of one embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 can be accessed via the hypervisor 496, which virtualizes the graphics acceleration module engine for the operating system 495.

[0103] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models in which the graphics acceleration module 446 is shared by multiple processes and partitions: time slice sharing and graphics directed shared.

[0104] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. To enable the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may follow these requirements: 1) The job requests of the application must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The graphics acceleration module 446 is guaranteed to complete the job requests of the application (including any translation faults) within a specified amount of time, or the graphics acceleration module 446 provides the ability to handle preempted jobs. 3) When operating in the directed shared programming model, fairness of the graphics acceleration module 446 between processes must be guaranteed.

[0105] In one embodiment, for the shared model, the application 480 needs to use the graphics acceleration module 446 type, work descriptor (WD), access mask register (AMR) value, and context save / restore region pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the target acceleration function for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is specifically formatted for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure for describing the work to be done by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application that sets the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user access mask override register (UAMOR), then the operating system may apply the current UAMOR value to the AMR value and then pass the AMR in the hypervisor call. Optionally, the hypervisor 496 may apply the current access mask override register (AMOR) value and then place the AMR in the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the valid address of a region in the application's address space 482 for the graphics acceleration module 446 to save and restore the context state. This pointer is optional if no state needs to be saved between jobs or when the job is preempted. The context save / restore region can be pinned system memory.

[0106] Upon receiving a system call, the operating system 495 may verify that the application 480 is registered and has been granted permission to use the graphics acceleration module 446. The operating system 495 then uses the information shown in Table 3 to call the hypervisor 496. Table 3 – OS to Hypervisor Call Parameters

[0107] Upon receiving a hypervisor call, the hypervisor 496 verifies that the operating system 495 is registered and has been granted permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into the process element linked list corresponding to the type of graphics acceleration module 446. The process element may include the information shown in Table 4. Table 4 - Process Element Information 1 Work Descriptor (WD) 2 Permission Mask Register (AMR) Value (Potentially Masked) 3 Effective Address (EA) Context Save / Resume Area Pointer (CSRP) 4 Process ID (PID) and Optional Thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual Address of Storage Segment Table Pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt Vector Table Derived from Hypervisor Call Parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilization Record Pointer 12 Storage Descriptor Register (SDR)

[0108] In one embodiment, the hypervisor initializes the registers 445 of multiple accelerator integrated slices 490.

[0109] As Figure 4F shown, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space for accessing the physical processor memories 401 to 402 and the GPU memories 420 to 423. In such an implementation, operations executed on the GPUs 410 to 413 utilize the same virtual / effective memory address space to access the processor memories 401 to 402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 401, a second portion is allocated to the second processor memory 402, a third portion is allocated to the GPU memory 420, and so on. Thus, the entire virtual / effective memory space (sometimes referred to as the effective address space) is distributed across each of the processor memories 401 to 402 and the GPU memories 420 to 423, allowing any processor or GPU to access any physical memory using the virtual address mapped to that memory.

[0110] In one embodiment, the bias / coherency management circuits 494A to 494E within one or more of the MMUs 439A to 439E ensure cache coherency between the host processor (e.g., 405) and the caches of the GPUs 410 to 413, and implement a bias technique for physical memory indicating where certain types of data should be stored. While Figure 4FMultiple instances of bias / coherence management circuits 494A - 494E are shown, but the bias / coherence circuits may be implemented within the MMU of one or more host processors 405 and / or within the accelerator integrated circuit 436.

[0111] One embodiment allows GPU attached memories 420 - 423 to be mapped as part of system memory and accessed using shared virtual memory (SVM) techniques, but without suffering the typical performance penalties associated with full system cache coherence. This ability to access GPU attached memories 420 - 423 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access computed results without the overhead of traditional I / O DMA data copying. Such traditional copying involves driver calls, interrupts, and memory mapped I / O (MMIO) accesses, all of which are inefficient relative to simple memory accesses. At the same time, the ability to access GPU attached memories 420 - 423 without cache coherence overhead can be critical to the execution time of offloaded computations. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 410 - 413. The efficiency of operand setting, result access, and GPU computation all play a role in determining the effectiveness of GPU offloading.

[0112] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which can be a page - granularity structure (i.e., controlled at the granularity of a memory page) including 1 or 2 bits per GPU attached memory page. One or more stolen memory ranges of GPU attached memories 420 - 423 may be employed to implement the bias table, with or without a bias cache in GPUs 410 - 413 (e.g., for caching frequently used / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0113] In one implementation, the bias table entries associated with each access to the GPU attached memories 420-423 are accessed before actually accessing the GPU memory, thereby causing the following operations. First, local requests from the GPUs 410-413 that look for their pages in the GPU bias (these local requests find their pages in the GPU bias) are directly forwarded to the corresponding GPU memories 420-423. Local requests from the GPUs (these local requests find their pages in the host bias) are forwarded to the processor 405 (e.g., via the high-speed link as discussed above). In one embodiment, requests from the processor 405 that look for the requested page in the host processor bias complete requests similar to normal memory reads. Alternatively, requests for GPU bias pages can be forwarded to the GPUs 410-413. Then, if the GPU is not currently using the page, it can transition the page to the host processor bias.

[0114] The bias state of a page can be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or a purely hardware-based mechanism for a limited set of cases.

[0115] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or queues a command descriptor) to the GPU to direct it to change the bias state and perform a cache flushing operation in the host for some transitions. The cache flushing operation is required for the transition from the host processor 405 bias to the GPU bias, but not for the reverse transition.

[0116] In one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 405. To access these pages, the processor 405 can request access from the GPU 410, which may or may not immediately grant access depending on the implementation. Thus, to reduce communication between the processor 405 and the GPU 410, it is advantageous to ensure that the GPU bias pages are those that are needed by the GPU but not by the host processor 405 (and vice versa).

[0117] Graphics Processing Pipeline

[0118] Figure 5 Displays a graphics processing pipeline 500 according to an embodiment. In one embodiment, a graphics processor can implement the displayed graphics processing pipeline 500. The graphics processor can be included within a parallel processing subsystem as described herein, the parallel processing subsystem being, for example, the parallel processor 200 of FIG. 2, which in one embodiment isFigure 1 Variants of the (multiple) parallel processors 112. Various parallel processing systems can implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., the parallel processing unit 202 of FIG. 2) as described herein. For example, a shader unit (e.g., the graphics multiprocessor 234 of FIG. 3) can be configured to perform the functions of one or more of the vertex processing unit 504, the tessellation control processing unit 508, the tessellation evaluation processing unit 512, the geometry processing unit 516, and the fragment / pixel processing unit 524. The functions of the data assembler 502, the primitive assembler 506, 514, 518, the tessellation unit 510, the rasterizer 522, and the raster operation unit 526 can also be performed by other processing engines and corresponding partitioning units (e.g., the partitioning units 220A to 220N of FIG. 2) within a processing cluster (e.g., the processing cluster 214 of FIG. 3). The graphics processing pipeline 500 can also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 can be executed by parallel processing logic within a general-purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 can access on-chip memory (e.g., the parallel processor memory 222 in FIG. 2) via a memory interface 528, which can be an instance of the memory interface 218 of FIG. 2.

[0119] In one embodiment, the data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. The data assembler 502 then outputs the vertex data including vertex attributes to the vertex processing unit 504. The vertex processing unit 504 is a programmable execution unit that executes a vertex shader program to illuminate and transform the vertex data as specified by the vertex shader program. The vertex processing unit 504 reads data stored in a cache, local, or system memory for use in processing the vertex data, and the vertex processing unit 504 can be programmed to transform the vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0120] A first instance of the primitive assembler 506 receives vertex attributes from the vertex processing unit 504. The primitive assembler 506 reads the stored vertex attributes as needed and constructs graphics primitives for processing by the tessellation control processing unit 508. The graphics primitives include triangles, line segments, points, patches, etc. supported by various graphics processing application programming interfaces (APIs).

[0121] The tessellation control processing unit 508 treats the input vertices as control points for geometric patches. The control points are transformed from an input representation of the patch (e.g., the basis of the patch) to a representation suitable for use by the tessellation evaluation processing unit 512 in surface evaluation. The tessellation control processing unit 508 may also compute tessellation factors for the edges of the geometric patch. The tessellation factors are applied to individual edges and quantify the view-dependent level of detail associated with that edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch surface into a plurality of geometric primitives such as line, triangle, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitives.

[0122] A second instance of the primitive assembler 514 receives vertex attributes from the tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and constructs graphics primitives for processing by the geometry processing unit 516. The geometry processing unit 516 is a programmable execution unit that executes a geometry shader program to transform the graphics primitives received from the primitive assembler 514 as specified by the geometry shader program. In one embodiment, the geometry processing unit 516 is programmed to subdivide the graphics primitives into one or more new graphics primitives and compute parameters for rasterizing the new graphics primitives.

[0123] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying the new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs graphics primitives for processing by the viewport scaling, culling, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or system memory for use in processing geometric data. The viewport scaling, culling, and clipping unit 520 performs clipping, culling, and viewport scaling and outputs the processed graphics primitives to the rasterizer 522.

[0124] The rasterizer 522 can perform depth culling and other depth-based optimizations. The rasterizer 522 also performs scan conversion of new graphics primitives to generate fragments and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 can be programmed to perform operations that produce shaded fragments or pixels output to the raster operations unit 526, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction. The fragment / pixel processing unit 524 can read data stored in the parallel processor memory or the system memory for use in processing fragment data. The fragment or pixel shader program can be configured to shade at a sample, pixel, tile, or other granularity depending on the sampling rate configured for the processing unit.

[0125] The raster operations unit 526 is a processing unit that performs raster operations including but not limited to stencil printing, z-testing, blending, etc., and outputs pixel data as processed graphics data to be stored in the graphics memory (e.g., the parallel processor memory 222 and / or Figure 1 the system memory 104 in FIG. 2), displayed on one or more display devices 110, or further processed by one of the one or more processors 102 or (multiple) parallel processors 112. In some embodiments, the raster operations unit 526 is configured to compress z or color data written to the memory and decompress z or color data read from the memory.

[0126] Automotive Display Glare Compensation

[0127] Typically when there is glare on a display screen, a user may be able to reduce the glare by tilting or otherwise moving the screen or changing their viewing position. Also, they may be able to move the room or close the curtains on a window, etc. However, when driving a car, the options for overcoming glare on the dashboard are limited, especially when driving a long distance in the same direction.

[0128] Now turning to Figure 6A, shows a simplified diagram of the interior of a car as seen from the driver's perspective. Typical things are shown, such as the driver's seat 602, the passenger seat 604, the steering wheel 606, the roof contour line 608, the console 610, the windshield 612, and the rearview mirror 614. In this car, the entire dashboard or at least a good portion of the occupied area in front of the driver and passenger is an electronic display 616. In some embodiments, it can be a single display, and in other embodiments, it can include one or more displays that are adjacent to each other so as to preferably appear seamless or nearly seamless.

[0129] Depending on the driver's preferences, this dashboard can be very colorful and busy, or well-organized and clean, and it is also equipped with many virtual gauges and dials, such as a speedometer, an odometer, an RPM (revolutions per minute) gauge, an audio system user interface (UI), a navigation / map UI, etc. To avoid clutter, these are not all shown, but are likely to appear when the car is started.

[0130] One or more cameras or glare sensors 618 can be positioned throughout the car. For convenience, only one sensor 618 is shown, but in reality, there may be more. When the sun or the headlights of a following vehicle produce glare on the dashboard 616, the glare can dangerously obscure the driver's view of critical instruments. For example, the speedometer 620 may have annoying glare 622 on it, making it difficult or impossible to read the speedometer. In such a case, the driver may simply touch the speedometer 620 with a finger and drag it to a new position 620'. Other dials or UIs there may simply move out of the way. Alternatively, the sensor 618 can be a microphone, and the driver can give a voice command to move the speedometer to another part of the dashboard. In the case where the sensor 618 is a camera or a glare sensor, if the sensor senses glare on the speedometer or the driver squinting at the current position of the speedometer, the sensor can instruct the circuitry in the car to automatically move the speedometer to another place on the dashboard 616.

[0131] Of course, the speedometer 620 is merely used as an example, and the representation of any or all instruments can be moved in a similar manner and for reasons other than glare. In an alternative embodiment, instead of moving the speedometer 620 (or any other instrument), the software driving the display can change the contrast or brightness, or make another adjustment only in the area where the speedometer is currently located to make it easier to view the speedometer. This method can also be helpful in the case of other fixed screens, such as arrival / departure displays at airports, which are sometimes difficult to view due to glare. In such cases, when glare is detected, the area of the display can be enhanced, while the non-glare areas are not adjusted. Alternatively, if there are other display monitors nearby, the information can simply be temporarily moved to another display.

[0132] Turning now to Figure 6B , a flowchart is shown that demonstrates moving an instrument, dial, UI, or anything else being displayed to a new glare-free location. Starting after 650, at decision block 652, it is determined whether glare that affects the driver's view of the instrument is detected on the area of the display. If so, at block 654, the instrument is moved to a new unobstructed location on the dashboard. Blocks 656, 658, and 660 respectively show that the instrument can be dragged, moved by voice command, or automatically moved to the new location. In another embodiment, especially when the instrument is moved automatically, it may not move but instead be copied elsewhere. In other words, the speedometer 620 ( Figure 6A ) can remain where it is, while a second speedometer 620' ( Figure 6A ) can appear in a different location, thus having two speedometers for a period of time. This solution would be helpful because the original speedometer would still be in the place where the driver expects it to be.

[0133] The process shown can be implemented as one or more modules in a logic instruction set stored in a non-transitory machine or computer-readable storage medium such as random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLA), field-programmable gate arrays (FPGA), complex programmable logic devices (CPLD), or in fixed-function hardware logic using circuit technologies such as, for example, application-specific integrated circuits (ASIC), complementary metal-oxide semiconductor (CMOS), or transistor-transistor logic (TTL) technology, or any combination thereof.

[0134] Reduce Dynamic Range

[0135] Typically, when there is glare on a display screen, a user can be able to reduce the glare by tilting or otherwise moving the screen or changing their viewing position. Also, they can be able to move the room or close the curtains on the window, etc. However, when driving a car, the options for overcoming glare on the windshield are limited, especially when you are driving a long distance in the same direction.

[0136] Turning now to Figure 7A , a simplified diagram of the interior of a car as seen looking forward from the driver's perspective is shown. Typical things are shown, such as the driver's seat 702, the passenger seat 704, the steering wheel 706, the roof contour line 708, the console 710, the windshield 712, and the rearview mirror 714. In this car, the entire dashboard 716 can be an electronic display, or it can be a traditional dashboard, or, as is more common currently, a hybrid of the two.

[0137] In this embodiment, the windshield 712 is an electronic display that can be semi-transparent. A camera 718, shown for illustrative purposes on the roof (it can be elsewhere), captures the scene in front of the car and displays it on the windshield so that the windshield appears like a windshield of ordinary glass. In this case, the sun 730 (or other bright glare, such as a reflection or headlights) shines directly into the driver's eyes. In a traditional car, pulling down the sun visor may or may not help in this situation.

[0138] Referring to Figure 7B , a high-dynamic range analysis can be performed on the output of the camera 718 by a circuit system. Any one of the CPUs / GPUs discussed and shown elsewhere in this document can be on-board and capable of performing the necessary analysis. Once a high dynamic threshold is detected, it indicates that glare is present. The area of the windshield with glare can be dimmed, such that a dim patch 732 appears and dims the sun 730 while still allowing everything else to be clearly seen.

[0139] Turning now to Figure 7C , a flowchart is shown that demonstrates the above method for reducing the dynamic range in a specific area of a display. Starting after block 750, in block 752, one can perform a high-dynamic analysis on data from the forward-facing camera(s). Block 754 can determine whether glare is detected. If so, then in the block 756 shown, this area of the windshield is dimmed.

[0140] The processes shown can be implemented as one or more modules in a logic instruction set stored in a non-transitory machine or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, PLA, FPGA, CPLD, in fixed-function hardware logic using circuit technologies such as, for example, ASIC, CMOS or TTL technology, or any combination thereof.

[0141] Transparent Dashboard

[0142] Now referring Figure 8A , an automobile 830 is shown. The automobile 830 may have a sensor 832, such as a camera. The front portion 834 of the automobile 830 obscures most of the front view and creates a large blind spot for almost everything beyond a few feet in front of the hood. This blind spot 836 is shown in parentheses and, in this case, includes a tree 838 of which the driver has only a partial view and a cat 840 that the driver cannot see at all. The tree may have branches 842 that have fallen due to a recent storm and are in the driver's blind spot 835.

[0143] Now turning Figure 8B , a simplified diagram of the interior of an automobile as seen looking forward from the driver's perspective is shown. Typical things are shown, such as a driver's seat 802, a passenger seat 804, a steering wheel 806, a roof contour line 808, a console 810, a windshield 812, and a rearview mirror 814. In this automobile, the entire dashboard 816 or at least a good portion of the occupied area in front of the driver and passenger is an electronic display. In some embodiments, the dashboard 816 can be a single display, and in other embodiments, the dashboard 816 can include one or more displays adjacent to each other so as to preferably appear seamlessly or nearly seamlessly. In some embodiments, the dashboard 816 can be several displays on discrete devices that exist in many current automobiles, such as a dashboard display, a radio or entertainment display, and a navigation (NAV) / map (MAP) display. In a later embodiment herein, the front of the automobile will not appear transparent, but rather the display can give the appearance of a window through the dashboard and the engine compartment.

[0144] Depending on the driver's preferences, this dashboard 816 can be very colorful and busy, or well-organized and clean, and it is also equipped with many virtual gauges and dials, such as a speedometer, an odometer, an RPM (revolutions per minute) gauge, an audio system user interface (UI), a navigation / map UI, etc. Most of these are not shown to avoid clutter, but are likely to appear when the automobile is started.

[0145] As looking forward Figure 8BAs shown in [Fig.], as expected, the top of the tree 838 is visible from the windshield. Since the dashboard 816 is a display of the scene that continues from the bottom of the windshield down to the ground, the driver can now also see the broken tree branch 842 and the cat 840 that may be in the path of the car 830. The various instruments normally displayed on the dashboard 816 can still be visible due to the overlap, as demonstrated by the speedometer 850.

[0146] In another embodiment in the case of adverse weather, such as heavy rain or thick fog, the cat 840 and the fallen tree branch 842 can be enhanced and appear as outlined or otherwise made more visible than in adverse weather.

[0147] Model-Based MR Navigation

[0148] The inside-out tracking system combines a depth camera that maps the environment visible to the camera, and this can be used to integrate real and virtual objects through proper interaction - for example, a virtual plant sitting on top of a real tabletop rather than falling through it. Another important use is to alert the user before he walks into a wall or over an obstacle.

[0149] One limitation of the system is that it can only map what it has already seen. So if the system sees the back of a chair or a sofa, and then the user turns his line of sight elsewhere while walking around the sofa, the system will not know the front or side surfaces of the sofa and will therefore not alert the user when he walks past the side of the sofa.

[0150] Now referring to Figure 9A , a user 900 wearing a head-mounted display (HMD) 902 is shown. The HMD is of the type worn for mixed reality or merged reality (MR) (sometimes referred to as augmented reality (AR)). The HMD 902 has a forward-facing (plural) camera that uses a dashed line to indicate the field of view 904. With this setup, the user can walk around the real world and see static or moving virtual objects superimposed on actual objects (e.g., virtual flowers and vases sitting on a real tabletop, an animated character walking through the room and running outside a real door).

[0151] However, this MR world is not without risks. Normally, only real things within the field of view 904 or things that the system already knows are in the room can be seen because the system has been there before and learned about the space and mapped the things. If it is the first time in a space or room or there are new or changed things in the room, there may be some hidden obstacles that do not enter the visual field until it is too late. This is especially likely when the field of view 904 of the depth camera is narrower compared to human vision.

[0152] The goal of the present invention is to use available scenes to identify objects and then fill in occluded or partially scanned areas based on the expected geometry of these objects. In Figure 9A , for example, when user 900 looks behind sofa 906, the system will identify the object as a sofa. The object is too long to be a chair or a loveseat. However, the seating portion of the sofa is in an occluded shape. The dashed box shows the occlusion 908.

[0153] Referring to Figure 9B , the system will fill in the remaining portions of the characteristics of the sofa, including the occluded shape 910. This "filling in" can be done by intelligent guesswork based on what the system has seen before. Also, there may be a native database of shapes. For example, the native database knows the remaining portions of such a sofa 906 or at least what a typical sofa looks like.

[0154] In other embodiments, the system can look in the cloud for objects to learn about the occluded shape 908. In yet another embodiment, the system can see other things in the room and assume that similar things are the same. For example, if the system sees a dining table and eight chairs but only has a clear view of one chair or partial views of several chairs, the system can use or combine this data to assume the occluded shapes of the remaining chairs. Although it may not be perfect, this will be sufficient to alert the user before the user moves past the occlusion area of the sofa 910 or chair and will be sufficient for practical model interaction between the object and the occlusion area 908 of the sofa. That is, for example, a virtual object will be rendered as lying on the extrapolated seating of the sofa rather than on the floor.

[0155] Now referring to Figure 10 , a flowchart is shown that depicts a model-based MR navigation system according to an embodiment of the present invention. After start box 1000, box 1002 determines whether a partial object with a partial scan is identified. If so, the unknown shape is filled in at box 1004. If not, box 1006 determines whether there are similar items in the field of view or that have already been seen in the room. If so, the unknown shape is filled in at box 1008. If not, box 1010 searches the cloud for the partial object, finds a matching or similar object, and fills in the occluded shape. Later, when the user shifts the field of view and observes more objects, the object and all extrapolated similar objects can be refined using the measured data.

[0156] The processes shown can be implemented as one or more modules in a logic instruction set stored in a non-transitory machine or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, PLA, FPGA, CPLD, etc., in fixed function hardware logic using circuit technologies such as, for example, ASIC, CMOS or TTL technologies, or any combination thereof.

[0157] Display Technology

[0158] Turning now to Figure 11 , a performance-enhanced computing system 1100 is shown. In the example shown, a processor 1110 is coupled to a display 1120. The processor 1110 generally generates images to be displayed on an LCD panel 1150 of the display 1120. In one example, the processor 1110 includes a communication interface such as, for example, a Video Graphics Array (VGA), DisplayPort (DP) interface, Embedded DisplayPort (eDP) interface, High-Definition Multimedia Interface (HDMI), Digital Visual Interface (DVI), and so on. The processor 1110 can be a graphics processor (e.g., a Graphics Processing Unit / GPU) that processes graphics data and generates images (e.g., video frames, still images) to be displayed on the LCD panel 1150. Additionally, the processor 1110 can include one or more image processing pipelines that generate pixel data. The image processing pipeline can conform to the OPENGL architecture or other suitable architectures. Further, the processor 1110 can be connected to a host processor (e.g., a Central Processing Unit / CPU), where the host processor executes one or more device drivers that control the processor 1100 and / or interact with the processor 1110.

[0159] The display 1120 shown includes a timing controller (TCON) 1130 that can individually address different pixels on the LCD panel 1150 and update each individual pixel on the LCD panel 1150 on a per-refresh cycle basis. In this regard, the LCD panel 1150 can include a plurality of liquid crystal elements, such as, for example, liquid crystals and integrated color filters. Each pixel of the LCD panel 1150 can include a triple of liquid crystal elements respectively having red, green, and blue filters. The LCD panel 1150 can arrange pixels in a two-dimensional (2D) array that is controlled via a row driver 1152 and a column driver 1154 to update the image being displayed by the LCD panel 1150. Accordingly, the TCON 1130 can drive the row driver 1152 and the column driver 1154 to address specific pixels of the LCD panel 1150. The TCON 1130 can also adjust the voltage provided to the liquid crystal elements in the pixels to change the light intensity passing through each of the three liquid crystal elements and thus change the color of the pixels displayed on the surface of the LCD panel 1150.

[0160] The backlight 1160 can include a plurality of light-emitting elements arranged at the edges of the LCD panel 1150, such as, for example, light-emitting diodes (LEDs). Accordingly, the light generated by the LEDs can be dispersed through the LCD panel 1150 by a diffuser (not shown). In another example, the LEDs are arranged in a 2D array directly behind the LCD panel 1150, and since each LED disperses light through one or more corresponding pixels of the LCD panel 1150 positioned in front of the LED, this configuration is sometimes referred to as direct backlighting. The light-emitting elements can also include compact fluorescent lamps (CFLs) arranged along one or more edges of the LCD panel 1150. To eliminate multiple edges, the combination of edges can be changed to achieve selective illumination of regions where less than the entire set of lighting elements is used with less power.

[0161] The light-emitting elements can also include one or more sheets of electroluminescent material placed behind the LCD panel 1150. In such cases, the light from the surface of the sheet can be dispersed through the pixels of the LCD panel 1150. Additionally, the sheet can be divided into a plurality of regions, such as, for example, quadrants. In one example, each region is individually controlled to illuminate only a portion of the LCD panel 1150. Other backlighting solutions can also be used.

[0162] The illustrated display 1120 also includes a backlight controller (BLC) 1140 that supplies voltage to the light-emitting elements of the backlight 1160. For example, the BLC 1140 can include a pulse-width modulation (PWM) driver (not shown) to generate a PWM signal that activates at least a portion of the light-emitting elements of the backlight 1160. The duty cycle and frequency of the PWM signal can dim the light generated by the light-emitting elements. For example, a 100% duty cycle can correspond to the light-emitting elements being fully on, while a 0% duty cycle can correspond to the light-emitting elements being fully off. Thus, intermediate duty cycles (e.g., 25%, 50%) generally cause the light-emitting elements to be on for a portion of the cycle period that is proportional to the percentage of the duty cycle. The cycle period can be fast enough such that the flicker of the light-emitting elements is imperceptible to the human eye. Additionally, the effect on the user may be that the level of light emitted by the backlight 1160 is lower than when the backlight 1160 is fully activated. The BLC 1140 can be separate from the TCON 1130 or can be incorporated into the TCON 1130.

[0163] Alternatively, an emissive display system can be used, where the LCD panel 1150 would be replaced by an emissive display panel (e.g., organic light-emitting diode / OLED), the backlight 1160 would be omitted, and the row driver 1152 and column driver 1154 can be used to directly modulate pixel color and brightness, respectively.

[0164] Distance-Based Display Resolution

[0165] Figure 12A A scenario is shown where a user 1218 interacts with a data processing device 1200 that includes a display unit 1228. The display processing device 1200 can include, for example, a notebook computer, a desktop computer, a tablet computer, a convertible tablet, a mobile internet device (MID), a personal digital assistant (PDA), a wearable device (e.g., a head-mounted display / HMD), a media player, etc., or any combination of the foregoing. The illustrated data processing device 1200 includes a processor 1224 (e.g., an embedded controller, a microcontroller, a host processor, a graphics processor) coupled to a memory 1222, which can include storage locations addressable by the processor 1224. As will be discussed in more detail, a distance sensor 1210 can enable distance-based display resolution with respect to the display unit 1228.

[0166] The illustrated memory 1222 includes display data 1226 that will be rendered on the display unit 1228. In one example, the processor 1224 performs data conversion on the display data 1226 before presenting the display data 1226 on the display unit 1228. The post - processing engine 1214 may be executed on the processor 1224 to receive the display data 1226 and the output of the distance sensor 1210. The post - processing engine 1214 may modify the display data 1226 to enhance the readability of the screen content on the display unit 1228, reduce power consumption in the data processing device 1200, and so on, or any combination of the above operations.

[0167] The illustrated memory 1222 stores display resolution settings 1216 in addition to the operating system 1212 and the applications 1220. The display resolution settings 1216 may specify the number of pixels of the display data 1226 that will be presented on the display unit 1228 along the length dimension and the width dimension. If the display data 1226 generated by the application 1220 is not compatible with the format of the display unit 1228, the processor 1224 may configure the scaling ratio of the display data 1226 to match the format of the display unit 1228. In this regard, the display resolution settings 1216 may be associated with and / or incorporated into the configuration data that defines other settings of the display unit 1228. Additionally, the display resolution settings 1216 may be defined in terms of unit distance or area (e.g., pixels per inch / PPI) or other suitable parameters.

[0168] The application 1220 may generate a user interface where the user 1218 may interact with the user interface to select the display resolution settings 1216 from one or more options provided through the user interface, type in the display resolution settings 1216 as the requested value, and so on. Thus, the size of the display data 1226 may be adjusted to fit the display resolution settings 1216 before being rendered on the display unit 1228.

[0169] The distance sensor 1210 may track the distance between the user 1218 and the display unit 1228, where the distance sensing may be triggered by physical buttons associated with the data processing device 1200 / display unit 1228, through the user interface provided by the loading of the application 1220 and / or the operating system 1220, and so on. For example, during the boot of the data processing device 1200, the operating system 1212 may execute an automatic process to trigger distance sensing in the background or foreground. The distance sensing may be performed periodically or continuously.

[0170] Figure 12BShows an example of a distance sensing scenario. In the example shown, distance sensor 1210 uses transceiver 1208 to transmit an electromagnetic beam 1202 in the direction of user 1218. Thus, transceiver 1202 can be positioned on the front surface of data processing device 1200( Figure 12A ). The electromagnetic beam 1202 can affect user 1218 and can be reflected / scattered from user 1218 as a return electromagnetic beam 1204. The return electromagnetic beam 1204 can be analyzed by, for example, processor 1224( Figure 12A ) and / or post - processing engine 1214( Figure 12A ) to determine the distance 1206 between user 1218 and display unit 1228( Figure 12A ). The distance 1206 can be used to adjust the display resolution setting 1216.

[0171] Display Layer

[0172] Now turning to Figure 13 , a display system 1300 is shown, where cascaded display layers 1361, 1362, and 1363 are used to implement spatial / temporal super - resolution in display component 1360. In the example shown, processor 1310 provides raw graphics data 1334 (e.g., video frames, still images) to system 1300 via bus 1320. The cascaded display program 1331 can be stored in memory 1330, where the cascaded display program 1331 can be part of a display driver associated with display component 1360. The shown memory 1330 also includes raw graphics data 1334 and decomposed graphics data 1335. In one example, the cascaded display program 1331 includes a temporal decomposition component 1332 and a spatial decomposition component 1333. The temporal decomposition component 1332 can perform temporal decomposition calculations, while the spatial decomposition component can perform spatial decomposition calculations. The cascaded display program 331 can derive the decomposed graphics data 1335 for presentation on each of the display layers 1361, 1362, and 1363 based on user configuration and raw graphics data 1334.

[0173] The display component 1360 can be implemented as an LCD (Liquid Crystal Display) used in, for example, a head - mounted display (HMD) application. More specifically, the display component 1360 can include a stack of an LCD panel, an interface board, a lens attachment, etc. Each panel can operate at a native resolution of, for example, 1280 * 1280 and at a refresh rate of 60Hz. Other native resolutions, refresh rates, display panel technologies, and / or layer configurations can be used.

[0174] Multiple Display Units

[0175] Figure 14FIG. 1400 shows a graphics display system 1400 that includes a set of display units 1430 (1430a - 1430n) that are generally operative to output a wide - screen (e.g., panoramic) presentation 1440 that includes coordinated content in an aggregated and structured topological form. In the example shown, data processing device 1418 includes a processor 1415 that applies a logic function 1424 to hardware configuration file data 1402 received from a set of display units 1430 via network 1420. Application of the logic function 1424 to the hardware configuration file data 1402 creates a set of automatic topology settings 1406 when no match is found between the hardware configuration file data and a set of settings in the hardware configuration file lookup table 1412. The shown set of automatic topology settings 1406 is transmitted from the display processing device 1418 to the display units 1430 via network 1420.

[0176] Processor 1415 may execute and run the logic function 1424 after receiving the logic function 1424 from the display driver 1410. In this regard, the display driver 1410 may include an automatic topology module 1408 that automatically configures and constructs the topology of the display units 1432 to create the presentation 1440. In one example, the display driver 1410 is a set of instructions that, when executed by the processor 1415, causes the data processing device 1418 to communicate with the display units 1430, video cards, etc., and perform automatic topology generation operations.

[0177] The data processing device 1418 may include, for example, a server, desktop computer, laptop computer, tablet computer, convertible tablet, MID, PDA, wearable device, media player, etc. Thus, the display processing device 1418 may include a hardware control module 1416, a storage device 1414, a random access memory (RAM, not shown), a controller card including one or more video controller cards, etc. In one example, the display units 1430 are flat panel displays (e.g., liquid crystal, active matrix, plasma, etc.), HMDs, video projection devices, etc. that cooperate with each other to produce the presentation 1440. Additionally, the presentation 1440 may be generated based on media files stored in the storage device 1414, where the media files may include, for example, movies, video clips, animations, advertisements, etc., or any combination of the foregoing.

[0178] The term "topology" can be considered as the quantity, scaling, shape, and / or other configuration parameters of the first display unit 1430a, the second display unit 1430b, the third display unit 1430n, etc. Accordingly, the topology of the display units 1430 can enable the presentation 1440 to be visually presented consistently such that the individual segments of the presentation 1440 are proportional and compatible with the original scale and extent of the media being played through the display units 1430. Thus, the topology can constitute spatial relationships and / or geometric properties that are not affected by the continuous changes in the shape or size of the content rendered in the presentation 1440. In one example, the automatic topology module 1408 includes a timing module 1426, a control module 1428, a signal monitor module 1432, and a signal display module 1434. The timing module 1426 can designate a particular display unit among a set of display units 1430 as a sample display unit. In such cases, the timing module 1426 can designate the remaining display modules 1430 as additional display units. In one example, the timing module 1426 automatically sets the form factor to be compatible with the hardware profile data 1402, where the presentation 1440 is automatically initiated by a sequence of graphics signals 1422.

[0179] In one example, the control module 1428 modifies a set of automatic topology settings 1406. Additionally, the signal monitor module 1432 can automatically monitor the sequence of graphics signals 1422 and trigger the storage device 1414 to associate a set of automatic topology settings 1406 with the hardware profile lookup table 1412. Further, the signal monitor module 1432 can automatically detect changes in a set of display units 1430 according to a set of change criteria and automatically generate a new topology profile corresponding to the changes in the set of display units 1430. Thereby, the new topology profile can be applied to the set of display units 1430. If the sequence of graphics signals 1422 does not meet a set of criteria, the signal monitor module 1432 can also trigger the signal display module 1434 to reapply a set of automatic topology settings 1406. If the hardware profile data 1402 does not support the automatic topology display of the sequence of graphics signals 1422, the data processing device 1418 can report an error and record the error in the error log 1413.

[0180] Cloud-Assisted Media Delivery

[0181] Now turning to Figure 15, the cloud gaming system 1500 includes a client 1540 coupled to a server 1520 via a network 1510. The client 1540 can generally be a consumer of graphical (e.g., games, virtual reality / VR, augmented reality / AR) content that is hosted, processed, and rendered on the server 1520. The illustrated scalable server 1520 has the capacity to provide graphical content to multiple clients simultaneously (e.g., by leveraging parallel and shared processing and rendering resources). In one example, the scalability of the server 1520 is limited by the capacity of the network 1510. Accordingly, there can be a threshold number of clients beyond which the service to all clients degrades.

[0182] In one example, the server 1520 includes a graphics processor (e.g., GPU) 1530, a host processor (e.g., CPU) 1524, and a network interface card (NIC) 1552. The NIC 1522 can receive requests for graphical content from the client 1540. Requests from the client 1540 can cause graphical content to be retrieved from memory via an application executed on the host processor 1524. The host processor 1524 can perform high-level operations such as, for example, determining the position, collisions, and motion of objects in a given scene. Based on these high-level operations, the host processor 1524 can generate rendering commands that are combined with scene data and executed by the graphics processor 1530. The rendering commands can cause the graphics processor 1530 to define scene geometry, shading, lighting, motion, textures, camera parameters, etc. for the scene to be presented via the client 1540.

[0183] More specifically, the illustrated graphics processor 1530 includes a graphics renderer 1532 that performs a rendering process according to the rendering commands generated by the host processor 1524. The output of the graphics renderer 1532 can be a raw video frame stream provided to a frame grabber 1534. The illustrated frame grabber 1534 is coupled to an encoder 1536 that can compress / format the raw video stream for transmission over the network 1510. The encoder 1536 can use various video compression algorithms such as, for example, the H.264 standard from the International Telecommunication Union Telecommunication Standardization Sector (ITU-T), the MPEG4 Advanced Video Coding (AVC) standard from the International Organization for Standardization / International Electrotechnical Commission (ISO / IEC), and so on.

[0184] The illustrated client 1540 (which can be a desktop computer, laptop computer, tablet computer, convertible computer, wearable device, MID, PDA, media player, etc.) includes a NIC 1542 to receive the transmitted video stream from the server 1520. The NIC 1522 can include the physical layer and the software layer foundation of the network interface in the client 1540 to facilitate communication on the network 1510. The client 1540 may also include a decoder 1544 that employs the same formatting / compression scheme as the encoder 1536. Thus, the decompressed video stream can be provided from the decoder 1544 to the video renderer 1546. The illustrated video renderer 1546 is coupled to a display 1548 that visually presents graphical content.

[0185] As already noted, the graphical content can include game content. In this regard, the client 1540 can execute a real-time interactive stream that involves collecting user input from an input device 1550 and delivering the user input to the server 1520 via the network 1510. This real-time interactive portion of cloud gaming presents challenges regarding latency.

[0186] Additional System Overview Examples

[0187] Figure 16 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, the system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and can be a single-processor desktop computer system, a multi-processor workstation system, or a server system having a large number of processors 1602 or processor cores 1607. In one embodiment, the system 1600 is a processing platform included in a system-on-chip (SoC) for use in a mobile device, a handheld device, or an embedded device.

[0188] Embodiments of the system 1600 can include or can be included within: a server-based game platform, a game console (including a game and media console), a mobile game console, a handheld game console, or an online game console. In some embodiments, the system 1600 is a mobile phone, a smartphone, a tablet computing device, or a mobile Internet device. The data processing system 1600 can also include, be coupled to, or be integrated within: wearable devices, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual display device. In some embodiments, the data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0189] In some embodiments, each of one or more processors 1602 includes one or more processor cores 1607 for processing instructions that, when executed, perform the operations of system and user software. In some embodiments, each of one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 can each process a different instruction set 1609, which can include instructions for facilitating the emulation of other instruction sets. The processor cores 1607 can also include other processing devices, such as digital signal processors (DSPs).

[0190] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 can have a single internal cache or multiple levels of internal caches. In some embodiments, the cache memory is shared among the various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC) (not shown), which can be shared among the processor cores 1607 using known cache coherence techniques. A register file 1606 is additionally included in the processor 1602, which can include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and instruction pointer registers). Some registers can be general purpose registers, while other registers can be specific to the design of the processor 1602.

[0191] In some embodiments, the processor 1602 is coupled to a processor bus 1610 to transfer communication signals (such as address, data, or control signals) between the processor 1602 and other components in the system 1600. In one embodiment, the system 1600 uses an exemplary 'hub' system architecture that includes a memory controller hub 1616 and an input / output (I / O) controller hub 1630. The memory controller hub 1616 facilitates communication between the memory device and other components of the system 1600, while the I / O controller hub (ICH) 1630 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1616 is integrated within the processor.

[0192] The memory device 1620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable performance to act as a process memory. In one embodiment, the memory device 1620 can operate as the system memory of the system 1600 to store data 1622 and instructions 1621 for use when one or more processors 1602 execute an application or process. The memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which can be coupled to the graphics processor 1608 in the processor 1602 to perform graphics and media operations.

[0193] In some embodiments, the ICH 1630 enables peripheral devices to be connected to the memory device 1620 and the processor 1602 via a high-speed I / O bus. The I / O peripheral devices include, but are not limited to: an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard disk drive, a flash memory, etc.), and a legacy I / O controller 1640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system. One or more universal serial bus (USB) controllers 1642 connect input devices (such as a keyboard and mouse 1644 combination). The network controller 1634 can also be coupled to the ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not restrictive, as other types of data processing systems configured in different ways can also be used. For example, the I / O controller hub 1630 can be integrated within the one or more processors 1602, or the memory controller hub 1616 and the I / O controller hub 1630 can be integrated within a discrete external graphics processor (such as the external graphics processor 1612).

[0194] Figure 17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A through 1702N, an integrated memory controller 1714, and an integrated graphics processor 1708. Figure 17Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the manner described elsewhere herein, but are not limited thereto. The processor 1700 may include additional cores up to and including additional core 1702N represented by the dashed box. Each of the processor cores 1702A through 1702N includes one or more internal cache units 1704A through 1704N. In some embodiments, each processor core is also capable of accessing one or more shared cache units 1706.

[0195] The internal cache units 1704A through 1704N and the shared cache unit 1706 represent a cache memory hierarchy within the processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of a shared mid-level cache (e.g., level 2 (L2), level 3 (L3), level 4 (L4), or other level cache), where the highest-level cache in front of the external memory is classified as the LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A through 1704N.

[0196] In some embodiments, the processor 1700 may also include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express bus). The system agent core 1710 provides management functions for the various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 for managing access to various external memory devices (not shown).

[0197] In some embodiments, one or more of the processor cores 1702A through 1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A through 1702N during multithreading. The system agent core 1710 may additionally include a power control unit (PCU) that includes logic and components for regulating the power states of the processor cores 1702A through 1702N and the graphics processor 1708.

[0198] In some embodiments, the processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled with a set of shared cache units 1706 and a system agent core 1710 including one or more integrated memory controllers 1714. In some embodiments, a display controller 1711 is coupled with the graphics processor 1708 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 may be a separate module coupled with the graphics processor via at least one interconnect, or may be integrated within the graphics processor 1708 or the system agent core 1710.

[0199] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units, such as point-to-point interconnects, switched interconnects, or other techniques, including techniques well known in the art, may be used. In some embodiments, the graphics processor 1708 is coupled with the ring interconnect 1712 via an I / O link 1713.

[0200] The exemplary I / O link 1713 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 1718, such as an eDRAM module. In some embodiments, each of the processor cores 1702 to 1702N and the graphics processor 1708 uses the embedded memory module 1718 as a shared last-level cache.

[0201] In some embodiments, the processor cores 1702A to 1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, the processor cores 1702A to 1702N are heterogeneous in terms of instruction set architecture (ISA), where one or more of the processor cores 1702A to 1702N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction value. In one embodiment, the processor cores 1702A to 1702N are heterogeneous in terms of microarchitecture, where one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. Additionally, the processor 1700 may be implemented on one or more chips or may be implemented as a SoC integrated circuit with the components shown in addition to other components.

[0202] Figure 18is a block diagram of a graphics processor 1800, which can be a discrete graphics processing unit or can be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates with memory via a mapped I / O interface to registers on the graphics processor and uses commands placed in the processor memory. In some embodiments, the graphics processor 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 can be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0203] In some embodiments, the graphics processor 1800 further includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and components of multi-layer video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or trans-coding media between one or more media coding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG, and Motion JPEG (MJPEG) formats).

[0204] In some embodiments, the graphics processor 1800 includes a block image transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, which include (for example) bit-boundary block transfers. However, in one embodiment, one or more components of the graphics processing engine (GPE) 1810 are used to perform 2D graphics operations. In some embodiments, the graphics processing engine 1810 is a computing engine for performing graphics operations, which include three-dimensional (3D) graphics operations and media operations.

[0205] In some embodiments, the GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions for 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 1812 includes programmable and fixed-function elements that perform various tasks in the elements and / or generated execution threads to the 3D / media subsystem 1815. Although the 3D pipeline 1812 can be used to perform media operations, embodiments of the GPE 1810 also include a media pipeline 1816, which is specifically used to perform media operations, such as video post-processing and image enhancement.

[0206] In some embodiments, media pipeline 1816 includes fixed function or programmable logic units for performing one or more specialized media operations in place of or on behalf of video codec engine 1806, such as video decode acceleration, video deinterleaving, and video encode acceleration. In some embodiments, media pipeline 1816 additionally includes a thread generation unit to generate threads for execution on 3D / media subsystem 1815. The generated threads perform computations of media operations on one or more graphics execution units included in 3D / media subsystem 1815.

[0207] In some embodiments, 3D / media subsystem 1815 includes logic for executing threads generated by 3D pipeline 1812 and media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching requests to available thread execution resources. Execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) for sharing data between threads and storing output data.

[0208] 3D / Media Processing

[0209] Figure 19 is a block diagram of graphics processing engine 1910 of a graphics processor according to some embodiments. In one embodiment, GPE 1910 is Figure 18 a version of GPE 1810 as shown in Figure 19 Elements in with the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0210] In some embodiments, GPE 1910 is coupled to command stream converter 1903, which provides a command stream to the 3D pipeline 1912 and media pipeline 1916 of the GPE. In some embodiments, command stream converter 1903 is coupled to a memory, which may be a system memory or one or more of an internal cache memory and a shared cache memory. In some embodiments, command stream converter 1903 receives commands from the memory and sends the commands to 3D pipeline 1912 and / or media pipeline 1916. The commands are instructions fetched from a ring buffer storing commands for 3D pipeline 1912 and media pipeline 1916. In one embodiment, the ring buffer may additionally include a batch command buffer storing multiple batches of multiple commands. 3D pipeline 1912 and media pipeline 1916 process the commands by performing operations via logic within their respective pipelines or by dispatching one or more execution threads to execution unit array 1914. In some embodiments, execution unit array 1914 is scalable such that the array includes a variable number of execution units based on the target power and performance levels of GPE 1910.

[0211] In some embodiments, sampling engine 1930 is coupled to a memory (e.g., cache memory or system memory) and execution unit array 1914. In some embodiments, sampling engine 1930 provides a memory access mechanism for execution unit array 1914 that allows the execution array 1914 to read graphics and media data from the memory. In some embodiments, sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0212] In some embodiments, the specialized media sampling logic in sampling engine 1930 includes denoising / deinterleaving module 1932, motion estimation module 1934, and image scaling and filtering module 1936. In some embodiments, denoising / deinterleaving module 1932 includes logic for performing one or more of a denoising or deinterleaving algorithm on decoded video data. The deinterleaving logic combines the interlaced variable length combinations of the video content into a single frame of the video. The denoising logic reduces or removes data noise from video and image data. In some embodiments, the denoising and deinterleaving logic is motion adaptive and uses spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, denoising / deinterleaving module 1932 includes specialized motion detection logic (e.g., within motion estimation engine 1934).

[0213] In some embodiments, the motion estimation engine 1934 provides hardware acceleration for video operations by performing video acceleration functions (such as motion vector estimation and prediction) on video data. The motion estimation engine determines motion vectors that describe the transformation of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on macroblock-level video that could otherwise be too computationally intensive to perform using a general-purpose processor. In some embodiments, the motion estimation engine 1934 is generally available to graphics processor components to assist with video decoding and processing functions that are sensitive or adaptive to the direction or magnitude of motion within the video data.

[0214] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to improve the visual quality of the resulting images and videos. In some embodiments, the scaling and filtering module 1936 processes image and video data during sampling operations before providing the data to the execution unit array 1914.

[0215] In some embodiments, the GPE 1910 includes a data port 1944 that provides an additional mechanism for the graphics subsystem to access memory. In some embodiments, the data port 1944 facilitates memory access for operations that include render target writes, constant buffer reads, temporary memory space reads / writes, and media surface access. In some embodiments, the data port 1944 includes a cache memory space for caching accesses to memory. The cache memory can be a single data cache or separated into multiple caches for multiple subsystems accessing memory via the data port (e.g., a render buffer cache, a constant buffer cache, etc.). In some embodiments, threads executing on the execution units in the execution unit array 1914 communicate with the data port by exchanging messages via the data distribution interconnect that couples each subsystem of the GPE 1910.

[0216] Execution Unit

[0217] Figure 20 is a block diagram of another embodiment of the graphics processor 2000. Figure 20 Elements with the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0218] In some embodiments, the graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A through 2080N. In some embodiments, the ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of multiple processors integrated within a multi-core processing system.

[0219] In some embodiments, the graphics processor 2000 receives multiple batches of commands via the ring interconnect 2002. The incoming commands are translated by a command stream converter 2003 in the pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A through 2080N. For 3D geometry processing commands, the command stream converter 2003 supplies the commands to a geometry pipeline 2036. For at least some media processing commands, the command stream converter 2003 supplies the commands to a video front end 2034, which is coupled to the media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encode / decode (MFX) 2033 engine for providing hardware-accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one of the graphics cores 2080A.

[0220] In some embodiments, the graphics processor 2000 includes scalable thread execution resources characterized by modular cores 2080A through 2080N (sometimes referred to as core slices), each modular core having a plurality of sub-cores 2050A through 2050N, 2060A through 2060N (sometimes referred to as corelets). In some embodiments, the graphics processor 2000 may have any number of graphics cores 2080A through 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor having a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes a plurality of graphics cores 2080A through 2080N, each graphics core including a set of first sub-cores 2050A through 2050N and a set of second sub-cores 2060A through 2060N. Each sub-core in the set of first sub-cores 2050A through 2050N includes at least a first set of execution units 2052A through 2052N and media / texture samplers 2054A through 2054N. Each sub-core in the set of second sub-cores 2060A through 2060N includes at least a second set of execution units 2062A through 2062N and samplers 2064A through 2064N. In some embodiments, each sub-core 2050A through 2050N, 2060A - 2060N shares a set of shared resources 2070A through 2070N. In some embodiments, these shared resources include shared cache memory and pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0221] Figure 21 Illustrated is threadable execution logic 2100, including an array of processing elements employed in some embodiments of the GPE. Figure 21 Those elements having the same reference numbers (or names) as elements in any other figure herein may operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0222] In some embodiments, the thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array including a plurality of execution units 2108A through 2108N, a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2100 includes one or more connections to memory (such as system memory or cache memory) via the instruction cache 2106, the data port 2114, the sampler 2110, and one of the execution unit arrays 2108A through 2108N. In some embodiments, each execution unit (e.g., 2108A) is an individual vector processor capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit array 2108A through 2108N includes any number of individual execution units.

[0223] In some embodiments, the execution unit array 2108A through 2108N is primarily used to execute "shader" programs. In some embodiments, the execution units in the arrays 2108A through 2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries (e.g., Direct3D and OpenGL) to be executed with minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders).

[0224] Each execution unit in the execution unit array 2108A through 2108N operates on an array of data elements. The number of data elements is the "execution size" or the number of channels for an instruction. An execution channel is a logical execution unit for data element access, masking, and flow control within an instruction. The number of channels may be independent of the number of physical arithmetic logic units (ALUs) or floating-point units (FPUs) for a particular graphics processor. In some embodiments, the execution units 2108A through 2108N support integer and floating-point data types.

[0225] The execution unit instruction set includes single instruction multiple data (SIMD). Various data elements can be stored in registers as compressed data types, and the execution unit processes these elements based on the data sizes of the various elements. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four separate 64-bit compressed data elements (quad-word (QW) sized data elements), eight separate 32-bit compressed data elements (double-word (DW) sized data elements), sixteen separate 16-bit compressed data elements (word (W) sized data elements), or thirty-two separate 8-bit data elements (byte (B) sized data elements). However, different vector widths and register sizes are possible.

[0226] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included for caching thread data during thread execution. In some embodiments, a sampler 2110 is included for providing texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functions to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0227] During execution, the graphics pipeline and the media pipeline send thread initiation requests to the thread execution logic 2100 via the thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics pipeline and the media pipeline and instantiates the requested threads on one or more execution units 2108A to 2108N. For example, the geometry pipeline (e.g., Figure 20 2036) dispatches vertex processing, tessellation, or geometry processing threads to the thread execution logic 2100 ( Figure 21 ). In some embodiments, the thread dispatcher 2104 can also handle runtime thread generation requests from executed shader programs.

[0228] Once a set of geometric objects has been processed and rasterized into pixel data, the pixel shader 2102 is invoked to further compute output information and cause the results to be written to an output surface (e.g., a color buffer, a depth buffer, a stencil buffer, etc.). In some embodiments, the pixel shader 2102 computes values for vertex attributes that are interpolated across the rasterized objects. In some embodiments, the pixel shader 2102 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations on the texture data and the input geometry compute the pixel color data for each geometric fragment, or discard one or more pixels for further processing.

[0229] In some embodiments, the data port 2114 provides a memory access mechanism for enabling the thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, the data port 2114 includes or is coupled to one or more cache memories (e.g., the data cache 2112) to cache data for memory access via the data port.

[0230] Figure 22 is a block diagram of a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, the graphics processor execution units support an instruction set having instructions of multiple formats. Solid boxes show components that are typically included in the execution unit instructions, while the dashed boxes include optional or components that are only included in a subset of the instructions. In some embodiments, the instruction formats 2200 described and shown are macro-instructions because they are the instructions supplied to the execution units, as opposed to micro-operations generated from instruction decoding (once the instruction has been processed).

[0231] In some embodiments, the graphics processor execution units natively support instructions in a 128-bit format 2210. A 64-bit compact instruction format 2230 may be used for some instructions based on the selected instruction, instruction options, and number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are restricted in the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary according to the embodiment. In some embodiments, a set of index values in an index field 2213 is used to partially compact the instruction. The execution unit hardware references a set of compression tables based on these index values and uses the compression table output to reconstruct the native instruction in the 128-bit format 2210.

[0232] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an add instruction, the execution unit performs a simultaneous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options, such as channel selection (e.g., predication) and data channel ordering (e.g., mixing). For 128-bit instructions 2210, the execution size field 2216 limits the number of data channels to be executed in parallel. In some embodiments, the execution size field 2216 is not available for the 64-bit compact instruction format 2230.

[0233] Some execution unit instructions have at most three operands, including two source operands src0 2220, src1 2222, and one destination 2218. In some embodiments, the execution unit supports dual-destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of the instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0234] In some embodiments, the 128-bit instruction format 2210 includes access / address mode information 2226 that specifies (e.g.) whether to use direct register addressing mode or indirect register addressing mode. When using direct register addressing mode, the register addresses of one or more operands are provided directly by bits in the instruction 2210.

[0235] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226 that specifies the address mode and / or access mode of the instruction. In one embodiment, the access mode defines the data access alignment of the instruction. Some embodiments support access modes including 16-byte aligned access mode and 1-byte aligned access mode, where the byte alignment of the access mode determines the access alignment of the instruction operands. For example, when in the first mode, the instruction 2210 may use byte-aligned addressing for source and destination operands, and when in the second mode, the instruction 2210 may use 16-byte aligned addressing for all source and destination operands.

[0236] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction will use direct addressing or indirect addressing. When using the direct register addressing mode, the bits in the instruction 2210 directly provide the register addresses of one or more operands. When using the indirect register addressing mode, the register addresses of one or more operands can be calculated based on the address register value and the address immediate field in the instruction.

[0237] In some embodiments, the instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For an 8-bit opcode, bits 4, 5, and 6 allow the execution unit to determine the type of opcode. The exact opcode grouping shown is merely exemplary. In some embodiments, the move and logic opcode group 2242 includes data move and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, the move and logic group 2242 shares the five most significant bits (MSB), where the move (mov) instruction takes the form 0000xxxxb and the logic instruction takes the form 0001xxxxb. The flow control instruction group 2244 (e.g., call, jmp) includes instructions that take the form 0010xxxxb (e.g., 0x20). The miscellaneous instruction group 2246 includes a mixture of instructions, including synchronization instructions (e.g., wait, send) that take the form 0011xxxxb (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, mul) that take the form 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data channels. The vector math group 2250 includes arithmetic instructions (e.g., dp4) that take the form 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product calculations on vector operands.

[0238] Graphics Pipeline

[0239] Figure 23 is a block diagram of another embodiment of the graphics processor 2300. Figure 23 Elements in (a figure) having the same reference numbers (or names) as elements in any other figure herein can operate or function in any manner similar to the ways described elsewhere herein, but are not limited thereto.

[0240] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, thread execution logic 2350, and a render output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or is controlled via commands issued to the graphics processor 2300 via the ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are translated by a command stream converter 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0241] In some embodiments, the command stream converter 2303 directs the operation of a vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by the command stream converter 2303. In some embodiments, the vertex fetcher 2305 provides vertex data to a vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2305 and the vertex shader 2307 execute vertex processing instructions by dispatching execution threads to execution units 2352A, 2352B via a thread dispatcher 2331.

[0242] In some embodiments, the execution units 2352A, 2352B are an array of vector processors having instruction sets for performing graphics and media operations. In some embodiments, the execution units 2352A, 2352B have additional L1 caches 2351 that are specific to each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0243] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware-accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides the backend evaluation of the tessellation output. The tessellator 2313 operates in the direction of the hull shader 2311 and includes dedicated logic for generating a detailed set of geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, if tessellation is not used, the tessellation components 2311, 2313, 2317 can be bypassed.

[0244] In some embodiments, a complete geometric object may be processed by the geometry shader 2319 via one or more threads dispatched to execution units 2352A, 2352B, or may proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on an entire geometric object (as opposed to vertices or vertex patches as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, the geometry shader 2319 may be programmed by a geometry shader program to perform geometric tessellation when the tessellation unit is disabled.

[0245] Before rasterization, the clipper 2329 processes vertex data. The clipper 2329 may be a fixed-function clipper or a programmable clipper with clipping and geometry shader functionality. In some embodiments, a rasterizer 2373 (e.g., a depth test component) in the render output pipeline 2370 dispatches pixel shaders to convert geometric objects into their per-pixel representation. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, an application may bypass the rasterizer 2373 and access the un-rasterized vertex data via the outflow unit 2323.

[0246] The graphics processor 2300 has an interconnect bus, an interconnect fabric, or some other interconnect mechanism that allows data and messages to be passed among the major components of the processor. In some embodiments, the execution units 2352A, 2352B and associated caches 2351, texture and media sampler 2354, and texture / sampler cache 2358 are interconnected via data ports 2356 to perform memory accesses and communicate with the render output pipeline components of the processor. In some embodiments, the sampler 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access paths.

[0247] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373 that converts vertex-based objects to associated pixel-based representations. In some embodiments, the rasterizer logic includes a winnower / masker unit for performing fixed-function triangle and line rasterization. Associated rendering cache 2378 and depth cache 2379 are also available in some embodiments. Pixel operation component 2377 performs pixel-based operations on data, although in some examples, pixel operations associated with 2D operations (e.g., bit blit and blending) are performed by 2D engine 2341 or, at display time, by display controller 2343 using overlapping display planes. In some embodiments, shared L3 cache 2375 is available to all graphics components, allowing data to be shared without using main system memory.

[0248] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from command stream converter 2303. In some embodiments, the media pipeline 2330 includes a separate command stream converter. In some embodiments, the video front end 2334 processes media commands before sending the commands to media engine 2337. In some embodiments, media engine 2337 includes a thread generation function for generating threads for dispatch to thread execution logic 2350 via thread dispatcher 2331.

[0249] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via a ring interconnect 2302, or some other interconnect bus or fabric. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic capable of operating independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which may be a system-integrated display device (such as in a laptop computer) or may be an external display device attached via a display device connector.

[0250] In some embodiments, the graphics pipeline 2320 and the media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces and are not specific to any one application programming interface (API). In some embodiments, the driver software of the graphics processor converts API dispatches specific to a particular graphics or media library into commands that can be processed by the graphics processor. In some embodiments, support is provided for the Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from the Khronos Group, the Direct 3D library from Microsoft Corporation, or support can be provided for both OpenGL and D3D. Support can also be provided for the Open Source Computer Vision Library (OpenCV). Future APIs with compatible 3D pipelines will also be supported if a mapping can be made from the pipeline of future API calls to the pipeline of the graphics processor.

[0251] Graphics Pipeline Programming

[0252] Figure 24A is a block diagram of an exemplary graphics processor command format 2400 according to some embodiments. Figure 24B is a block diagram of an exemplary graphics processor command sequence 2410 according to an embodiment. Figure 24A The solid boxes in show the components that are typically included in a graphics command, while the dashed boxes include optional components or components that are only included in a subset of graphics commands. Figure 24A The exemplary graphics processor command format 2400 of includes data fields for identifying the target client 2402 of the command, the command operation code (opcode) 2404, and the associated data 2406 of the command. A sub-opcode 2405 and a command size 2408 are also included in some commands.

[0253] In some embodiments, the client 2402 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser examines the client field of each command to adjust the further processing of the command and route the command data to the appropriate client unit. In some embodiments, the graphics processor client units include a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once a command is received by a client unit, the client unit reads the opcode 2404 and (if present) the sub-opcode 2405 to determine the operation to be performed. The client unit uses the information in the data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned by a multiple of the double-word length.

[0254] Figure 24B The flowchart in [the figure] illustrates an exemplary graphics processor command sequence 2410. In some embodiments, software or firmware of a data processing system characterized by an embodiment of a graphics processor uses a version of the illustrated command sequence to initiate, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for illustrative purposes only, as embodiments are not limited to these particular commands or this command sequence. Additionally, the commands may be issued as a batch of commands in a command sequence such that the graphics processor will process the command sequence in at least a partially simultaneous manner.

[0255] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline flush command 2412 to cause any active graphics pipeline to complete the current outstanding commands of the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. Executing the pipeline flush causes the active graphics pipeline to complete any outstanding commands. In response to the pipeline flush, the command parser of the graphics processor will suspend command processing until the active rendering engine has completed the outstanding operations and the associated read caches are invalidated. Optionally, any data marked 'dirty' in the render cache may be flushed to memory. In some embodiments, the pipeline flush command 2412 may be used for pipeline synchronization or before placing the graphics processor in a low power state.

[0256] In some embodiments, a pipeline select command 2413 is used when the command sequence requires the graphics processor to make an explicit switch between pipelines. In some embodiments, only one pipeline select command 2413 is required in the execution context before issuing pipeline commands, unless the context is to issue commands for both pipelines. In some embodiments, a pipeline flush command 2412 is required immediately before making a pipeline switch via the pipeline select command 2413.

[0257] In some embodiments, the pipeline control command 2414 configures the graphics pipeline for operation and programs the 3D pipeline 2422 and the media pipeline 2424. In some embodiments, the pipeline control command 2414 configures the pipeline state of the active pipeline. In one embodiment, the pipeline control command 2414 is used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0258] In some embodiments, the return buffer status command 2416 is used to configure a set of return buffers for enabling corresponding pipeline write data. Some pipeline operations require allocating, selecting, or configuring one or more return buffers that write intermediate data into the return buffers during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, the return buffer status 2416 includes selecting the size and number of return buffers for a set of pipeline operations.

[0259] The remaining commands in the command sequence differ based on the active pipelines for the operations. Based on the pipeline determination 2420, the command sequence is customized according to the 3D pipeline 2422 and the media pipeline 2424, where the 3D pipeline starts with the 3D pipeline state 2430 and the media pipeline starts at the media pipeline state 2440.

[0260] The commands for the 3D pipeline state 2430 include 3D state setting commands for: vertex buffer status, vertex element status, constant color status, depth buffer status, and other status variables that will be configured before processing 3D primitive commands. The values of these commands are determined at least in part based on the particular 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass specific pipeline elements if those elements will not be used.

[0261] In some embodiments, the 3D primitive 2432 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitive 2432 are forwarded to the vertex fetch function in the graphics pipeline. The vertex fetch function uses the 3D primitive 2432 command data to generate vertex data structures. The vertex data structures are stored in one or more return buffers. In some embodiments, the 3D primitive 2432 commands are used to perform vertex operations on 3D primitives via the vertex shader. To process the vertex shader, the 3D pipeline 2422 dispatches shader execution threads to the graphics processor execution units.

[0262] In some embodiments, the 3D pipeline 2422 is triggered by executing a 2434 command or event. In some embodiments, a register write triggers command execution. In some embodiments, execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, a pipeline synchronization command is used to trigger command execution to dump a clear command sequence through the graphics pipeline. The 3D pipeline will perform geometric processing on 3D primitives. Once the operations are complete, the resulting geometric objects are rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0263] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific use and programming of the media pipeline 2424 depend on the media or compute operations to be performed. During media decoding, specific media decoding operations may be offloaded to the media pipeline. In some embodiments, the media pipeline may also be bypassed, and the resources provided by one or more general-purpose processing cores may be used to perform media decoding, either wholly or in part. In one embodiment, the media pipeline also includes elements for general-purpose graphics processing unit (GPGPU) operations, where the graphics processor is used to perform SIMD vector operations using a compute shader program that is not explicitly related to the rendering of graphics primitives.

[0264] In some embodiments, the media pipeline 2424 is configured in a manner similar to the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into the command queue before the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring media pipeline elements that will be used to process media objects. This includes data for configuring video decoding and video encoding logic within the media pipeline (such as encoding or decoding modes). In some embodiments, the media pipeline state commands 2440 also support using one or more pointers for "indirect" state elements that contain a batch of state settings.

[0265] In some embodiments, the media object command 2442 supplies a pointer to a media object to be processed by a media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before the media object command 2442 is issued. Once the pipeline state is configured and the media object command 2442 is queued, the media pipeline 2424 is triggered via an execute command 2444 or an equivalent execution event (e.g., a register write). The output from the media pipeline 2424 can then be post-processed by operations provided by the 3D pipeline 2422 or the media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0266] Graphics Software Architecture

[0267] Figure 25 Exemplary graphics software architecture of a data processing system 2500 according to some embodiments is shown. In some embodiments, the software architecture includes a 3D graphics application 2510, an operating system 2520, and at least one processor 2530. In some embodiments, the processor 2530 includes a graphics processor 2532 and one or more general-purpose processor cores 2534. The graphics application 2510 and the operating system 2520 each execute in the system memory 2550 of the data processing system.

[0268] In some embodiments, the 3D graphics application 2510 includes one or more shader programs, which include shader instructions 2512. The shader language instructions may be in a high-level shader language, such as High-Level Shader Language (HLSL) or OpenGL Shading Language (GLSL). The application also includes executable instructions 2514 in machine language suitable for execution by the general-purpose processor cores 2534. The application also includes geometric objects 2516 defined by vertex data.

[0269] In some embodiments, the operating system 2520 is an operating system from Microsoft Corporation, a proprietary UNIX-like operating system using a variant of the Linux kernel, or an open-source UNIX-like operating system. When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a low-level shader language. The compilation may be Just-In-Time (JIT) compilation, or the application may perform shader pre-compilation. In some embodiments, during compilation of the 3D graphics application 2510, high-level shaders are compiled into low-level shaders.

[0270] In some embodiments, the user-mode graphics driver 2526 includes a backend shader compiler 2527 that is used to convert shader instructions 2512 into a hardware-specific representation. When the OpenGL API is in use, shader instructions 2512 in the GLSL high-level language are passed to the user-mode graphics driver 2526 for compilation. In some embodiments, the user-mode graphics driver 2526 uses operating system kernel-mode functions 2528 to communicate with the kernel-mode graphics driver 2529. In some embodiments, the kernel-mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0271] IP Core Implementation

[0272] One or more aspects of at least one embodiment can be implemented by representative code stored on a machine-readable medium that represents and / or defines logic within an integrated circuit, such as a processor. For example, the machine-readable medium may include instructions representing various logics within the processor. When read by the machine, the instructions can cause the machine to fabricate logic for performing the techniques described herein. Such representations (referred to as "IP cores") are reusable units of the logic of an integrated circuit and can be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model can be supplied to various consumers or manufacturing facilities that load the hardware model on a manufacturing machine for fabricating the integrated circuit. The integrated circuit can be fabricated such that the circuit performs operations associated with any of the embodiments described herein.

[0273] Figure 26 is a block diagram showing an IP core development system 2600 according to an embodiment, which can be used to fabricate an integrated circuit to perform operations. The IP core development system 2600 can be used to generate a modular, reusable design that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2630 can use a high-level programming language (e.g., C / C++) to generate a software simulation 2610 of the IP core design. The software simulation 2610 can be used to design, test, and verify the behavior of the IP core. Then, a register transfer level (RTL) design can be created or synthesized from the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of an integrated circuit that models the flow of digital signals between hardware registers (including the associated logic performed using the modeled digital signals). In addition to the RTL design 2615, lower-level designs at the logic level or transistor level can also be created, designed, or synthesized. Thus, the specific details of the initial design and simulation can vary.

[0274] The RTL design 2615 or equivalent can be further synthesized by a design facility into a hardware model 2620, which can be in a hardware description language (HDL) or some other representation of physical design data. The HDL can be further simulated or tested to verify the IP core design. A non - volatile memory 2640 (e.g., a hard disk, flash memory, or any non - volatile storage medium) can be used to store the IP core design for delivery to a third - party manufacturing facility 2665. Alternatively, the IP core design can be transmitted (e.g., via the Internet) through a wired connection 2650 or a wireless connection 2660. The manufacturing facility 2665 can then manufacture an integrated circuit that is at least partially based on the IP core design. The manufactured integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.

[0275] Figure 27 FIG. is a block diagram showing an exemplary system - on - a - chip integrated circuit 2700 according to an embodiment. The system - on - a - chip integrated circuit can be manufactured using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., a CPU), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which can be a modular IP core from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic, including a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, I 2 S / I 2 2C controller 2740. Additionally, the integrated circuit can include a display device 2745 that is coupled to one or more of a high - definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage can be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface can be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0276] Additionally, other logic and circuitry can be included in the processors of the integrated circuit 2700, including additional graphics processors / cores, peripheral interface controllers, or general - purpose processor cores.

[0277] Additional Notes and Examples

[0278] Example 1 may include a device for reducing glare on an electronic display dashboard, the device comprising: an electronic display dashboard in a vehicle, the dashboard for displaying a plurality of objects including at least one of a virtual dial, an instrument, and a user interface (UI); a sensor for sensing glare on the dashboard; and means for moving any one of the objects away from the glare.

[0279] Example 2 may include the device as described in Example 1, wherein the sensor is a camera.

[0280] Example 3 may include the device as described in Example 1, wherein the means for moving any one of the objects away from the glare is for a user to drag the object to a new position.

[0281] Example 4 may include the device as described in Example 1, wherein the means for moving any one of the objects away from the glare object is performed by a voice command.

[0282] Example 5 may include the device as described in Example 2, wherein the means for moving any one of the objects away from the glare to a new position is automatically performed when the camera senses glare.

[0283] Example 6 may include the device as described in Example 2, wherein when the camera senses glare, the object is duplicated at a second position on the dashboard.

[0284] Example 7 may include a method for reducing glare on an electronic display dashboard, the method comprising: providing an electronic display dashboard in a vehicle, the dashboard for displaying a plurality of objects including at least one of a virtual dial, an instrument, and a user interface (UI); sensing glare on the dashboard; and moving any one of the objects away from the glare.

[0285] Example 8 may include the method as described in Example 7, wherein the sensing is performed by a camera.

[0286] Example 9 may include the method as described in Example 7, wherein the object is dragged by a user to a new position.

[0287] Example 10 may include the method as described in Example 7, wherein the object is moved to a new position by a voice command.

[0288] Example 11 may include the method as described in Example 8, wherein when the camera senses glare, the object is moved to a new position.

[0289] Example 12 may include the method as described in Example 8, wherein when the camera senses glare, the object is replicated at a second position on the dashboard.

[0290] Example 13 may include at least one computer-readable medium having instructions stored thereon that, when executed, cause a processor to perform the steps of Examples 7 - 12.

[0291] Example 14 may include a method for reducing glare on a windshield, the method comprising: providing an electronically - displayable windshield on a vehicle; providing at least a camera to provide video to the windshield that displays a driver's view; detecting glare in a zone of the windshield; and dimming the zone until the glare disappears.

[0292] Example 15 may include the method as described in Example 14, further comprising: performing a high - dynamic - range analysis on the video to determine the presence and location of the glare.

[0293] Example 16 may include at least one computer-readable medium having instructions stored thereon that, when executed, cause a processor to perform the steps of Examples 14 - 15.

[0294] Example 17 may include a device for reducing glare on a windshield, the device comprising: an electronically - displayable windshield on a vehicle; at least a camera for providing video to the windshield that displays a driver's view; a sensor for detecting glare in a zone of the windshield; and means for dimming the zone until the glare disappears.

[0295] Example 18 may include the device as described in Example 17, further comprising: means for performing a high - dynamic - range analysis on the video to determine the presence and location of the glare.

[0296] Example 19 may include a method for reducing blind spots in front of a dashboard, the method comprising: providing an electronically - displayable dashboard in a vehicle; providing video of an area in front of the vehicle to be displayed on the dashboard, the video being a view as if there were no front of the vehicle.

[0297] Example 20 may include the method as described in Example 19, wherein an object occluded by the front of the vehicle is visible on the dashboard.

[0298] Example 21 may include the method as described in Example 19, wherein the video is provided by at least one camera.

[0299] Example 22 may include the method as described in Example 19, wherein the dashboard further displays a plurality of objects including at least one of a virtual dial, a gauge, and a user interface (UI) superimposed on the video.

[0300] Example 23 may include the method as described in Example 19, wherein the view from the windshield closely matches the view on the dashboard.

[0301] Example 24 may include the method as described in Example 23, wherein the electronic display dashboard includes most of the area below the windshield.

[0302] Example 25 may include the method as described in Example 19, wherein the electronic display dashboard includes at least one discrete display that gives the appearance of a window outside the front of the vehicle.

[0303] Example 26 may include at least one computer-readable medium having instructions stored thereon that, when executed, cause a processor to perform the steps of Examples 19 - 25.

[0304] Example 27 may include a device for reducing blind spots in front of a dashboard, the device including: an electronic display dashboard in a vehicle; and a video of the area in front of the vehicle to be displayed on the dashboard, the video being a view as if the front of the vehicle were not there.

[0305] Example 28 may include the device as described in Example 27, wherein an object blocked by the front of the vehicle is visible on the dashboard.

[0306] Example 29 may include the device as described in Example 27, further including: at least one camera for providing the video.

[0307] Example 30 may include the device as described in Example 27, wherein the dashboard further includes: when activated, a plurality of objects including at least one of a virtual dial, a gauge, and a user interface (UI) superimposed on the video.

[0308] Example 31 may include the device as described in Example 27, wherein the view from the windshield closely matches the view on the dashboard.

[0309] Example 32 may include the device as described in Example 31, wherein the electronic display dashboard includes most of the area below the windshield.

[0310] Example 33 may include the device as described in Example 27, wherein the electronic display dashboard includes at least one discrete display that presents an appearance as a window outside in front of the vehicle.

[0311] Example 34 may include a method for filling an occluded area, the method including: providing a mixed reality experience to a user wearing a head-mounted display (HMD) communicatively coupled to a processor; providing an outward-facing camera on the HMD for providing real-world live video onto which virtual objects are superimposed; using the processor to identify a partial object in the camera's field of view, the partial object having a visible portion and an occluded portion; and filling the occluded portion.

[0312] Example 35 may include the method as described in Example 34, wherein the occluded portion is filled by the processor that has a memory of having previously seen the occluded portion.

[0313] Example 36 may include the method as described in Example 34, wherein the occluded portion is filled by the processor that has a memory of having previously seen something similar.

[0314] Example 37 may include the method as described in Example 34, wherein the occluded portion is filled by the processor that has a memory of having previously seen a similar partial view of several similar things in the same room.

[0315] Example 38 may include the method as described in Example 34, wherein the occluded portion is filled by the processor that will go to the cloud and search for the entire object based on the partial object.

[0316] Example 39 may include at least one computer-readable medium having instructions stored thereon that, when executed, cause a processor to perform the steps of Examples 34 - 38.

[0317] Example 40 may include a system for filling an occluded area, the system including: a head-mounted display for providing a mixed reality experience to a user; a processor communicatively coupled to the HMD; an outward-facing camera on the HMD for providing real-world live video onto which virtual objects are superimposed; the processor for identifying a partial object in the camera's field of view, the partial object having a visible portion and an occluded portion; and means for filling the occluded portion.

[0318] Example 41 may include the system as described in Example 40, wherein the occluded portion is filled by the processor that has a memory of having previously seen the occluded portion.

[0319] Example 42 may include the system as described in Example 40, wherein the occluded portion is filled by the processor, which has a memory of having seen similar things before.

[0320] Example 43 may include the system as described in Example 40, wherein the occluded portion is filled by the processor, which has a memory of having seen partial views of several similar things in the same room before.

[0321] Example 44 may include the system as described in Example 40, wherein the occluded portion is filled by the processor, which will go to the cloud and search for the whole object based on the partial object.

[0322] Example 45 may include a device for reducing glare on an electronic display dashboard, the device including: an electronic display dashboard in a vehicle, the dashboard being configured to display a plurality of objects including at least one of virtual dials, gauges, and a user interface (UI); means for sensing glare on the dashboard; and means for moving any one of the objects away from the glare.

[0323] Example 46 may include the device as described in Example 45, wherein the means for sensing is performed by a camera.

[0324] Example 47 may include the device as described in Example 45, wherein the means for moving is dragged by a user to a new position.

[0325] Example 48 may include the device as described in Example 45, wherein the means for moving is performed by a voice command.

[0326] Example 49 may include the device as described in Example 46, wherein the means for moving the object to a new position is triggered when the camera senses glare.

[0327] Example 50 may include the method as described in Example 8, wherein when the camera senses glare, the object is duplicated at a second position on the dashboard.

[0328] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components being discussed and may apply to electrical, mechanical, fluid, optical, electromagnetic, electro-mechanical, or other connections. Additionally, the terms "first", "second", etc. may be used herein solely for ease of discussion and do not convey any specific temporal or chronological significance unless otherwise indicated. Further, it should be understood that the indefinite article "a" or "an" carries the meaning of "one or more" or "at least one".

[0329] As used in this application and the claims, a list of items described by the phrase "one or more" can mean any combination of the listed items. For example, the phrase "at least one of A, B, and C" means A, B, C; A and B; A and C; B and C; or A, B, and C.

[0330] Embodiments have been described above with reference to specific embodiments. However, those skilled in the art will understand that various modifications and changes can be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. Accordingly, the foregoing description and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. A display system for a vehicle, comprising: an electronic display; a sensor interface for receiving video data of an external environment from at least one camera disposed on the vehicle, the external environment including a blind spot area of the vehicle; and a processing circuitry operatively coupled to the electronic display and the sensor interface, the processing circuitry being configured to: display an instrument representation in the electronic display, the instrument representation corresponding to an operation of the vehicle; and in response to an event occurring in the vehicle: display a view of an occluded object in the electronic display based on the video data, wherein the occluded object is present in the external environment within the blind spot area of the vehicle; and change a display of the instrument representation in the electronic display.

2. The display system according to claim 1, wherein the instrument representation includes one or more objects, and wherein changing the display of the instrument representation includes: moving the one or more objects of the instrument representation relative to a display of the view of the occluded object.

3. The display system according to claim 2, wherein moving the display of the instrument representation includes: superimposing the one or more objects of the instrument representation on the view of the occluded object.

4. The display system according to claim 1, wherein the instrument representation includes one or more virtual instruments or dials corresponding to an operation of the vehicle.

5. The display system according to claim 4, wherein the one or more virtual instruments or dials include a speedometer or a revolutions per minute (RPM) meter.

6. The display system according to claim 1, wherein the electronic display is included in an instrument panel of the vehicle.

7. The display system according to claim 1, wherein the blind spot is partially occluded from a driver's perspective by a part of the vehicle.

8. The display system according to claim 1, wherein the event is an action from a driver.

9. A non-transitory computer-readable storage medium capable of storing instructions that, when executed, cause at least one processing device of a display system for a vehicle to perform the following steps: receive video of an external environment from at least one camera disposed on the vehicle, the external environment including a blind spot area of the vehicle; display an instrument representation in the electronic display of the vehicle, the instrument representation corresponding to an operation of the vehicle; and in response to an event occurring in the vehicle: display a view of an occluded object in the electronic display based on the video data, wherein the occluded object is present in the external environment within the blind spot area of the vehicle; and change a display of the instrument representation in the electronic display.

10. The non-transitory computer-readable storage medium according to claim 9, wherein the instrument representation includes one or more objects, and wherein changing the display of the instrument representation includes: moving the one or more objects of the instrument representation relative to a display of the view of the occluded object.

11. The non-transitory computer-readable storage medium according to claim 10, wherein Moving the display of the instrument representation includes: superimposing the one or more objects of the instrument representation onto the view of the occluded object.

12. The non-transitory computer-readable storage medium according to claim 9, wherein, the instrument representation includes one or more virtual gauges or dials corresponding to the operation of the vehicle.

13. The non-transitory computer-readable storage medium according to claim 12, wherein, the one or more virtual gauges or dials include a speedometer or a revolutions per minute (RPM) gauge.

14. The non-transitory computer-readable storage medium according to claim 9, wherein, the electronic display is included in the instrument panel of the vehicle.

15. The non-transitory computer-readable storage medium according to claim 9, wherein, the blind spot is partially occluded by a part of the vehicle from the driver's perspective.

16. The non-transitory computer-readable storage medium according to claim 9, wherein, the event is an action from the driver.

17. A device for a vehicle, comprising: means for receiving video of an external environment from at least one camera disposed on the vehicle, the external environment including a blind spot area of the vehicle; means for displaying an instrument representation in an electronic instrument panel display, the instrument representation corresponding to the operation of the vehicle; means for displaying a view of an occluded object in the electronic instrument panel display based on the video data in response to an event occurring in the vehicle, wherein the occluded object is present in the external environment within the blind spot area of the vehicle; and means for changing the instrument representation in the electronic instrument panel display in response to the event occurring in the vehicle.

18. The device according to claim 17, wherein, the instrument representation includes one or more objects, and wherein the means for changing the instrument representation includes: means for moving the one or more objects of the instrument representation relative to the display of the view of the occluded object; and means for superimposing the one or more objects of the instrument representation onto the view of the occluded object.

19. The device according to claim 17, wherein, the instrument representation includes one or more virtual gauges or dials corresponding to the operation of the vehicle, and wherein the one or more virtual gauges or dials include a speedometer or a revolutions per minute (RPM) gauge.

20. The device according to claim 17, wherein, the electronic instrument panel display is provided by a display device included in the instrument panel of the vehicle.

21. The device according to claim 17, wherein, the blind spot is partially occluded by a part of the vehicle from the driver's perspective.

22. A method, comprising: receiving video of an external environment from at least one camera disposed on a vehicle, the external environment including a blind spot area of the vehicle; displaying an instrument representation in the electronic display of the vehicle, the instrument representation corresponding to the operation of the vehicle; and in response to an event occurring in the vehicle: Based on the video data, display a view of the occluded object in the electronic display, where the occluded object exists in the external environment within the blind spot area of the vehicle; and change the display of the instrument representation.

23. The method according to claim 22, wherein, the instrument representation includes one or more objects, and wherein changing the display of the instrument representation includes: moving the one or more objects of the instrument representation relative to the display of the view of the occluded object; and superimposing the one or more objects of the instrument representation onto the view of the occluded object.

24. The method according to claim 22, wherein, the instrument representation includes one or more virtual instruments or dials corresponding to the operation of the vehicle, and wherein the one or more virtual instruments or dials include a speedometer or a revolutions per minute (RPM) meter.

25. The method according to claim 22, wherein, the electronic display is included in the instrument panel of the vehicle.

26. The method according to claim 22, wherein, the blind spot is partially occluded by a part of the vehicle from the driver's perspective.

27. The method according to claim 22, wherein, the event is an action from the driver.

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