Fault positioning method, system and device of eMMC and medium

Abstract

The embodiment of the invention provides a fault positioning method, system and device of an eMMC and a medium, the eMMC comprises a first pin, and the method comprises the following steps: determining an operation stage of the eMMC; under the condition that the operation stage of the eMMC is a first type stage, configuring the first pin to be in a GPIO (General Purpose Input / Output) mode; respectively calling a first function at a plurality of function calling points of the first type stage, so that the first pin respectively outputs a waveform signal with a preset period number at each function calling point; obtaining the waveform signal output by the first pin through oscillographic equipment, and generating visual waveform data; and determining the fault position of the eMMC based on the visual waveform data, so as to quickly obtain the state information of the eMMC, thereby improving the efficiency of judging the fault position of the eMMC.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence technology, and particularly to a method, system, device and medium for fault location of eMMC. Background Art

[0002] eMMC (embedded MultiMediaCard), namely embedded multimedia card, is a standard for flash memory cards, established and released by the Joint Electron Device Engineering Council (JEDEC). It is mainly used for storing data, such as files like operating systems, applications, photos, videos, music, etc., and provides an integrated storage solution by encapsulating flash memory and a controller in a small chip, which is very suitable for use in electronic devices such as mobile devices, tablets, smart TVs, etc.

[0003] During the development of eMMC, it is often necessary to adapt to new NandFlash particles. At the same time, in order to adapt to new NandFlash particles or improve performance, the firmware of eMMC also needs to be optimized or updated. Due to the introduction of new variables, the eMMC module may encounter various problems during the testing process, such as read / write errors, data loss, performance degradation, etc. Developers need to obtain the status information of eMMC and judge the location where the eMMC fails based on the obtained status information.

[0004] However, during the Brom stage when eMMC is running, it is impossible to determine the location where the eMMC fails by modifying the code. For the problems that occur during the Brom stage, only the scope of the problem can be minimized as much as possible, reproduce the problem on a specific verification platform, and then use the JTAG (Joint Test Action Group) method to determine the location where the eMMC fails. This method has cumbersome steps and results in low efficiency. Summary of the Invention

[0005] The main purpose of the embodiments of this application is to propose a method, system, device and medium for fault location of eMMC, aiming to quickly obtain the status information of eMMC, thereby improving the efficiency of determining the location where the eMMC fails.

[0006] To achieve the above object, in the first aspect of the embodiments of this application, a method for fault location of eMMC is proposed. The eMMC includes a first pin, and the method includes:

[0007] Determine the operating stage in which the eMMC is located;

[0008] When the operating stage in which the eMMC is located is a first type of stage, configure the first pin as the GPIO mode;

[0009] Call the first function at multiple function call points in the first type of stage, so that the first pin outputs waveform signals with a preset number of cycles at each of the function call points;

[0010] Obtain the waveform signal output by the first pin through an oscilloscope device and generate visual waveform data;

[0011] Determine the fault location of the eMMC based on the visual waveform data.

[0012] Through the method provided by the first aspect, the fault location of the eMMC can be quickly determined, greatly simplifying the process of eMMC fault location, improving the efficiency of judging the location where the eMMC fails, and solving the problem that in the prior art, the location where the eMMC fails cannot be judged by modifying the code during the Brom stage when the eMMC is running, and can only be judged by cumbersome steps.

[0013] In a possible implementation manner, the first type of stage is one of the following: Brom stage, Boot stage, or Firmware stage.

[0014] In a possible implementation manner, the preset number of cycles corresponding to the waveform signals output at each of the function call points is different.

[0015] In a possible implementation manner, after determining the running stage of the eMMC, the method further includes:

[0016] When the running stage of the eMMC is the second type of stage, configure the first pin to the UART mode;

[0017] Based on the UART mode, send a program code data packet to the host device through the first pin;

[0018] Parse the program code data packet through the host device to generate program code information;

[0019] Determine the fault location of the eMMC based on the program code information.

[0020] In a possible implementation manner, the second type of stage is the Boot stage or the Firmware stage.

[0021] In a possible implementation manner, parsing the program code data packet through the host device to generate program code information includes:

[0022] The host device divides the program code data packet into multiple data packets;

[0023] The host device sorts and reorganizes the multiple data packets to generate program code information.

[0024] In a possible implementation manner, the oscilloscope device includes a logic analyzer.

[0025] To achieve the above object, a second aspect of the embodiments of the present application provides a fault location system for an eMMC. The eMMC includes a first pin, and the system includes:

[0026] A stage determination module: configured to determine the operating stage of the eMMC;

[0027] A pin configuration module: configured to configure the first pin as a GPIO mode when the operating stage of the eMMC is a first type of stage;

[0028] A function call module: configured to call a first function at multiple function call points in the first type of stage, so that the first pin outputs waveform signals with a preset number of cycles at each of the function call points;

[0029] A data processing module: configured to obtain the waveform signals output by the first pin through an oscilloscope device and generate visual waveform data;

[0030] A data analysis module: configured to determine the fault location of the eMMC based on the visual waveform data.

[0031] Through the system provided in the second aspect, the fault location of the eMMC can be quickly determined, the process of eMMC fault location is greatly simplified, the efficiency of determining the location where the eMMC fails is improved, and the problem in the prior art that the location where the eMMC fails cannot be determined by modifying the code during the Brom stage when the eMMC is running, and the location where the eMMC fails can only be determined through cumbersome steps is solved.

[0032] In a third aspect, an electronic device is provided. The electronic device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the fault location method of the eMMC described in any possible implementation manner in the first aspect is implemented.

[0033] In a fourth aspect, a computer-readable storage medium is provided. The storage medium stores a computer program, and when the computer program is executed by a processor, the fault location method of the eMMC described in any possible implementation manner in the first aspect is implemented.

[0034] As can be seen from the technical solutions provided by one or more embodiments of the present specification above, the method for fault location of eMMC provided by the embodiments of the present application, the eMMC includes a first pin, and the method includes: determining the operating stage in which the eMMC is located; when the operating stage in which the eMMC is located is a first type of stage, configuring the first pin as a GPIO mode; calling a first function at multiple function call points in the first type of stage, so that the first pin outputs a waveform signal with a preset number of cycles at each of the function call points; obtaining the waveform signal output by the first pin through an oscilloscope device and generating visual waveform data; determining the fault location of the eMMC based on the visual waveform data. It realizes quickly obtaining the status information of the eMMC, improves the efficiency of judging the location where the eMMC fails, and solves the problem that in the prior art, in the Brom stage when the eMMC is running, it is impossible to judge the location where the eMMC fails by modifying the code, and only can judge the location where the eMMC fails through cumbersome steps. Description of the Drawings

[0035] In order to more clearly illustrate the technical solutions in one or more embodiments of the present specification or the prior art, the following will briefly introduce the drawings required for the description of one or more embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present specification. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic flowchart of the method for fault location of eMMC provided by the embodiments of the present application;

[0037] Figure 2 It is a structural block diagram of an electronic device according to an embodiment of the present application. Detailed Embodiments

[0038] In order to enable those skilled in the art to better understand the technical solutions in the present specification, the following will clearly and completely describe the technical solutions in one or more embodiments of the present specification with reference to the drawings in one or more embodiments of the present specification. Obviously, the described one or more embodiments are only part of the embodiments of the present specification, rather than all the embodiments. Based on one or more embodiments in the present specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this document.

[0039] It should be noted that, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first", "second", etc. in the specification, claims and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0041] In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other. The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0042] Figure 1 is an optional flow chart of the eMMC fault locating method provided in the embodiment of the present application. Figure 1 The method may include but is not limited to steps S100 to S500.

[0043] First, as Figure 1 As shown, a fault location method of an eMMC is provided, the eMMC includes a first pin, and the method includes:

[0044] S100: Determine the operation stage of the eMMC.

[0045] It should be noted that the operation phase of eMMC mainly includes three phases, namely Brom phase, Boot phase and Firmware phase. Among them, Brom phase is usually solidified inside the chip and is determined and integrated by developers during the system-level chip design phase.

[0046] S200: When the operation stage of the eMMC is the first type stage, configure the first pin to be in GPIO mode.

[0047] It should be noted that when the main controller does not use the HS400 and HS400ES modes, the first pin is configured as a GPIO output mode, that is, the first pin is set to a state where a level signal can be sent to an external device.

[0048] It should also be noted that the pins of eMMC are mainly divided into power pins, signal pins, control pins and other special pins. Among them, the power pins include VCC, VCCQ, etc., which are used to provide power supply; the signal pins include CMD (command), CLK (clock), DATA0 - DATA7 (data bus), etc.; the control pins include RESET (reset), etc., which are used to control the reset operation of the eMMC device; the other special pins include the Data Strobe (data strobe) pin, etc. Specifically, the first pin is the Data Strobe pin, which is used to provide a data synchronization signal to the host controller in the HS400 and HS400ES high - speed data transfer modes. In these modes, the Data Strobe signal is synchronized with the transmission of data bits to ensure that data is accurately received within the correct clock cycle, improving the stability and reliability of data transmission. The Data Strobe pin is mainly enabled in the two high - speed modes of HS400 and HS400ES. In the HS400 mode, eMMC supports double - data - rate transmission, that is, data can be transmitted on both the rising edge and the falling edge of the clock signal. At this time, the Data Strobe signal of the Data Strobe pin serves as the synchronization reference for data, and is synchronized with the transmission of data bits to ensure high - speed and accurate data transmission; while in the HS400ES mode, the Data Strobe signal is further enhanced to provide more stable data transmission performance. In the prior art, when eMMC communicates with the host controller, during the initialization process of the eMMC device, a bus calibration or bus timing adjustment process will be carried out to avoid problems such as data transmission errors or system instability caused by any timing mismatch on the bus. However, in this application, by using the Data Strobe pin for communication between eMMC and the host controller, the bus calibration or bus timing adjustment process is omitted, simplifying the communication between eMMC and the host controller and ensuring the stability and reliability of data transmission.

[0049] Among them, when the host controller needs to use the HS400 and HS400ES modes, the host controller will send a mode - switching command of CMD6 to eMMC. After receiving the mode - switching command of CMD6, eMMC will switch the function of the first pin Data Strobe from the GPIO function to the normal function, and then the host controller can normally use the function of the Data Strobe pin.

[0050] S300: Call the first function at multiple function call points in the first - type stage respectively, so that the first pin outputs waveform signals with a preset number of cycles at each function call point.

[0051] It should be noted that by respectively outputting waveform signals with a preset number of cycles at the function call point, the debugging and testing work can be greatly facilitated. The waveform period is a key parameter in hardware communication and timing control. Different waveform periods will cause different behavioral responses of the hardware. Therefore, by presetting the waveform period, the eMMC status can be observed and analyzed. By observing the waveform changes at the function call point with an oscilloscope device, the real-time status of the eMMC can be intuitively understood. If the waveform period is abnormal, it means that there is some fault or problem with the eMMC. Comparing the actually observed waveform with the expected waveform can quickly locate the fault point. At the same time, by presetting the waveform period, it helps to test the performance and stability of the eMMC, so as to ensure that the eMMC can work properly in actual applications and improve the test efficiency.

[0052] In addition, the waveform signal includes a square wave signal. The square wave signal has clear waveform characteristics, including a fixed frequency, amplitude, and duty cycle, and also has obvious rising and falling edges. These edges appear as clear jump points in the time domain. The waveform of the square wave signal is simple and easy to measure, and a test device can be used to accurately measure it. Through the analysis of the test data, developers can clearly observe the response of the eMMC, so as to accurately locate the fault point or judge the operation stage information of the eMMC. By adjusting parameters such as the frequency and amplitude of the square wave signal, the device performance under various working conditions can be simulated, so as to find potential problems and optimize them. Since the waveform characteristics of the square wave signal are clear, it can provide more accurate information in fault detection. Compared with other types of signals, the square wave signal is less susceptible to noise and interference, thus improving the accuracy of fault detection. Using the square wave signal for fault detection is usually a non-destructive test method and will not cause any damage to the device during the test, thus ensuring the integrity and reliability of the eMMC. It can be understood that the embodiments of the present application do not limit the category of the waveform signal.

[0053] In some embodiments, the frequency of the square wave signal can be set to 200 MHz. The higher the frequency of the square wave signal, the shorter its period, and thus it has a higher resolution on the time axis. A 200 MHz square wave signal means that the time length of each period is 5 ns, providing a higher resolution. The high-frequency square wave signal can more sensitively reflect the minute changes inside the device, thus helping to discover potential faults, and the high-frequency square wave signal can support a higher data transmission rate and provide richer information.

[0054] S400. Obtain the waveform signal output by the first pin through an oscilloscope device and generate visual waveform data.

[0055] S500. Determine the fault location of the eMMC based on the visual waveform data.

[0056] Through the method provided by the first aspect, the fault location of the eMMC is quickly determined, greatly simplifying the process of eMMC fault location, improving the efficiency of judging the fault location of the eMMC, and solving the problem that in the prior art, the fault location of the eMMC cannot be judged by modifying the code during the Brom stage when the eMMC is running, and only the cumbersome steps can be used to judge the fault location of the eMMC.

[0057] In a possible implementation manner, the first type of stage is one of the following: Brom stage, Boot stage or Firmware stage.

[0058] It should be noted that the eMMC mainly includes three stages. Among them, the first stage is the Brom (Boot ROM) stage. The program in the Brom stage is usually unchangeable. Brom is a read-only memory embedded inside the system-on-chip, and its content has been solidified during the chip manufacturing process, and users cannot directly modify the program therein. What is stored in Brom is the first batch of boot programs after the device is powered on. These programs are crucial for the subsequent startup process of the device. They are responsible for tasks such as initializing the CPU, loading the driver of the startup medium, judging the startup mode, and loading the boot program of the next stage. Since the stability and reliability of these programs are of great significance for the normal startup and operation of the device, they are usually designed to be read-only to prevent users from accidentally or maliciously modifying them. If the program in Brom needs to be updated, it usually needs to be achieved by replacing the entire system-on-chip, which is a complex and costly operation. Therefore, in most cases, users cannot directly change the program in the Brom stage. The second stage of the eMMC is the Boot stage. The main boot program is responsible for loading and initializing the operating system or a higher-level boot loader. These boot programs are usually stored in specific partitions or user data areas of the eMMC. Since these partitions are writable, users can change these boot programs through specific methods. The third stage of the eMMC is the Firmware stage. Firmware is the fixed software code stored in the device and is used for the initialization and operation of the device. Different from the program in Brom, the firmware can usually be updated. Firmware updates usually involve writing new firmware code into the storage medium of the device (such as the firmware partition of the eMMC) and being loaded and executed by the boot program when the device starts up. The reasons for firmware updates may include fixing known bugs, adding new functions, improving performance or enhancing security, etc. Users can download and install new firmware versions through the update tools provided by the device manufacturer or online update services.

[0059] In a possible implementation manner, the preset number of cycles corresponding to the waveform signals output by each of the function call points is different.

[0060] It should be noted that the preset number of cycles corresponding to the waveform signals output at each function call point is different, which can greatly facilitate debugging and testing work. The waveform period is a key parameter in hardware communication and timing control. Different waveform periods will cause different behavioral responses of the hardware. Therefore, by outputting different waveform periods, the eMMC status can be observed and analyzed. By observing the waveform changes at the function call point with an oscilloscope device, the real-time status of the eMMC can be intuitively understood. If the waveform period is abnormal, it means that there is some fault or problem with the eMMC. Comparing the actually observed waveform with the expected waveform can quickly locate the fault point, which helps to test the performance and stability of the eMMC, thus ensuring that the eMMC can work properly in actual applications and improving the test efficiency.

[0061] In a possible implementation manner, after determining the operation stage in which the eMMC is located, the method further includes: when the operation stage in which the eMMC is located is a second type of stage, configuring the first pin as the UART mode; based on the UART mode, sending a program code data packet to the host device through the first pin; parsing the program code data packet by the host device to generate program code information; and determining the fault location of the eMMC based on the program code information.

[0062] Specifically, the first pin is the Data Strobe pin, which is used to provide a data synchronization signal to the main controller in the HS400 and HS400ES high-speed data transmission modes. In these modes, the Data Strobe signal is synchronized with the transmission of data bits to ensure that data is accurately received within the correct clock cycle, improving the stability and reliability of data transmission. The DataStrobe pin is mainly enabled in these two high-speed modes of HS400 and HS400ES. In the HS400 mode, the eMMC supports double data rate transmission, that is, data can be transmitted on both the rising edge and the falling edge of the clock signal. At this time, the Data Strobe signal of the Data Strobe pin serves as the synchronization reference for data and is synchronized with the transmission of data bits to ensure high-speed and accurate data transmission; while in the HS400ES mode, the Data Strobe signal is further enhanced to provide more stable data transmission performance.

[0063] Among them, when the main controller does not use the HS400 and HS400ES modes, the first pin is configured as a UART interface to obtain program code information. The UART interface has a relatively simple connection. It does not require additional clock signal lines or other complex control signal lines, only two data lines, namely the transmit line and the receive line. In contrast, other communication interfaces such as I2C and SPI may require more pins, increasing the complexity of the hardware connection. This makes the UART interface more concise in hardware design and reduces the complexity of wiring. At the same time, the UART communication protocol is relatively simple. Communication can be carried out only by configuring basic parameters such as the baud rate. The setting of these parameters is usually completed through the UART control register, and the configuration process is relatively intuitive and simple. In addition, due to the simple hardware connection and small number of pins of the UART interface, the cost of the device can be significantly reduced, and the development difficulty of developers can be reduced.

[0064] It should be noted that setting the first pin as a UART interface requires setting UART parameters for the first pin. Among them, the UART parameters include the baud rate. In some embodiments, the baud rate is set to 921600 bps. The UART interface is a widely used asynchronous serial communication technology that allows two devices to perform two-way data transmission. The baud rate is the unit for measuring the UART communication speed, indicating the number of bits transmitted per second. The baud rate of 921600 bps provides a higher data transmission speed compared to common lower baud rates such as 9600 bps and 19200 bps. This means that more data can be transmitted in the same amount of time, improving the communication efficiency and reducing the time required for data transmission. Although a higher baud rate may increase the complexity and cost of the hardware, appropriate configuration and optimization can enable it to maintain communication stability while achieving high-speed data transmission. A higher baud rate usually means a higher signal frequency, which can enhance the anti-interference ability of the communication to a certain extent and reduce communication errors caused by noise or interference.

[0065] It should also be noted that when the main controller needs to use the HS400 and HS400ES modes, the main controller sends a mode switching command of CMD6 to the eMMC. After receiving the mode switching command of CMD6, the eMMC switches the function of the first pin Data Strobe from the UART function to the normal function, and the main controller can then normally use the function of the Data Strobe pin.

[0066] In a possible implementation manner, the second type of stage is the Boot stage or the Firmware stage.

[0067] It should be noted that the second stage of eMMC is the Boot stage. The main boot program is responsible for loading and initializing the operating system or a higher-level boot loader. These boot loaders are usually stored in specific partitions or the user data area of the eMMC. Since these partitions are writable, users can change these boot loaders through specific methods. The third stage of eMMC is the Firmware stage. Firmware is the fixed software code stored in the device and is used for device initialization and operation. Different from the programs in Brom, firmware is usually updatable. Firmware updates usually involve writing new firmware code into the storage medium of the device (such as the firmware partition of eMMC) and being loaded and executed by the boot program when the device starts. The reasons for firmware updates may include fixing known bugs, adding new features, improving performance, or enhancing security, etc. Users can download and install new firmware versions through the update tools provided by the device manufacturer or online update services.

[0068] In a possible implementation manner, the host device parses the program code data packet to generate program code information, including: the host device divides the program code data packet into multiple data packets; the host device sorts and reorganizes the multiple data packets to generate program code information.

[0069] It should be noted that after the host device receives multiple data packets, it first checks the multiple data packets. The checksum is recalculated based on the checksum carried in the data packet to obtain a check value. The recalculated checksum is compared with the checksum carried in the data packet. If the two are consistent, it is considered that the data packet has not had an error during transmission; if they are inconsistent, it is considered that the data packet has an error and error handling is required. After passing the check, the host device identifies the start and end of each data packet to correctly reorganize the data packets and splice these data packets back into a complete program code. This process improves the reliability and accuracy of data transmission.

[0070] In a possible implementation manner, the oscilloscope device includes a logic analyzer.

[0071] In some embodiments, a logic analyzer is typically equipped with a graphical user interface that can display waveform diagrams, timing diagrams, etc. in real time, and at the same time provide functions such as data decoding, statistical analysis, and protocol analysis. These functions enable developers to intuitively understand the state and changes of signals, thereby locating and solving problems more quickly. In addition, the logic analyzer can further process and analyze the captured data, such as filtering out unnecessary data, sorting the data, or calculating the frequency of the signal. Most logic analyzers work by passively monitoring voltage changes on signal lines without interfering with the system under test. This non-intrusive monitoring method ensures the normal operation of the system under test while providing accurate measurement results. Advanced logic analyzers support automatic decoding of multiple communication protocols (such as SPI, I2C, UART, etc.), greatly simplifying the complexity of protocol layer debugging, which enables developers to more easily understand and analyze the communication process in a digital system, thereby locating and solving problems in eMMC more quickly. In addition, the logic analyzer provides precise timestamp recording, which can be accurate to the nanosecond level or even the picosecond level, helping developers understand the timing relationship between signals. Additionally, it can be understood that the embodiments of the present application do not limit the type of test equipment.

[0072] To achieve the above object, a second aspect of the embodiments of the present application proposes a fault location system for an eMMC. The eMMC includes a first pin. The system includes:

[0073] A stage determination module: used to determine the operating stage of the eMMC.

[0074] A pin configuration module: used to configure the first pin as the GPIO mode when the operating stage of the eMMC is a first type of stage.

[0075] It should be noted that when the main controller does not use the HS400 and HS400ES modes, configuring the first pin as the output mode includes configuring the first pin as the GPIO output mode, that is, the first pin is set to a state where it can send level signals to external devices.

[0076] It should also be noted that the pins of eMMC are mainly divided into power pins, signal pins, control pins and other special pins. Among them, the power pins include VCC, VCCQ, etc., which are used to provide power supply; the signal pins include CMD (command), CLK (clock), DATA0 - DATA7 (data bus), etc.; the control pins include RESET (reset), etc., which are used to control the reset operation of the eMMC device; the other special pins include the Data Strobe (data strobe) pin, etc. Specifically, the first pin is the Data Strobe pin, which is used to provide a data synchronization signal to the host controller in the HS400 and HS400ES high - speed data transfer modes. In these modes, the Data Strobe signal is synchronized with the transmission of data bits to ensure that data is accurately received within the correct clock cycle, improving the stability and reliability of data transmission. The Data Strobe pin is mainly enabled in the two high - speed modes of HS400 and HS400ES. In the HS400 mode, eMMC supports double - data - rate transmission, that is, data can be transmitted on both the rising edge and the falling edge of the clock signal. At this time, the Data Strobe signal of the Data Strobe pin is used as the synchronization reference for data, synchronized with the transmission of data bits to ensure high - speed and accurate data transmission; while in the HS400ES mode, the Data Strobe signal is further enhanced to provide more stable data transmission performance. In the prior art, when eMMC communicates with the host controller, during the initialization process of the eMMC device, a bus calibration or bus timing adjustment process will be carried out to avoid problems such as data transmission errors or system instability caused by any timing mismatch on the bus. However, in this application, by using the Data Strobe pin for communication between eMMC and the host controller, the bus calibration or bus timing adjustment process is omitted, simplifying the communication between eMMC and the host controller and ensuring the stability and reliability of data transmission.

[0077] Among them, when the host controller needs to use the HS400 and HS400ES modes, the host controller will send a mode - switching command of CMD6 to eMMC. After receiving the mode - switching command of CMD6, eMMC will switch the function of the first pin Data Strobe from the GPIO function to the normal function, and then the host controller can normally use the function of the Data Strobe pin.

[0078] Function call module: used to call the first function at multiple function call points in the first - type stage, so that the first pin outputs waveform signals with a preset number of cycles at each of the function call points.

[0079] It should be noted that the first type of stage is the Brom stage, Boot stage, or Firmware stage. Among them, the first stage of eMMC is the Brom (Boot ROM) stage. The program in the Brom stage is usually unchangeable. Brom is a read-only memory embedded inside the system-on-chip, and its content has been solidified during the chip manufacturing process, and users cannot directly modify the program therein. What is stored in Brom is the first batch of boot programs after the device is powered on. These programs are crucial for the subsequent startup process of the device. They are responsible for tasks such as initializing the CPU, loading the driver programs of the startup medium, determining the startup mode, and loading the boot programs of the next stage. Since the stability and reliability of these programs are of great significance for the normal startup and operation of the device, they are usually designed to be read-only to prevent users from accidentally or maliciously modifying them. If the program in Brom needs to be updated, it usually needs to be achieved by replacing the entire system-on-chip, which is a complex and costly operation. Therefore, in most cases, users cannot directly change the program in the Brom stage. The second stage of eMMC is the Boot stage. The main boot program is responsible for loading and initializing the operating system or a higher-level boot loader. These boot programs are usually stored in specific partitions or user data areas of eMMC. Since these partitions are writable, users can change these boot programs through specific methods. The third stage of eMMC is the Firmware stage. Firmware is the fixed software code stored in the device and is used for the initialization and operation of the device. Different from the program in Brom, the firmware is usually updatable. Firmware updates usually involve writing new firmware code into the storage medium of the device (such as the firmware partition of eMMC) and being loaded and executed by the boot program when the device starts up. The reasons for firmware updates may include fixing known bugs, adding new functions, improving performance, or enhancing security, etc. Users can download and install new firmware versions through the update tools provided by the device manufacturer or online update services.

[0080] It should also be noted that outputting waveform signals with a preset number of cycles at the function call points can ensure that each function is executed at the correct time, avoid eMMC failures or instabilities caused by chaotic execution orders, and also help optimize the performance of the device. By reasonably arranging the call order and execution time of functions, unnecessary waiting and delays can be reduced, and the response speed and overall performance of eMMC can be improved. When an eMMC failure occurs, locating the function call points can help developers quickly locate the problem. By checking the execution situation and relevant parameters of the function call points, it is easier to find the root cause of the problem and perform corresponding repairs and optimizations.

[0081] Data processing module: configured to obtain the waveform signal output from the first pin through an oscilloscope device and generate visual waveform data.

[0082] Data analysis module: configured to determine the fault location of the eMMC based on the visual waveform data.

[0083] Through the system provided by the second aspect, the fault location of the eMMC can be quickly determined, greatly simplifying the process of eMMC fault location, improving the efficiency of determining the location where the eMMC fails, and solving the problem in the prior art that the location where the eMMC fails cannot be determined by modifying the code during the Brom stage when the eMMC is running, and only the location where the eMMC fails can be determined through cumbersome steps.

[0084] An embodiment of the present application also provides an electronic device, as Figure 2 shown. The electronic device 1400 includes:

[0085] One or more processors 1410;

[0086] A memory 1420, on which one or more programs are stored. When the one or more programs are executed by the one or more processors 1410, the one or more processors 1410 implement the eMMC fault location method provided by any embodiment of the present application.

[0087] The memory 1420, as a non-transitory network system, can be used to store non-transitory software programs and non-transitory computer-executable programs. In addition, the memory 1420 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state storage devices. In some embodiments, the memory 1420 may optionally include a memory 1420 remotely disposed relative to the processor 1410, and these remote memories 1420 may be connected to the processor 1410 through a network. Examples of the above networks include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0088] The memory 1420 may be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM), etc. The memory 1420 may store an operating system and other application programs. When implementing the technical solutions provided by the embodiments of the present specification through software or firmware, the relevant program codes are stored in the memory 1420 and are called by the processor 1410 to execute the methods of the embodiments of the present application.

[0089] The processor 1410 can be implemented in the form of a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, etc., and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0090] In some embodiments, the electronic device further includes:

[0091] An input / output interface for implementing information input and output;

[0092] A communication interface for implementing communication interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.);

[0093] A bus for transmitting information between various components of the device (such as the processor 1410, the memory 1420, the input / output interface, and the communication interface);

[0094] Among them, the processor 1410, the memory 1420, the input / output interface, and the communication interface can achieve communication connections with each other inside the device through the bus.

[0095] An embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, and the computer-executable instructions are used to execute the eMMC fault location method provided in any embodiment of the present application.

[0096] An embodiment of the present application further provides a computer program product, including a computer program or computer instructions. The computer program or computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the computer device executes the eMMC fault location method provided in any embodiment of the present application.

[0097] The system architecture and application scenarios described in the embodiments of the present application are for more clearly explaining the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art know that with the evolution of the system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0098] Those of ordinary skill in the art can understand that all or part of the processes in the above-described method embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the method embodiments as described above. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or an external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0099] Those of ordinary skill in the art can understand that all or some of the steps and systems disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technologies, CD-ROM, digital versatile disk (DVD), or other optical disk storage, magnetic cassettes, tapes, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium typically includes computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0100] Some embodiments of the present application have been described above with reference to the accompanying drawings, which do not limit the scope of the present invention. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the present invention shall fall within the scope of the rights of the present application.

[0101] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and their appropriate combinations.

[0102] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily need to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0103] In addition, in each embodiment of the present application, each functional unit can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

[0104] Each embodiment in this specification is described in a progressive manner. The same or similar parts between each embodiment can be referred to each other, and the key points of each embodiment are the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0105] The above describes specific embodiments of this specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0106] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings, which do not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A method for locating a fault of an eMMC, characterized in that: The eMMC includes a first pin, and the method includes: Determine the operation stage of the eMMC; When the operation stage of the eMMC is the first type stage, configuring the first pin to be in GPIO mode; Calling the first function at multiple function calling points in the first type stage respectively, so that the first pin outputs a waveform signal with a preset number of cycles at each of the function calling points; Acquire the waveform signal output by the first pin through an oscilloscope device, and generate visualized waveform data; A fault location of the eMMC is determined based on the visualized waveform data.

2. The method according to claim 1, characterized in that The first type of stage is one of the following: Brom stage, Boot stage or Firmware stage.

3. The method according to claim 1, characterized in that: The preset number of cycles corresponding to the waveform signals output by each of the function call points is different.

4. The method according to claim 1, characterized in that After determining the operation stage of the eMMC, the method further includes: When the operation stage of the eMMC is the second type stage, configuring the first pin to a UART mode; Based on the UART mode, sending a program code data packet to a host device through the first pin; Parsing the program code data packet by the host computer device to generate program code information; A fault location of the eMMC is determined based on the program code information.

5. The method according to claim 4, characterized in that The second type of stage is a Boot stage or a Firmware stage.

6. The method according to claim 4, characterized in that The upper computer device parses the program code data packet to generate program code information, including: The host computer device divides the program code data packet into multiple data packets; The host computer device sorts and reorganizes the multiple data packets to generate program code information.

7. The method according to claim 1, characterized in that The oscilloscope equipment includes a logic analyzer.

8. A fault location system based on eMMC, characterized in that: The eMMC includes a first pin, and the system includes: A phase determination module: used to determine the operation phase of the eMMC; A pin configuration module: configured to configure the first pin to a GPIO mode when the operation stage of the eMMC is a first type stage; Function calling module: used for respectively calling the first function at a plurality of function calling points in the first type stage, so that the first pin outputs a waveform signal of a preset number of cycles at each of the function calling points; Data processing module: used for acquiring the waveform signal output by the first pin through an oscilloscope device and generating visual waveform data; Data analysis module: used to determine the fault location of the eMMC based on the visualized waveform data.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the eMMC fault locating method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the eMMC fault locating method according to any one of claims 1 to 7 is implemented.

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