Method, system and equipment for improving execution efficiency of addressing space of external program of single-chip microcomputer and medium

Abstract

The invention provides a single-chip microcomputer external program addressing space execution efficiency improving method and system, and the method comprises the steps: copying a paging call code of a single-chip microcomputer to a project directory, modifying a corresponding parameter, and adding the paging call code to a project; selecting and using an extension linker in equipment of a target option, selecting code pages in a target, and setting the number of pages and starting and ending addresses; selecting and combining the HEX file in the output, and generating an extended linear address record format; formulating a page where a function is located in the user table segment information; burning the generated HEX file into a serial memory; and the PAGESEL is used for switching the paging. According to the method, the direct mapping instruction cache controller is used for improving the program execution efficiency, when the CPU initiates the instruction reading operation every time, the instruction cache controller can read the content of four continuous addresses and store the content in the data memory of the instruction cache controller, four pieces of read data are returned by each read instruction, the efficiency is improved by more than four times, and the method can be flexibly expanded.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded systems on a chip, and particularly to a method, system, device and medium for improving the execution efficiency of the external program addressing space of a single-chip microcomputer. Background Art

[0002] Generally, the program space of an 8051 SoC (System On Chip) system is limited by the structure of the CPU and can only address 64 KB of space. For some 8051 SoC system cores, the program address bus can be configured as 23 bits, that is, 8 MB. When the CPU addresses 0x0 to 0x7FFF, the high bits of the program address bus are 0 because the lowest 32 KB of the program space stores the reset, interrupt vector table, and some common / share / root program spaces. When the CPU addresses above 0x7FFF, a specific address of a special function register (SFR) needs to be configured. This address stores an 8-bit PAGESEL, which is concatenated to the [23:15] bits of the address bus to form a 24-bit address. The high 8 bits (address [23:15]) indicate 256 page numbers (or bank numbers), and the low 15 bits (address [14:0]) indicate the address offset within a specific page.

[0003] In an MCU, due to limited pin numbers, a serial NOR Flash is usually used as the external program storage space. One disadvantage of a serial NOR Flash is its low execution efficiency and inability to perform in-place execution (XIP) like a parallel NOR Flash.

[0004] Therefore, it is necessary to provide a new method to solve the above technical problems. Summary of the Invention

[0005] To achieve the above objects and other advantages of the present invention, a first object of the present invention is to provide a method for improving the execution efficiency of the external program addressing space of a single-chip microcomputer, including the following steps:

[0006] Copy the paged call code of the single-chip microcomputer to the project directory, modify the corresponding parameters, and add the paged call code to the project;

[0007] Select to use an extended linker in the device of the target options;

[0008] Select code paging in the target of the target options, and specify the number of paging used and the start and end addresses;

[0009] Select to merge the HEX file in the output of the target option and generate an extended linear address record format;

[0010] Specify the page where the function is located in the user table segment information of the locator of the extended linker under the target option;

[0011] Burn the generated HEX file into the external serial memory;

[0012] Use the PAGESEL of the special function register to switch the page;

[0013] Further, the single-chip microcomputer is configured as an 8051 series single-chip microcomputer.

[0014] Further, the page call code is configured as KEIL / C51 / LIB / L51_bank.A51;

[0015] The step of modifying the corresponding parameters includes:

[0016] Modify the corresponding number of pages and mode parameters.

[0017] Further, the extended linker is configured as LX51.

[0018] Further, the merged HEX file is configured as Merge32K Hexfile;

[0019] The extended linear address record format is configured as HEX-386 format.

[0020] Further, the step of using the PAGESEL of the special function register to switch the page includes:

[0021] Use PAGESEL[7:0] to switch the BANK; where PAGESEL is located at the 0x94 address of the special function register, the reset value is 1, and the software setting range is 1 to 255.

[0022] Further, it further includes the step:

[0023] Access the tag memory of the instruction cache controller through the block number access instruction of the physical address issued by the single-chip microcomputer;

[0024] If the read area number is equal to the area number of the current main memory address and VALID is 1, the cache hits;

[0025] If the read area number is not equal to the area number of the current main memory address or VALID is 0, perform cache line replacement.

[0026] The second object of the present invention is to provide a system for improving the execution efficiency of the external program addressing space of a single-chip microcomputer. Applying the above method, it includes an instruction cache controller, a serial memory controller, and an off-chip serial memory; wherein,

[0027] The instruction cache controller uses a direct mapping structure. The physical address is divided into a tag, a block number index address, and a byte selection. It includes a tag memory and a data memory inside; it reads data in a bypass read mode. When the cache hits, it directly fetches data from the cache. When the cache misses, it reads data from the memory and writes this data into the cache at the same time;

[0028] The write operation of the off-chip serial memory does not pass through the instruction cache controller.

[0029] The third object of the present invention is to provide a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above method.

[0030] The fourth object of the present invention is to provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the above method.

[0031] Compared with the prior art, the beneficial effects of the present invention are:

[0032] The present invention provides a method, a system, a device, and a medium for improving the execution efficiency of the external program addressing space of a single-chip microcomputer. It uses a direct mapping instruction cache controller to improve the program execution efficiency. When the CPU initiates a read instruction operation each time, the instruction cache controller can read the contents of 4 consecutive addresses and store them in the data memory of the instruction cache controller, realizing that each read instruction returns 4 read data, and the efficiency is increased by more than 4 times. And it can be flexibly expanded, such as expanding the number of bytes read from the off-chip serial memory at one time to improve the hit rate, etc.

[0033] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and implement it according to the content of the specification, the following takes the preferred embodiments of the present invention and combines the drawings to elaborate in detail as follows. The specific implementation manners of the present invention are given in detail by the following embodiments and their accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present invention and form a part of this application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0035] Figure 1 It is a flowchart of a method for improving the execution efficiency of the external program addressing space of a single-chip microcomputer;

[0036] Figure 2 is the principle block diagram of the instruction cache controller;

[0037] Figure 3 is the schematic diagram of the comparison logic;

[0038] Figure 4 is the overall block diagram of the system for improving the execution efficiency of the external program addressing space of the single-chip microcomputer;

[0039] Figure 5 is the schematic diagram of the computer device;

[0040] Figure 6 is the schematic diagram of the computer-readable storage medium. Specific Embodiments

[0041] Next, in combination with the accompanying drawings and specific embodiments, the present invention will be further described. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. It should be noted that, on the premise of no conflict, the following-described embodiments or technical features can be combined arbitrarily to form new embodiments.

[0042] All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts fall within the scope of protection of the present invention.

[0043] In the present application, the accompanying drawing numbers are only used to distinguish each step in the solution and are not used to limit the execution order of each step. The specific execution order shall be subject to the description in the specification.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0045] Embodiment 1

[0046] A method for improving the execution efficiency of the external program addressing space of a single-chip microcomputer uses the method of code paging (CODE BANKING), as Figure 1 shown, and includes the following steps:

[0047] S1. Copy the paged call code of the single-chip microcomputer to the project directory, modify the corresponding parameters, and add the paged call code to the project;

[0048] In some embodiments, the single-chip microcomputer is configured as an 8051 series single-chip microcomputer. That is, the method provided in this embodiment can be applied to an 8051 SoC system to improve the program execution efficiency when the program space is located in an external serial memory.

[0049] Further, the paged call code is configured as KEIL / C51 / LIB / L51_bank.A51;

[0050] The step of modifying the corresponding parameters includes:

[0051] Modify the corresponding number of pages (banks) and mode parameters.

[0052] That is, copy KEIL / C51 / LIB / L51_bank.A51 to the project directory, modify the corresponding bank number, mode and other parameters, and add this L51_bank.A51 to the project.

[0053] S2. Select to use the extended linker in the device of the target options;

[0054] Further, the extended linker is configured as LX51. That is, select to use LX51 in Options for Target->Device.

[0055] S3. Select code paging in the target of the target options, and specify the number of pages used and the start and end addresses; that is, select Code banking in Options for Target->Target, and specify how many banks to use, as well as Start and End.

[0056] S4. Select to merge the HEX file in the output of the target options and generate an extended linear address record format;

[0057] Further, the merged HEX file is configured as Merge32K Hexfile;

[0058] The extended linear address record format is configured as the HEX-386 format.

[0059] That is, select Merge32K Hexfile in Options for Target->Output, and generate the HEX-386 format.

[0060] S5. Specify the page where the function is located in the user segment information of the locator of the extended linker under the target option; that is, in Options for Target->LX51 Locate's User Segments, specify which bank a certain function is located in. For example:?PR?PP1?BANK_TEST(B1:0x9000) means to place the PP1 function at the address starting from 0x9000 in bank1.

[0061] The final generated HEX file is arranged as follows:

[0062] BANK Address Range COMMON BANK 0x000000 to 0x007FFF (0 to 32KB) BANK1 0x008000 to 0x00FFFF (32KB to 64KB) BANK2 0x010000 to 0x017FFF (32KB to 64KB) BANK3 0x018000 to 0x01FFFF (32KB to 64KB) BANK4 0x020000 to 0x027FFF (32KB to 64KB) BANK5 0x028000 to 0x02FFFF (32KB to 64KB) … … BANK254 0x7F8000 to 0x7FFFFF (32KB to 64KB)

[0063] S6. Burn the generated HEX file into the external serial memory;

[0064] S7. Use the PAGESEL of the special function register to switch the page.

[0065] Furthermore, when using, PAGESEL[7:0] needs to be used to switch the BANK. PAGESEL is located at the SFR 0x94 address, the reset value is 1, and the software setting range is 1 to 255. The actual MemAddr for accessing the external serial memory is {PAGESEL[7:0], MemAddr[14:0]}, with a total of 23 address lines, and an address space of 8MB can be addressed.

[0066] In some embodiments, as Figures 2 - 4 shown, it further includes the steps:

[0067] Access the tag memory of the cache controller through the block number access instruction of the physical address sent by the single-chip microcomputer; specifically, when the MCU executes an instruction, it first sends a physical address, and uses the block number to access the tag memory.

[0068] If the read zone number is equal to the zone number of the current main memory address and VALID is 1, then the cache hit;

[0069] If the read zone number is not equal to the zone number of the current main memory address or VALID is 0, then the cache miss, and cache line replacement is required.

[0070] In this way, every time the CPU issues a read instruction operation, the instruction cache controller can read the contents of 4 consecutive addresses and store them in the data memory of the instruction cache controller. A single external serial memory read requires sending a byte read command and three bytes of read addresses, and each byte requires 8 external serial memory clocks. This embodiment can achieve 4 read data returned for each read instruction, with the efficiency increased by more than 4 times.

[0071] Embodiment 2

[0072] A system for improving the execution efficiency of the external program addressing space of a single-chip microcomputer applies the method for improving the execution efficiency of the external program addressing space of a single-chip microcomputer provided in Embodiment 1. For the detailed description of the method for improving the execution efficiency of the external program addressing space of a single-chip microcomputer provided in Embodiment 1, reference can be made to the corresponding description in Embodiment 1, which will not be elaborated here. As Figures 2 - 4 shown, the system includes an instruction cache controller, a serial memory controller, and an external serial memory; among them,

[0073] As Figure 2 shown, the instruction cache controller uses a direct mapping structure. The physical address is divided into a tag, a block number index address, and a byte selection. For example: the physical address is divided into 3 parts: Tag 6 bits, block number index address 8 bits (256 cache lines), byte selection 2 bits (select the required byte from 4 bytes and return it to the CPU). It internally includes a tag memory and a data memory. For example: one Tag memory is configured as 256X7 bit (6 bit tag + 1 bit valid), and one Data memory is configured as 256X32 bit; it reads data in a look aside manner. When the cache hits (Cache hit), it directly fetches data from the cache. When the cache misses (Cache miss), it reads data from the memory and simultaneously writes this data into the cache; in this embodiment, the size of the instruction cache (Cache) is set to 2KB.

[0074] The write operation of the external serial memory does not pass through the instruction cache controller.

[0075] As Figure 3 shown, when the MCU executes an instruction, it first issues a physical address (Physical Address) and accesses the Tag memory with the block number. If the read area number is equal to the area number of the current main memory address and VALID is 1, then the cache hits (Cache hit); if the area numbers are not equal or VALID is 0, then the cache misses (Cache miss), and cache line replacement is required.

[0076] In this way, each time the CPU initiates a read instruction operation, the instruction cache controller can read the contents of 4 consecutive addresses and store them in the Data memory of the instruction cache controller. A single external serial memory read requires sending a byte read command and three bytes of read addresses, and each byte requires 8 external serial memory clocks. This embodiment can achieve 4 read data returned for each read instruction, with the efficiency increased by more than 4 times.

[0077] This embodiment designs the instruction cache controller using a direct mapping structure and writes it in Verilog scripting language. This embodiment can be flexibly extended, for example, by expanding the number of bytes read from the external serial memory at one time to improve the hit rate, etc.

[0078] Embodiment 3

[0079] A computer device 800, as Figure 5 shown, includes a memory 810, a processor 820, and a computer program 830 stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a method for improving the execution efficiency of the external program addressing space of a single-chip microcomputer. For a detailed description of the method, reference can be made to the corresponding description in the above method embodiments, and details will not be repeated here.

[0080] Embodiment 4

[0081] A computer-readable storage medium, as Figure 6 shown, stores a computer program thereon. When the computer program is executed by a processor, it implements the steps of a method for improving the execution efficiency of the external program addressing space of a single-chip microcomputer. For a detailed description of the method, reference can be made to the corresponding description in the above method embodiments, and details will not be repeated here.

[0082] The number of devices and the processing scale described here are used to simplify the description of the present invention. Applications, modifications, and variations of the present invention will be apparent to those skilled in the art.

[0083] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and embodiments. It can be fully applied to various fields suitable for the present invention. For those skilled in the art, additional modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and the illustrated examples here.

[0084] The device, computer device, non-volatile computer storage medium, and method provided by the embodiments of this specification are corresponding. Therefore, the device, computer device, and non-volatile computer storage medium also have beneficial technical effects similar to those of the corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the corresponding device, computer device, and non-volatile computer storage medium will not be elaborated here.

[0085] Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, the method steps can be logically programmed to enable the controller to implement the same functions in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, such a controller can be regarded as a hardware component, and the devices included therein for implementing various functions can also be regarded as the structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software units for implementing the method and the structures within the hardware component.

[0086] The systems, devices, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. For the convenience of description, when describing the above devices, they are described as various units according to their functions. Of course, when implementing one or more embodiments of this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0087] Those skilled in the art should understand that the embodiments of this specification can be provided as a method, system, or computer program product. Therefore, the embodiments of this specification can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0088] This specification is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0089] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0090] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0091] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0092] The specification may be described in the general context of computer-executable instructions executed by a computer, such as program units. Generally, program units include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communications network. In a distributed computing environment, program units may be located in local and remote computer storage media, including storage devices.

[0093] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0094] The above is only for the embodiments of this specification and is not intended to limit one or more embodiments of this specification. For those skilled in the art, one or more embodiments of this specification may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of one or more embodiments of this specification shall be included within the scope of the claims of one or more embodiments of this specification.

Claims

1. A method for improving the execution efficiency of a single-chip microcomputer external program addressing space, characterized in that: The following steps are involved: Copy the paging call code of the microcontroller to the project directory, modify the corresponding parameters, and add the paging call code to the project; In the target device options, select Use extended linker; Select code paging in the target of the target option, and specify the number of pages to be used and the start and end addresses; In the output of the target option, select Merge HEX file and generate extended linear address record format; Specifying the page where the function is located in the user table segment information of the locator of the extended linker under the target option; Burn the generated HEX file into the off-chip serial memory; The paging is switched using the PAGESEL special function register.

2. A method for improving the execution efficiency of a single-chip microcomputer external program addressing space as claimed in claim 1, characterized in that: The single chip microcomputer is configured as a 8051 series single chip microcomputer.

3. A method for improving the execution efficiency of a single-chip microcomputer external program addressing space as claimed in claim 2, characterized in that: The paging call code is configured as KEIL / C51 / LIB / L51_bank.A51; The step of modifying the corresponding parameters comprises: Modify the corresponding paging number and mode parameters.

4. A method for improving the execution efficiency of a single-chip microcomputer external program addressing space as claimed in claim 3, characterized in that: The extended linker is configured as LX51.

5. A method for improving the execution efficiency of a single-chip microcomputer external program addressing space as claimed in claim 4, characterized in that: The merged HEX file is configured as Merge32K Hexfile; The extended linear address record format is configured in HEX-386 format.

6. A method for improving the execution efficiency of a single-chip microcomputer external program addressing space as claimed in claim 1, characterized in that: The step of switching the paging by using the PAGESEL of the special function register comprises: Use PAGESEL[7:0] to switch BANK; PAGESEL is located at address 0x94 of the special function register, the reset value is 1, and the software setting range is 1 to 255.

7. A method for improving the execution efficiency of a single-chip microcomputer external program addressing space as claimed in claim 1, characterized in that: Also includes the steps: Accessing the tag memory of the instruction cache controller through the block number of the physical address issued by the single chip microcomputer; If the read area number is equal to the area number of the current main memory address and VALID is 1, the cache hits; If the read area number is not equal to the area number of the current main memory address or VALID is 0, a cache line replacement is performed.

8. A system for improving the execution efficiency of external program addressing space of a single-chip microcomputer, applying the method according to any one of claims 1 to 7, characterized in that: It includes an instruction cache controller, a serial memory controller, and an off-chip serial memory; wherein, The instruction cache controller uses a direct mapping structure, the physical address is divided into a tag, a block number index address, and a byte selection, and includes a tag memory and a data memory internally; a bypass readout method is used to read data, when a cache hits, data is directly taken from the cache, and when a cache misses, data is read from the memory and simultaneously written into the cache; The write operation of the off-chip serial memory does not pass through the instruction cache controller.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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