Memory and firmware optimization method thereof

Abstract

The invention provides a memory and a firmware optimization method thereof, and the memory comprises at least one flash memory control unit which is provided with at least one flash memory unit; the interface flash memory unit is used for storing firmware to be tested; the trigger control unit is used for generating a corresponding test instruction according to a preset test item; the main control unit is used for modifying data in firmware to be tested according to the test instruction and controlling the flash memory unit to execute corresponding operation according to the test instruction and the firmware to be tested after data modification; the main control unit is also used for identifying operation information when the flash memory unit executes the operation, and optimizing the firmware to be tested according to the operation information to obtain the optimized firmware; and the read-only storage unit is used for storing the optimized firmware. According to the memory and the firmware optimization method thereof provided by the invention, the firmware can be subjected to test optimization.

Description

Technical Field

[0001] The present invention relates to the field of storage, and particularly to a memory and a method for optimizing its firmware. Background Art

[0002] With the wide application of memories in consumer electronic devices such as smart TVs, set-top boxes, and mobile terminals, the memory needs to achieve a balance among data reliability, stability, and operating efficiency. The memory adopts a cooperative architecture of an ARM architecture main control and NAND flash memory, and realizes core functions such as bad block management, garbage collection, and performance optimization through firmware. Its highly integrated characteristics result in a complex system environment with multiple modules operating in parallel inside.

[0003] Traditional white-box testing has single conditions and is difficult to simulate multi-module concurrency, abnormal attacks, and differences in different flash memory characteristics in real scenarios, resulting in insufficient verification of core functions such as bad block management and garbage collection of the firmware. Therefore, how to test and optimize the firmware of the memory is a technical problem to be solved urgently. Summary of the Invention

[0004] The purpose of the present invention is to provide a memory and a method for optimizing its firmware, which can test and optimize the firmware.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions: The present invention provides a memory, including: At least one flash control unit, on which at least one flash unit is configured; An interface flash unit for storing the firmware to be tested; A trigger control unit for generating corresponding test instructions according to preset test items; A main control unit for modifying data in the firmware to be tested according to the test instructions, and controlling the flash unit to execute corresponding operations according to the test instructions and the firmware with modified data; the main control unit is further used to identify operation information when the flash unit executes operations, and optimize the firmware to be tested according to the operation information to obtain an optimized firmware; A read-only storage unit for storing the optimized firmware.

[0006] In an embodiment of the present invention, the test instructions include a reset instruction; the main control unit optimizes the firmware to be tested according to the following steps: Setting reset durations of different sizes according to the reset instruction; At each reset duration, respectively performing a reset operation on the flash control unit, and determining whether the logical units in the flash unit respond normally: When all logical units can respond normally, retain this reset duration; Otherwise, eliminate this reset duration; Sort the retained reset durations and obtain the minimum reset duration, denoted as the target reset time; Update the reset time in the firmware configuration table of the firmware to be tested according to the target reset time, so as to obtain an optimized firmware.

[0007] In an embodiment of the present invention, the test instruction includes an identity recognition instruction; the main control unit optimizes the firmware to be tested according to the following steps: Change the identity information of at least one logical unit in the identity configuration table of the firmware to be tested according to the identity recognition instruction; After the flash control unit performs a reset operation, identify the identity information of each logical unit; Judge whether each changed identity information matches the corresponding identified identity information: When there is at least one changed identity information that matches the corresponding identified identity information, perform a reset operation on the flash control unit, restore the identity configuration table, and optimize the identity verification mechanism in the firmware to be tested, so as to obtain an optimized firmware.

[0008] In an embodiment of the present invention, the test instruction includes a bad block identification instruction; the main control unit optimizes the firmware to be tested according to the following steps: Change the bad block information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the bad block identification instruction; After the flash control unit performs a reset operation, identify the bad block information of each physical block in each logical unit in each flash unit; Judge whether each changed bad block information matches the corresponding identified bad block information: When there is at least one changed bad block information that matches the corresponding identified bad block information, perform a reset operation on the flash control unit, restore the bad block table, and optimize the bad block verification mechanism in the firmware to be tested, so as to obtain an optimized firmware.

[0009] In an embodiment of the present invention, the test instruction includes a phase adjustment instruction; the main control unit optimizes the firmware to be tested according to the following steps: Adjust the phases of the data strobe signal and the data bus signal of the flash control unit according to the phase adjustment instruction; After the flash control unit performs a reset operation, adjust the communication protocol of the flash control unit; Under each of the communication protocols, determine whether the flash memory control unit can normally switch between the high-speed mode and the low-speed mode: When the flash memory control unit cannot normally switch between the high-speed mode and the low-speed mode under at least one communication protocol, perform a reset operation on the flash memory control unit to recover the data strobe signal and the data bus signal, and optimize the memory training mechanism in the firmware to be tested to obtain an optimized firmware.

[0010] In an embodiment of the present invention, the test instruction includes an error correction algorithm adjustment instruction; the main control unit optimizes the firmware to be tested according to the following steps: Adjust the error correction algorithm of the memory according to the error correction algorithm adjustment instruction, and change the number of error bits of at least one physical block in at least one logical unit in the flash memory unit in the error statistics table of the firmware to be tested; After the flash memory control unit performs a reset operation, identify the number of error bits of each physical block in each logical unit; Determine whether each changed number of error bits matches the corresponding identified number of error bits: When there is at least one changed number of error bits that matches the corresponding identified number of error bits, perform a reset operation on the flash memory control unit, restore the error correction algorithm and the error statistics table, and optimize the error correction mechanism in the firmware to be tested to obtain an optimized firmware.

[0011] In an embodiment of the present invention, in the same flash memory control unit, when a plurality of flash memory units are configured thereon, the number of logical units included in the flash memory units is the same; the test instruction includes a mapping test instruction; the main control unit optimizes the firmware to be tested according to the following steps: Change the mapping data of at least one flash memory unit and its logical unit in the data mapping table of the firmware to be tested according to the mapping test instruction; After the flash memory control unit performs a reset operation, read the mapping data of the logical unit in the data mapping table to enable the logical unit to perform wear leveling operations and garbage collection operations; Determine whether the logical unit with the changed mapping data normally performs wear leveling operations and garbage collection operations: When there is at least one logical unit with the changed mapping data that cannot perform wear leveling operations and / or garbage collection operations, restore the mapping data in the data mapping table, and optimize the wear leveling mechanism and the garbage collection mechanism in the firmware to be tested to obtain an optimized firmware.

[0012] In an embodiment of the present invention, the memory further includes a voltage adjustment unit for providing a core power supply with different voltage magnitudes; the test instruction includes a voltage regulation instruction; the main control unit optimizes the firmware to be tested according to the following steps: The voltage adjustment unit provides a core power supply with different voltage magnitudes according to the voltage regulation instruction; After the flash control unit performs a reset operation, data of the logic unit is read under each core power supply; Determine whether the flash control unit can normally read the data of the logic unit: When the data of the logic unit cannot be read, adjust the core power supply of the logic unit until the data of the logic unit is normally read, and record the voltage of the core power supply of the logic unit; When the data of the logic unit is normally read, record the voltage of the core power supply of the logic unit; Update the corresponding voltage table according to the voltage of the core power supply of each logic unit recorded to obtain the optimized firmware.

[0013] In an embodiment of the present invention, the memory further includes a timeout test instruction; the main control unit optimizes the firmware to be tested according to the following steps: Change the read / write timeout information of at least one physical block in at least one logic unit in the bad block table of the firmware to be tested according to the timeout test instruction; After the flash control unit performs a reset operation, perform random read / write operations on the physical block; Determine whether the physical block with the changed read / write timeout information can normally perform random read / write operations: When the physical block with the changed read / write timeout information cannot perform random read / write operations, perform a reset operation on the flash control unit to restore the bad block table and optimize the read / write timeout mechanism in the firmware to be tested to obtain the optimized firmware.

[0014] The present invention also discloses a method for optimizing the firmware of a memory, the memory including at least one flash control unit, and the flash control unit configuring at least one flash unit; the firmware optimization method includes: Store the firmware to be tested through the interface flash unit; The trigger control unit generates corresponding test instructions according to preset test items; The main control unit modifies the data in the firmware to be tested according to the test instructions, and controls the flash unit to perform corresponding operations according to the test instructions and the firmware to be tested with the modified data; The main control unit identifies the operation information of the flash memory unit during operation, and optimizes the firmware to be tested according to the operation information to obtain the optimized firmware; The optimized firmware is stored in the read-only storage unit.

[0015] As described above, the present invention provides a memory and its firmware optimization method. Through a systematic firmware testing method (including error correction algorithms, mapping management, voltage regulation, and timeout testing), the processing ability of the firmware is significantly improved, and problems such as insufficient traditional test coverage and poor compatibility are solved. By dynamically simulating abnormal scenarios (such as voltage fluctuations, mapping errors, timeout failures, etc.), potential risks in the firmware processing flow are comprehensively identified, and the stability and adaptability of the firmware are optimized.

[0016] Of course, it is not necessary for any product implementing the present invention to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic diagram of a memory in an embodiment of the present invention; Figure 2 It is a flowchart of a firmware optimization method for a memory in an embodiment of the present invention.

[0019] In the figure: 10, main control unit; 20, flash memory control unit; 30, flash memory unit; 31, logic unit; 40, power supply unit; 50, voltage adjustment unit; 60, trigger control unit; 70, read-only storage unit; 80, random access storage unit; 90, interface flash memory unit; 100, first interface unit; 110, second interface unit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0021] Please refer to Figure 1, this application discloses a memory, which can be an Embedded MultiMedia Card (eMMC) or a Universal Flash Storage (UFS). The memory can communicate with an electronic device through the CMD line and the DATA0~7 lines, and execute operations such as reading, writing, and erasing by receiving instructions from the electronic device. The electronic device can send instructions through the CMD line and transmit data through the DATA0~7 lines. The communication protocol between the memory and the electronic device can follow the JEDEC protocol. The memory can include a main control unit 10, a flash control unit 20, a flash memory unit 30, a power supply unit 40, a voltage adjustment unit 50, a trigger control unit 60, a read-only memory unit 70, a random access memory unit 80, an interface flash memory unit 90, a first interface unit 100, and a second interface unit 110.

[0022] In some embodiments, the main control unit 10 can be a Microcontroller Unit (MCU). The main control unit 10 can be used to execute specific control tasks, such as reading data and processing instructions from the electronic device. The CPU core of the main control unit 10 can be designed based on the RISC-V architecture to execute various control and computing tasks.

[0023] In some embodiments, the number of flash control units 20 (FPGA NAND Flash Controller) can be at least one. The flash control unit 20 can be responsible for managing the operations of the flash memory unit 30. The flash control unit 20 can support multiple models of flash memory units 30. The flash control unit 20 can have 4 independent channels, and each channel can be connected to a flash memory unit 30. A channel refers to the data transmission channel between the flash control unit 20 and the flash memory unit 30, and each channel can operate independently, thereby improving the parallelism and efficiency of data transmission.

[0024] In some embodiments, the flash memory cell 30 refers to a packaged NAND flash memory. Packaging is to encapsulate the logic unit 31 (DIE) and other necessary components (such as pins, heat sinks, etc.) together to form a complete and directly usable flash memory cell 30. A flash memory cell 30 may contain at least one logic unit 31 (DIE), for example, it may include one, two, or four logic units 31. The DIE is the core part of the flash memory cell 30 and is the actual storage medium. The DIE can be composed of a large number of physical blocks. Each DIE can operate independently and perform operations such as reading, writing, and erasing. In a flash memory cell 30, one or more logic units 31 (DIE) share a set of data signals. Multiple DIEs communicate with the outside through the same set of data pins, thereby reducing the number of pins required for packaging and lowering the cost and complexity.

[0025] In some embodiments, for different memories, the number of internal flash memory control units 20 can be different, and the number of flash memory cells 30 configured on each flash memory control unit 20 is also different. However, in the same flash memory control unit 20, when multiple flash memory cells 30 are configured thereon, the number of logic units 31 included in the flash memory cells 30 needs to be the same.

[0026] In some embodiments, when testing and optimizing the firmware of the memory, it is necessary to combine and arrange different numbers of flash memory cells 30 and different numbers of logic units 31 respectively to obtain multiple test modes, and under each test mode, test and optimize the firmware of the memory respectively to verify the compatibility of the firmware. For example, the four channels of the flash memory control unit 20 can be respectively represented as Channel 0~3, the four logic units 31 of the first flash memory cell 30 can be respectively represented as DIE 00~03, the four logic units 31 of the second flash memory cell 30 can be respectively represented as DIE 10~13, the four logic units 31 of the third flash memory cell 30 can be respectively represented as DIE 20~23, and the four logic units 31 of the fourth flash memory cell 30 can be respectively represented as DIE 30~33. Among them, DIE ab can represent the (b + 1)th logic unit on the (a + 1)th channel. At this time, by combining and arranging different numbers of flash memory cells 30 and different numbers of logic units 31, the following multiple test modes can be obtained: The first test mode (Mode 1): DIE 00 is connected to Channel 0, DIE 10 is connected to Channel 1, DIE 20 is connected to Channel 2, and DIE 30 is connected to Channel 3.

[0027] Second Test Mode (Mode 2): DIE 01 is connected to Channel 0, DIE 11 is connected to Channel 1, DIE 21 is connected to Channel 2, and DIE 31 is connected to Channel 3.

[0028] Third Test Mode (Mode 3): DIE 02 is connected to Channel 0, DIE 12 is connected to Channel 1, DIE 22 is connected to Channel 2, and DIE 32 is connected to Channel 3.

[0029] Fourth Test Mode (Mode 4): DIE 03 is connected to Channel 0, DIE 13 is connected to Channel 1, DIE 23 is connected to Channel 2, and DIE 33 is connected to Channel 3.

[0030] Fifth Test Mode (Mode 5): DIE 01 and DIE 03 are connected to Channel 0, DIE 11 and DIE 13 are connected to Channel 1, DIE 21 and DIE 23 are connected to Channel 2, and DIE 31 and DIE 33 are connected to Channel 3.

[0031] Sixth Test Mode (Mode 6): DIE 00 and DIE 01 are connected to Channel 0, DIE 10 and DIE 11 are connected to Channel 1, DIE 20 and DIE 21 are connected to Channel 2, and DIE 30 and DIE 31 are connected to Channel 3.

[0032] Seventh Test Mode (Mode 7): DIE 00 and DIE 02 are connected to Channel 0, DIE 10 and DIE 12 are connected to Channel 1, DIE 20 and DIE 22 are connected to Channel 2, and DIE 30 and DIE 32 are connected to Channel 3.

[0033] Eighth Test Mode (Mode 8): DIE 01 and DIE 02 are connected to Channel 0, DIE 11 and DIE 12 are connected to Channel 1, DIE 21 and DIE 22 are connected to Channel 2, and DIE 31 and DIE 32 are connected to Channel 3.

[0034] Ninth Test Mode (Mode 9): DIE 00, DIE 01, DIE 02, and DIE 03 are connected to Channel 0.

[0035] Tenth Test Mode (Mode 10): DIE 10, DIE 11, DIE 12, and DIE 13 are connected to Channel 1.

[0036] Eleventh Test Mode (Mode 11): DIE 20, DIE 21, DIE 22, and DIE 23 are connected to Channel 2.

[0037] Twelfth Test Mode (Mode 12): DIE 30, DIE 31, DIE 32, and DIE 33 are connected to Channel 3.

[0038] Thirteenth Test Mode (Mode 13): DIE 00, DIE 01, DIE 02, and DIE 03 are connected to Channel 0, and DIE 10, DIE 11, DIE 12, and DIE 13 are connected to Channel 1.

[0039] Fourteenth Test Mode (Mode 11): DIE 20, DIE 21, DIE 22, and DIE 23 are connected to Channel 2, and DIE 30, DIE 31, DIE 32, and DIE 33 are connected to Channel 3.

[0040] Fifteenth Test Mode (Mode 15): DIE 00, DIE 01, DIE 02, and DIE 03 are connected to Channel 0, and DIE 20, DIE 21, DIE 22, and DIE 23 are connected to Channel 2.

[0041] Sixteenth Test Mode (Mode 16): DIE 10, DIE 11, DIE 12, and DIE 13 are connected to Channel 1, and DIE 30, DIE 31, DIE 32, and DIE 33 are connected to Channel 3.

[0042] The Seventeenth Test Mode (Mode 17): DIE 00, DIE 01, DIE 02, and DIE 03 are connected to Channel 0, DIE 10, DIE 11, DIE 12, and DIE 13 are connected to Channel 1, DIE 20, DIE 21, DIE 22, and DIE 23 are connected to Channel 2, and DIE 30, DIE 31, DIE 32, and DIE 33 are connected to Channel 3.

[0043] In some embodiments, for the same flash memory cell 30 (encapsulated NAND flash memory), multiple internal logic units 31 (DIEs) can be of the same model or different models. If the logic units 31 are of different models, the main differences lie in the page size, physical block size, plane, speed, error correction code (ECC), and the voltage of the power supply (VCC / VCCQ). If the logic units 31 are of the same model, the main differences lie in the products after the same model is iterated in different ways.

[0044] In some embodiments, a page is the smallest programmable (writeable) and readable unit in the flash memory cell 30. Different models of DIEs may have different page sizes, such as 4KB, 8KB, or 16KB. The difference in page size affects the read / write efficiency of data, the management method of the controller, and the performance of the memory.

[0045] In some embodiments, a physical block is the smallest erasable unit in the flash memory cell 30 and consists of multiple pages. Different models of DIEs may have different block sizes, such as 256KB, 512KB, or 1MB. The difference in block size affects the efficiency of the erase operation, the lifespan of the memory, and the management strategy of the controller.

[0046] In some embodiments, a plane is a logical partition inside the flash memory cell 30, and each plane can independently perform certain operations (such as reading and writing). Different models of DIEs may have different numbers of planes, such as 1 plane, 2 planes, or 4 planes. The number of planes affects the parallel operation ability of the memory, thus affecting the performance.

[0047] In some embodiments, Speed refers to the read / write speed of the DIE, which is usually expressed in data transfer rate (such as MB / s). Different models of DIEs may have different read / write speeds. The difference in Speed will affect the overall performance of the memory, especially in high-load or multi-task scenarios.

[0048] In some embodiments, ECC (Error Correction Code) is used to detect and correct data errors in the flash memory cells 30. Different models of DIEs may support different ECC strengths, such as 1-bit ECC, 4-bit ECC, or stronger error correction capabilities. The difference in ECC will affect the reliability and data integrity of the memory.

[0049] In some embodiments, VCC is the core working power supply of the DIE, and VCCQ is the interface power supply for the I / O interface. Different models of DIEs may have different VCC / VCCQ voltages, such as 1.8V, 3.3V, or other voltages. The difference in voltage will affect the power consumption, compatibility of the DIE, and the interface design with other components.

[0050] In some embodiments, the power supply unit 40 can be the power management module of the memory, responsible for providing the interface power supply (VCCQ) and the core power supply (VCC). The voltage adjustment unit 50 can be used to dynamically adjust the voltage values of VCCQ and VCC. The voltage adjustment unit 50 can provide VCCQ and VCC with different voltage magnitudes through an internal voltage regulation circuit (such as a DC-DC converter or an LDO voltage regulator). Different models of flash memory cells 30 may require different VCCQ and VCC voltage values. The voltage adjustment unit 50 can be adapted to a variety of flash memory cells 30.

[0051] In some embodiments, the trigger control unit 60 can set corresponding trigger conditions according to different verification purposes and conditions. For example, trigger a test at a specific time point, trigger a test in a specific signal state (such as an error signal, a completion signal), or trigger a test under specific input conditions (such as a specific data pattern, a specific command). The trigger control unit 60 can automatically generate corresponding test instructions according to the preset test items. These test instructions can be used to drive the flash memory control unit 20 to perform specific operations, such as reading data, writing data, erasing a block, and performing ECC verification. By generating test instructions, the trigger control unit 60 can fully cover the compatibility test requirements of the firmware. Among them, the test instructions can include reset instructions, identification instructions, bad block identification instructions, phase adjustment instructions, error correction algorithm adjustment instructions, mapping test instructions, voltage regulation instructions, timeout test instructions, etc. Among them, the test items can also include testing the firmware of the memory through all test instructions in each of the above test modes.

[0052] In some embodiments, the read-only storage unit 70 may be a non-volatile memory (Read-Only Memory, ROM) for storing data in the long term. A program, such as firmware, may be stored in the read-only storage unit 70. The program may be a set of pre-written instructions that guide the main control unit 10 on how to start and operate. These instructions include device initialization, peripheral configuration, and possibly a Bootloader. The Bootloader can be used to load updated programs or operating systems, etc.

[0053] In some embodiments, the random storage unit 80 may be a volatile memory (Random Access Memory, RAM) for temporarily storing data and program code. The random storage unit 80 can be used to temporarily store data. When the main control unit 10 executes a program, the program code can be loaded from the read-only storage unit 70 into the random storage unit 80 for execution.

[0054] In some embodiments, the interface flash unit (SPI Flash) 90 may be a flash unit based on the SPI (Serial Peripheral Interface) interface for storing data. The firmware to be tested refers to that during the development or debugging phase, the firmware may need to be tested and verified multiple times to ensure the correctness of its functions and the compliance of its performance. The interface flash unit 90 can store the firmware to be tested and provide a data source for testing. During the testing process, the firmware to be tested in the interface flash unit 90 can be loaded into the random storage unit 80 to verify its functions. If the firmware to be tested needs to be modified or upgraded, it can be stored and updated through the interface flash unit 90.

[0055] In some embodiments, the first interface unit 100 (Universal Asynchronous Receiver / Transmitter UART) may be an asynchronous serial communication interface for data transmission between devices. The first interface unit 100 can use two signal lines (TX and RX) for full-duplex communication. The first interface unit 100 can be used to implement serial communication between the memory and external devices (such as a PC, a microcontroller).

[0056] In some embodiments, the second interface unit 110 (Universal Serial Bus USB) may be a universal serial bus that supports high-speed data transmission and device connection. The second interface unit 110 can be used to implement high-speed data transmission between the memory and external devices (such as a PC, a smart phone).

[0057] In some embodiments, the main control unit 10 may modify the data in the firmware to be tested according to a test instruction, and control the flash memory unit 30 to perform corresponding operations according to the test instruction and the firmware to be tested after modifying the data. The main control unit 10 is further configured to identify the operation information of the flash memory unit 30 when performing an operation, and optimize the firmware to be tested according to the operation information to obtain an optimized firmware. The read-only storage unit 70 can be used to store the optimized firmware.

[0058] In some embodiments, when the test instruction is a reset instruction, the main control unit 10 may optimize the firmware to be tested according to the following steps: set different reset durations according to the reset instruction; at each reset duration, perform a reset operation on the flash memory control unit 20 respectively, and determine whether the logic unit responds normally: when all logic units 31 can respond normally, retain the reset duration; otherwise, eliminate the reset duration; sort the retained reset durations, and obtain the minimum reset duration, denoted as the target reset time; update the reset time in the firmware configuration table of the firmware to be tested according to the target reset time to obtain an optimized firmware.

[0059] In some embodiments, the reset instruction can be used to perform a reset operation on the flash memory control unit 20 to restore it to its initial state. Through the reset instruction, the response ability of the flash memory control unit 20 under different reset durations can be verified to ensure its reliability and stability. The main control unit 10 can generate a series of different reset durations (such as 1 ms, 2 ms, 5 ms, etc.) according to the reset instruction for testing. At each reset duration, the main control unit 10 can perform a reset operation on the flash memory control unit 20 respectively, and determine whether the logic unit 31 responds normally.

[0060] In some embodiments, the main control unit 10 can sequentially perform a reset operation on the flash memory control unit 20, each time using a set reset duration. After the reset operation is completed, the main control unit 10 checks whether the logic unit 31 of the flash memory control unit 20 responds normally. When a certain logic unit 31 shows a normal response, it means that the logic unit 31 can be correctly initialized and perform subsequent operations. When a certain logic unit 31 shows an abnormal response, it means that the logic unit 31 cannot be correctly initialized or an error occurs.

[0061] In some embodiments, when all logic units 31 can respond normally, retain the reset duration. If all logic units 31 can respond normally at a certain reset duration, then the reset duration is considered valid and retained. If one or some logic units 31 cannot respond normally at a certain reset duration, then the reset duration is considered invalid and eliminated.

[0062] In some embodiments, the main control unit 10 may sort all the reserved reset durations and select the shortest one as the target reset time. The target reset time represents the shortest reset duration for which the flash control unit 20 can respond normally. The main control unit 10 may write the target reset time into the firmware configuration table of the firmware to be tested, updating the reset time parameter. The updated firmware is the optimized firmware, and its reset time is optimized to the shortest valid value, thereby improving the efficiency and performance of the firmware.

[0063] In some embodiments, when the test instruction is an identity recognition instruction, the main control unit 10 may optimize the firmware to be tested according to the following steps: change the identity information of at least one logical unit 31 in the identity configuration table of the firmware to be tested according to the identity recognition instruction; after the flash control unit 20 performs a reset operation, identify the identity information of each logical unit 31; determine whether each changed identity information matches the corresponding identified identity information: when there is at least one changed identity information that matches the corresponding identified identity information, perform a reset operation on the flash control unit 20 to restore the identity configuration table and optimize the identity verification mechanism in the firmware to be tested to obtain the optimized firmware.

[0064] In some embodiments, the identity recognition instruction can be used to verify the identity information of the logical unit 31 of the flash memory unit 30 to ensure that its identity information is consistent with the configuration information. Through the identity recognition instruction, it can be verified whether the identity verification mechanism of the firmware is effective and the identity verification mechanism in the firmware can be optimized.

[0065] In some embodiments, the main control unit 10 may modify the identity information (such as identity ID, check code, etc.) of at least one logical unit 31 in the identity configuration table. The purpose of this step is to simulate the change of the identity information to test the response ability of the identity verification mechanism. The main control unit 10 performs a reset operation on the flash control unit to restore it to the initial state. After the reset is completed, the main control unit 10 reads the identity information of each logical unit 31. The main control unit 10 compares the changed identity information in the identity configuration table with the read identity information. When they match, it can be indicated that the changed identity information is consistent with the identified identity information. When they do not match, it can be indicated that the changed identity information is inconsistent with the identified identity information.

[0066] In some embodiments, if the changed identity information of at least one logic unit 31 matches the identified identity information, it indicates that there is a problem with the identity verification mechanism. The main control unit 10 performs a reset operation on the flash control unit to restore the identity configuration table to its original state. The main control unit 10 optimizes the identity verification mechanism in the firmware to be tested according to the test results. The optimization may include improving the accuracy of identity verification, increasing protection measures for identity information, optimizing the identity verification algorithm, etc. After the optimization is completed, the optimized firmware can be generated.

[0067] In some embodiments, when the test instruction is a bad block identification instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: change the bad block information of at least one physical block in at least one logic unit in the bad block table of the firmware to be tested according to the bad block identification instruction; after the flash control unit performs a reset operation, identify the bad block information of each physical block in each logic unit; determine whether each changed bad block information matches the corresponding identified bad block information: when there is at least one changed bad block information that matches the corresponding identified bad block information, perform a reset operation on the flash control unit to restore the bad block table and optimize the bad block verification mechanism in the firmware to be tested to obtain the optimized firmware.

[0068] In some embodiments, the bad block identification instruction can be used to verify the bad block information of the physical blocks in the logic unit 31 of the flash memory unit 30 to ensure the effectiveness of the bad block management mechanism. Through the bad block identification instruction, verify whether the bad block verification mechanism is accurate and optimize the bad block management function in the firmware.

[0069] In some embodiments, the main control unit 10 can modify the bad block mark of the physical blocks in at least one logic unit 31 in the bad block table (such as marking a normal block as a bad block or vice versa). The purpose of this step is to simulate the change of bad block information and test the fault tolerance and recovery ability of the bad block management mechanism. The main control unit 10 performs a reset operation on the flash control unit 20 to trigger the reloading of the bad block information. After the reset is completed, the main control unit 10 rescans all physical blocks to obtain the actual bad block status information.

[0070] In some embodiments, the main control unit 10 compares the modified bad block mark in the bad block table with the actual bad block status scanned: a match indicates that the modified bad block mark is consistent with the actual status (for example: the physical block marked as a bad block is indeed unavailable). A mismatch indicates that the modified bad block mark is contradictory to the actual status (for example: the physical block marked as a bad block is actually available).

[0071] In some embodiments, when there is at least one changed bad block information that matches the corresponding identified bad block information, a reset operation is performed on the flash control unit 20 to restore the bad block table to its original state (undoing the modifications during testing). Subsequently, the bad block verification mechanism in the firmware is optimized according to the matching results. For example, the accuracy of the bad block detection algorithm is improved, the fault tolerance processing ability of the bad block table is enhanced, the update strategy of the bad block marking is optimized, etc. Finally, the optimized firmware is generated to ensure more reliable bad block management.

[0072] In some embodiments, when the test instruction is a phase adjustment instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: adjust the phase of the data strobe signal and the data bus signal of the flash control unit according to the phase adjustment instruction; after the flash control unit performs a reset operation, adjust the communication protocol of the flash control unit; under each communication protocol, determine whether the flash control unit can normally switch between the high-speed mode and the low-speed mode: when the flash control unit cannot normally switch between the high-speed mode and the low-speed mode under at least one communication protocol, perform a reset operation on the flash control unit to restore the data strobe signal and the data bus signal, and optimize the memory training mechanism in the firmware to be tested to obtain the optimized firmware.

[0073] In some embodiments, the phase adjustment instruction can be used to optimize the phase relationship between the data strobe signal (DQS) and the data bus signal (DQ) of the flash control unit to ensure the timing stability of the flash interface of the flash control unit 20 in different operating modes and improve the data transmission reliability.

[0074] In some embodiments, the main control unit 10 can adjust the sampling phase of the data strobe signal and the transmission phase of the data bus signal according to the phase adjustment instruction to find the optimal phase relationship and ensure the stability of the signal during the high-low speed mode switch. After performing the reset operation, the main control unit 10 can reconfigure the communication protocol parameters of the flash control unit 20 and adjust settings such as timing parameters and drive strength.

[0075] In some embodiments, the main control unit 10 needs to test under each protocol configuration: the switch from the high-speed mode to the low-speed mode, the switch from the low-speed mode to the high-speed mode, and check whether the data transmission is complete, whether the timing meets the requirements, and whether there are signal integrity problems during the switching process.

[0076] In some embodiments, when the main control unit 10 finds an abnormal switch, it needs to perform a reset operation to restore the original signal phase, analyze the failure reason (such as insufficient setup / hold time, etc.), and at the same time optimize the memory training mechanism in the firmware. For example, the memory training mechanism in the firmware can be optimized from aspects such as improving the phase calibration algorithm, optimizing the mode switch timing, and enhancing the error detection mechanism, and the optimized firmware is obtained.

[0077] In some embodiments, when the test instruction is an error correction algorithm adjustment instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: adjust the error correction algorithm of the memory according to the error correction algorithm adjustment instruction, and change the number of error bits of at least one physical block in at least one logical unit in the error statistics table of the firmware to be tested; after the flash control unit executes a reset operation, identify the number of error bits of each physical block in each logical unit; determine whether each changed number of error bits matches the corresponding identified number of error bits: when there is at least one changed number of error bits that matches the corresponding identified number of error bits, execute a reset operation on the flash control unit to restore the error correction algorithm and the error statistics table, and optimize the error correction mechanism in the firmware to be tested to obtain the optimized firmware.

[0078] In some embodiments, the error correction algorithm adjustment instruction can be used to verify and optimize the error correction code (ECC) algorithm to evaluate the effectiveness of the current error correction mechanism and optimize the error detection and correction capabilities. The main control unit 10 can adjust the parameters of the currently used ECC algorithm (such as the error correction ability of the BCH code or the number of iterations of the LDPC code), and artificially modify the number of error bits of specific physical blocks in the error statistics table to simulate different error scenarios and test the adaptability of the error correction mechanism.

[0079] In some embodiments, after the flash control unit 20 executes a reset, it is necessary to rescan all physical blocks and use the adjusted ECC algorithm to count the actual number of error bits, and record it in the error statistics table at the same time. Subsequently, two sets of data can be compared: the artificially modified number of error bits (expected value) and the actually detected number of error bits (measured value).

[0080] In some embodiments, when there is at least one changed number of error bits that matches the corresponding identified number of error bits, it can be considered that the algorithm has misjudgment or missed judgment. At this time, a reset can be executed to restore the original ECC algorithm. Subsequently, the error handling mechanism of the firmware can be optimized, such as optimizing the error handling mechanism in the firmware from aspects such as improving the error detection threshold, optimizing the ECC algorithm selection strategy, enhancing the error prediction mechanism, and adjusting the read retry strategy, and the optimized firmware can be obtained.

[0081] In some embodiments, when the test instruction is a mapping test instruction, the main control unit 10 may optimize the firmware to be tested according to the following steps: change the mapping data of at least one flash memory cell and its logical unit in the data mapping table of the firmware to be tested according to the mapping test instruction; after the flash memory control unit performs a reset operation, read the mapping data of the logical unit in the data mapping table to enable the logical unit to perform wear leveling operation and garbage collection operation; determine whether the logical unit with the changed mapping data normally performs wear leveling operation and garbage collection operation: when there is at least one logical unit with the changed mapping data that cannot perform wear leveling operation and / or garbage collection operation, restore the mapping data in the data mapping table, and optimize the wear leveling mechanism and garbage collection mechanism in the firmware to be tested to obtain the optimized firmware.

[0082] In some embodiments, the mapping test instruction can be used to verify the effectiveness of the logical-physical address mapping mechanism of the firmware to evaluate the reliability of the two core functions of wear leveling and garbage collection.

[0083] In some embodiments, the main control unit 10 can artificially modify the mapping relationship from a specific logical block (LUN) to a physical block in the data mapping table (Flash Translation Layer, FLT) to simulate a test scenario. The test scenario can include simulating block mapping in extreme wear conditions, creating a severely fragmented mapping state, and setting atypical address mapping relationships.

[0084] In some embodiments, after the flash memory control unit 20 performs a reset, the main control unit 10 reloads the mapping table and automatically triggers a background processing flow, including wear leveling and garbage collection. Wear leveling refers to reallocating high-usage blocks. Garbage collection refers to reclaiming blocks occupied by invalid data. Subsequently, the main control unit 10 can monitor system behavior, including whether data migration is successfully executed, whether high-wear blocks are correctly identified, whether invalid data space is effectively reclaimed, and whether data consistency is maintained, to verify whether the mapping table update is correct, whether the bad block marking is accurate, and whether the spare block is used reasonably.

[0085] In some embodiments, when there is at least one logical unit with the changed mapping data that cannot perform wear leveling operation and / or garbage collection operation, the original mapping table data can be restored, and the failure reasons can be deeply analyzed, including defects in the wear leveling algorithm, unreasonable GC trigger conditions, resource allocation strategy problems, etc. Subsequently, the wear leveling mechanism and garbage collection mechanism of the firmware can be optimized, for example, optimizing the error handling mechanism in the firmware from aspects such as improving the wear evaluation algorithm, optimizing the GC trigger threshold, enhancing the abnormal mapping processing ability, and improving the background task scheduling efficiency, to obtain the optimized firmware.

[0086] In some embodiments, when the test instruction is a voltage regulation instruction, the main control unit 10 can optimize the firmware to be tested according to the following steps: The voltage adjustment unit provides core power supplies with different voltage magnitudes according to the voltage regulation instruction; after the flash control unit performs a reset operation, the data of the logic unit is read under each core power supply; it is determined whether the flash control unit can read the data of the logic unit normally: when the data of the logic unit cannot be read, the core power supply of the logic unit is adjusted until the data of the logic unit is read normally, and the voltage of the core power supply of the logic unit is recorded; when the data of the logic unit is read normally, the voltage of the core power supply of the logic unit is recorded; the voltage table of the corresponding firmware to be tested is updated according to the recorded voltage of the core power supply of each logic unit to obtain the optimized firmware.

[0087] In some embodiments, the voltage regulation instruction can be used to dynamically adjust the voltage of the core power supply of the flash unit 30 to optimize the read / write stability and power consumption. Through this test, the operating stability of each logic unit 31 at different voltages can be determined, and an optimal voltage table (Voltage Table) can be established to achieve adaptive voltage regulation to improve the data reliability of the flash under different environments (temperature, aging degree).

[0088] In some embodiments, the voltage adjustment unit provides voltages of core power supplies with different magnitudes according to the instruction (such as 1.8V, 2.5V, 3.3V, etc.). By simulating the influence of voltage fluctuations on the flash unit 30, the data readability of the logic unit 31 under low voltage / high voltage is tested.

[0089] In some embodiments, after the flash control unit 20 performs a reset (to ensure that the voltage setting takes effect), the data of the logic unit 31 is attempted to be read at each voltage level, and the data integrity (whether the ECC check passes) is checked, and the success / failure status of the read is recorded at the same time.

[0090] In some embodiments, the main control unit 10 can judge the read result and adjust the voltage. For example, if the data of a certain logic unit cannot be read (failed), the voltage can be adjusted step by step (increased or decreased) until the data can be read normally (the lowest feasible voltage is found), and the optimal voltage value of the logic unit is recorded. When the data of a certain logic unit is read normally, the current voltage value is directly recorded.

[0091] In some embodiments, the main control unit 10 may update the voltage table according to the test results and record the optimal operating voltage of each logic unit 31. Subsequently, the firmware may also be optimized, for example, from aspects such as adaptive voltage scaling (AVS), low-power optimization, and error recovery mechanisms, to obtain the optimized firmware. Among them, adaptive voltage scaling (AVS) refers to dynamically adjusting the voltage according to the environment or aging degree. Low-power optimization refers to using the lowest feasible voltage while ensuring stability. The error recovery mechanism refers to the backup strategy (such as retry, error correction) when the voltage adjustment fails.

[0092] In some embodiments, when the test instruction is a timeout test instruction, the main control unit 10 may optimize the firmware to be tested according to the following steps: change the read / write timeout information of at least one physical block in at least one logic unit in the bad block table of the firmware to be tested according to the timeout test instruction; after the flash control unit performs a reset operation, perform random read / write operations on the physical block; determine whether the physical block with the changed read / write timeout information can normally perform random read / write operations: when the physical block with the changed read / write timeout information cannot perform random read / write operations, perform a reset operation on the flash control unit to restore the bad block table and optimize the read / write timeout mechanism in the firmware to be tested, so as to obtain the optimized firmware.

[0093] In some embodiments, the timeout test instruction can be used to verify whether the read / write timeout mechanism of the flash memory unit is effective. Through this test, the processing ability of the bad block management (BBM) for abnormal timeout blocks can be detected to optimize the read / write timeout strategy of the firmware and improve data reliability.

[0094] In some embodiments, the main control unit 10 may artificially modify the read / write timeout information of some physical blocks in the bad block table (BBT). For example, set the timeout time of a normal block to be extremely short (simulating timeout failure), or set the timeout time of a bad block to be normal (testing the recovery mechanism).

[0095] In some embodiments, after the flash control unit 20 performs a reset (to ensure that the update of the bad block table takes effect), random read / write operations (Read / Write) may be performed on the target physical block to check whether the read / write fails due to the timeout setting. The target physical block refers to the physical block with the modified read / write timeout information described above.

[0096] In some embodiments, when the target physical block fails to complete read / write (triggered by timeout), it indicates that the timeout setting of the bad block table affects normal operation. At this time, the original data of the bad block table needs to be restored, and the timeout detection mechanism of the firmware needs to be optimized (such as adjusting the timeout threshold). Subsequently, the read / write timeout mechanism of the firmware can be optimized from aspects such as dynamic timeout adjustment, intelligent bad block marking, and error recovery strategy, and the optimized firmware can be obtained. Among them, dynamic timeout adjustment refers to adjusting the timeout threshold according to the state of the physical block (such as wear level). Intelligent bad block marking refers to avoiding misjudging normal blocks as bad blocks. The error recovery strategy refers to the automatic retry or data recovery mechanism after timeout.

[0097] It can be seen that in the above solution, through a systematic firmware testing method (including error correction algorithms, mapping management, voltage regulation, and timeout testing), the processing ability of the firmware is significantly improved, and problems such as insufficient traditional test coverage and poor compatibility are solved. By dynamically simulating abnormal scenarios (such as voltage fluctuations, mapping errors, timeout failures, etc.), potential risks in the firmware processing flow are comprehensively identified, and the stability and adaptability of the firmware are optimized.

[0098] Please refer to Figure 2 , the present invention also provides a method for optimizing the firmware of a memory. This firmware optimization method can be applied to the above-mentioned memory. The firmware optimization method includes: Step S10: Store the firmware to be tested through the interface flash unit; Step S20: The trigger control unit generates corresponding test instructions according to the preset test items; Step S30: The main control unit modifies the data in the firmware to be tested according to the test instructions, and controls the flash unit to execute corresponding operations according to the test instructions and the firmware to be tested with modified data; Step S40: The main control unit identifies the operation information of the flash unit during the execution of the operation, and optimizes the firmware to be tested according to the operation information to obtain the optimized firmware; Step S50: Store the optimized firmware through the read-only storage unit.

[0099] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. This specification selects and specifically describes these embodiments to better explain the principle and practical application of the present invention, so that those skilled in the art in the relevant technical field can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that: include: at least one flash memory control unit, on which at least one flash memory unit is configured; An interface flash memory unit for storing the firmware to be tested; A trigger control unit, used to generate corresponding test instructions according to preset test items; A main control unit, used to modify data in the firmware to be tested according to the test instruction, and control the flash memory unit to perform corresponding operations according to the test instruction and the firmware to be tested after the modified data; the main control unit is also used to identify operation information of the flash memory unit when performing the operation, and optimize the firmware to be tested according to the operation information to obtain the optimized firmware; The read-only storage unit is used to store the optimized firmware.

2. The memory according to claim 1, characterized in that: The test instruction includes a reset instruction; the main control unit optimizes the firmware to be tested according to the following steps: Setting different reset durations according to the reset instruction; At each of the reset durations, a reset operation is performed on the flash memory control unit, and it is determined whether the logic unit in the flash memory unit responds normally: When all logic units can respond normally, the reset duration is retained; Otherwise, remove the reset duration; Sort the reserved reset durations and obtain the minimum reset duration, which is expressed as the target reset time; The reset time of the firmware configuration table of the firmware to be tested is updated according to the target reset time to obtain the optimized firmware.

3. The memory according to claim 1, characterized in that: The test instruction includes an identity recognition instruction; the main control unit optimizes the firmware to be tested according to the following steps: Changing the identity information of at least one logical unit in the identity configuration table of the firmware to be tested according to the identity identification instruction; After the flash memory control unit performs a reset operation, identifying identity information of each of the logic units; Determine whether each changed identity information matches the corresponding identified identity information: When there is at least one changed identity information that matches the corresponding recognized identity information, a reset operation is performed on the flash memory control unit, the identity configuration table is restored, and the identity verification mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

4. The memory according to claim 1, characterized in that: The test instruction includes a bad block identification instruction; the main control unit optimizes the firmware to be tested according to the following steps: Modify the bad block information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the bad block identification instruction; After the flash memory control unit performs a reset operation, identifying bad block information of each physical block in each logical unit in each of the flash memory units; Determine whether each changed bad block information matches the corresponding identified bad block information: When there is at least one modified bad block information that matches the corresponding identified bad block information, a reset operation is performed on the flash memory control unit, the bad block table is restored, and the bad block check mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

5. The memory according to claim 1, characterized in that: The test instruction includes a phase adjustment instruction; the main control unit optimizes the firmware to be tested according to the following steps: adjusting the phase of the data strobe signal and the data bus signal of the flash memory control unit according to the phase adjustment instruction; After the flash memory control unit performs a reset operation, adjusting a communication protocol of the flash memory control unit; Under each of the communication protocols, determining whether the flash memory control unit switches normally between the high-speed mode and the low-speed mode: When the flash memory control unit cannot normally switch between the high-speed mode and the low-speed mode under at least one communication protocol, a reset operation is performed on the flash memory control unit to restore the data selection signal and the data bus signal, and the memory training mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

6. The memory according to claim 1, characterized in that: The test instruction includes an error correction algorithm adjustment instruction; the main control unit optimizes the firmware to be tested according to the following steps: adjusting the error correction algorithm of the memory according to the error correction algorithm adjustment instruction, and changing the number of error bits of at least one physical block in at least one logical unit in the flash memory unit in the error statistics table of the firmware to be tested; After the flash memory control unit performs a reset operation, identifying the number of error bits of each physical block in each of the logical units; Determine whether each modified error bit number matches the corresponding identified error bit number: When there is at least one changed error bit number that matches the corresponding identified error bit number, a reset operation is performed on the flash memory control unit, the error correction algorithm and the error statistics table are restored, and the error correction mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

7. The memory according to claim 1, characterized in that: In the same flash memory control unit, when multiple flash memory units are configured thereon, the flash memory units include the same number of logic units; the test instruction includes a mapping test instruction; the main control unit optimizes the firmware to be tested according to the following steps: Modify mapping data of at least one flash memory unit and its logic unit in the data mapping table of the firmware to be tested according to the mapping test instruction; After the flash memory control unit performs a reset operation, mapping data of the logic unit in the data mapping table is read so that the logic unit performs a wear leveling operation and a garbage collection operation; Determine whether the logical unit whose mapping data is changed performs wear leveling and garbage collection operations normally: When there is at least one logic unit whose mapping data is changed and cannot perform wear leveling operation and / or garbage collection operation, the mapping data in the data mapping table is restored, and the wear leveling mechanism and garbage collection mechanism in the firmware to be tested are optimized to obtain optimized firmware.

8. The memory according to claim 1, characterized in that: The memory further includes a voltage adjustment unit, and the voltage adjustment unit is used to provide a core power supply with different voltages; the test instruction includes a voltage adjustment instruction; and the main control unit optimizes the firmware to be tested according to the following steps: The voltage adjustment unit provides core power supply with different voltages according to the voltage adjustment instruction; After the flash memory control unit performs a reset operation, reading data of the logic unit under each of the core power supplies; Determine whether the flash memory control unit reads the data of the logic unit normally: When the data of the logic unit cannot be read, adjusting the core power supply of the logic unit until the data of the logic unit can be read normally, and recording the voltage of the core power supply of the logic unit; When the data of the logic unit is read normally, recording the voltage of the core power supply of the logic unit; The corresponding voltage table is updated according to the recorded voltage of the core power supply of each of the logic units to obtain optimized firmware.

9. The memory according to claim 1, characterized in that: The memory also includes a timeout test instruction; the main control unit optimizes the firmware to be tested according to the following steps: Modify the read and write timeout information of at least one physical block in at least one logical unit in the bad block table of the firmware to be tested according to the timeout test instruction; After the flash memory control unit performs a reset operation, performing a random read and write operation on the physical block; Determine whether the physical block with the changed read / write timeout information can perform random read / write operations normally: When the physical block whose read / write timeout information is changed cannot perform random read / write operations, a reset operation is performed on the flash memory control unit to restore the bad block table, and the read / write timeout mechanism in the firmware to be tested is optimized to obtain the optimized firmware.

10. A method for optimizing memory firmware, characterized in that: The memory includes at least one flash memory control unit, and the flash memory control unit is configured with at least one flash memory unit; the firmware optimization method includes: storing the firmware to be tested via the interface flash memory unit; The trigger control unit generates corresponding test instructions according to the preset test items; The main control unit modifies the data in the firmware to be tested according to the test instruction, and controls the flash memory unit to perform corresponding operations according to the test instruction and the firmware to be tested after the modified data; Identifying, by the main control unit, operation information of the flash memory unit when performing an operation, and optimizing the firmware to be tested according to the operation information to obtain an optimized firmware; The optimized firmware is stored in a read-only storage unit.

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