Pixel circuit and display panel

Abstract

This application discloses a pixel circuit and display panel. The pixel circuit includes: a scanning control module for writing data signals; a data storage module connected between the scanning control module and a power supply for storing the data signals; and a light-emitting module for driving light-emitting elements based on power flowing through the data storage module. The data storage module includes a resistive memory whose impedance is controlled by the voltage difference between the data signal and the power supply, so that the power flowing through the data storage module has a voltage loss corresponding to the data signal. The pixel circuit uses the resistive memory to store data signals, eliminating capacitors and some switching transistors, significantly reducing the pixel circuit's footprint and effectively increasing the pixel density of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a pixel circuit and a display panel. Background Art

[0002] With the development of display technology, display panels have become an indispensable part of electronic devices and are widely used in various electronic devices such as televisions, computers, mobile phones, tablets, e-readers, game consoles, automobiles, home appliances, medical equipment, etc.

[0003] Pixel circuits are key components of display panels. They consist of a series of tiny electronic components (such as transistors) that control the color and brightness of each pixel in the display panel. With technological advancements and rising consumer demand, the performance requirements for display panels are also becoming increasingly demanding. Pixel density (PPI) is a key metric for measuring display panel clarity. PPI refers to the number of pixels per inch (pixels per inch). A higher PPI results in a more detailed image, richer colors, and better visual quality. However, in some electronic devices, due to size limitations, display panels require a very high PPI to meet display requirements. Current display panels still lack the PPI required for high-PPI display applications.

[0004] Therefore, it is desired to provide an improved pixel circuit and display panel to solve the above problems. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a pixel circuit and a display panel to reduce the occupied area of the pixel circuit and improve the pixel density of the display panel.

[0006] According to one aspect of the present invention, there is provided a pixel circuit, comprising:

[0007] A scanning control module, used for writing data signals;

[0008] A data storage module, connected between the scanning control module and the power supply, and configured to store the data signal; and

[0009] a light emitting module that drives a light emitting element based on the power flowing through the data storage module,

[0010] The data storage module includes a resistive memory, the impedance of which is controlled by a voltage difference between the data signal and the power supply, so that the power supply has a voltage loss corresponding to the data signal after passing through the data storage module.

[0011] Optionally, when the data signal is valid, the resistive memory is in a low-resistance state, and the power supply drives the light-emitting element to emit light; when the data signal is invalid, the resistive memory is in a high-resistance state, and the power supply drives the light-emitting element to stop emitting light.

[0012] Optionally, the voltage of the power supply is lower than a high level of the data signal and higher than a low level of the data signal.

[0013] Optionally, the scanning control module includes a first switching tube, a first current end of the first switching tube receives the data signal, a second current end is connected to the second end of the resistive memory, a control end receives a scanning signal, a first end of the resistive memory is connected to the power supply, and the light-emitting module includes the light-emitting element, a first end of the light-emitting element is connected to the second end of the resistive memory, and a second end receives a common voltage.

[0014] When the scan signal is valid, the data signal is written into the resistive memory, and when the scan signal is invalid, the power source drives the light-emitting element through the resistive memory.

[0015] Optionally, the light-emitting module further includes a current source, which is connected between the resistive memory and the light-emitting element, or the current source is connected between the power supply and the resistive memory. When the scan signal is invalid, the current source limits the resistive memory bias to a value less than the write voltage of the resistive memory.

[0016] Optionally, the scanning control module includes a selector, a first end of the selector receives the data signal, a second end of the selector is connected to the second end of the resistive memory, the first end of the resistive memory receives the scanning signal, the light emitting module includes the light emitting element, a first end of the light emitting element is connected to the second end of the resistive memory, and the second end receives the common voltage.

[0017] When the absolute value of the voltage difference between the first terminal and the second terminal of the selector is greater than / equal to the threshold voltage, the selector is turned on.

[0018] When the scanning signal is valid, the data signal is written into the resistive memory, and when the scanning signal is invalid, the power source drives the light-emitting element through the resistive memory.

[0019] The scanning signal is in an effective state when it is at a first level, and is in an ineffective state when it is at a second level. The second level of the scanning signal serves as the power supply.

[0020] Optionally, the data signal is in a valid state when it is at a high level, and is in an invalid state when it is at a low level. The initial state of the resistive memory is a high-resistance state, and the voltage difference between the high level of the data signal and the threshold voltage is greater than the first level of the scan signal.

[0021] Optionally, the light-emitting module further includes a current source, which is connected between the resistive memory and the light-emitting element, or the current source is connected between the power supply and the resistive memory. When the scan signal is invalid, the current source limits the bias voltage of the resistive memory to a value less than the write voltage of the resistive memory, and makes the low level of the data signal greater than the difference between the voltage value of the second end of the resistive memory and the threshold voltage, and the difference between the high level of the data signal and the threshold voltage is less than the voltage value of the second end of the resistive memory.

[0022] Optionally, the light emitting module further includes a third switch tube, a first current terminal of the third switch tube is connected to the first terminal of the light emitting element, a second current terminal is connected to a reference ground, and a control terminal receives a reset signal.

[0023] Optionally, the light emitting module further includes a fourth switch tube, a first current end of the fourth switch tube is connected to the second end of the resistive memory, a second current end is connected to the first end of the light emitting element, and a control end receives a control signal.

[0024] Optionally, the resistive memory is formed above or below the first switch tube, the current source, the third switch tube and / or the fourth switch tube.

[0025] According to a second aspect of the present invention, a display panel is provided, comprising the pixel circuit described above.

[0026] The pixel circuit and display panel provided by the present invention utilize resistive memory in pixel circuits through an innovative combination of circuit design, semiconductor devices, and processes. This eliminates the capacitors in traditional pixel circuits, significantly reduces the area occupied by the pixel circuits, and effectively increases the pixel density of the display panel, thereby realizing a compact, reliable, and low-cost high-pixel-density (Pixel Per Inch, PPI) display panel.

[0027] In some optional embodiments, the pixel circuit includes only three switching tubes. If the problem of resetting the light-emitting element is ignored, the pixel circuit includes only two switching tubes. The pixel circuit has low requirements on the number of switching tubes, which can further reduce the area of the pixel circuit and improve the pixel density of the display panel.

[0028] In some optional embodiments, a selector is used to write data, and the number of switching tubes included in the pixel circuit is only two. If the problem of resetting the light-emitting element is ignored, the number of switching tubes included in the pixel circuit is only one. The pixel circuit's requirement on the number of switching tubes is further reduced, which can further reduce the area of the pixel circuit and improve the pixel density of the display panel.

[0029] In some optional embodiments, both the resistive memory and the selector can be fabricated above each switch transistor as a back-end of line (BEOL) process, eliminating the need for pixel circuit floor space. This allows for high PPI and high reliability. Practice has proven that this pixel circuit can be fabricated down to a size of 20nm or less. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0031] Figure 1 shows a block diagram of a pixel circuit according to an embodiment of the present invention;

[0032] Figure 2 shows a structural diagram of a resistive memory according to an embodiment of the present invention;

[0033] Figure 3 shows a circuit diagram of a pixel circuit according to a first embodiment of the present invention;

[0034] Figure 4 shows a circuit diagram of a pixel circuit according to a second embodiment of the present invention;

[0035] Figure 5 A circuit diagram of a pixel circuit according to a third embodiment of the present invention is shown. DETAILED DESCRIPTION

[0036] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0037] Many specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without these specific details.

[0038] It should be understood that the connection / coupling of A and B in the embodiment of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiment of the present application is not limited to this.

[0039] In one traditional pixel circuit, dynamic random access memory (DRAM) is used to store data. Each bit of data is stored in a separate capacitor. The capacitor and the connected transistor together form a memory cell. The capacitor stores charge, while the transistor acts as a switch to control the reading and storing of the charge. In this technical solution, capacitors are used to directly store the data signal DATA. However, these capacitors are typically large, which is not conducive to reducing the pixel circuit's footprint. Moreover, the data stored in the capacitor is significantly affected by the capacitor's capacitance and the leakage current of the switch transistor, resulting in low reliability. In another traditional pixel circuit, static random access memory (SRAM) is used to store data, using a bistable bipolar flip-flop (Bistable Latching Circuitry) to store each bit of data. The main disadvantage of SRAM is that it requires six transistors to store each bit of data, which makes SRAM's storage density lower than DRAM and is even more difficult to reduce the pixel circuit's footprint.

[0040] In an embodiment of the present invention, the state of a resistive memory is changed by utilizing the voltage difference between a data signal and a power supply, and a light-emitting element is driven accordingly based on the state of the resistive memory. The resistive memory has a very small feature size, achieving a good compromise in terms of speed, area, number of write cycles, and power consumption. Furthermore, the resistive memory can eliminate the capacitor elements required by conventional technologies, achieving display driving with a small number of switching transistors, significantly reducing the area occupied by the pixel circuit and effectively improving the pixel density (PPI) of the display panel.

[0041] In the following embodiments, a pixel circuit is described in detail using an organic light-emitting diode (OLED) as an example of a light-emitting element. It should be understood that, in actual operation, those skilled in the art may replace the organic light-emitting diode light-emitting element in the pixel circuit with other types of light-emitting elements, such as a light-emitting diode (LED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro-LED), a mini light-emitting diode (Mini-LED), an organic laser diode (OLD), etc.

[0042] The following describes embodiments of the pixel circuit and display panel provided in the present application in conjunction with the accompanying drawings.

[0043] Figure 1 FIG. 4 is a block diagram of a pixel circuit according to an embodiment of the present invention.

[0044] like Figure 1 As shown, the pixel circuit 100 includes a scan control module 110, a data storage module 120 and a light emitting module 130. The pixel circuit 100 drives the light emitting element OLED in the light emitting module 130 to emit light according to at least a data signal DATA, a scan signal SCAN and a reference signal Vref.

[0045] The scan control module 110 is used to write the data signal DATA. The scan control module 110 is controlled by the scan signal SCAN. For example, when the scan signal SCAN is valid, that is, during the scan phase, the scan control module 110 conducts the current path from the data signal DATA to the data storage module 120, so that the data signal DATA is written to the data storage module 120. When the scan signal SCAN is invalid, that is, during the light-emitting phase, the scan control module 110 closes the current path from the data signal DATA to the data storage module 120.

[0046] The data storage module 120 is used to store the data signal DATA. In an embodiment of the present invention, the data storage module 120 includes a resistive memory ReRAM, which is a non-volatile memory based on the reversible conversion of the resistance of a non-conductive material between a high resistance state and a low resistance state under the action of an external electric field. The first end of the resistive memory ReRAM is connected to the power supply AVDD, and the second end is connected to the scanning control module 110 and the light-emitting module 130 respectively. In the scanning phase, the data signal DATA is written into the data storage module 120 through the scanning control module 110; in the light-emitting phase, the power supply AVDD flows through the data storage module 120 to drive the light-emitting module 130 to emit light. In some embodiments, the power supply AVDD has the same voltage value in the scanning phase and the light-emitting phase. In some other embodiments, the power supply AVDD is a power supply with an adjustable voltage value, which has different voltage values in the scanning phase and the light-emitting phase.

[0047] In an embodiment of the present invention, the data signal DATA is used to adjust the impedance of the resistive memory in the data storage module 120 to achieve the purpose of writing the data signal DATA into the data storage module 120. Therefore, the method of writing data in the present invention is to store the data signal by defining the corresponding relationship between the impedance of the resistive memory and the data signal and adjusting the impedance of the resistive memory using the voltage difference between the data signal and the power supply. This is completely different from the traditional technology of directly storing data signals using capacitors. For example, a data signal DATA with a low level is defined as being in a valid state and a data signal DATA with a high level is defined as being in an invalid state. Then, the voltage of the power supply AVDD is less than the high level of the data signal DATA and greater than the low level of the data signal DATA. Therefore, when the data signal DATA is valid, the resistive memory ReRAM is in a first resistance state (e.g., a low resistance state); when the data signal DATA is in an invalid state, the resistive memory ReRAM is in a second resistance state (e.g., a high resistance state). It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art can modify the definitions of the valid state and invalid state of data and the correspondence between the resistance state of the resistive memory ReRAM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is valid, the resistive memory ReRAM is in the resistance state corresponding to the data "1", and when the data signal DATA is invalid, the resistive memory ReRAM is in the resistance state corresponding to the data "0".

[0048] The light-emitting module 130 includes a current source and a light-emitting element. Power supply AVDD flows through the data storage module 120 and the current source to drive the light-emitting element. The current source can be connected between the power supply and the data storage module 120, or between the data storage module 120 and the light-emitting element. The current source is used to control the current in the pixel circuit, turning it off during the scanning phase and maintaining the current in the pixel circuit during the light-emitting phase to prevent the state of the resistive memory from changing. During the light-emitting phase, the current source limits the resistive memory bias voltage to less than / significantly less than the resistive memory's write voltage. Therefore, once the state of the resistive memory is determined during the scanning phase, it does not change during the light-emitting phase. The current source is controlled by a reference signal Vref, an analog signal that can be used to adjust the current level of the current source. In some embodiments, the reference signal Vref is a signal with a constant voltage value, and all pixel circuits 100 in the display panel can share the same reference signal Vref. In other embodiments, to prevent a low-current current source from being mis-enable during the scanning phase, the voltage value of the reference signal Vref can be adjusted during the scanning phase to directly turn the current source off. For example, a current source is connected between the data storage module 120 and the light-emitting element. During the scanning phase, the reference signal Vref is inactive, shutting off the current path from the data storage module 120 to the light-emitting module 130. During the light-emitting phase, the reference signal Vref is active, conducting the current path from the data storage module 120 to the light-emitting module 130 and limiting the resistive memory bias voltage to less than / far less than the write voltage of the resistive memory, thereby preventing the resistive memory from flipping state. During the light-emitting phase, the power supply AVDD passes through the data storage module 120, resulting in a voltage loss corresponding to the data signal DATA. Therefore, when driving the light-emitting module 130 to emit light, a corresponding voltage loss occurs, causing the light-emitting element OLED to emit light corresponding to the data signal DATA. For example, when the data signal DATA is active, the resistive memory ReRAM is in a low-resistance state, resulting in a low voltage loss for the power supply AVDD passing through the ReRAM, driving the light-emitting element OLED to emit light. When the data signal DATA is inactive, the resistive memory ReRAM is in a high-resistance state, preventing the current from the power supply AVDD from passing through the ReRAM, and thus the light-emitting element OLED stops emitting light.

[0049] In an embodiment of the present invention, during the scanning phase, the scan signal SCAN is active, and the data signal DATA is written to the data storage module 120 via the scan control module 110. The data signal DATA stores data by adjusting the impedance of the resistive RAM (ReRAM). During the light-emitting phase, the scan signal SCAN is inactive, and the power supply AVDD, after flowing through the data storage module 120, experiences a voltage loss corresponding to the data signal DATA. Consequently, when the light-emitting module 130 is driven to emit light, a corresponding voltage loss occurs, causing the light-emitting element OLED to emit light corresponding to the data signal DATA. Therefore, the pixel circuit 100 does not directly utilize the resistive RAM (ReRAM) to store the data signal DATA. Instead, during the scanning phase, the voltage difference between the data signal DATA and the power supply is used to change the state of the ReRAM. During the light-emitting phase, the light-emitting element OLED is driven accordingly based on the state of the ReRAM. By utilizing the ReRAM to store the data signal DATA, the pixel circuit 100 eliminates the switches and capacitors required by conventional technologies, significantly reducing the area occupied by the pixel circuit 100 and effectively increasing the pixel density of the display panel.

[0050] Figure 2 FIG. 4 shows a structural diagram of a resistive memory according to an embodiment of the present invention.

[0051] like Figure 2 As shown, the resistive memory ReRAM includes a conductive layer 11, a dielectric layer 12 and a conductive layer 13 stacked in sequence. The dielectric layer 12 is, for example, a metal oxide dielectric layer. Wires are connected to the two conductive layers 11 and 13 respectively to facilitate data writing and data reading.

[0052] The resistive switching principle of ReRAM is based on the conductive path (generally called conductive filament) in the resistive switching layer of the device. That is, by applying different pulse voltage excitations to the upper and lower electrodes, the dielectric layer undergoes resistive switching, resulting in physical changes.

[0053] The conductive filaments can be in two states in the resistive layer: on or off: a non-volatile low resistance state (LRS) or a high resistance state (HRS), thereby achieving the distinction and storage of the "0" and "1" states.

[0054] There are two ways to form conductive filaments in the dielectric layer. The first is from within the insulating layer, where soft breakdown creates oxygen vacancies in the oxide dielectric, which then form conductive filaments. The second is from outside the electrode layer, where electrical stress is used to introduce active metal ions into the dielectric, forming conductive filaments composed of metal atoms. These two filament formation methods also determine the two mainstream ReRAM technology paths: Oxygen Vacancy-based ReRAM (OxRAM) and Conductive Bridge ReRAM (CBRAM). In OxRAM, the conductive filaments in the resistive layer are formed by oxygen vacancies; in CBRAM, the conductive filaments are composed of metal ions.

[0055] Resistive memory relies on the voltage difference between its two terminals to distinguish whether the data being written is a "0" or a "1." Those skilled in the art can configure the direction of the resistive memory based on actual needs. For example, in the first and third embodiments of the present invention, it is defined that when the bias voltage of the resistive memory is greater than zero (the voltage value at the first terminal is greater than the voltage value at the second terminal), a conductive filament is formed, the resistive memory is in a low-resistance state, and the data written is a "1." Conversely, when the bias voltage of the resistive memory is less than zero (the voltage value at the first terminal is less than the voltage value at the second terminal), the conductive filament is destroyed, the resistive memory is in a high-resistance state, and the data written is a "0." In the second embodiment of the present invention, it is defined that when the bias voltage of the resistive memory is greater than zero (the voltage value at the second terminal is greater than the voltage value at the first terminal), a conductive filament is formed, the resistive memory is in a low-resistance state, and the data written is a "1." Conversely, when the bias voltage of the resistive memory is less than zero (the voltage value at the second terminal is less than the voltage value at the first terminal), the conductive filament is destroyed, the resistive memory is in a high-resistance state, and the data written is a "0." It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art can change the direction of the resistive memory according to actual needs, and accordingly adjust the conduction state of the pixel circuit in the scanning stage, the correspondence between the high and low levels in each stage, and / or the type of the switching tube.

[0056] Figure 3 A circuit diagram of a pixel circuit according to a first embodiment of the present invention is shown.

[0057] like Figure 3 As shown, in the pixel circuit 200 , the scanning control module 210 includes a first switch tube SW1 , the data storage module 220 includes a resistive memory ReRAM, and the light emitting module 230 includes a current source SW2 , a third switch tube SW3 and a light emitting element OLED.

[0058] Specifically, the first current terminal of the first switch SW1 receives the data signal DATA, the second current terminal is connected to the second terminal of the resistive memory ReRAM, and the control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the second terminal of the resistive memory ReRAM, the second current terminal is connected to the first terminal (anode) of the light-emitting element OLED, and the control terminal receives the reference signal Vref. The first current terminal of the third switch SW3 is connected to the first terminal of the light-emitting element OLED, the second current terminal is connected to the reference ground, and the control terminal receives the reset signal RESETB. The second terminal (cathode) of the light-emitting element OLED receives the common voltage Vcom. The first terminal of the resistive memory ReRAM is connected to the power supply AVDD, and the second terminal of the resistive memory ReRAM is connected to the second current terminal of the first switch SW1 and the first current terminal of the current source SW2, respectively. When the scan signal SCAN is valid or invalid, the data signal DATA is written to the resistive memory ReRAM. When the scan signal SCAN is invalid, the power supply AVDD drives the light-emitting element OLED through the resistive memory ReRAM. In some embodiments, the reference signal Vref is active during both the scanning phase and the light-emitting phase to limit the voltage across the resistive memory to less than the write voltage of the resistive memory. In other embodiments, the reference signal Vref is in an invalid state during the scanning phase to turn off the current source SW2, and the reference signal Vref is in an effective state during the light-emitting phase to limit the voltage across the resistive memory to less than the write voltage of the resistive memory.

[0059] In this embodiment, a data signal DATA having a low level is defined as being in a valid state, and a data signal DATA having a high level is defined as being in an invalid state. The voltage of the power supply AVDD is higher than the low level of the data signal DATA and lower than the high level of the data signal DATA. Therefore, when the data signal DATA is valid, the voltage at the first terminal of the resistive memory ReRAM (i.e., the voltage of the power supply AVDD) is higher than the voltage at the second terminal of the resistive memory ReRAM (i.e., the low level of the data signal DATA), the resistive memory ReRAM is in a low-resistance state, and data "1" is written. When the data signal DATA is invalid, the voltage at the first terminal of the resistive memory ReRAM (i.e., the voltage of the power supply AVDD) is lower than the voltage at the second terminal of the resistive memory ReRAM (i.e., the high level of the data signal DATA), the resistive memory ReRAM is in a high-resistance state, and data "0" is written. It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art can adjust the conduction state of the pixel circuit in the scanning stage, the correspondence between the high and low levels in each stage, and / or the type of the switch tube according to the actual needs of the resistive memory, so that when the data signal DATA is valid, the resistive memory ReRAM is in a resistive state corresponding to the data "1", and when the data signal DATA is invalid, the resistive memory ReRAM is in a resistive state corresponding to the data "0".

[0060] During the scanning stage, the scan signal SCAN is valid and the reset signal RESETB is valid. Therefore, the first switching transistor SW1 and the third switching transistor SW3 are turned on. The current source SW2 is turned off during the scanning stage. The reference signal Vref can be in an invalid state or a valid state. When the reference signal Vref is in an invalid state, the current source SW2 is turned off. When the reference signal Vref is in a valid state, the current source SW2 controls the voltage across the resistive memory ReRAM to be much smaller than the write voltage, because it can be considered that the current source SW2 is in an off state. At this time, the first end of the resistive memory ReRAM is connected to the power supply AVDD, the voltage value of the power supply AVDD is V0, the second end of the resistive memory ReRAM receives the data signal DATA, and there is a voltage difference between the first end and the second end of the resistive memory ReRAM, so that the resistive memory ReRAM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid, that is, the voltage on the data line is the low level VdataL, V0 > VdataL, the voltage at the first end of the resistive memory ReRAM (i.e., the voltage value of the power supply AVDD) is higher than the voltage at the second end of the resistive memory ReRAM (i.e., the low level of the data signal DATA), and a conductive filament is formed in the resistive memory ReRAM, which is in a low-resistance state, representing the written data "1"; if the data signal DATA is invalid, that is, the voltage on the data line is the high level VdataH, V0 < VdataH, the voltage at the first end of the resistive memory ReRAM (i.e., the voltage value of the power supply AVDD) is lower than the voltage at the second end of the resistive memory ReRAM (i.e., the high level of the data signal DATA), and the conductive filament in the resistive memory ReRAM is damaged, which is in a high-resistance state, representing the written data "0". The impedance of the resistive memory ReRAM determines whether the light-emitting element OLED can emit light during the light-emitting stage. That is, the data signal DATA is written into the resistive memory ReRAM by adjusting the impedance of the resistive memory ReRAM. During the scanning stage, the resistive memory ReRAM is disconnected from the light-emitting element OLED, and the first end of the light-emitting element OLED is connected to the reference ground to reset the residual charge on the light-emitting element OLED.

[0061] During the light-emitting phase, the scan signal SCAN is inactive and the reset signal RESETB is inactive. Therefore, the first and third switches SW1 and SW3 are off, and the current source SW2 is on. At this point, the resistive memory ReRAM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light-emitting element OLED through the resistive memory ReRAM. Therefore, after the power supply AVDD flows through the resistive memory ReRAM, it experiences a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the resistive memory ReRAM is in a low-impedance state, and the voltage loss of the power supply AVDD after flowing through the resistive memory ReRAM is minimal or almost zero, allowing the light-emitting element OLED to be successfully driven to emit light. If the data signal DATA is invalid, the resistive memory ReRAM is in a high-impedance state, and the voltage loss of the power supply AVDD after flowing through the resistive memory ReRAM is significant, making it impossible to drive the light-emitting element OLED to emit light.

[0062] In addition, if the light-emitting element OLED in the pixel circuit 200 does not have high requirements for anode reset, the problem of the light-emitting element OLED needing to be reset can be ignored, and the third switch tube SW3 can be omitted. Then the number of switch tubes included in the pixel circuit 200 can be only two (the first switch tube SW1 and the current source SW2), and the pixel circuit 200 has low requirements for the number of switch tubes.

[0063] In this embodiment, the first switch SW1 , the current source SW2 and the third switch SW3 may be transistors of types such as bipolar junction transistors (BJTs), field effect transistors (FETs), and insulated gate bipolar transistors (IGBTs).

[0064] As an example, the first switch SW1, the current source SW2, and the third switch SW3 are all P-channel metal oxide semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to a voltage threshold, that is, when its control terminal receives a low-level control signal, the current path from the first current terminal to the second current terminal is conductive. When the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, that is, when its control terminal receives a high-level control signal, the current path from the first current terminal to the second current terminal is disconnected. Therefore, it is defined that the scan signal SCAN, the reference signal Vref, and the reset signal RESETB having a low level are in an active state, while the scan signal SCAN, the reference signal Vref, and the reset signal RESETB having a high level are in an inactive state. It should be understood that the embodiments of the present invention are not limited to this, and those skilled in the art may modify the types of the first switch SW1, the current source SW2, and the third switch SW3, and the specific active and inactive levels of the scan signal SCAN, the reference signal Vref, and the reset signal RESETB according to actual needs.

[0065] In this embodiment, during the light-emitting stage, due to the presence of the current source SW2, the voltage across the resistive memory ReRAM is controlled to be much smaller than the write voltage, thereby not causing the state of the resistive memory to flip, and the state of the resistive memory can be stably maintained during the light-emitting stage.

[0066] Figure 4 A circuit diagram of a pixel circuit according to a second embodiment of the present invention is shown.

[0067] like Figure 4 As shown, in the pixel circuit 300 , the scanning control module 310 includes a selector, the data storage module 320 includes a resistive memory ReRAM, and the light emitting module 330 includes a current source SW2 , a third switch tube SW3 and a light emitting element OLED.

[0068] Specifically, the first terminal of the selector (selector) receives a data signal DATA, and the second terminal is connected to the second terminal of the resistive memory (ReRAM). The first current terminal of the current source SW2 is connected to the second terminal of the resistive memory (ReRAM), the second current terminal is connected to the first terminal (anode) of the light-emitting element (OLED), and the control terminal receives a reference signal (Vref). The first current terminal of the third switch (SW3) is connected to the first terminal of the light-emitting element (OLED), the second current terminal is connected to the reference ground, and the control terminal receives a reset signal (RESETB). The second terminal (cathode) of the light-emitting element (OLED) receives a common voltage (Vcom). The first terminal of the resistive memory (ReRAM) is connected to a scan signal (SCAN), and the second terminal of the resistive memory (ReRAM) is connected to the second terminal of the selector (selector) and the first current terminal of the current source SW2, respectively. When the scan signal (SCAN) is valid, the data signal DATA is written to the resistive memory (ReRAM). When the scan signal (SCAN) is invalid, the high-level scan signal (SCAN) passes through the resistive memory (ReRAM) to drive the light-emitting element (OLED). In some embodiments, the reference signal (Vref) is active during both the scan and light-emitting phases to limit the voltage across the resistive memory (OLED) to less than the write voltage of the resistive memory. In other embodiments, the reference signal Vref is in an invalid state during the scanning phase to turn off the current source SW2, and the reference signal Vref is in an effective state during the light-emitting phase to limit the voltage across the resistive memory to less than the write voltage of the resistive memory.

[0069] In this embodiment, the scan signal SCAN is in an active state when it is at a first level, and in an inactive state when it is at a second level. In the light emitting stage, the high level of the scan signal SCAN is reused as the power supply AVDD.

[0070] In this embodiment, the selector selector is preset with a threshold voltage. When the absolute value of the voltage difference between the first and second terminals of the selector selector is greater than or equal to the threshold voltage, the selector selector is turned on. When the absolute value of the voltage difference between the first and second terminals of the selector selector is less than the threshold voltage, the selector selector is turned off. As an example, the selector selector includes a first diode D1, an anode of the first diode D1 receives the data signal DATA, and a cathode of the first diode D1 is connected to the second terminal of the resistive memory ReRAM.

[0071] Specifically, in this selector, when a forward bias voltage greater than the threshold voltage Vd is applied, the impedance is very low, and the selector is turned on. When the bias voltage is reduced to less than the threshold voltage Vd, the impedance is very high, and the selector is turned off. In some embodiments, the selector can be any combination of traditional diode types such as PN diodes, Schottky diodes, or bipolar junction transistors (BJTs). It can also be an ovonic threshold switch (OTS), which is similar to phase change resistive memory (PCM), but differs in that its molecules do not crystallize. A ovonic threshold switch can be implemented by adding other elements (such as arsenic) to the phase change material to prevent crystallization. Each time the voltage is removed and the temperature drops, it returns to an amorphous state and never reaches a crystalline state. Therefore, it cannot be used as a resistive memory but can be used as a switch.

[0072] In this embodiment, a data signal DATA with a high level is defined as being in an active state, and a data signal DATA with a low level is defined as being in an inactive state. The initial state of the resistive memory ReRAM is a high-impedance state, and the high level of the data signal DATA is greater than a threshold voltage Vd, which is also greater than the first level of the scan signal SCAN. Therefore, when the data signal DATA is active, the selector (selector) is turned on, and the voltage at the first terminal of the resistive memory ReRAM (i.e., the first level of the scan signal SCAN) is lower than the voltage at the second terminal of the resistive memory ReRAM (i.e., the high level VdataH of the data signal DATA). The resistive memory ReRAM is in a low-impedance state, and data "1" is written. When the data signal DATA is inactive, the selector (selector) is turned off, and the resistive memory ReRAM remains in a high-impedance state, and data "0" is written. It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art can change the direction of the resistive memory according to actual needs, and accordingly adjust the conduction state of the pixel circuit in the scanning stage, the correspondence between the high and low levels at each stage, and / or the type of the switch tube, so that when the data signal DATA is valid, the resistive memory ReRAM is in a resistive state corresponding to the data "1", and when the data signal DATA is invalid, the resistive memory ReRAM is in a resistive state corresponding to the data "0".

[0073] During the scan phase, the scan signal SCAN is active, the reference signal Vref is inactive, and the reset signal RESETB is active, so the third switch SW3 is turned on. The current source SW2 is off during the scan phase, and the reference signal Vref can be either inactive or active. When the reference signal Vref is inactive, the current source SW2 is off. When the reference signal Vref is active, the current source SW2 controls the voltage across the resistive memory ReRAM to be significantly lower than the write voltage, as the current source SW2 can be considered to be off. At this point, the first terminal of the resistive memory ReRAM is connected to the scan signal SCAN having a first level, the voltage of the scan signal SCAN being Vp. The second terminal of the resistive memory ReRAM receives the data signal DATA. A voltage difference exists between the first and second terminals of the resistive memory ReRAM, causing the resistive memory ReRAM to have an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid (i.e., the voltage on the data line is high level VdataH), the voltage at the first terminal of the resistive memory ReRAM (i.e., the first level of the scan signal SCAN) is lower than the voltage at the second terminal of the resistive memory ReRAM (i.e., the high level VdataH of the data signal DATA). A conductive filament forms in the resistive memory ReRAM, placing it in a low-resistance state, indicating that data "1" has been written. If the data signal DATA is invalid (i.e., the voltage on the data line is low level VdataL), the selector is in the off state, and the resistive memory ReRAM cannot form a conductive filament, maintaining a high-resistance state, indicating that data "0" has been written. The impedance of the resistive memory ReRAM determines whether the light-emitting element OLED can emit light during the light-emitting phase. In other words, the data signal DATA is written to the resistive memory ReRAM by adjusting the impedance of the resistive memory ReRAM. During the scanning phase, the resistive memory ReRAM is disconnected from the light-emitting element OLED. The first terminal of the light-emitting element OLED is connected to the reference ground to reset any residual charge on the light-emitting element OLED.

[0074] During the light-emitting phase, the scan signal SCAN is inactive, the reference signal Vref is active, and the reset signal RESETB is inactive. Therefore, the third switch SW3 is off and the current source SW2 is on. At this time, the resistive memory ReRAM has an impedance corresponding to the data signal DATA, and the high-level scan signal SCAN is connected to the light-emitting element OLED through the resistive memory ReRAM. Therefore, after the high-level scan signal SCAN flows through the resistive memory ReRAM, it experiences a voltage loss corresponding to the data signal DATA. If the data signal DATA is active, the resistive memory ReRAM is in a low-resistance state, and the voltage loss of the high-level scan signal SCAN through the resistive memory ReRAM is minimal or almost zero, allowing the light-emitting element OLED to be successfully driven to emit light. If the data signal DATA is inactive, the resistive memory ReRAM is in a high-resistance state, and the voltage loss of the high-level scan signal SCAN through the resistive memory ReRAM is significant, making it impossible to drive the light-emitting element OLED to emit light.

[0075] In addition, if the light-emitting element OLED in the pixel circuit 300 does not have high requirements for anode reset, the problem of the light-emitting element OLED needing to be reset can be ignored, and the third switch tube SW3 can be omitted. Then the number of switch tubes included in the pixel circuit 300 can be only one (current source SW2), and the pixel circuit 300 has low requirements for the number of switch tubes.

[0076] In this embodiment, the current source SW2 and the third switch SW3 may be transistors of types such as a bipolar junction transistor (BJT), a field effect transistor (FET), or an insulated gate bipolar transistor (IGBT).

[0077] As an example, the current source SW2 and the third switch SW3 are both P-channel metal oxide semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to a voltage threshold, that is, when its control terminal receives a low-level control signal, the current path from the first current terminal to the second current terminal is conductive. When the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, that is, when its control terminal receives a high-level control signal, the current path from the first current terminal to the second current terminal is disconnected. Therefore, it is defined that the scan signal SCAN and the reset signal RESETB having a low level are in an active state, and the scan signal SCAN and the reset signal RESETB having a high level are in an inactive state. It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art may modify the types of the first switch SW1, the current source SW2, and the third switch SW3, and the specific levels of the scan signal SCAN and the reset signal RESETB in the active and inactive states according to actual needs.

[0078] In this embodiment, when the resistive memory ReRAM drives the light-emitting element OLED, the low level of the data signal DATA is higher than the difference between the voltage at the second terminal of the resistive memory ReRAM and the threshold voltage, while the high level of the data signal DATA is lower than the difference between the voltage at the second terminal of the resistive memory ReRAM and the threshold voltage. Therefore, the selector selector does not conduct, and there is no leakage of additional current through the selector selector. During the light-emitting phase, the voltage across the resistive memory ReRAM is controlled to be significantly lower than the write voltage due to the presence of current source SW2. This prevents the resistive memory from flipping state, allowing the state of the resistive memory to be stably maintained during the light-emitting phase. The "0" or "1" of the data signal is permanently retained in the resistive memory ReRAM, which is crucial for the stability of the drive current during the display period.

[0079] Figure 5 A circuit diagram of a pixel circuit according to a third embodiment of the present invention is shown.

[0080] like Figure 5 As shown, in the pixel circuit 400 , the scanning control module includes a first switch tube SW1 , the data storage module includes a resistive memory ReRAM, and the light emitting module includes a current source SW2 , a third switch tube SW3 , a fourth switch tube SW4 and a light emitting element OLED.

[0081] Specifically, the first current terminal of the first switch SW1 receives the data signal DATA, the second current terminal is connected to the second terminal of the resistive memory ReRAM, and the control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the power supply AVDD, the second current terminal is connected to the first terminal of the resistive memory ReRAM, and the control terminal receives the reference signal Vref. The first current terminal of the third switch SW3 is connected to the first terminal of the light-emitting element OLED, the second current terminal is connected to the reference ground, and the control terminal receives the reset signal RESETB. The first current terminal of the fourth switch SW4 is connected to the second terminal of the resistive memory ReRAM, the second current terminal is connected to the first terminal (anode) of the light-emitting element OLED, and the control terminal receives the control signal EMB. The second terminal (cathode) of the light-emitting element OLED receives the common voltage Vcom. In this embodiment, the first terminal of the resistive memory ReRAM is connected to the power supply AVDD via the current source SW2, and the second terminal of the resistive memory ReRAM is connected to the second current terminal of the first switch SW1 and the first current terminal of the fourth switch, respectively. When the scan signal SCAN is valid or invalid, the data signal DATA is written into the resistive memory ReRAM. When the scan signal SCAN is invalid, the power supply AVDD drives the light-emitting element OLED through the resistive memory ReRAM. In this embodiment, the current source SW2 and the fourth switch SW4 are both P-type transistors. During the scanning phase, the reference signal Vref is at a low level, turning on the current source SW2 as a conductive switch. The control signal EMB is at a high level, turning off the fourth switch SW4 to prevent the light-emitting element OLED from turning on. During the light-emitting phase, the reference signal Vref is an analog signal of a predetermined value, which adjusts the current of the current source SW2 to limit the voltage across the resistive memory to less than the write voltage of the resistive memory. The control signal EMB is at a low level, turning on the fourth switch SW4 to drive the light-emitting element OLED to emit light.

[0082] In this embodiment, a data signal DATA having a low level is defined as being in a valid state, and a data signal DATA having a high level is defined as being in an invalid state. The voltage of the power supply AVDD is higher than the low level of the data signal DATA and lower than the high level of the data signal DATA. Therefore, when the data signal DATA is valid, the voltage at the first terminal of the resistive memory ReRAM (i.e., the voltage of the power supply AVDD) is higher than the voltage at the second terminal of the resistive memory ReRAM (i.e., the low level of the data signal DATA), the resistive memory ReRAM is in a low-resistance state, and data "1" is written. When the data signal DATA is invalid, the voltage at the first terminal of the resistive memory ReRAM (i.e., the voltage of the power supply AVDD) is lower than the voltage at the second terminal of the resistive memory ReRAM (i.e., the high level of the data signal DATA), the resistive memory ReRAM is in a high-resistance state, and data "0" is written. It should be understood that the embodiments of the present invention are not limited to this. Those skilled in the art can change the direction of the resistive memory according to actual needs, and accordingly adjust the conduction state of the pixel circuit in the scanning stage, the correspondence between the high and low levels at each stage, and / or the type of the switch tube, so that when the data signal DATA is valid, the resistive memory ReRAM is in a resistive state corresponding to the data "1", and when the data signal DATA is invalid, the resistive memory ReRAM is in a resistive state corresponding to the data "0".

[0083] In the scanning stage, the scan signal SCAN is valid, the reset signal RESETB is valid, the reference signal Vref is valid, and the control signal EMB is invalid. Therefore, the first switching transistor SW1, the current source SW2, and the third switching transistor SW3 are turned on, and the fourth switching transistor SW4 is turned off. At this time, the first end of the resistive memory ReRAM is connected to the power supply AVDD, the voltage value of the power supply AVDD is V0, the second end of the resistive memory ReRAM receives the data signal DATA, and there is a voltage difference between the first end and the second end of the resistive memory ReRAM, so that the resistive memory ReRAM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid, that is, the voltage on the data line is the low level VdataL, V0 > VdataL, the voltage at the first end of the resistive memory ReRAM (i.e., the voltage value of the power supply AVDD) is higher than the voltage at the second end of the resistive memory ReRAM (i.e., the low level of the data signal DATA), and a conductive filament is formed in the resistive memory ReRAM, which is in the low-resistance state, representing the written data "1"; if the data signal DATA is invalid, that is, the voltage on the data line is the high level VdataH, V0 < VdataH, the voltage at the first end of the resistive memory ReRAM (i.e., the voltage value of the power supply AVDD) is lower than the voltage at the second end of the resistive memory ReRAM (i.e., the high level of the data signal DATA), and the conductive filament in the resistive memory ReRAM is destroyed, which is in the high-resistance state, representing the written data "0". The impedance of the resistive memory ReRAM determines whether the light-emitting element OLED can emit light in the light-emitting stage. That is, the data signal DATA is written into the resistive memory ReRAM by adjusting the impedance of the resistive memory ReRAM. In the scanning stage, the resistive memory ReRAM is disconnected from the light-emitting element OLED, and the first end of the light-emitting element OLED is connected to the reference ground to reset the residual charge on the light-emitting element OLED.

[0084] During the light-emitting phase, the scan signal SCAN is inactive, the reset signal RESETB is inactive, the reference signal Vref is an analog signal for regulating current, and the control signal EMB is active. Therefore, the first and third switches SW1 and SW3 are off, the current source SW2 controls the current in the circuit, and the fourth switch SW4 is on. At this time, the resistive memory ReRAM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light-emitting element OLED through the resistive memory ReRAM. Therefore, after the power supply AVDD flows through the resistive memory ReRAM, it has a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the resistive memory ReRAM is in a low-impedance state, and the voltage loss of the power supply AVDD after flowing through the resistive memory ReRAM is minimal or almost zero, which can successfully drive the light-emitting element OLED to emit light. If the data signal DATA is invalid, the resistive memory ReRAM is in a high-impedance state, and the voltage loss of the power supply AVDD after flowing through the resistive memory ReRAM is significant, making it impossible to drive the light-emitting element OLED to emit light.

[0085] In addition, if the light-emitting element OLED in the pixel circuit 400 does not have high requirements for anode reset, the problem of the light-emitting element OLED needing to be reset can be ignored, and the third switch tube SW3 can be omitted. Then the number of switch tubes included in the pixel circuit 400 can be only three (the first switch tube SW1, the current source SW2 and the fourth switch tube SW4), and the pixel circuit 400 has low requirements for the number of switch tubes.

[0086] In this embodiment, the first switch SW1 , the current source SW2 , the third switch SW3 and the fourth switch SW4 may be bipolar junction transistors (BJTs), field effect transistors (FETs), insulated gate bipolar transistors (IGBTs) and other types of transistors.

[0087] As an example, the first switch SW1, current source SW2, third switch SW3, and fourth switch SW4 are all P-channel metal oxide semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to a voltage threshold, that is, when its control terminal receives a low-level control signal, the current path from the first current terminal to the second current terminal is conductive. When the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, that is, when its control terminal receives a high-level control signal, the current path from the first current terminal to the second current terminal is disconnected. Therefore, the scan signal SCAN, reference signal Vref, reset signal RESETB, and control signal EMB at a low level are defined as being in an active state, while the scan signal SCAN, reference signal Vref, reset signal RESETB, and control signal EMB at a high level are defined as being in an inactive state. It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art may modify the types of the first switch tube SW1, the current source SW2, the third switch tube SW3, and the fourth switch tube SW4, and the specific levels of the scan signal SCAN, the reference signal Vref, the reset signal RESETB, and the control signal EMB in the valid state and the invalid state according to actual needs.

[0088] In this embodiment, during the light-emitting stage, due to the presence of the current source SW2, the voltage across the resistive memory ReRAM is controlled to be much smaller than the write voltage, thereby not causing the state of the resistive memory to flip, and the state of the resistive memory can be stably maintained during the light-emitting stage.

[0089] Furthermore, due to certain deficiencies in existing resistive RAM (ReRAM) processes, which result in variations in the ReRAM's on-resistance, this embodiment swaps the positions of the current source SW2 and the ReRAM, and introduces a fourth switch SW4. This avoids variations in the ReRAM's on-resistance due to variations in process or write conditions, further preventing inconsistencies in the pixel circuit's drive current.

[0090] exist Figure 3 and Figure 4 In the embodiment, the resistive memory ReRAM can be formed above or below the first switch tube SW1, the current source SW2, the third switch tube SW3 and / or the fourth switch tube SW4. Figure 5 In the embodiment, the resistive memory ReRAM can be formed above or below the first switch transistor SW1, the current source SW2, the third switch transistor SW3 and / or the fourth switch transistor SW4, which can further reduce the occupied area of the pixel circuit.

[0091] In addition, the present invention also provides a display panel, comprising a plurality of Figures 3 to 5 Any one of the pixel circuits, multiple pixel circuits are arranged in an array in the display panel, a column of pixel circuits share a data line, a row of pixel circuits share a scan line, and all pixel circuits can share a common voltage. The type of display panel can be any one of the following display panels: low-temperature polysilicon organic light-emitting diode (LTPS OLED) display panel, micro organic light-emitting diode (Micro-OLED) display panel, mini organic light-emitting diode (Mini Organic Light Emitting Diode, Mini-OLED) display panel, micro light-emitting diode (Micro-LED) display panel, passive matrix organic light-emitting diode (Passive Matrix Organic Light Emitting Diode, Passive Matrix OLED) display panel, active matrix organic light-emitting diode (Active Matrix Organic Light Emitting Diode, Active Matrix OLED) display panel, flexible organic light-emitting diode (Flexible Organic Light Emitting Diode, Flexible OLED) display panel, transparent organic light-emitting diode (Transparent Organic Light Emitting Diode, Transparent OLED) display panel, etc. This application does not impose any restrictions on this.

[0092] In summary, the present invention provides a pixel circuit and display panel. Through an innovative combination of circuit design, semiconductor devices, and processes, resistive memory is applied to the pixel circuit, eliminating the capacitor in the traditional pixel circuit, greatly reducing the occupied area of the pixel circuit, and effectively improving the pixel density of the display panel, thereby realizing a compact, reliable, and low-cost high-PPI display panel.

[0093] In some optional embodiments, the pixel circuit includes only three switching tubes. If the problem of resetting the light-emitting element is ignored, the pixel circuit includes only two switching tubes. The pixel circuit has low requirements on the number of switching tubes.

[0094] In some optional embodiments, a selector is used for data writing, and the number of switching tubes included in the pixel circuit is only two. If the problem of resetting the light-emitting element is ignored, the number of switching tubes included in the pixel circuit is only one, and the pixel circuit further reduces the requirement for the number of switching tubes.

[0095] In some optional embodiments, both the resistive memory and the selector can be fabricated above each switch transistor as a back-end of line (BEOL) process, eliminating the need for pixel circuit floor space. This allows for high PPI and high reliability. Practice has proven that this pixel circuit can be fabricated down to a size of 20nm or less.

[0096] Some examples of pixel circuits and display panels according to the embodiments of the present invention are described above. However, the embodiments of the present invention are not limited thereto and may be expanded and deformed in other ways.

[0097] For example, it should be understood that the reference ground potential in the aforementioned embodiments may be replaced by other non-zero reference potentials (having positive or negative voltage amplitudes) or controlled varying reference signals in alternative embodiments.

[0098] At the same time, those skilled in the art will appreciate that, in conjunction with the various exemplary structures and methods described in the embodiments disclosed herein, different configuration methods or adjustment methods can be used for each structure or reasonable variations of the structure to achieve the described functions, but such implementations should not be considered beyond the scope of this application. Furthermore, it should be understood that the connection relationships between the various components of the amplifier in the aforementioned figures in the embodiments of this application are for illustrative purposes only and do not impose any limitations on the embodiments of this application.

[0099] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0100] While embodiments of the present invention have been described above, these embodiments do not exhaustively describe all details and do not limit the invention to the specific embodiments described. Obviously, many modifications and variations are possible based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel circuit comprising: A scanning control module, used for writing data signals; A data storage module, connected between the scanning control module and the power supply, and configured to store the data signal; as well as A light emitting module comprising a light emitting element and a current source, wherein the light emitting element is driven based on the power flowing through the data storage module. The data storage module includes a resistive memory, wherein the impedance of the resistive memory is controlled by a voltage difference between the data signal and the power supply, so that the power supply has a voltage loss corresponding to the data signal after flowing through the data storage module. The current source is connected between the resistive memory and the light emitting element, or the current source is connected between the power supply and the resistive memory, When the scan signal is invalid, the current source limits the bias voltage of the resistive memory to be less than the write voltage of the resistive memory.

2. The pixel circuit according to claim 1, wherein: When the data signal is valid, the resistive memory is in a low-resistance state, and the power supply drives the light-emitting element to emit light. When the data signal is invalid, the resistive memory is in a high-resistance state, and the power supply drives the light-emitting element to stop emitting light.

3. The pixel circuit according to claim 1, wherein: The voltage of the power supply is lower than a high level of the data signal and higher than a low level of the data signal.

4. The pixel circuit according to claim 1, wherein: The scanning control module includes a first switching tube, wherein the first current end of the first switching tube receives the data signal, the second current end is connected to the second end of the resistive memory, and the control end receives the scanning signal. The first end of the resistive memory is connected to the power supply. The light-emitting module includes the light-emitting element, the first end of the light-emitting element is connected to the second end of the resistive memory, and the second end receives the common voltage. When the scan signal is valid, the data signal is written into the resistive memory, and when the scan signal is invalid, the power source drives the light-emitting element through the resistive memory.

5. The pixel circuit according to claim 1, wherein: The scanning control module includes a selector, wherein a first end of the selector receives the data signal and a second end of the selector is connected to the second end of the resistive memory, wherein the first end of the resistive memory receives the scanning signal; the light emitting module includes the light emitting element, wherein a first end of the light emitting element is connected to the second end of the resistive memory, and a second end receives a common voltage. When the absolute value of the voltage difference between the first terminal and the second terminal of the selector is greater than / equal to the threshold voltage, the selector is turned on. When the scanning signal is valid, the data signal is written into the resistive memory, and when the scanning signal is invalid, the power source drives the light-emitting element through the resistive memory. The scanning signal is in an effective state when it is at a first level, and is in an ineffective state when it is at a second level. The second level of the scanning signal serves as the power supply. The pixel circuit according to claim 5 , wherein: The data signal is in a valid state when it is at a high level, and in an invalid state when it is at a low level. The initial state of the resistive memory is a high-resistance state, and the voltage difference between the high level of the data signal and the threshold voltage is greater than the first level of the scan signal.

7. The pixel circuit according to claim 5, wherein: When the scan signal is invalid, the current source makes the low level of the data signal greater than the difference between the voltage value of the second end of the resistive memory and the threshold voltage, and the difference between the high level of the data signal and the threshold voltage less than the voltage value of the second end of the resistive memory.

8. The pixel circuit according to claim 4 or 5, wherein: The light emitting module further includes a third switch tube, wherein a first current terminal of the third switch tube is connected to the first terminal of the light emitting element, a second current terminal is connected to a reference ground, and a control terminal receives a reset signal.

9. The pixel circuit according to claim 8, wherein: The light emitting module further includes a fourth switch tube, a first current end of the fourth switch tube is connected to the second end of the resistive memory, a second current end is connected to the first end of the light emitting element, and a control end receives a control signal.

10. The pixel circuit according to claim 9, wherein: The resistive memory is formed above or below the first switch tube, the current source, the third switch tube and / or the fourth switch tube.

11. A display panel comprising the pixel circuit according to any one of claims 1 to 10.

Images