A method for preparing a semiconductor structure

Abstract

The present invention provides a method for manufacturing a semiconductor structure, which is applied to the field of semiconductor technology. The present invention includes providing a substrate including a PMOS region and an NMOS region, forming grooves in the substrate on both sides of the gate structure in the PMOS region, forming a stress isolation layer to fill the grooves, forming a tensile stress memory layer to cover the hard mask layer in the NMOS region and the stress isolation layer in the PMOS region, and annealing the tensile stress memory layer; by adjusting the preparation process sequence of the tensile stress memory layer and the corresponding grooves in the source and drain regions of the PMOS transistor, the present invention realizes the function that the stress isolation layer can block the stress transfer of the tensile stress memory layer, avoids the influence of the tensile stress memory layer on the PMOS transistor during the annealing process, that is, ensures the device performance of the PMOS transistor, and at the same time improves the electron mobility of the NMOS transistor, thereby achieving the purpose of simplifying the manufacturing process of CMOS devices and reducing the manufacturing cost (for example, eliminating the photomask for removing the tensile stress memory layer in the PMOS region).

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a method for preparing a semiconductor structure. Background Art

[0002] In semiconductor manufacturing processes, especially when manufacturing complementary metal oxide semiconductor (CMOS) devices, in order to improve the performance of CMOS devices, stress technology (SMT) is currently commonly used to induce stress in the channel regions of MOS transistors.

[0003] NMOS transistors require tensile stress, and PMOS transistors require compressive stress. Therefore, after selectively removing the native strained material on the surface of the NMOS or PMOS region according to the stress properties of the native strained material, annealing can be performed, so that the stress is memorized in the transistor gate polysilicon or diffusion region. In the existing process, SMT only improves the mobility of NMOS transistors, that is, a native strained material with tensile stress is selected and covered on the substrate and the surfaces of NMOS and PMOS transistors by chemical vapor deposition.

[0004] However, tensile stress will reduce the performance of PMOS transistors. Therefore, before annealing, it is necessary to etch and remove the strained material on the surface of PMOS transistors, which obviously increases a mask formation process, a photolithography and etching process, resulting in an increase in the manufacturing process of integrated circuits and an increase in manufacturing costs. Summary of the Invention

[0005] The purpose of the present invention is to provide a method for preparing a semiconductor structure, which simplifies the manufacturing process of CMOS devices and reduces manufacturing costs while avoiding the degradation of the device performance of PMOS transistors.

[0006] To solve the above technical problems, the present invention provides a method for preparing a semiconductor structure, which may at least include: providing a substrate, where the substrate includes a PMOS region and an NMOS region.

[0007] Forming a plurality of mutually separated gate structures respectively on the PMOS region and the NMOS region of the substrate.

[0008] Forming a hard mask layer to cover the outer surface of the gate structure and the substrate on both sides thereof.

[0009] Forming a plurality of grooves respectively in the substrate on both sides of the gate structure in the PMOS region. Forming a stress isolation layer to fill the grooves.

[0010] Forming a tensile stress memory layer to cover the hard mask layer in the NMOS region and the stress isolation layer in the PMOS region.

[0011] Performing an annealing treatment on the tensile stress memory layer.

[0012] In an alternative example, the dielectric constant of the stress isolation layer may be less than 3.

[0013] In an alternative example, the stress isolation layer may include at least one of an anti-reflection layer, an amorphous material layer, an organic material layer, or a photoresist.

[0014] In an alternative example, after annealing the tensile stress memory layer, it further includes: removing the tensile stress memory layer and the stress isolation layer to re-expose the groove, and forming a first embedded epitaxial layer to fill the groove.

[0015] In an alternative example, after forming the first embedded epitaxial layer to fill the groove, the method for manufacturing the semiconductor structure in the present invention may further include: removing the hard mask layer, and performing subsequent processes on the NMOS region of the substrate to form an electrical structure including source and drain regions, and the source and drain regions are filled with a second embedded epitaxial layer.

[0016] In an alternative example, before forming the tensile stress memory layer, the method for manufacturing the semiconductor structure in the present invention may further include: forming a transition layer to cover the hard mask layer of the NMOS region and the stress isolation layer of the PMOS region.

[0017] In an alternative example, the material of the transition layer may include at least one of a low-temperature oxide or a silicon oxynitride compound.

[0018] In an alternative example, before forming the first embedded epitaxial layer to fill the groove, the method for manufacturing the semiconductor structure in the present invention may further include: wet etching the inner surface of the groove to adjust the shape of the groove.

[0019] In an alternative example, before forming the stress isolation layer to fill the groove, the method for manufacturing the semiconductor structure in the present invention may further include: wet etching the inner surface of the groove to adjust the shape of the groove.

[0020] In an alternative example, after forming the gate structure, the method for manufacturing the semiconductor structure in the present invention may further include: forming spacer structures on both sidewalls of the gate structure.

[0021] In an alternative example, the material of the tensile stress memory layer may include tensile stress silicon nitride.

[0022] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0023] The method for preparing the semiconductor structure provided by the present invention includes: providing a substrate, the substrate including a PMOS region and an NMOS region; forming a plurality of mutually separated gate structures respectively on the PMOS region and the NMOS region of the substrate; forming a hard mask layer to cover the outer surface of the gate structures and the substrate on both sides thereof; forming a plurality of grooves respectively in the substrate on both sides of the gate structures in the PMOS region; forming a stress isolation layer to fill the grooves; forming a tensile stress memory layer to cover the hard mask layer in the NMOS region and the stress isolation layer in the PMOS region; and annealing the tensile stress memory layer.

[0024] In the present invention, by adjusting the preparation process sequence of the tensile stress memory layer and the corresponding grooves in the source and drain regions of the PMOS transistor, it is achieved that before the tensile stress memory layer for improving the electron mobility of the NMOS transistor is integrally covered on the substrate, the corresponding grooves in the source and drain regions of the PMOS transistor are first filled with the stress isolation layer, and the unexpected effect is: the stress isolation layer has the function of blocking the stress transfer of the tensile stress memory layer, avoiding the influence of the tensile stress memory layer on the PMOS transistor during the annealing process, that is, ensuring the device performance of the PMOS transistor and at the same time improving the electron mobility of the NMOS transistor; and, due to the presence of the stress isolation layer, before annealing the tensile stress memory layer, it is not necessary to first remove the tensile stress memory layer in the PMOS region, and the purpose of simplifying the manufacturing process of the CMOS device and reducing the manufacturing cost (for example, omitting the photomask for removing the tensile stress memory layer in the PMOS region) is achieved. Description of the Drawings

[0025] The drawings are used to provide a further understanding of the present application and constitute a part of the specification, and are used to explain the present application together with the following specific embodiments, but do not constitute a limitation to the present application. In the drawings:

[0026] Figure 1 It is a schematic flow chart of the method for preparing the semiconductor structure provided in an embodiment of the present invention.

[0027] Figure 2 It is a schematic structural diagram of the PMOS transistor and the NMOS transistor formed on the substrate in an embodiment of the present invention.

[0028] Figure 3 It is a schematic structural diagram of the hard mask layer formed on the substrate in an embodiment of the present invention.

[0029] Figure 4 It is a schematic structural diagram of the grooves formed in the substrate in an embodiment of the present invention.

[0030] Figure 5 It is a schematic structural diagram of the stress isolation layer formed on the substrate in an embodiment of the present invention.

[0031] Figure 6 Schematic diagram of the structure after removing part of the stress isolation layer in an embodiment of the present invention.

[0032] Figure 7 Schematic diagram of the structure after forming a tensile stress memory layer on the substrate in an embodiment of the present invention.

[0033] Figure 8 In an embodiment of the present invention, for Figure 7 Partial enlarged view of part of the structure A in.

[0034] Figure 9 Schematic diagram of the structure after removing the tensile stress memory layer in an embodiment of the present invention.

[0035] Figure 10 Schematic diagram of the structure after removing the stress isolation layer filled in the groove on the substrate in an embodiment of the present invention.

[0036] Figure 11 Schematic diagram of the structure of the groove after adjusting the shape in an embodiment of the present invention.

[0037] Figure 12 Schematic diagram of the structure after forming a first embedded epitaxial layer in the groove in an embodiment of the present invention.

[0038] Figure 13 Schematic diagram of the structure after removing the remaining hard mask layer in an embodiment of the present invention.

[0039] Figure 14 Schematic diagram of the structure after forming source and drain regions in the NMOS region in an embodiment of the present invention.

[0040] Among them, the reference numerals are:

[0041] 100 - Substrate, 100P - PMOS region, 100N - NMOS region, 101 - Groove, 101’ - Groove after adjusting the shape, 110 - Shallow trench isolation structure, 121 - Pad oxide layer, 121 - Gate oxide layer, 130 - Gate layer, 251P - First gate structure, 251N - Second gate structure, 140 - Sidewall structure, 141 - First sidewall, 142 - Second sidewall, 143 - Third sidewall, 150 - Hard mask layer, 160 / 160’ - Stress isolation layer, 170 - Transition layer, 180 - Tensile stress memory layer, 190 - First embedded epitaxial layer, A - Locally enlarged area.

[0042] In the drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn to actual scale. Detailed implementation manners

[0043] In order to make the technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although the accompanying drawings show exemplary implementation methods of the present invention, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0044] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in illustrating the purpose of the embodiments of the present invention. It will be understood that the meanings of "on...", "above..." and "above..." in the present invention should be interpreted in the broadest way, so that "on..." not only means that it is "on" something and there are no intervening features or layers (i.e., directly on something), but also includes the meaning of being "on" something and having intervening features or layers.

[0045] Please refer to Figure 1 As shown, it is a schematic flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present invention. Figure 1 As shown, the method for preparing a semiconductor structure provided by an embodiment of the present invention includes at least the following steps:

[0046] Step S101 : providing a substrate, wherein the substrate includes a PMOS region and an NMOS region.

[0047] In step S102 , a plurality of gate structures separated from each other are formed and respectively located on the PMOS region and the NMOS region of the substrate.

[0048] Step S103 : forming a hard mask layer to cover the outer surface of the gate structure and the substrate on both sides thereof.

[0049] Step S104 , forming a plurality of grooves in the substrate on both sides of the gate structure in the PMOS region.

[0050] Step S105 , forming a stress isolation layer to fill the groove.

[0051] Step S106 , forming a tensile stress memory layer to cover the hard mask layer in the NMOS region and the stress isolation layer in the PMOS region.

[0052] Step S107 , performing annealing treatment on the tensile stress memory layer.

[0053] In order to enable those of ordinary skill in the art to which the present invention pertains to easily understand the method for fabricating a semiconductor structure in an embodiment of the present invention, the following will further describe the method for fabricating the semiconductor structure proposed by the present invention with reference to various structural schematic diagrams during the fabrication process of the fabrication method.

[0054] Please refer to Figures 2 to 14 as shown, Figures 2 to 14 which is a partial structural schematic diagram during the fabrication process of the method for fabricating a semiconductor structure provided in an embodiment of the present invention.

[0055] Please refer to Figure 2 and perform step S101: Provide a substrate 100 as the setting basis for the semiconductor structure in an embodiment of the present invention, and divide the substrate 100 into a PMOS region 100P and an NMOS region 100N. In one embodiment, the semiconductor structure may be a CMOS transistor, and the CMOS transistor may include a PMOS transistor (hereinafter simply referred to as a PMOS transistor) and an NMOS transistor (hereinafter simply referred to as an NMOS transistor) arranged adjacent to each other; the substrate 100 may be any suitable substrate material known in the art, for example, at least one of the materials mentioned below: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or may be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may also be a double-sided polished wafer (DSP), or may also be a ceramic substrate such as alumina, a quartz or glass substrate, etc. Exemplarily, the substrate 100 in this embodiment is, for example, a silicon wafer or a doped silicon wafer, but is not limited thereto. An isolation structure may also be formed in the substrate 100 to define the PMOS region 100P and the NMOS region 100N; wherein, the isolation structure may be a shallow trench isolation structure 110; Exemplarily, the shallow trench isolation structure 110 in an embodiment of the present invention may be strip-shaped; and, a well structure may be formed in the PMOS region 100P and the NMOS region 100N respectively through an ion implantation process, but the ion types of the well structures in the PMOS region 100P and the NMOS region 100N are opposite. For example, an N-type well is formed in the substrate 100 of the PMOS region 100P, while a P-type well is formed in the substrate 100 of the NMOS region 100N to prepare for the subsequent formation of MOS transistors respectively.

[0056] Please continue to refer toFigure 2 Execute step S102: Then, by using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and other processes, a pad oxide layer 121, a gate oxide layer 122 and a gate layer 130 are sequentially formed from bottom to top on the PMOS region 100P and the NMOS region 100N of the substrate 100. And at least one of a dry etching process or a wet etching process, such as an etching process, is used to etch the gate layer 130 and a part of the gate oxide layer 122, so as to respectively form at least one discrete gate structure on the substrate 100 of the PMOS region 100P and the NMOS region 100N. For the convenience of distinction, in the embodiment of the present invention, the gate structure located on the PMOS region 100P is called the first gate structure and is denoted by the reference numeral 251P, and the gate structure located on the NMOS region 100N is called the second gate structure and is denoted by the reference numeral 251N, but not limited thereto. Then, the spacer structures 140 can be further formed on the sidewalls on both sides of the first gate structure 251P and the second gate structure 251N by using deposition, photolithography and etching processes.

[0057] In one embodiment, both the pad oxide layer 121 and the gate oxide layer 122 can be single-layer structures, such as silicon oxide layers, but not limited thereto; the material of the gate layer 130 can be single-crystalline silicon, polycrystalline silicon, amorphous silicon, doped silicon, silicon germanium (SiGe), or other suitable semiconductor materials, but not limited thereto; the spacer structure 140 can have a multi-layer structure, such as Figure 2 The first spacer 141, the second spacer 142 and the third spacer 143 stacked in sequence along the direction parallel to the surface of the substrate 100 (hereinafter simply referred to as the horizontal direction) as shown, and the first spacer 141 is in direct contact with the sidewall of the gate layer 130. Specifically, the first spacer 141, the second spacer 142 and the third spacer 143 can respectively include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), or a combination of the above materials, but not limited thereto. Exemplarily, the materials of the first spacer 141 and the third spacer 143 are silicon oxide (SiO2), while the material of the second spacer 142 is silicon nitride (SiN).

[0058] Please refer to Figure 3, perform step S103: A hard mask layer 150 can be conformally formed on the substrate 100 by using a deposition process such as chemical vapor deposition to protect components and / or parts on the NMOS region 100N, such as the second gate structure 251N. In one embodiment, the hard mask layer 150 can conformally cover the top surfaces of all the gate structures on the substrate 100 and the surfaces of the sidewall structures 140 on their sidewalls, as well as the substrate 100 exposed between adjacent gate structures. The material of the hard mask layer 150 can be silicon nitride.

[0059] It should be understood that "conformal" in the embodiments of the present invention refers to constructing a continuous structural shape by utilizing the similarity and correlation in the morphology between two or more shapes.

[0060] Please refer to Figure 4 , perform step S104: At least one of an etching process such as a dry etching process or a wet etching process can be used to etch and remove a part of the hard mask layer 150, the pad oxide layer 121, and the substrate 100 in the PMOS region 100P of the substrate 100 along a direction perpendicular to the surface of the substrate 100 (hereinafter simply referred to as the vertical direction) to respectively form a groove 101 (corresponding positions of the source-drain regions) in the substrate 100 on both sides of the first gate structure 251P.

[0061] It should be noted that in other embodiments, after performing the above step S104 to form the groove 101 in the substrate 100 on both sides of the first gate structure 251P by using an etching process, a wet etching process (i.e., the wet etching) is directly used to etch the inner surface of the groove 101 ( Figure 4 as shown) to adjust the shape of the groove 101 (the adjusted shape is an irregular bowl shape as shown in Figure 11 ), and then subsequent corresponding steps are performed, that is, the shape of the groove 101 is adjusted first, and then the stress isolation layer 160 is filled. For the sake of simplifying the drawings, the embodiments of the present invention only show the solution of forming the stress isolation layer 160 first and then adjusting the shape of the groove 101, but are not limited thereto.

[0062] Please refer to Figure 5 and Figure 6 , perform step S105: Then, a stress isolation layer 160 that buries the corresponding gate structures can be formed on both the PMOS region 100P and the NMOS region 100N of the substrate 100 by using a deposition process. In this setting, the stress isolation layer 160 will also fill the groove 101 synchronously, as shown in Figure 5As shown. Next, the etching process is further used to remove a part of the height of the stress isolation layer 160 in the vertical direction, so that the remaining stress isolation layer 160' after etching only fills the groove 101, that is, the top surface of the remaining stress isolation layer 160' after etching is flush with the opening of the groove 101, as Figure 6 shown. In one embodiment, the material of the stress isolation layer 160 may be a multi-cavity film layer material with a dielectric constant less than 3 (k < 3), such as an anti-reflection layer, an amorphous material layer, an organic material layer, or a photoresist, but not limited thereto; preferably, the anti-reflection layer may include at least one of oxides, nitrides, and oxynitrides, such as organic substances such as crosslinked resin, thermally induced acid generator, and surfactant; the amorphous material layer includes amorphous carbon.

[0063] Obviously, when manufacturing the CMOS device by using the manufacturing method provided in the embodiment of the present invention, on the basis that the hard mask layer 150 shields the components and / or devices in the NMOS region 100N, first, the groove 101 for preparing the source and drain regions of the PMOS transistor is etched in the substrate 100 of the PMOS region 100P, and the stress isolation layer 160 having a stress transfer blocking effect on the tensile stress memory layer is filled in the groove 101, and then the tensile stress memory layer 180 is formed by using step S106, thereby avoiding the influence of the tensile stress memory layer 180 on the PMOS transistor during the annealing process, that is, ensuring the device performance of the PMOS transistor and at the same time improving the electron mobility of the NMOS transistor.

[0064] Please refer to Figure 7 and Figure 8, perform steps S106 and S107: Using a deposition process, such as at least one of physical vapor deposition, chemical vapor deposition, atomic layer deposition and other processes, conformally cover a transition layer 170 and a tensile stress memory layer 180 in sequence from bottom to top on the NMOS region 100N and the PMOS region 100P of the substrate 100, and then anneal the substrate 100 to utilize the stress transfer effect of the tensile stress memory layer 180 to achieve the purpose of improving the electron mobility of the formed NMOS transistor (located in the NMOS region 100N). In an embodiment, the material of the transition layer 170 can be a low-temperature oxide such as silicon dioxide, or a dielectric antireflection coating material layer such as silicon oxynitride; the material of the tensile stress memory layer 180 can be tensile stress silicon nitride, but is not limited thereto. Obviously, since in the embodiment of the present invention, before annealing the tensile stress memory layer 180 which has an improving effect on the electron mobility of the NMOS transistor, the groove 101 for forming the source and drain regions of the PMOS transistor in the PMOS region 100P is filled with the stress isolation layer 160, so there is no need to remove the tensile stress memory layer 180 covering the PMOS region 100P, and annealing can be carried out, that is, the purpose of simplifying the manufacturing process of the CMOS device and reducing the manufacturing cost (for example, omitting the photomask for removing the tensile stress memory layer 180 at the PMOS region 100P) is achieved.

[0065] Please refer to Figure 9 and Figure 10 , following the execution of step S107: The tensile stress memory layer 180 on the substrate 100 can be removed first by using an etching process such as a dry etching process, and then the stress isolation layer 160 filled in the groove 101 of the PMOS region 100P of the substrate 100 can be further removed, that is, the groove 101 is re-exposed.

[0066] Please refer to Figure 11 , following the above step S107: The inner surface of the groove 101 can be etched by using an etching process such as a wet etching process (i.e., the wet etching) to adjust the shape of the groove 101 to meet the actual design requirements. Exemplarily, in the embodiment of the present invention, the Figures 11 to 14 The groove with the adjusted shape is denoted by the reference numeral 101', and the shape of the groove 101' with the adjusted shape is shown as an irregular bowl shape, but is not limited thereto.

[0067] Please refer to Figures 12 to 14, perform step S107: Deposit a first embedded epitaxial layer 190 in the groove 101' after adjusting its shape and then perform subsequent processes such as ion implantation on it. At this time, the material of the first embedded epitaxial layer 190 is germanium silicide to form the source region S and the drain region D of the PMOS transistor. Then, following step S107, further remove the remaining hard mask layer 150 on the substrate 100 to expose again the second gate structure 251N of the NMOS region 100N of the substrate 100 and the film materials on both sides thereof. Furthermore, by using an etching process, grooves for serving as the source region S and the drain region D of the NMOS transistor can be further formed in the substrate 100 on both sides of the second gate structure 251N, and by using an epitaxial process, a second embedded epitaxial layer is formed in the grooves serving as the source region S and the drain region D of the NMOS transistor, and the material of the second embedded epitaxial layer is silicon phosphide. Other corresponding processes can be carried out subsequently.

[0068] In summary, the method for preparing a semiconductor structure provided by the present invention includes: providing a substrate, the substrate including a PMOS region and an NMOS region, forming a plurality of gate structures separated from each other on the PMOS region and the NMOS region of the substrate respectively, forming a hard mask layer covering the outer surfaces of the gate structures and the substrate on both sides thereof, forming a plurality of grooves in the substrate on both sides of the gate structures in the PMOS region respectively, forming a stress isolation layer to fill the grooves, forming a tensile stress memory layer covering the hard mask layer in the NMOS region and the stress isolation layer in the PMOS region, and annealing the tensile stress memory layer.

[0069] In the present invention, by adjusting the preparation process sequence of the tensile stress memory layer and the corresponding grooves of the source and drain regions of the PMOS transistor, before the tensile stress memory layer for improving the electron mobility of the NMOS transistor is integrally covered on the substrate, the corresponding grooves of the source and drain regions of the PMOS transistor are first filled with the stress isolation layer, and the unexpected effect obtained is that: the stress isolation layer has the function of blocking the stress transfer of the tensile stress memory layer, avoiding the influence of the tensile stress memory layer on the PMOS transistor during the annealing process, that is, ensuring the device performance of the PMOS transistor and simultaneously improving the electron mobility of the NMOS transistor; and, due to the presence of the stress isolation layer, before annealing the tensile stress memory layer, it is not necessary to first remove the tensile stress memory layer in the PMOS region, and the purpose of simplifying the manufacturing process of the CMOS device and reducing the manufacturing cost (for example, omitting the photomask for removing the tensile stress memory layer in the PMOS region) is achieved.

[0070] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0071] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments of the device, electronic device and computer-readable storage medium, since they are basically similar to the method embodiments, the description is relatively simple, and reference can be made to the partial description of the method embodiments for the relevant parts.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate, the substrate including a PMOS region and an NMOS region; Forming a plurality of mutually separated gate structures respectively on the PMOS region and the NMOS region of the substrate; Forming a hard mask layer to cover the outer surface of the gate structure and the substrate on both sides thereof; Forming a plurality of grooves respectively in the substrate on both sides of the gate structure in the PMOS region; Forming a stress isolation layer to fill the grooves; Forming a tensile stress memory layer to cover the hard mask layer in the NMOS region and the stress isolation layer in the PMOS region; Performing an annealing treatment on the tensile stress memory layer; Removing the tensile stress memory layer and the stress isolation layer to re-expose the grooves; Forming a first embedded epitaxial layer to fill the grooves.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein, The dielectric constant of the stress isolation layer is less than 3.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein, The stress isolation layer includes at least one of an anti-reflection layer, an amorphous material layer, an organic material layer or a photoresist.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein, After forming the first embedded epitaxial layer to fill the grooves, it further includes: Removing the hard mask layer; Performing subsequent processes on the NMOS region of the substrate to form an electrical structure including a source region and a drain region, and the source region and the drain region are filled with a second embedded epitaxial layer.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein Before forming the tensile stress memory layer, it further includes: Forming a transition layer to cover the hard mask layer in the NMOS region and the stress isolation layer in the PMOS region.

6. The manufacturing method of the semiconductor structure as described in claim 5, characterized in that, The material of the transition layer includes at least one of a low-temperature oxide or a silicon oxynitride compound.

7. The method for preparing a semiconductor structure according to claim 1, wherein, Before forming the first embedded epitaxial layer to fill the grooves, or before forming the stress isolation layer to fill the grooves, it further includes: Performing wet etching on the inner surface of the grooves to adjust the shape of the grooves.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein After forming the gate structure, it further includes: Forming sidewall structures on the sidewalls on both sides of the gate structure.

9. The method for fabricating a semiconductor structure according to claim 1, wherein, The material of the tensile stress memory layer includes tensile stress silicon nitride.

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