Semiconductor device and manufacturing method

Abstract

The invention provides a semiconductor device and a manufacturing method. As a non-limiting example, various aspects of the present disclosure provide a stackable semiconductor device having a small size and a fine pitch and a method of manufacturing the same.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Current semiconductor devices and methods for manufacturing semiconductor devices are inadequate, for example, causing too low sensitivity, excessive cost, reduced reliability, or too large package size. By comparing conventional and traditional approaches with the present invention as described in the remaining part of this application with reference to the drawings, additional limitations and disadvantages of such approaches will become apparent to those skilled in the art. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of the present invention provide a stackable semiconductor device having a small size and a fine pitch and a manufacturing method thereof.

[0004] An embodiment of the present invention provides a semiconductor device, which includes: a substrate having a top substrate surface, a bottom substrate surface, and a lateral substrate surface extending between the top substrate surface and the bottom substrate surface; a semiconductor die having a top die surface, a bottom die surface, and a lateral die side surface extending between the top die surface and the bottom die surface, wherein the bottom die surface is coupled to the top substrate surface; a metal pillar having a top pillar surface, a bottom pillar surface, and a lateral pillar surface extending between the top pillar surface and the bottom pillar surface, wherein the bottom pillar surface is coupled to the top substrate surface by an adhesive member and is positioned outside the area of the top substrate surface covered by the semiconductor die; and a packaging material encapsulating at least a part of the lateral die side surface and at least a part of the lateral pillar surface.

[0005] In the semiconductor device, the adhesive member includes solder.

[0006] In the semiconductor device, the top pillar surface is coplanar with the top die surface.

[0007] In the semiconductor device, the top pillar surface is coplanar with the top surface of the packaging material.

[0008] In the semiconductor device, the top pillar surface is coplanar with the top surface of the packaging material.

[0009] The semiconductor device includes an upper substrate having a top upper substrate surface, a bottom upper substrate surface, and a lateral upper substrate surface extending between the top upper substrate surface and the bottom upper substrate surface.

[0010] In the semiconductor device, the upper substrate includes a bottom conductive pattern formed integrally with the metal pillar.

[0011] In the semiconductor device, the metal pillar is plated on the conductive pattern.

[0012] In the semiconductor device, the upper substrate includes a top conductive pattern that is directly positioned above the metal pillar and is formed integrally with the bottom conductive pattern and the metal pillar.

[0013] In the semiconductor device, each of the lateral die surfaces is coplanar with a corresponding lateral substrate surface of the lateral substrate and a corresponding upper lateral substrate surface of the upper lateral substrate.

[0014] Another embodiment of the present invention provides a method of manufacturing a semiconductor device, the method comprising: coupling a bottom surface of a semiconductor die to a top surface of a first substrate; providing a second substrate including a metal pillar extending from a bottom surface of the second substrate; and coupling a bottom surface of the metal pillar to the top surface of the first substrate.

[0015] In the method, the coupling the bottom surface of the metal pillar to the top surface of the first substrate includes coupling the bottom surface of the metal pillar to the top surface of the first substrate with an adhesive member.

[0016] In the method, the adhesive member includes solder.

[0017] In the method, the second substrate includes an insulating member, and the method includes removing at least a portion of the insulating member after coupling the bottom surface of the metal pillar.

[0018] In the method, the second substrate includes a seed layer on a top surface of the insulating member, and the method includes removing the seed layer after coupling the bottom surface of the metal pillar to the top surface of the first substrate.

[0019] In the method, the provided second substrate includes a bottom conductive pattern on which the metal pillar is plated.

[0020] The method includes removing the bottom conductive pattern after coupling the bottom surface of the metal pillar.

[0021] Another embodiment of the present invention provides a method of manufacturing a semiconductor device, the method comprising: coupling a bottom surface of a semiconductor die to a top surface of a first substrate; forming a second substrate, the second substrate comprising: metal pillars extending from the second substrate; an adhesive member on a surface of the metal pillars; and an insulating member surrounding at least a portion of the metal pillars; and coupling the adhesive member to the top surface of the first substrate.

[0022] The method includes forming the metal pillars at least in part by plating the metal pillars on a conductive pattern of the second substrate.

[0023] The method includes forming the adhesive member at least in part by patterning a temporary material on the insulating member and forming the adhesive member on the surface of the metal pillars. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A cross-sectional view of a semiconductor device showing various aspects of the present invention;

[0025] Figure 2 A cross-sectional view of a semiconductor device showing various aspects of the present invention;

[0026] Figures 3A to 3F A view showing a method of manufacturing a semiconductor device illustrating various aspects of the present invention;

[0027] Figures 4A to 4I A view showing a method of manufacturing a semiconductor device illustrating various aspects of the present invention; and

[0028] Figures 5A to 5F A view showing a method of manufacturing a semiconductor device illustrating various aspects of the present invention. DETAILED DESCRIPTION

[0029] The following discussion presents various aspects of the present invention by providing examples of the present invention. Such examples are non-limiting, and thus, the scope of various aspects of the present invention should not necessarily be limited by any particular characteristics of the provided examples. In the following discussion, the phrases "for example," "such as," and "exemplary" are non-limiting and are generally synonymous with "as an example and not a limitation," "by way of example and not a limitation," and the like.

[0030] As used herein, "and / or" means any one or more of the items in the list joined by "and / or". As an example, "x and / or y" means any element in the three-element set {(x), (y), (x, y)}. In other words, "x and / or y" means "one or both of x and y". As another example, "x, y and / or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, "x, y and / or z" means "one or more of x, y and z".

[0031] The terminology used herein is for the purpose of describing particular instances only and is not intended to limit the invention. As used herein, the singular forms are also intended to include the plural forms unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "has" and the like when used in this specification, specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0032] It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, without departing from the teachings of the invention, the first element, first component or first section discussed below may be referred to as the second element, second component or second section. Similarly, various spatial terms such as "upper", "above", "lower", "below", "side", "lateral", "horizontal", "vertical" and the like may be used to relatively distinguish one element from another. However, it should be understood that without departing from the teachings of the invention, the components may be oriented differently. For example, a semiconductor device may be rotated laterally such that its "top" surface faces horizontally and its "side" surface faces vertically.

[0033] It will also be understood that the terms coupled, connected, attached and the like include direct and indirect (e.g., with intervening elements) coupling, connection, attachment, etc., unless otherwise expressly indicated. For example, if element A is coupled to element B, then element A may be indirectly coupled to element B through an intermediate signal distribution structure, or element A may be directly coupled to element B (e.g., directly adhered to, directly welded to, attached by direct metal-to-metal bonding), etc.

[0034] In the drawings, the dimensions of structures, layers, regions, etc. (e.g., absolute and / or relative dimensions) may be exaggerated for clarity. Although such dimensions typically indicate example embodiments, they are not restrictive. For example, if structure A is described as larger than region B, this typically indicates an example embodiment, but it generally does not require that structure A be larger than structure B unless otherwise indicated. Additionally, in the drawings, like reference numerals may refer to like elements throughout the description.

[0035] Various aspects of the present invention provide a semiconductor device and a method of manufacturing the same, which may be characterized by a small footprint, small thickness, and fine pitch pattern pitch. For example, the semiconductor device may be stackable.

[0036] Various aspects of the present invention provide a semiconductor device, which includes a substrate, a semiconductor die coupled to one surface of the substrate, metal pillars coupled to the surface of the substrate, and a package that encapsulates the semiconductor die and the metal pillars and exposes the metal pillars. For example, the metal pillars may be formed vertically along holes in the package.

[0037] Various aspects of the present invention provide a method of manufacturing a semiconductor device, the method including: providing a carrier substrate including metal pillars and an insulating member surrounding the metal pillars; coating and patterning a photoresist on the surface of the insulating member; performing plating on the metal pillars; coupling the metal pillars to the substrate; removing the photoresist and the carrier substrate; and forming a package that encapsulates the metal pillars.

[0038] Various aspects of the present invention provide a method of manufacturing a semiconductor device, the method including: providing a seed layer and a photoresist on the surface of a carrier substrate; forming metal pillars by performing plating in the pattern of the photoresist; removing the photoresist; coupling the metal pillars to the substrate; forming a package that encapsulates the metal pillars; and removing the carrier substrate.

[0039] For example, various aspects of the present invention may provide a semiconductor device, which includes metal pillars having a fine pitch on the top surface of a substrate, wherein the metal pillars are exposed outside the package, thereby providing a stackable semiconductor device having a small size and a fine pitch pattern pitch. For example, the semiconductor device may further include an upper substrate coupled to the metal pillars.

[0040] Various aspects of the present invention will now be described in detail with reference to the drawings, such that they may be readily practiced by those skilled in the art.

[0041] Figure 1 A cross-sectional view of a semiconductor device according to various aspects of the present invention is shown. For example, an example semiconductor device 100 may include a substrate 110, a semiconductor die 120, metal pillars 130, a package 140, and conductive balls 150.

[0042] For example, the substrate 110 can be formed of a general printed circuit board (PCB) or a lead frame. Moreover, the substrate 110 can be formed of a silicon-based built-in substrate by semiconductor processes. Although not shown separately, for example, the substrate 110 can include one or more conductive layers (e.g., metals, etc.), which are electrically coupled to form pads on the top and bottom surfaces of the substrate, thereby providing electrical connection to the overlying semiconductor die 120 or metal pillars 130 to the underlying conductive balls 150. For example, such conductive layers of the substrate 110 can include copper (Cu), aluminum (Al), their alloys, etc., but the scope of the present invention is not limited to this case. Additionally, to enhance connectivity, a metal such as gold (Au) can be applied to the pads.

[0043] For example, the semiconductor die 120 can include an integrated circuit chip separated (or singulated or diced) from a semiconductor wafer. The semiconductor die 120 can include any one of a variety of different types of circuits, for example, a central processing unit (CPU), a digital signal processor (DSP), a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband chip-on-system (SoC) processor, a sensor, an application specific integrated circuit, etc.

[0044] For example, the semiconductor die 120 can input electrical signals to a first surface (e.g., the bottom surface, etc.) and / or output electrical signals from the first surface (e.g., the bottom surface, etc.) through conductive pads 121. For example, the conductive pads 121 can be connected to the internal patterns (or conductive layers) of the semiconductor die 120 and generally can include aluminum (Al) and / or other conductive materials. Additionally, the conductive pads 121 of the semiconductor die 120 can be electrically connected to the balls (or pads or other interconnect structures) formed on the top surface of the substrate 110 through a conductive adhesive member 120a (e.g., including solder, conductive epoxy, etc.). It should be noted that direct metal-to-metal (e.g., solderless) metallurgical bonding can also be utilized. For example, the semiconductor die 120 can include a passivation layer that insulates regions other than the regions where the conductive pads 121 are exposed. Although only one conductive pad 121 is discussed, any number of such conductive pads can exist.

[0045] For example, the semiconductor die 120 can include a second surface 122 (e.g., the top surface) opposite to the first surface (e.g., the bottom surface). For example, the second surface 122 can be exposed to the outside (e.g., exposed from the encapsulation material). For example, the second surface 122 can have the same height as the top surface of the encapsulant 140, and the top surface of the encapsulant 140 will be exposed to the outside of the encapsulant 140. In this example configuration, the semiconductor die 120 can be configured to facilitate heat dissipation from the semiconductor die 120 to the outside.

[0046] The metal posts 130 project from the top surface of the substrate 110. For example, the metal posts 130 can be made of metal (e.g., copper, etc.), and can be positioned in an area other than the area where the semiconductor die 120 is positioned. For example, the metal posts 130 can be electrically connected to the substrate 110 through a conductive adhesive member 130a (e.g., including solder, etc.). Additionally, the metal posts 130 can be exposed from the upper portion (e.g., from the upper surface) of the package 140. In some cases, the end 131 of the metal post 130 can extend further from the substrate 110 than from the package 140, for example, projecting from the top surface of the package 140. When another semiconductor device is stacked on the semiconductor device 100, the semiconductor devices can be electrically connected to each other through the metal posts 130.

[0047] In an example implementation, for example, the width of the metal posts 130 can be in the range of about 10 μm to about 15 μm. Thus, compared with the case of using solder bumps with a diameter of about 350 μm, the metal posts 130 can be implemented with a fine pitch on the substrate 110, thereby reducing the total size of the semiconductor device 100 including the substrate 110. Additionally, many metal posts 130 can be positioned on the substrate 110 with the same small size (and / or multiple sizes), providing a higher degree of freedom in designing the semiconductor device 100 aspect.

[0048] For example, the package 140 can be formed on the first surface (e.g., the top surface) of the substrate 110 to surround the semiconductor die 120 and the metal posts 130 (e.g., to surround and / or contact their lateral surfaces, etc.). For example, the package 140 can be made of any of a variety of materials (e.g., general resin, etc.), and can protect the semiconductor die 120 and the metal posts 130 from external impacts while fixing the positions of the semiconductor die 120 and the metal posts 130.

[0049] The conductive balls 150 (or any of a variety of interconnect structures, for example, conductive bumps, conductive pillars, or posts, etc.) can be formed under the substrate 110 (e.g., formed on Figure 1 the bottom surface of the substrate 110 in ). For example, the conductive balls 150 can be made of solder, and can be coupled to the interconnect structures (e.g., pads, traces, balls, bumps, etc.) on the bottom surface of the substrate 110. The conductive balls 150 can be later connected to an external circuit to provide a path for inputting electrical signals into the substrate 110 and / or outputting electrical signals from the substrate 110.

[0050] As described above, in the example semiconductor device 100, the metal pillars 130 with fine pitch are positioned (or formed) on the top surface of the substrate 110 and exposed to the outside of the package 140, thereby implementing the fine pitch and providing for the stacking of another semiconductor device on the semiconductor device 100 (or vice versa), while reducing the overall size.

[0051] In an example embodiment, another substrate or insert may be stacked (or formed) on the top side of the semiconductor die 120 and / or the package 140. Examples of such embodiments are provided at Figure 2 and are now described.

[0052] Figure 2 A cross-sectional view of a semiconductor device in accordance with various aspects of the present invention is shown. For example, the example semiconductor device 200 may include a substrate 110, a semiconductor die 120, metal pillars 130, an upper substrate 230, a package 140, and conductive balls 150. Functional components that are the same as those of the Figure 1 example semiconductor device 100 are denoted by the same reference numerals, and the following description will generally focus on the Figure 2 differences between the example semiconductor device 200 and the Figure 1 example semiconductor device 100.

[0053] The upper substrate 230 is positioned along the top surface of the package 140. Additionally, the upper substrate 230 includes a plurality of conductive patterns 231 (or portions thereof) that are exposed from the bottom surface of the upper substrate 230 (or at the bottom surface of the upper substrate 230) to the top surface of the package 140. The upper substrate 230 may be electrically connected to a semiconductor device stacked on the upper substrate 230 via the conductive patterns 231 (or portions thereof) that are exposed from the top surface of the upper substrate 230 (or at the top surface of the upper substrate 230). Additionally, the conductive patterns 231 may be electrically connected to the metal pillars 130 in various regions of the example device 200 (e.g., regions other than the region where the semiconductor die 120 is positioned). For example, the upper substrate 230 may be electrically connected to the substrate 110 via the metal pillars 130.

[0054] As described above, the example semiconductor device 200 may be formed to have a fine pitch pattern (e.g., conductors, pads, traces, pads, etc.) by providing the metal pillars 130 without performing laser drilling (or ablation) on the package 140. Additionally, the example semiconductor device 200 may be configured to provide for the stacking of another semiconductor device on the semiconductor device 200 (or vice versa), for example, by connecting the upper substrate 230 to the metal pillars 130.

[0055] In the following, an exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention will be described. For example, the exemplary method can be used to manufacture any one or all of the exemplary semiconductor devices discussed herein, or any part thereof.

[0056] Figures 3A to 3F Views illustrating an exemplary method of manufacturing a semiconductor device according to various aspects of the present invention are shown.

[0057] Referring to Figure 3A , an exemplary method of manufacturing a semiconductor device according to various aspects of the present invention may include providing (or forming) a metal pillar 130 on a carrier substrate 10, and providing (or forming) an insulating member 20 covering the metal pillar 130. For example, the carrier substrate 10 may include a metal, a dielectric material, a semiconductor material, and the like. For example, the insulating member 20 may be formed by molding, but aspects of the present invention are not limited to this case. For example, the insulating member 20 may be formed by spin coating, vapor deposition, printing, and the like. Additionally, the insulating member 20 may be patterned on the carrier substrate 10, and electroplating or electroless plating may be performed (for example) using the carrier substrate 10 as a seed layer, thereby forming the metal pillar 130. For example, the metal pillar 130 may be made of copper (Cu), aluminum (Al), and the like. For example, the metal pillar 130 may be formed by plating the metal pillar 130 (for example) on a seed layer, on a conductive pattern (such as a pad, a solder pad, a trace, etc.) of the carrier substrate 10, on a seed layer, and the like.

[0058] Referring to Figure 3B , a photoresist 30 (or a photoresist layer) is formed (such as coated, etc.) and patterned on the insulating member 20, and electroplating or electroless plating is performed on the area exposed by the pattern of the photoresist 30, thereby increasing the height of the metal pillar 130. For example, such a plating may be the same material and / or a different material as the metal pillar 130. Moreover, a conductive adhesive member 130a may be further formed on the metal pillar 130 (for example, in addition to adding metal to the metal pillar 130 and / or instead of adding metal to the metal pillar 130). For example, the conductive adhesive member 130a may be made of a general soldering material, but aspects of the present invention are not limited to this case.

[0059] Referring to Figure 3C , the photoresist 30 (or the photoresist layer) and the carrier substrate 10 are removed. For example, the photoresist 30 may be removed by a general ashing process, and the carrier substrate 10 may be removed by grinding (such as tape grinding, etc.), by peeling a tape (if a tape is formed at the interface between the photoresist 30 and the carrier substrate 10), by chemical / mechanical planarization, and the like. Accordingly, the conductive adhesive member 130a formed on the metal pillar 130 and the metal pillar 130 (or a part thereof) may be exposed.

[0060] Refer to Figure 3D , in a state where the conductive adhesive member 130a is flipped to face downward, the metal pillar 130 is coupled to the substrate 110. In an exemplary embodiment, the substrate 110 may be in a state where the semiconductor die 120 is coupled to the substrate 110 before the metal pillar 130, and the conductive adhesive member 130a may be aligned with respect to patterns (e.g., traces, pads, solder pads, etc.) formed on the substrate 110, thereby coupling the metal pillar 130 and the substrate 110 to each other. For example, such coupling may be performed by thermocompression bonding, mass reflow, direct metal-to-metal (e.g., solderless) bonding, conductive adhesives, etc.

[0061] Refer to Figure 3E , the encapsulant 140 (or encapsulation material) may fill the region between the insulating member 20 and the substrate 110 to encapsulate the semiconductor die 120 and the metal pillar 130. The encapsulant 140 may be formed to encapsulate the internal components from at least one side (e.g., from the lateral side, etc.). Additionally, although not shown separately, an underfill may also optionally be formed around the conductive pads 121 of the semiconductor die 120 before the encapsulant 140.

[0062] Additionally, refer to Figure 3E , the insulating member 20 may be removed after the encapsulant 140 is formed. For example, the insulating member 20 may be removed by grinding (e.g., tape grinding, etc.), etching, chemical / mechanical planarization, etc. Thus, the top surface 122 of the semiconductor die 120 may be exposed from the upper portion (e.g., from the upper surface) of the encapsulant 140. In this situation, for example, due to the difference in physical properties when removing the insulating member 20, the metal pillar 130 (e.g., its end surface) may also be exposed from the upper portion of the encapsulant 140 and / or may also protrude upward from the top surface of the encapsulant 140.

[0063] Refer to Figure 3F , conductive balls 150 (or other interconnect structures, e.g., pillars, studs, bumps, etc.) are formed on the bottom surface of the substrate 110. The conductive balls 150 may be formed to correspond to patterns (e.g., traces, solder pads, pads, under bump metallization layers, etc.) on the bottom surface of the substrate 110, thereby providing a path for connection to an external circuit.

[0064] Hereinafter, another manufacturing method of a semiconductor device according to an embodiment of the present invention will be described. For example, the exemplary method may be used to manufacture any one or all of the exemplary semiconductor devices described herein, or any part thereof.

[0065] Figures 4A to 4I Views illustrating a method of manufacturing a semiconductor device according to various aspects of the present invention are shown. For example, the exemplary method may be associated with Figures 3A to 3FThe illustrated example methods share any or all features.

[0066] Refer to Figure 4A and Figure 4B According to various aspects of the present invention, an example method of manufacturing a semiconductor device may include forming a seed layer 11 and a photoresist 12 (or a photoresist layer) on the surface of a carrier substrate 10. For example, the seed layer 11 may be formed of a metal such as copper (Cu) or a metal sheet, but aspects of the present invention are not limited to this case.

[0067] Refer to Figure 4C For example, a pattern is formed in the photoresist 12 by masking. For example, the pattern may be configured to expose an area corresponding to a metal pillar 130 to be formed later.

[0068] Refer to Figure 4D Using the seed layer 11 as a seed, electroplating is performed, thereby forming a plating layer 13. The plating layer 13 may be formed in and / or outside the pattern 12a of the photoresist 12. For example, it may be formed on a portion of the seed layer 11 exposed by the pattern 12a of the photoresist 12. It should be noted that the plating layer 13 may be formed on any of a variety of conductive patterns (e.g., pads, solder pads, traces, etc.). For example, the plating layer 13 may be integrally formed with the conductor on which the plating layer 13 is deposited.

[0069] Refer to Figure 4E The photoresist 12 and the plating layer 13 may be polished (e.g., tape polishing, etc.) or generally thinned. Additionally, the plating layer 13 caused by the polishing may constitute the metal pillar 130. However, this step is performed optionally. If this step is not performed, then the plating layer 13 may be the same as the metal pillar 130.

[0070] Refer to Figure 4F The photoresist 12 may be removed. As described above, for example, the photoresist 12 may be removed by ashing, thereby exposing the seed layer 11 and the metal pillar 130.

[0071] Refer to Figure 4G A conductive adhesive member 130a is formed under the metal pillar 130, and the metal pillar 130 and the substrate 110 may be coupled to each other through the conductive adhesive member 130a. It should be noted that, for example, the conductive adhesive member 130 may be formed on the metal pillar 130 as discussed herein with respect to FIG. 3, may be formed on the substrate 110 before attaching the metal pillar 130, etc. Here, the semiconductor die 120 may be coupled to the substrate 110 before the metal pillar 130. For example, the conductive adhesive member 130a may be aligned with respect to a pattern (e.g., traces, pads, solder pads, etc.) formed on the substrate 110, thereby coupling the metal pillar 130 and the substrate 110 to each other.

[0072] Refer toFigure 4H The encapsulant 140 (e.g., molding material, general dielectric material, etc.) can be formed (e.g., molded, spin-coated, vapor deposited, etc.) to fill the region between the seed layer 11 and the substrate 110, for example, to encapsulate the semiconductor die 120 and the metal pillars 130 (e.g., their lateral surfaces, etc.). For example, the encapsulant 140 can be formed to encapsulate the internal components from at least one side. Additionally, although not shown separately, an individual underfill can also optionally be formed around the conductive pads 121 of the semiconductor die 120 before the encapsulant 140.

[0073] Additionally, referring to Figure 4H After the encapsulant 140 is formed, the carrier substrate 10 and the seed layer 11 can be removed. For example, the insulating member 20 can be removed by grinding (e.g., tape grinding, etc.), etching, chemical / mechanical planarization, general planarization, etc. Thus, the top surface 122 of the semiconductor die 120 can be exposed from the upper portion (e.g., from the upper surface) of the encapsulant 140. In this situation, for example, due to the difference in physical properties when the insulating member 20 is removed, the metal pillars 130 (e.g., their top surfaces) can also be exposed from the upper portion of the encapsulant 140 and / or can also be formed to protrude upward from the top surface of the encapsulant.

[0074] Referring to Figure 4I Conductive balls 150 (or other interconnect structures, e.g., columns, posts, bumps, etc.) are formed on the bottom surface of the substrate 110. The conductive balls 150 can be formed to correspond to a pattern (e.g., traces, pads, pads, under bump metallization layers, etc.) formed on the bottom surface of the substrate 110, thereby providing a path for connection to an external circuit.

[0075] Hereinafter, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described. For example, the example method can be used to manufacture any or all of the example semiconductor devices described herein, or any part thereof.

[0076] Figures 5A to 5F Views illustrating a method of manufacturing a semiconductor device according to various aspects of the present invention are shown. For example, the example method can share any or all features with the Figures 3A to 3F example method illustrated and / or with the Figures 4A to 4I example method illustrated.

[0077] Referring to Figure 5A, an exemplary method of fabricating a semiconductor device according to various aspects of the present invention may include providing (or forming) a conductive pattern 231 (e.g., a trace, a pad, a stud, etc.) and a metal pillar 130 on a carrier substrate 10, and providing (or forming) an insulating member 20 covering the conductive pattern 231 and the metal pillar 130. For example, the insulating member 20 may be formed by molding, but aspects of the present invention are not limited to this case. For example, the insulating member 20 may be formed by spin coating, vapor deposition, printing, etc.

[0078] Additionally, in an exemplary embodiment, the insulating member 20 may be patterned on the carrier substrate 10 first, and electroplating or electroless plating may be performed using the carrier substrate 10 as a seed layer, for example, thereby forming the conductive pattern 231. Next, after patterning the insulating member 20, a plated metal pillar 130 may be formed using the conductive pattern 231 (e.g., a stud, a pad, a trace, etc.) and / or the carrier substrate 10 as a seed layer, for example. For example, the plating layer 13 may be formed integrally with a conductor (e.g., a seed layer, a stud, a pad, a trace, etc.) plated with the plating layer 13.

[0079] See Figure 5B , a photoresist 30 (or a photoresist layer) is formed (e.g., coated, etc.) and patterned on the insulating member 20, and electroplating or electroless plating is performed on the area exposed by the pattern of the photoresist 30, thereby increasing the height of the metal pillar 130. For example, such a plating may be of the same material and / or a different material as the metal pillar 130. Moreover, a conductive adhesive member 130a may be further formed on the metal pillar 130 (e.g., in addition to and / or instead of adding metal to the metal pillar 130). For example, the conductive adhesive member 130a may be made of a general soldering material, but aspects of the present invention are not limited to this case.

[0080] See Figure 5C , the photoresist 30 (or the photoresist layer) and the carrier substrate 10 are removed. For example, the photoresist 30 may be removed by a general ashing process, and the carrier substrate 10 may be removed by grinding (e.g., tape grinding, etc.) or by peeling a tape (if the tape is formed at the interface between the photoresist 30 and the carrier substrate 10), by chemical / mechanical polarization, etc. Thus, the conductive adhesive member 130a formed on the metal pillar 130 and the metal pillar 130 (or a portion thereof) may be exposed. In such a manner, an exemplary upper substrate 230 having the conductive pattern 231 and the metal pillar 130 may be formed. In this step, a portion of the insulating member 20 may also be removed, thereby further exposing the metal pillar 130. In an exemplary embodiment, if the thickness of the insulating member 20 is reduced and the thickness of the photoresist 30 is increased, a relatively large portion of the metal pillar 130 may be exposed by removing the photoresist 30.

[0081] Refer to Figure 5D In the state where the conductive adhesive member 130a is turned over to face downward, the metal posts 130 are coupled to the substrate 110. In an exemplary embodiment, the substrate 110 may be in a state where the semiconductor die 120 is coupled to the substrate 110 before the metal posts 130, and the conductive adhesive member 130a may be aligned relative to the patterns (e.g., traces, pads, solder pads, etc.) formed on the substrate 110, thereby coupling the metal posts 130 and the substrate 110 to each other. For example, such coupling may be performed by thermocompression bonding, mass reflow, direct metal-to-metal (e.g., solderless) bonding, conductive adhesives, etc.

[0082] In addition, refer to Figure 5D such that the conductive pattern 231 of the upper substrate 230 is exposed upward. Thus, semiconductor devices to be stacked in subsequent steps can be easily electrically connected to the conductive pattern 231.

[0083] Refer to Figure 5E such that the encapsulant 140 (or encapsulation material) fills the region between the upper substrate 230 and the substrate 110 to encapsulate the semiconductor die 120 and the metal posts 130. The encapsulant 140 may be formed to encapsulate the internal components from one side (e.g., from the lateral side, etc.). In addition, although not shown separately, an individual underfill may also optionally be formed around the conductive pads 121 of the semiconductor die 120 before the encapsulant 140.

[0084] Refer to Figure 5F such that conductive balls 150 (or other interconnect structures, e.g., pillars, studs, bumps, etc.) are formed on the bottom surface of the substrate 110. The conductive balls 150 may be formed to correspond to the patterns (e.g., traces, solder pads, pads, under bump metallization layers, etc.) on the bottom surface of the substrate 110, thereby providing a path for connection to an external circuit.

[0085] Although the semiconductor device and its manufacturing method according to various aspects of the present invention have been described with reference to certain supporting examples and / or embodiments, those skilled in the art will understand that the scope of the present invention is not limited to the specific examples disclosed, but rather the present invention will include all embodiments, examples, and implementations that fall within the scope of the appended claims.

[0086] The discussions herein include numerous illustrative figures showing various portions of an electronic device assembly and its manufacturing method. For clarity of illustration, such figures do not show all aspects of each exemplary assembly. Any exemplary assembly and / or method provided herein may share any or all features with any or all other assemblies and / or methods provided herein.

[0087] In summary, various aspects of the present invention provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of the present invention provide a stackable semiconductor device having a small size and a fine pitch and a method of manufacturing the same. Although the foregoing has been described with reference to certain aspects and examples, those skilled in the art will understand that various changes can be made and equivalents can be substituted without departing from the scope of the present invention. Additionally, many modifications can be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular examples disclosed, but that the present invention will include all examples falling within the scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate having a top substrate side, a bottom substrate side, and a lateral substrate side extending between the top substrate side and the bottom substrate side; a semiconductor die having a top die side, a bottom die side, and a lateral die side extending between the top die side and the bottom die side, wherein the bottom die side includes a conductive pad that is coupled and electrically connected to the top substrate side by a first adhesive member; a second adhesive member including solder; a metal pillar having a top pillar end, a bottom pillar end, and a lateral pillar side extending between the top pillar end and the bottom pillar end, wherein the second adhesive member electrically couples the bottom pillar end to the top substrate side, and the metal pillar is positioned laterally outside a region of the top substrate side covered by the semiconductor die, and wherein a bottom surface of the second adhesive member is coplanar with a bottom surface of the first adhesive member; and a packaging material that directly contacts and laterally surrounds at least a portion of the lateral die side, at least a portion of the lateral pillar side, and the second adhesive member.

2. The semiconductor device according to claim 1, wherein, the top pillar end is solderless.

3. The semiconductor device according to claim 1, wherein, the metal pillar includes a copper pillar.

4. The semiconductor device according to claim 1, wherein, a width of the metal pillar is in a range of 10 μm to 15 μm.

5. The semiconductor device according to claim 1, including an upper substrate having a top upper substrate side, a bottom upper substrate side coupled to the top die side and coupled to the packaging material, and a lateral upper substrate side extending between the top upper substrate side and the bottom upper substrate side, wherein, the upper substrate includes a conductive pattern coupled to the top pillar end and an insulating member that laterally surrounds the conductive pattern adjacent to the top pillar end.

6. The semiconductor device according to claim 5, wherein, a portion of the conductive pattern is directly vertically above the top die side.

7. The semiconductor device according to claim 5, wherein, the metal pillar is integrally formed with the conductive pattern without an intervening material therebetween, and the top pillar end is completely in contact with and covered by the conductive pattern.

8. The semiconductor device according to claim 7, wherein, the metal pillar is directly plated on the conductive pattern.

9. The semiconductor device according to claim 5, wherein, the packaging material includes a plurality of lateral sides, each of the plurality of lateral sides being coplanar with a respective one of the lateral substrate sides and a respective one of the lateral upper substrate sides.

10. A semiconductor device, comprising: a substrate having a top substrate side, a bottom substrate side, and a lateral substrate side extending between the top substrate side and the bottom substrate side; A semiconductor die having a top die side, a bottom die side, and a lateral die side extending between the top die side and the bottom die side, wherein the bottom die side is coupled to the top substrate side; A metal column having a top column end, a bottom column end, and a lateral column side extending between the top column end and the bottom column end, wherein: The metal column is positioned laterally outside the area of the top substrate side covered by the semiconductor die; At least a portion of the metal column is positioned transversely to the semiconductor die and between the top die side and the bottom die side; The bottom column end is at least as low as at least a portion of the bottom die side; The bottom column end is electrically coupled to the top substrate side with an adhesive member; and The top column end is at least as high as the top die side in the vertical direction; A conductive pattern connected to the top column end; and An insulating member directly contacting the top die side, the insulating member laterally surrounding a lower portion of the conductive pattern adjacent to the top column end, wherein the conductive pattern includes a lower surface exposed from the insulating member and exposed from the metal column, and wherein no portion of the conductive pattern contacts the top die side.

11. The semiconductor device according to claim 10, wherein, The metal column includes a copper-plated column.

12. The semiconductor device according to claim 10, comprising a packaging material that encapsulates at least a portion of the lateral die side and the lateral column side, and contacts and covers at least a portion of the lower surface of the conductive pattern.

13. The semiconductor device according to claim 12, wherein, A portion of the metal column protrudes from the top side of the packaging material.

14. The semiconductor device according to claim 10, wherein, Most of the metal column is lower than the top die side.

15. The semiconductor device according to claim 10, wherein, The insulating member includes a molding that laterally surrounds the conductive pattern.

16. A method of manufacturing a semiconductor device, the method comprising: Providing a first component, the first component including: A first substrate having a top substrate surface and a bottom substrate surface; and A semiconductor die having a top die surface, a bottom die surface, and a lateral die side surface extending between the top die surface and the bottom die surface, wherein the bottom die surface is coupled to the top substrate surface and covers a die-covered area of the top substrate surface; Providing a second component, the second component including: A second substrate having a top substrate surface and a bottom substrate surface; and A plurality of metal columns, each metal column having a top column end, a bottom column end coupled to the bottom substrate surface of the second substrate, and a lateral column surface extending between the top column end and the bottom column end; and Electrically coupling each of the bottom column ends to the top substrate surface of the first substrate at a corresponding position outside the die-covered area with a corresponding adhesive member, wherein after the coupling, there is no gap between the top die surface and the second component.

17. The method according to claim 16, comprising: forming an encapsulation material that encapsulates each of the lateral die side surfaces and each of the lateral pillar surfaces; and after forming the encapsulation material, removing the second substrate.

18. The method according to claim 16, comprising: forming an encapsulation material that encapsulates each of the lateral die side surfaces and each of the lateral pillar surfaces; and after forming the encapsulation material, removing the top portion of the second component such that after removal, the corresponding top pillar ends of each of the metal pillars are coplanar with the top die surface and the top surface of the encapsulation material.

19. The method according to claim 16, wherein: the second component includes an insulating member that covers at least a portion of each of the lateral pillar surfaces; and the insulating member remains as part of the completed semiconductor device.

20. A method of manufacturing a semiconductor device, the method comprising: coupling a bottom side of a semiconductor die to a top side of a substrate; providing a component that includes a base and a plurality of metal pillars extending from the base; coupling the component to the substrate, wherein a first pillar end of each of the plurality of metal pillars is attached to the top side of the substrate at a position laterally outside of a region of the top side of the substrate covered by the semiconductor die; forming an encapsulant between the base and the top side of the substrate, the encapsulant laterally surrounding the semiconductor die and a lateral pillar side of each of the plurality of metal pillars; and removing the base of the component to expose a second pillar end of each of the plurality of metal pillars from the encapsulant.

21. The method according to claim 20, wherein coupling the component to the substrate includes coupling a first pillar end of each of the plurality of metal pillars to the top side of the substrate with an adhesive member.

22. The method according to claim 21, wherein the adhesive member includes solder.

23. The method according to claim 20, wherein the base includes a metal layer.

24. The method according to claim 23, wherein the metal layer includes copper.

25. The method according to claim 20, wherein the base includes an insulating member.

26. The method according to claim 25, wherein before removing the base, the insulating member contacts the top side of the encapsulant and the top side of the semiconductor die.

27. The method according to claim 20, wherein the encapsulant includes a molding material.

28. The method according to claim 20, wherein removing the base of the component includes grinding the base of the component.

29. The method according to claim 20, further comprising: forming an interconnect structure on the bottom side of the substrate.

30. A semiconductor device, comprising: a substrate having a top substrate side, a bottom substrate side, and a lateral substrate side extending between the top substrate side and the bottom substrate side; A semiconductor die having a top die side, a bottom die side, and a lateral die side extending between the top die side and the bottom die side, wherein the bottom die side is coupled to the top substrate side; A metal post having a top post end, a bottom post end, and a lateral post side extending between the top post end and the bottom post end, wherein: At least a portion of the metal post is positioned directly transverse to the semiconductor die; The bottom post end is coupled to the top substrate side with an adhesive member including solder; An encapsulation material adjacent to the lateral die side and the lateral post side in a lateral direction; and A mold material directly contacting the widest portion of the lateral post side, wherein the mold material directly contacts the encapsulation material.

31. The semiconductor device according to claim 30, wherein, The bottom post end is lower than the bottom die side.

32. The semiconductor device according to claim 30, wherein, A portion of the encapsulation material is directly vertically located between the top substrate side and the bottom die side.

33. The semiconductor device according to claim 30, wherein, The encapsulation material directly contacts and laterally surrounds the adhesive member.

34. The semiconductor device according to claim 30, wherein, At least the bottom side of the mold material directly contacts the encapsulation material.

35. The semiconductor device according to claim 30, wherein, The top post end is solderless.

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