Power amplifier, radio frequency module and electronic equipment

Abstract

The embodiment of the invention provides a power amplifier, a radio frequency module and electronic equipment. The power amplifier comprises a signal input end, a signal output end and a plurality of tube cores which are connected in parallel; the tube core comprises electrode finger strips extending along a first direction, and the electrode finger strips comprise a grid electrode finger strip, a source electrode finger strip and a drain electrode finger strip; in the second direction, the signal input end and the signal output end are located on the two sides of the multiple tube cores respectively, and the second direction is perpendicular to the first direction. The extension direction of the electrode finger strips is perpendicular to the signal input / output direction, so that the performance of the electrode finger strips can be optimized to the maximum extent and the requirement of high power can be met under the limited layout area, and the flexible possibility is created for the circuit architecture design.

Description

Technical Field

[0001] The present application relates to the field of communication technologies, and in particular, to a power amplifier, a radio frequency module, and an electronic device. Background Art

[0002] Power amplifiers are widely used in the field of radio frequency wireless communication. The mainstream power amplifiers adopted in the current communication industry include types such as LDMOS (Laterally Diffused Metal Oxide Semiconductor) process, high-voltage (28v / 48v) GaN (gallium nitride) process, and GaAs (gallium arsenide) material process. Among them, the GaAs material process includes HBT (Heterojunction bipolar transistor) process and pHEMT (Pseudomorphic High electron mobility transistor) process. In the base station scenario, the LDMOS and high-voltage GaN processes are mainly used. In the terminal scenario, the GaAs HBT process is mostly applied. At present, there are also related studies on the application of low-voltage new GaN processes in the terminal scenario.

[0003] With the development of technology, the power demand of products is getting higher and higher. Under the high-power demand, the layout structure of traditional power amplifiers will occupy a large space and cannot meet the requirements of the design space. Summary of the Invention

[0004] In view of this, the present application provides a power amplifier, a radio frequency module, and an electronic device to solve the problem that the layout structure of traditional power amplifiers in the prior art will occupy a large space under high-power demand.

[0005] In a first aspect, an embodiment of the present application provides a power amplifier, including a signal input end, a signal output end, and a plurality of die connected in parallel; the die includes electrode finger bars extending along a first direction, and the electrode finger bars include gate finger bars, source finger bars, and drain finger bars; in a second direction, the signal input end and the signal output end are respectively located on both sides of the plurality of die, and the second direction is perpendicular to the first direction.

[0006] In the power amplifier provided by the embodiment of the present application, the extending direction of the electrode finger bars is perpendicular to the signal input / output direction. Thus, the die can be connected in parallel in the second direction of the signal input / output to increase the total gate width, or the die can be connected in parallel in the first direction of the extension of the electrode finger bars to increase the total gate width. It can make full use of the space in the second direction and reduce the length occupied in the first direction. Compared with the traditional device layout method, it is not necessary to sacrifice the optimal electrical performance of the electrode finger bars to reduce the occupation of the first direction. The power amplifier provided by the embodiment of the present application can be applied to high-voltage GaN-based devices and can also be applied to low-voltage GaN-based devices. It can optimize the performance of the electrode finger bars to the greatest extent and meet the requirements of high power under a limited layout area, and creates flexible possibilities for the circuit architecture design.

[0007] The power amplifier includes a gate lead connected to the signal input end and a drain lead connected to the signal output end. The gate finger bars are connected to the gate lead, and the drain finger bars are connected to the drain lead. A plurality of dies arranged in the second direction form a die row. The plurality of dies in one die row share one drain lead and one gate lead, thus realizing the parallel connection of the plurality of dies.

[0008] In some embodiments, it is set that the die row is located between adjacent drain leads and gate leads. Using the die row to separate the drain lead and the gate lead can avoid the signal of the drain lead from coupling with the signal of the gate lead, which may cause the power amplifier to fail to output normally, and thus can ensure the normal operation of the power device.

[0009] In some embodiments, the power amplifier includes at least one structure group. The structure group includes two die rows adjacent in the first direction. The two die rows in the structure group share one gate lead or one drain lead, realizing flexible wiring of the gate lead and the drain lead.

[0010] In some embodiments, the number of dies in the two die rows in the structure group is equal. With such a setting, the space in the second direction can be reasonably utilized to avoid space waste. And it can make the arrangement of multiple dies in the power amplifier regular, so the arrangement of the electrode finger bars is regular, which is beneficial to the etching uniformity.

[0011] In some embodiments, the power amplifier includes n structure groups connected in parallel. The n structure groups are arranged in the first direction, where n is a positive integer and n≥2. When designing the layout of the device, after setting a certain number of dies in the die row, the total gate width can be increased by increasing the number of structure groups to meet the power requirements and balance the space occupied by the overall device in the first direction and the second direction.

[0012] In some embodiments, in a die row, adjacent dies share drain fingers and / or share source fingers. The first end of the gate lead is connected to the signal input terminal, the second end is connected to the gate fingers, the first end of the drain lead is connected to the drain fingers, and the second end is connected to the signal output terminal. The first ends of at least two gate leads respectively electrically connected to two adjacent structural groups are electrically connected, and the second ends of at least two drain leads respectively electrically connected to two adjacent structural groups are electrically connected. When the number of dies in the die row is fixed, the design of the embodiment of the present application can reduce the length occupied by the die row in the second direction and save the layout space of the power amplifier. In addition, when it is necessary to further save the space in the first direction y, the number of dies in the die row can be appropriately increased to meet the high-power requirements.

[0013] In some embodiments, in at least one die row: two sets of electrode fingers of at least two dies are arranged in a staggered manner in the second direction. Such an arrangement can disperse the heat dissipation distribution in the device, reduce local hot spots, and improve the overall performance reliability of the system in applications.

[0014] In some embodiments, at least one die row includes a first die, a second die, and a third die. The second die is located between the first die and the third die. The first die and the second die are adjacent. There are m dies between the third die and the second die, where m is an integer and m≥0. Two sets of electrode fingers of the first die and the second die are arranged in a staggered manner in the second direction, and two sets of electrode fingers of the second die and the third die are arranged in a staggered manner in the second direction. Moreover, the electrode fingers of the first die and the electrode fingers of the third die are offset in the same direction relative to the electrode fingers of the second die. Such an arrangement can not only disperse the heat dissipation distribution in the device, but also minimize the width of the die row in the first direction to meet the requirements of high-power devices for layout space. In addition, it can also minimize the current phase difference between different dies and ensure the device performance.

[0015] In some embodiments, the power amplifier includes microstrip lines. The microstrip lines include a first microstrip line and a second microstrip line. At least one die row includes a fourth die and a fifth die. Two sets of electrode fingers of the fourth die and the fifth die are arranged in a staggered manner in the second direction. Along the first direction, the distance between the electrode fingers of the fourth die and the drain lead is greater than the distance between the electrode fingers of the fifth die and the drain lead. The drain fingers of the fourth die are electrically connected to the drain lead through the first microstrip line, and the gate fingers of the fifth die are electrically connected to the gate lead through the second microstrip line. The setting of the first microstrip line and the second microstrip line can reduce the phase difference of the output signals of the fourth die and the fifth die, make the phases as consistent as possible, thereby improving the synthesis effect of the output signals of each parallel die and enhancing the device performance.

[0016] In some embodiments, the lengths of the electrode fingers of at least two of the multiple die are not equal. With this arrangement, the difference in the signal transmission paths between different die can be compensated, and further, the phase difference of the output signals of different die can be balanced, so that the final current synthesis reaches the optimal output state, thereby improving the overall electrical performance of the device.

[0017] In some embodiments, the multiple die include a sixth die and a seventh die, and the length of the electrode fingers of the sixth die is greater than that of the electrode fingers of the seventh die; the power amplifier includes a microstrip line; the microstrip line includes a third microstrip line, and the third microstrip line is electrically connected to the gate fingers of the seventh die; and / or, the microstrip line includes a fourth microstrip line, and the fourth microstrip line is electrically connected to the drain fingers of the seventh die. By using the microstrip line, the phase difference of the output signals of the seventh die and the sixth die can be balanced, so that the final current synthesis reaches the optimal output state, thereby improving the overall electrical performance of the device.

[0018] In a second aspect, based on the same inventive concept, an embodiment of the present application further provides a radio frequency module, including the power amplifier provided in any embodiment of the present application.

[0019] In a third aspect, based on the same inventive concept, an embodiment of the present application further provides an electronic device, including the radio frequency module provided in any embodiment of the present application.

[0020] The power amplifier, radio frequency module, and electronic device provided in the embodiments of the present application have the following beneficial effects: By setting the extending direction of the electrode fingers perpendicular to the signal input / output direction, it is possible to parallel the die in the second direction of the signal input / output to increase the total gate width, and it is also possible to parallel the die in the first direction in which the electrode fingers extend to increase the total gate width. The space in the second direction can be fully utilized, and the length occupied in the first direction can be reduced. Compared with the traditional device layout method, it is not necessary to sacrifice the optimal electrical performance of the electrode fingers to reduce the occupation of the first direction. The power amplifier provided in the embodiments of the present application can optimize the performance of the electrode fingers to the maximum extent and meet the requirements of high power under a limited layout area, and creates flexible possibilities for the circuit architecture design. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0022] Figure 1 It is a stacked structure diagram of a GaN device in the prior art;

[0023] Figure 2It is a stack structure diagram of a GaAs HBT device in the prior art;

[0024] Figure 3 It is a stack structure diagram of a GaN device provided by an embodiment of the present application;

[0025] Figure 4 It is a schematic structural diagram of a power amplifier in the prior art;

[0026] Figure 5 It is a schematic diagram of a power amplifier provided by an embodiment of the present application;

[0027] Figure 6 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0028] Figure 7 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0029] Figure 8 It is a comparison schematic diagram of a power amplifier provided by an embodiment of the present application and a traditional power amplifier;

[0030] Figure 9 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0031] Figure 10 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0032] Figure 11 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0033] Figure 12 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0034] Figure 13 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0035] Figure 14 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0036] Figure 15 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0037] Figure 16 It is another schematic diagram of a power amplifier provided by an embodiment of the present application;

[0038] Figure 17 It is a schematic diagram of a circuit architecture provided by an embodiment of the present application. Detailed implementation manners

[0039] To better understand the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0040] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0041] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0042] It should be understood that the term "and / or" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0043] Figure 1 It is a stacked structure diagram of a GaN device in the prior art. Figure 1 The GaN device in it is a high-voltage GaN device. As Figure 1 shown, the high-voltage GaN device includes an AlN (aluminum nitride) transition layer 012, an AlGaN (aluminum gallium nitride) buffer layer 013, a GaN channel layer 014, an AlGaN barrier layer 015 stacked on a SiC / Si (silicon carbide / silicon) substrate 011, as well as a gate 016, a source 017 and a drain 018. Due to the piezoelectric effect, a two-dimensional electron gas is formed in the GaN channel layer 014 along the interface between the GaN channel layer 014 and the AlGaN barrier layer 015 to conduct electricity, and the two-dimensional electron gas serves as a conductive channel between the source 017 and the drain 018. From Figure 1 it can be seen that a gate field plate 0161 connected to the gate 016 and a source field plate 0171 connected to the source 017 are also provided in the high-voltage GaN device. The field plate is an important part of the high-voltage GaN device, and its function is to control the charge distribution and the electric field distribution.

[0044] Figure 2 It is a stacked structure diagram of a GaAs HBT device in the prior art. As Figure 2As shown, the GaAs HBT device includes an n+ GaAs sub-collector region 022, an n GaAs collector region 023, a p+ GaAs base region 024, an n InGaP (indium gallium phosphide) layer 025, an n+ GaAs layer 026, as well as a base 027, an emitter 028, and a collector 029, which are stacked on a GaAs substrate 021. The GaAs HBT device is a vertical current device.

[0045] Currently, high-voltage GaN devices are mainly applied to base station scenarios, such as high-voltage (28V / 48V) GaN process devices, while GaAs HBT devices are mainly applied to terminal scenarios. However, GaAs HBT devices have disadvantages in thermal reliability in terminal scenarios. Embodiments of this application provide a low-voltage GaN power amplifier device for application in terminal scenarios. Terminal products can be, for example, portable electronic devices such as mobile phones, tablets, and smart wearable products (such as watches). The operating voltage (i.e., the drain voltage) of the low-voltage GaN power amplifier device provided by the embodiments of this application is Vo, where Vo ≤ 15V. In some embodiments, Vo ≤ 12V. Optionally, Vo ≥ 3V.

[0046] Figure 3 It is a stack structure diagram of a GaN device provided by an embodiment of this application. Figure 3 The GaN device in it is a low-voltage GaN device, such as Figure 3As shown, the low-voltage GaN device sequentially includes an SiC / Si substrate 031, an AlN transition layer 032, an AlGaN buffer layer 033, a GaN channel layer 034, an AlGaN barrier layer 035, as well as a gate 036, a source 037, and a drain 038. Optionally, the low-voltage GaN device further includes a nucleation layer located between the SiC / Si substrate 031 and the AlN transition layer 032. The nucleation layer has a lattice structure and / or a coefficient of thermal expansion, and the nucleation layer is suitable for bridging the lattice misalignment and / or the coefficient of thermal expansion mismatch between the substrate layer and the upper layer. Optionally, the low-voltage GaN device further includes an AlN insertion layer located between the GaN channel layer 034 and the AlGaN barrier layer 035. Optionally, the low-voltage GaN device further includes a GaN cap layer located on the side of the AlGaN barrier layer 035 away from the GaN channel layer 034. The low-voltage GaN device utilizes the piezoelectric effect to form a two-dimensional electron gas in the GaN channel layer 034 for conduction. The low-voltage GaN device provided by the embodiments of the present application can be fabricated by the following process: First, an SiC / Si substrate is provided, which has a high-resistance property, a sheet resistance > 5 kohm·cm, and a thickness of 50 μm to 300 μm; then, an AlN / AlGaN multi-layer structure is grown on the substrate to form a nucleation layer, a transition layer, and a buffer layer, and the total thickness of the nucleation layer, the transition layer, and the buffer layer is about 300 nm to 2 μm; then, a GaN channel layer and an AlN insertion layer are grown, and the total thickness is about 100 nm to 500 nm; then, a barrier layer and a cap layer are grown, and the total thickness is about 5 to 30 nm; finally, a gate, a source, and a drain are fabricated. The fabrication processes of the gate, the source, and the drain include, but are not limited to, evaporation, electroplating, sputtering, etc. The metals used for fabricating the gate, the source, and the drain include one or more combinations of elements such as Ti (titanium), Al, Ni (nickel), Au (gold), Pt (platinum), etc.

[0047] Comparison Figure 2 and Figure 3 It can be seen that the low-voltage GaN device and the GaAs HBT device have completely different physical structures. From Figure 1 and Figure 3 It can also be seen that there are also certain differences in the structures of the low-voltage GaN device and the high-voltage GaN device. For example, the low-voltage GaN device does not need to be provided with a field plate structure. In addition, the distance Lds between the source and the drain in the low-voltage GaN device is ≤ 3 μm, and the thickness of the barrier layer is about 5 nm to 20 nm. While in the high-voltage GaN device, the distance Lds between the source and the drain is ≥ 5 μm, and the thickness of the barrier layer is about 25 nm to 35 nm. That is, the size of the low-voltage GaN device is generally smaller than that of the high-voltage GaN device. Although there are differences in their sizes, the electrode layout of the low-voltage GaN power amplifier device can be designed with reference to the traditional high-voltage GaN power amplifier device.

[0048] Figure 4It is a schematic structural diagram of a power amplifier in the prior art. Figure 4 It shows a top view schematic diagram. As Figure 4 shown, in a traditional power amplifier structure, there are multiple die 03 connected in parallel. The die 03 includes gate fingers 031, source fingers 032, and drain fingers 033. The gate fingers 031, source fingers 032, and drain fingers 033 all extend along the first direction a. The multiple die 03 are arranged in the second direction b and connected in parallel. The first direction a is perpendicular to the second direction b. The die 03 is the basic unit in the power amplifier, and by connecting the die 03 in parallel, a larger current or power can be synthesized. Figure 4 The arrow in it indicates the signal flow direction. The signal is input from the left and output from the right, that is, the signal flow direction of the power amplifier is from left to right. In other words, the signal input / output direction is the first direction a. Figure 4 In it, the extension direction of each electrode finger is parallel to the signal input / output direction.

[0049] When designing a power amplifier, the total gate width is equivalent to the power, that is, the larger the designed total gate width, the greater the power. The width of the gate finger in the power amplifier is the gate length, and the length of the gate finger is the gate width. In Figure 4 the gate width is the length of the gate finger 031 in the first direction a, and the total gate width is the product of the number of gate fingers 031 and the length of the gate finger 031. And Figure 4 this traditional device layout method has the following problems in high-power applications: when the length of a single gate finger 031 is fixed, more die 03 need to be connected in parallel in the second direction b to meet the high-power requirements, which will cause the device to occupy a large length in the second direction b (i.e., the direction perpendicular to the signal input / output direction). When the space of the module system is limited, it is difficult to layout the power amplifier; when the number of die 03 connected in parallel is fixed, increasing the length of a single gate finger 031 can meet the requirement of the total gate width, but since the longer the length of the gate finger 031, the greater the loss, increasing the length of the gate finger 031 may miss the optimal finger length for electrical performance, resulting in serious power loss. It can be seen that the traditional device layout method cannot meet the requirements of layout space and the optimal electrode finger length at the same time under high-power requirements. Especially when considering manufacturing a low-voltage GaN power amplifier device for use in terminal products, the requirement for the miniaturization of the power amplifier device size is relatively high.

[0050] To solve the problems existing in the layout method of the traditional power amplifier in high-power applications, the embodiment of the present application provides a solution. By setting the extension direction of the electrode finger to be perpendicular to the signal transmission direction and reasonably using the layout space in two directions, the performance of the electrode finger can be optimized to the greatest extent under the condition of a limited layout area, and the requirements of layout space and the optimal finger length can be met in high-power applications.

[0051] Figure 5 Schematic diagram of a power amplifier provided by an embodiment of the present application. As Figure 5 shown, the power amplifier includes a signal input terminal 10, a signal output terminal 20, and a plurality of die 30 connected in parallel; the die 30 includes a set of electrode finger bars 40 extending along a first direction y, and the electrode finger bars 40 include gate finger bars 41, source finger bars 42, and drain finger bars 43; a plurality of die 30 arranged along a second direction x form a die row 30H, and the second direction x is perpendicular to the first direction y. The term "perpendicular to each other" as used in the present application means approximately perpendicular to each other. For example, if the angle between the first direction y and the second direction x satisfies the range of [95°, 105°], it is considered that the two are perpendicular to each other. Among them, the width of the gate finger bar 41 is smaller than the widths of the source finger bar 42 and the drain finger bar 43, Figure 5 and the gate finger bar 41 is only schematically shown by thin black lines.

[0052] In the second direction x, the signal input terminal 10 and the signal output terminal 20 are respectively located on both sides of the plurality of die 30. Figure 5 schematically shows that the signal in the power amplifier is input from the left and output from the right, that is, the signal input / output direction is the second direction x.

[0053] Figure 5 is a top view schematic diagram of the power amplifier. As Figure 5 shown, the "electrode finger bar extending along the first direction y" means that the length direction of the electrode finger bar 40 is the first direction y, and correspondingly, the width direction of the electrode finger bar 40 is the second direction x; "in the second direction x, the signal input terminal 10 and the signal output terminal 20 are respectively located on both sides of the plurality of die 30" means that the signal input terminal 10 and the signal output terminal 20 are respectively arranged on both sides of the plurality of die 30 in the second direction x; in some embodiments, a non-zero angle is formed between the virtual connection line between the signal input terminal 10 and the signal output terminal 20 and the second direction x; in another embodiment, the virtual connection line between the signal input terminal 10 and the signal output terminal 20 is in the second direction x; the "plurality of die 30 arranged along the second direction x" means that the die 30 are arranged at intervals in the second direction x. Specifically, the width direction of the electrode finger bar 40 in the die 30 is the second direction x, or it can be said that the width direction of the die 30 is the second direction x.

[0054] As Figure 5As shown, the power amplifier further includes a gate lead 51 and a drain lead 52. Among them, the gate finger 41 is connected to the signal input terminal 20 through the gate lead 51, and the drain finger 43 is connected to the signal output terminal 20 through the drain lead 52. The signal input from the signal input terminal 10 enters the gate fingers 41 of multiple parallel die 30 through the gate lead 51, and then the signals output from the drain fingers 43 of the multiple die 30 are merged through the drain lead 52 and output by the signal output terminal 20.

[0055] In the power amplifier provided by the embodiment of the present application, the extending direction of the electrode finger 40 is set perpendicular to the signal input / output direction. It is possible to parallel the die 30 in the second direction x of the signal input / output to increase the total gate width, or parallel the die 30 in the first direction y in which the electrode finger 40 extends to increase the total gate width. With such a setting, the space in the second direction x can be fully utilized, and the length occupied in the first direction y (i.e., the direction perpendicular to the signal input / output direction) can be reduced. And compared with the traditional device layout method, it is not necessary to sacrifice the best electrical performance of the electrode finger 40 to reduce the occupation of the first direction y. The embodiment of the present application can optimize the performance of the electrode finger to the maximum extent and meet the requirements of high power under a limited layout area, and creates flexible possibilities for the circuit architecture design.

[0056] In some embodiments, as Figure 5 shown, multiple die 30 in one die row 30H share one drain lead 52 and one gate lead 51. That is, multiple drain fingers 43 in the same die row 30H are connected to the same drain lead 52, and multiple gate fingers 41 are connected to the same gate lead 51, so as to realize the parallel connection of multiple die 30.

[0057] Optionally, both the gate lead 51 and the drain lead 52 extend along the second direction x. The linear shapes of the gate lead 51 and the drain lead 52 are not limited to straight lines, and their linear shapes can also be broken lines or curves. Setting the extending directions of the drain lead 52 and the gate lead 51 to cross the extending direction of the electrode finger 40 can facilitate the connection between the gate finger 41 and the gate lead 51, and also facilitate the connection between the drain finger 43 and the drain lead 52, which is beneficial to reducing the winding length of the leads and saving space.

[0058] In some embodiments, as Figure 5 shown, the die row 30H is located between adjacent drain lead 52 and gate lead 51. In other words, there is a die row 30H spaced between adjacent drain lead 52 and gate lead 51. Separating the drain lead 52 and the gate lead 51 can prevent the signal of the drain lead 52 from coupling to the signal of the gate lead 51, which may cause the power amplifier to fail to output normally, thereby ensuring the normal operation of the power device.

[0059] As Figure 5 shown, in the die row 30H, adjacent dies 30 share the drain finger bars 43 or the source finger bars 42. When the number of dies 30 in the die row 30H is fixed, the design of the embodiment of the present application can reduce the length occupied by the die row 30H in the second direction x and save the layout space of the power amplifier. In addition, when it is necessary to further save the space in the first direction y, the number of dies 30 in the die row 30H can be appropriately increased to meet the high-power requirements.

[0060] In some embodiments, the power amplifier includes a structure group. One structure group includes two die rows 30H. Since the signal input / output direction is the second direction x, it is easy to arrange the leads so that the die rows 30H in the structure group are connected in parallel. That is, multiple dies 30 in the structure group are connected in parallel. As Figure 5 shown, the structure group 60 includes two die rows 30H adjacent in the first direction y. The two die rows 30H in the structure group 60 share a gate lead 51. In the first direction y, two drain leads 52 are respectively located on both sides of the structure group 60. In this embodiment, the signal is input by the gate lead 51 located in the middle of the two die rows 30H, and then the output signal is synthesized by the upper and lower sides of the structure group 60 and output.

[0061] In some other embodiments, the two die rows in the structure group share a drain lead. Figure 6 Another schematic diagram of the power amplifier provided by the embodiment of the present application, as Figure 6 shown, the structure group 60 includes two die rows 30H adjacent in the first direction y. The two die rows 30H in the structure group 60 share a drain lead 52. In the first direction y, two gate leads 51 are respectively located on both sides of the structure group 60. In this embodiment, the signal is input by the gate leads 51 located on the upper and lower sides of the structure group 60, and then the output signal is synthesized between the two die rows 30H and output.

[0062] As Figure 5 or Figure 6 shown, the number of dies 30 in the two die rows 30H in the structure group 60 is equal. With such a setting, the space in the second direction x can be reasonably utilized to avoid space waste. And it can make the arrangement of multiple dies 30 in the power amplifier regular, so that the electrode finger bars 40 are arranged regularly, which is beneficial to the etching uniformity.

[0063] In some embodiments, the power amplifier includes n structure groups 60 connected in parallel. The n structure groups 60 are arranged along the first direction y, and n is a positive integer and n≥2. Taking n = 4 as an example, Figure 7 Another schematic diagram of the power amplifier provided by the embodiment of the present application. As Figure 7As shown, the power amplifier includes four structural groups 60 connected in parallel. Each structural group 60 includes two rows of dies 30H. Each row of dies 30H includes four dies 30 connected in parallel. Then each structural group 60 includes eight dies 30, and the power amplifier includes a total of 32 dies 30. When performing layout design on the device, after setting a certain number of dies 30 in the row of dies 30H, the total gate width can be increased by increasing the number of structural groups 60 to meet the power requirements and balance the space occupied by the overall device in the first direction y and the second direction x.

[0064] It can be seen from Figure 7 that the first end of the gate lead 51 is connected to the signal input terminal 10, and the second end is connected to the gate finger 41. The first end of the drain lead 52 is connected to the drain finger 43, and the second end is connected to the signal output terminal 20. The first ends of at least two gate leads 51 respectively electrically connected to two adjacent structural groups 60 are electrically connected, and the second ends of at least two drain leads 52 respectively electrically connected to two adjacent structural groups 60 are electrically connected, thus realizing the parallel connection of two adjacent structural groups 60. Figure 7 shows that two rows of dies 30H in a structural group 60 share one gate lead 51. That is, one gate lead 51 and two drain leads 52 need to be set for a structural group 60, and the first ends of the two gate leads 51 respectively corresponding to two adjacent structural groups 60 are electrically connected. Figure 7 shows that two adjacent structural groups 60 share one drain lead 52 and two other drain leads 52 each for their own use. That is, the second ends of two drain leads 52 respectively electrically connected to two adjacent structural groups 60 are electrically connected. In some other embodiments, it may be that two adjacent structural groups 60 do not share the drain lead 52, then two drain leads 52 are respectively set for each structural group 60, and the second ends of the four drain leads 52 respectively electrically connected to two adjacent structural groups 60 are electrically connected.

[0065] Figure 8 This is a schematic diagram for comparing a power amplifier provided by an embodiment of the present application with a traditional power amplifier. Figure 8 In Figure A is a schematic layout diagram of a power amplifier provided by an embodiment of the present application, and Figure B is a schematic layout diagram of a traditional power amplifier. Taking each structural group 60 including eight dies 30 as an example, the length of the gate finger 41 is 125 μm, that is, the single-finger gate width is 125 μm, and the total gate width is 4 mm. Both Figure A and Figure B include four structural groups 60. In Figure A, the gate lead 51 and the drain lead 52 extend along the second direction x, and in Figure B, the gate lead 51 and the drain lead 52 extend along the first direction y. The other process conditions (such as gate length, source-drain spacing, etc.) of Figure A and Figure B are the same. Figure 8In the figure, an arrow indicates the signal transmission direction, and it can be understood that the signal is input from the left and output from the right. In the traditional power amplifier layout, the extending direction of the electrode finger bars is parallel to the signal input / output direction, while in the embodiment of the present application, the extending direction of the electrode finger bars 40 is perpendicular to the signal input / output direction. By comparing Figure A and Figure B, it can be seen that when the total gate width is the same, the design of the embodiment of the present application makes proper use of the space in the second direction x and can reduce the space occupied by the device in the first direction y.

[0066] Figure 8 In Figure A of the present application, taking a single die row including 4 dies 30 as an example, in order to meet the requirement of the total gate width, more dies 30 can be further connected in parallel in the die row. Figure 9 Another schematic diagram of a power amplifier provided by the embodiment of the present application is as Figure 9 shown. A die row 30H includes 8 dies 30, and 2 structural groups 60 are arranged along the first direction y. When Figure 9 the length of the electrode finger bars 50, the spacing between the source finger bars 42 and the drain finger bars 43, and other process conditions are the same as those in Figure 8 Figure A of the present application, Figure 9 it can also meet the design requirement of the total gate width. Figure 9 Compared with the design of Figure 8 Figure A of the present application, the embodiment can further save 50% of the space in the first direction y. Adopting the design of Figure 9 the embodiment can make the device arrangement more compact, appropriately increase the space occupied by the device in the second direction x, and can reduce the number of structural groups 60 connected in parallel in the first direction y, thereby further reducing the space occupied by the device in the first direction y.

[0067] In some embodiments, two groups of electrode finger bars 40 of at least two dies 30 in at least one die row 30H are arranged in a staggered manner in the second direction x. Among them, the two dies 30 with the electrode finger bars 40 arranged in a staggered manner can be adjacent or not adjacent.

[0068] Figure 10 Another schematic diagram of a power amplifier provided by the embodiment of the present application is as Figure 10 shown. At least one die row 30H includes a first die 31 and a second die 32; in the second direction x, the electrode finger bars 40 of the first die 31 and the electrode finger bars 40 of the second die 32 are arranged in a staggered manner. That is, the electrode finger bars 40 of the first die 31 and the electrode finger bars 40 of the second die 32 are not aligned in the second direction x. Such an arrangement can disperse the heat dissipation distribution in the device, reduce local hot spots, and can increase the overall performance reliability of the system in application.

[0069] In the electrode fingers 40, the lengths of the gate fingers 41, source fingers 42, and drain fingers 43 are substantially equal. Two sets of electrode fingers 40 of adjacent two dies 20 are arranged in a staggered manner in the second direction x, and the staggering length of the two sets of electrode fingers 40 in the first direction y is L, and L is not greater than half of the length of the electrode fingers 40. On the one hand, it can avoid the large length of a single die row 30H in the first direction y, which affects the space occupied by the device in the first direction y; on the other hand, it can avoid the excessive signal phase difference between adjacent dies 30, which affects the synthesis effect of the output signal.

[0070] Figure 10 Taking the example that two die rows 30H in a structure group 60 share a gate lead 51. In some other embodiments, Figure 11 Another schematic diagram of the power amplifier provided by the embodiment of the present application is shown in Figure 11 As shown, two die rows 30H in the structure group 60 share a drain lead 52, and two sets of electrode fingers 40 of at least two dies 30 in at least one die row 30H are arranged in a staggered manner in the second direction x.

[0071] As shown in Figure 10 At least one die row 30H includes a first die 31, a second die 32, and a third die 33. The second die 32 is located between the first die 31 and the third die 33. The first die 31 and the second die 32 are adjacent, and there are m dies between the third die 33 and the second die 32. m is an integer and m≥0; Figure 10 Taking m = 0 as an example. Two sets of electrode fingers 40 of the first die 31 and the second die 32 are arranged in a staggered manner in the second direction x. Two sets of electrode fingers 40 of the second die 32 and the third die 33 are arranged in a staggered manner in the second direction x, and the electrode fingers 40 of the first die 31 and the electrode fingers 40 of the third die 33 are offset in the same direction relative to the electrode fingers 40 of the second die 32. In other words, two sets of electrode fingers 40 of the first die 31 and the third die 33 are offset in a direction away from the drain lead 52 connected to these three dies 30 relative to the electrode fingers 40 of the second die 32. Or rather, the electrode fingers 40 of the second die 32 are offset in a direction away from the gate lead 52 connected to these three dies 30 relative to two sets of electrode fingers 40 of the first die 31 and the third die 33.

[0072] In Figure 10As can be seen from the top - down layout diagram, the electrode finger bars 40 of the second die 32 are offset upward relative to the two sets of electrode finger bars 40 of the first die 31 and the third die 33. Considering that if the electrode finger bars 40 of the second die 32 are offset upward relative to the electrode finger bars 40 of the first die 31, and the electrode finger bars 40 of the third die 33 are offset upward relative to the electrode finger bars 40 of the second die 32, it will not only cause the width of the die row 30H where these three dies 30 are located to become larger in the first direction y, affecting the overall size of the device, but also cause the phase difference of the current signals in these three dies 30 to become larger, affecting the device performance. The design of the embodiment of the present application can not only disperse the heat dissipation distribution in the device, but also minimize the width of the die row 30H in the first direction y to meet the requirements of the layout space for high - power devices. In addition, it can also minimize the current phase difference between different dies 30 to ensure the device performance.

[0073] In some embodiments, as Figure 10 shown, the two sets of electrode finger bars 40 of any two adjacent dies 30 in the die row 30H are stagger - arranged in the second direction x, and the electrode finger bars 40 of the odd - numbered dies 30 are offset and misaligned in the same direction relative to the electrode finger bars 40 of the even - numbered dies 30. Such an arrangement can make the heat dissipation in the device more dispersed and further improve the performance reliability of the device.

[0074] In other embodiments, Figure 12 is another schematic diagram of a power amplifier provided by the embodiment of the present application. As Figure 12 shown, there are two sets of electrode finger bars 40 of two adjacent dies 30 in the die row 30H that are stagger - arranged in the second direction x, and there are also two sets of electrode finger bars 40 of two adjacent dies 30 that are aligned in the second direction x. Among them, the number of continuously aligned dies 30 is two or more.

[0075] Figure 12 The two adjacent and aligned dies 30 shown in do not share common electrode finger bars. In other embodiments, there are two sets of electrode finger bars 40 of two adjacent dies 30 in the die row 30H that are stagger - arranged in the second direction x, and there are also two sets of electrode finger bars 40 of two adjacent dies 30 that are aligned in the second direction x. Among them, the two adjacent and aligned dies 30 do not share a common source finger bar 42 or a common drain finger bar 43. This is not shown in the drawings here.

[0076] In other embodiments, the two sets of electrode finger bars 40 of at least two dies 30 in at least one die row 30H are stagger - arranged in the second direction x, and microstrip lines are arranged in the power amplifier to balance the signal phase difference between different dies 30. Figure 13 is another schematic diagram of a power amplifier provided by the embodiment of the present application. AsFigure 13 As shown, the power amplifier includes a microstrip line 70. The microstrip line 70 is a type of transmission line with low signal transmission loss. The microstrip line 70 includes a first microstrip line 71 and a second microstrip line 72. The two groups of electrode fingers 40 of the fourth die 34 and the fifth die 35 are arranged offset in the second direction x. Along the first direction y, the distance between the electrode fingers 40 of the fourth die 34 and the drain lead 52 is greater than the distance between the electrode fingers 40 of the fifth die 35 and the drain lead 52. The drain fingers 43 of the fourth die 34 are electrically connected to the drain lead 52 through the first microstrip line 71, and the gate fingers 41 of the fifth die 35 are electrically connected to the gate lead 51 through the second microstrip line 72. Since the distance between the electrode fingers 40 of the fourth die 34 and the drain lead 52 is relatively large, the transmission distance of the signal output by the fourth die 34 to the drain lead 52 is relatively long. Setting the first microstrip line 71 between the drain fingers 43 of the fourth die 34 and the drain lead 52 can reduce the loss of the signal output by the fourth die 34. Since the distance between the electrode fingers 40 of the fifth die 35 and the gate lead 51 is relatively large, the transmission distance of the input signal transmitted by the gate lead 51 to the fifth die 35 is relatively long. Setting the second microstrip line 72 between the gate fingers 41 of the fifth die 35 and the gate lead 51 can reduce the loss of the input signal provided to the fifth die 35. In this embodiment, setting the first microstrip line 71 and the second microstrip line 72 can reduce the phase difference of the signals output by the fourth die 34 and the fifth die 35, making the phases as consistent as possible, thereby improving the synthesis effect of the signals output by the parallel dies 30 and enhancing the device performance.

[0077] Figure 10 In the embodiment, to illustrate the offset setting method of the die 30, three sequentially arranged dies are named the first die 31, the second die 32, and the third die 33. Figure 13 In order to illustrate the setting method of the microstrip line 70, the dies are named the fourth die 34 and the fifth die 35. Figure 10 In the embodiment, the application Figure 13 When implementing the scheme of setting the microstrip line 70 in the embodiment, it can be understood that in Figure 10 the first die 31 and the third die 33 are equivalent to the fourth die 34, and the second die 32 is equivalent to the fifth die 35. The first microstrip line 71 can be correspondingly set for the first die 31 and the third die 33, and the second microstrip line 72 can be set for the second die 32.

[0078] In some embodiments, the lengths of the electrode fingers 40 of at least two dies 30 in the power amplifier are not equal. The dies 30 with unequal lengths of the electrode fingers 40 can be located in the same die row 30H or in different die rows 30H. Figure 14 Another schematic diagram of the power amplifier provided by the embodiment of the present application is shown in Figure 14 ​As shown, multiple die 30 include a sixth die 36 and a seventh die 37, and the length of the electrode fingers 40 of the sixth die 36 is greater than the length of the electrode fingers 40 of the seventh die 37. Figure 13 The signal input terminal 10 and the signal output terminal 20 are shown. It can be seen that among the die rows 30H, the distance from the die 30 in the first die row 30H counted from top to bottom to both the signal input terminal 10 and the signal output terminal 20 is relatively far. The seventh die 37 is located in the first die row 30H, while the distance from the sixth die 36 to both the signal input terminal 10 and the signal output terminal 20 is relatively close. It can be understood that the signal transmission path via the seventh die 37 is greater than the signal transmission path via the sixth die 36. By setting the length difference between the electrode fingers 40 of the sixth die 36 and the electrode fingers 40 of the seventh die 37, the signal transmission path difference between the two can be compensated, and further, the phase difference of the output signals of the two can be balanced, so that the final current synthesis reaches the optimal output state, thereby improving the overall electrical performance of the device.

[0079] Figure 14 It shows a situation where die 30 with unequal lengths of electrode fingers 40 are located in different die rows 30H. In some other embodiments, die 30 with unequal lengths of electrode fingers 40 are arranged in the same die row 30H. Figure 15 Another schematic diagram of a power amplifier provided by an embodiment of the present application is shown. Taking the example that two sets of electrode fingers 40 of two adjacent die 30 in the die row 30H are misaligned in the second direction x. As Figure 15 shown, the die row 30H includes 4 die 30, and the lengths of the electrode fingers 40 of the four die 30 counted from left to right are L1, L2, L3, and L4 respectively. For example, L1 = L4, L2 = L3, and L1 ≠ L2; or L1 = L2, L3 = L4, and L3 ≠ L2. In practice, the length of the electrode fingers 40 of each die 30 can be set according to the specific position of the die 30. By optimizing the length of the electrode fingers 40 in each die 30, the current synthesis output by multiple die 30 can reach the optimal output state, thereby improving the overall electrical performance of the device.

[0080] Figure 15 In the embodiment, two sets of electrode fingers 40 of two adjacent die 30 in the die row 30H are misaligned in the second direction x, and the die row 30H includes die 30 with unequal lengths of electrode fingers 40. On the basis of being able to disperse the heat dissipation in the structure group, the length of the electrode fingers 40 in the die 30 is further optimized, so that the current synthesis output by multiple die 30 can reach the optimal output state.

[0081] In some other embodiments, Figure 16 Another schematic diagram of a power amplifier provided by an embodiment of the present application is shown. As Figure 16As shown, the length of the electrode finger 40 of the sixth die 36 is greater than the length of the electrode finger 40 of the seventh die 37. The microstrip line 70 includes a third microstrip line 73, and the third microstrip line 73 is electrically connected to the gate finger 41 of the seventh die 37; and / or, the microstrip line 70 includes a fourth microstrip line 74, and the fourth microstrip line 74 is electrically connected to the drain finger 43 of the seventh die 37. In this embodiment, the microstrip line 70 is arranged to be connected to the seventh die 37, which can balance the phase difference between the output signals of the seventh die 37 and the sixth die 36 by using the microstrip line 70, so that the final current synthesis reaches the optimal output state, thereby improving the overall electrical performance of the device.

[0082] In some embodiments, Figure 17 is a schematic diagram of a circuit architecture provided by an embodiment of the present application. As Figure 17 shown, the circuit includes a first power amplifier 100 and a second power amplifier 200. Figure 17 The signal flow direction is indicated by an arrow. The signal output end of the first power amplifier 100 is connected to the functional circuit 300, and the output end of the functional circuit 300 is connected to the signal output end of the second power amplifier 200. That is, the signal output by the first power amplifier 100 is provided to the functional circuit 300, and the signals output by the functional circuit 300 and the second power amplifier 200 are integrated and then output. The design of the embodiment of the present application can reduce the space occupied by the first power amplifier 100 and the second power amplifier 200, and arrange high-power power amplifier devices in a limited layout space. The possibility of implementing other high-efficiency power amplifier architectures in the module system.

[0083] The source lead connected to the source finger 42 in the die 30 is not shown in the accompanying drawings of the above embodiments. Optionally, the source lead is grounded. Combining the above Figure 3 for understanding, the source 037 (that is, the source finger 42) is connected to the source lead through a via hole penetrating the substrate 031 below.

[0084] Based on the same inventive concept, an embodiment of the present application also provides a radio frequency module, and the radio frequency module includes the power amplifier provided by any embodiment of the present application. The structure of the power amplifier has been described in the above embodiments and will not be repeated here. The radio frequency module provided by the embodiment of the present application may be, for example, a radio frequency front-end module.

[0085] Based on the same inventive concept, an embodiment of the present application also provides an electronic device, and the electronic device includes the radio frequency module provided by any embodiment of the present application. The electronic device may be, for example, a terminal product such as a mobile phone, a television, a tablet computer, an e-book, or an in-vehicle display.

[0086] In this specification, for the same or similar parts among the various embodiments, reference can be made to each other. In particular, for the apparatus embodiments and terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and for the relevant parts, reference can be made to the descriptions in the method embodiments.

Claims

1. A power amplifier, characterized in that, it includes a signal input end, a signal output end, and a plurality of die connected in parallel; the die includes electrode fingers extending in a first direction, and the electrode fingers include gate fingers, source fingers, and drain fingers; in a second direction, the signal input end and the signal output end are respectively located on two sides of the plurality of die, and the second direction is perpendicular to the first direction.

2. The power amplifier according to claim 1, characterized in that, the power amplifier includes a gate lead connected to the signal input end and a drain lead connected to the signal output end, the gate fingers are connected to the gate lead, and the drain fingers are connected to the drain lead; a plurality of the die arranged in the second direction form a die row, and a plurality of the die in one die row share one drain lead and one gate lead.

3. The power amplifier according to claim 2, characterized in that, the die row is located between the adjacent drain lead and gate lead.

4. The power amplifier according to claim 3, characterized in that, the power amplifier includes at least one structure group, and the structure group includes two die rows adjacent in the first direction; the two die rows in the structure group share one gate lead or one drain lead.

5. The power amplifier according to claim 4, characterized in that, the number of die in the two die rows in the structure group is equal.

6. The power amplifier according to claim 4, characterized in that, the power amplifier includes n structure groups connected in parallel, and the n structure groups are arranged in the first direction, n is a positive integer and n≥2; the first end of the gate lead is connected to the signal input end, the second end is connected to the gate fingers, the first end of the drain lead is connected to the drain fingers, and the second end is connected to the signal output end; the first ends of at least two gate leads respectively electrically connected to two adjacent structure groups are electrically connected, and the second ends of at least two drain leads respectively electrically connected to two adjacent structure groups are electrically connected.

7. The power amplifier according to claim 2, characterized in that, in the die row, adjacent die share the drain fingers and / or the source fingers.

8. The power amplifier according to claim 2, characterized in that, in at least one die row: two sets of the electrode fingers of at least two die are arranged in a staggered manner in the second direction.

9. The power amplifier according to claim 8, characterized in that, at least one die row includes a first die, a second die, and a third die, the second die is located between the first die and the third die, the first die and the second die are adjacent, and there are m die spaced between the third die and the second die, m is an integer and m≥0; The two sets of electrode finger bars of the first die and the second die are arranged with a dislocation in the second direction, the two sets of electrode finger bars of the second die and the third die are arranged with a dislocation in the second direction, and the electrode finger bars of the first die and the electrode finger bars of the third die are offset and dislocated in the same direction relative to the electrode finger bars of the second die.

10. The power amplifier according to claim 8, wherein, the power amplifier includes a microstrip line, and the microstrip line includes a first microstrip line and a second microstrip line; at least one of the die rows includes a fourth die and a fifth die, and the two sets of electrode finger bars of the fourth die and the fifth die are arranged with a dislocation in the second direction; along the first direction, the distance between the electrode finger bars of the fourth die and the drain lead is greater than the distance between the electrode finger bars of the fifth die and the drain lead; the drain finger bars of the fourth die are electrically connected to the drain lead through the first microstrip line, and the gate finger bars of the fifth die are electrically connected to the gate lead through the second microstrip line.

11. The power amplifier according to claim 2, wherein, the lengths of the electrode finger bars of at least two of the multiple dies are not equal.

12. The power amplifier according to claim 11, wherein, the multiple dies include a sixth die and a seventh die, and the length of the electrode finger bars of the sixth die is greater than the length of the electrode finger bars of the seventh die; the power amplifier includes a microstrip line; the microstrip line includes a third microstrip line, and the third microstrip line is electrically connected to the gate finger bars of the seventh die; and / or, the microstrip line includes a fourth microstrip line, and the fourth microstrip line is electrically connected to the drain finger bars of the seventh die.

13. The power amplifier according to claim 1, wherein, the material of the power amplifier includes gallium nitride.

14. The power amplifier according to claim 1, wherein, the operating voltage of the power amplifier is Vo, and Vo ≤ 15V.

15. A radio frequency module, wherein, it includes the power amplifier according to any one of claims 1 to 14.

16. An electronic device, wherein, it includes the radio frequency module according to claim 15.

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