Method and device for dividing synchronous network of power system based on mutual impedance

Abstract

The invention discloses a mutual impedance-based power system synchronous network division method, which is characterized in that a simplified node admittance matrix of a power system is constructed, that is, only line reactance and transformer reactance are considered when the matrix is constructed, given values are set for the line reactance and the transformer reactance, and parameters of other equipment do not need to be considered; the mutual impedance of any two nodes is determined based on the node admittance matrix, and the electrical coupling strength between the nodes is evaluated according to the mutual impedance, so that the nodes are divided into different synchronization networks, and compared with the prior art, the point-by-point search efficiency is higher.

Description

Technical Field

[0001] The present invention belongs to the technical field of power grid frequency zoning, and particularly relates to a method and device for dividing a synchronous network of a power system based on mutual impedance. Background Art

[0002] A synchronous network (also known as a synchronous area) refers to a group of power equipment in a power system. These equipment are electrically connected to each other and can maintain frequency synchronization under normal operation. The generator sets within each synchronous network operate at the same frequency, and good power regulation can be achieved between the loads and generator sets within the synchronous network. For a complex large power grid with AC-DC hybrid connection, DC lines may divide the system into two or more synchronous networks. With the development of long-distance DC power transmission technology, the number of synchronous networks will increase.

[0003] During the arrangement of power grid operation modes or the planning and design of grid frameworks, it is often necessary to establish a frequency response model for the power grid for frequency simulation analysis. The frequency fast time-domain simulation method based on single-node equivalence is still applicable within a single synchronous network. For a system with multiple synchronous networks, such as an AC-DC hybrid large power grid, there are nearly 100,000 bus nodes. When it is necessary to analyze the frequency of each synchronous network separately, it is necessary to divide the synchronous networks within the system. For example, it is difficult to accurately find the boundary of the synchronous network based on the power grid operation mode data in the BPA data card format. While using an optimal path search algorithm such as the Dijkstra algorithm can accurately locate the synchronous network boundary through branch search, applying it to a large power grid with a huge number of nodes will result in low search efficiency and long time consumption. Summary of the Invention

[0004] Based on this, the present invention aims to propose a method and device for dividing a synchronous network of a power system based on mutual impedance, construct a simplified nodal admittance matrix of the system, and thus divide the nodes within the system into each synchronous network according to the mutual impedance between the nodes.

[0005] In a first aspect, the present invention proposes a method for dividing a synchronous network of a power system based on mutual impedance, including:

[0006] Obtain the node and branch parameters of the power system, where the branch parameters include line reactance and transformer reactance;

[0007] Construct a nodal admittance matrix of the power system according to the node and branch parameters;

[0008] Traverse the nodes of the power system, determine the mutual impedance between the currently traversed node and other nodes within the power system based on the nodal admittance matrix. When the mutual impedance between two nodes meets the set conditions, they are divided into the same synchronous network until all nodes are traversed.

[0009] Further, determining the mutual impedance between the currently traversed node and other nodes in the power system based on the nodal admittance matrix includes:

[0010] Calculating the inverse of the nodal admittance matrix to obtain the nodal impedance matrix;

[0011] Determining the mutual impedance between the currently traversed node and other nodes in the power system according to the nodal impedance matrix.

[0012] Further, traversing the nodes of the power system, determining the mutual impedance between the currently traversed node and other nodes in the power system, and dividing two nodes with mutual impedance meeting the set conditions into the same synchronous network until all nodes are traversed, including:

[0013] Taking the node with the smallest current number as the currently traversed node, the remaining unpartitioned nodes except the currently traversed node as the target nodes, determining the synchronous network where the currently traversed node is located, querying the mutual impedance between the currently traversed node and each target node in the nodal impedance matrix, and dividing the target nodes corresponding to the mutual impedance meeting the set conditions into the synchronous network where the currently traversed node is located until all nodes in the power system are divided into several synchronous networks.

[0014] Further, obtaining the node and branch parameters of the power system includes:

[0015] Determining the node information of the power system and setting given values for the line reactance and transformer reactance between nodes.

[0016] Further, setting given values for the line reactance and transformer reactance between nodes includes:

[0017] Setting the line reactance and transformer reactance of the AC line to 10 -9 p.u., and setting the line reactance of the DC line to 10 9 p.u.

[0018] Further, the set condition is that the mutual impedance between two nodes is less than the set threshold.

[0019] Further, the set condition is that the mutual impedance between two nodes satisfies |Z| < 1 p.u.

[0020] In a second aspect, the present invention provides a device for dividing a synchronous network of a power system based on mutual impedance, including:

[0021] A parameter acquisition module, configured to acquire the node and branch parameters of the power system, and the branch parameters include line reactance and transformer reactance;

[0022] A matrix construction module, configured to construct the nodal admittance matrix of the power system according to the node and branch parameters;

[0023] A node division module is used to traverse the nodes of a power system, determine the mutual impedance between the currently traversed node and other nodes in the power system based on the node admittance matrix, and divide two nodes into the same synchronous network when their mutual impedance meets the set conditions until all nodes are traversed.

[0024] In a third aspect, the present invention provides an electronic device, including a memory storing computer-executable instructions and a processor. When the computer-executable instructions are executed by the processor, the device performs each step of the method for dividing a synchronous network of a power system based on mutual impedance provided in the first aspect.

[0025] In a fourth aspect, the present invention provides a readable storage medium storing a computer-executable program, which can implement each step of the method for dividing a synchronous network of a power system based on mutual impedance provided in the first aspect when the program is executed.

[0026] The present invention has the following beneficial effects compared with the prior art:

[0027] The present invention proposes a method for dividing a synchronous network of a power system based on mutual impedance, constructs a simplified node admittance matrix of the power system, that is, only considers the line reactance and transformer reactance when constructing the matrix, and sets given values for the line reactance and transformer reactance, without considering the parameters of other devices. Based on the node admittance matrix, the mutual impedance between any two nodes is determined, and the electrical coupling strength between nodes is evaluated according to the mutual impedance, so as to divide each node into different synchronous networks. Compared with the prior art, the efficiency of point-by-point search is higher, and it reflects the physical connectivity of the power grid, providing strong support in aspects such as system scheduling, stability analysis, and fault handling. Description of the Drawings

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0029] Figure 1 It is a flowchart for implementing the method for dividing a synchronous network of a power system based on mutual impedance provided in an embodiment of the present invention;

[0030] Figure 2 It is a structural diagram of a device for dividing a synchronous network of a power system based on mutual impedance provided in an embodiment of the present invention;

[0031] Figure 3 It is an architecture diagram of an electronic device provided in an embodiment of the present invention. Detailed Embodiments

[0032] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0033] Referring to Figure 1 , an embodiment of the present invention provides a method for dividing a power system synchronization network based on mutual impedance, including the following steps:

[0034] Step S110. Obtain the node and branch parameters of the power system, where the branch parameters include line reactance and transformer reactance.

[0035] In this step, the nodes and branches in the system are determined according to the given power system line diagram. Nodes usually represent the connection points of the power system, and branches represent the electrical connections between two nodes. Among them, only the line reactance and transformer reactance are considered for the branch parameters, and it is not necessary to obtain the reactance parameters of other equipment. The admittance between nodes is calculated according to the line reactance and transformer.

[0036] In a further embodiment, in order to further simplify the matrix construction process, given values are set for the line reactance and transformer reactance between nodes. When setting the given values, it is followed that the reactance of the AC line is extremely small and the reactance of the DC line is extremely large. For example, the line reactance and transformer reactance of the AC line are set to 10 -9 p.u., and the line reactance of the DC line is set to 10 9 p.u.

[0037] Step S120. Construct the node admittance matrix of the power system according to the node and branch parameters.

[0038] The process of constructing the node admittance matrix in this step is similar to the conventional construction of the node admittance matrix. The difference is only that only the line reactance and transformer reactance are considered, and further given values are set for the line reactance and transformer reactance. Accordingly, the admittance between any two nodes can be calculated to form the elements of the matrix. Among them, the diagonal elements of the matrix represent the sum of the admittances of all branches directly connected to node i, and the non-diagonal elements represent the admittance between node i and node j. The formed N×N node admittance matrix can be expressed as follows:

[0039]

[0040] In a further implementation manner, in order to speed up the subsequent node traversal, the node impedance matrix can be obtained by inverting the node admittance matrix before traversal, as shown below:

[0041]

[0042] The elements in the nodal impedance matrix represent the mutual impedance between nodes.

[0043] Step S130. Traverse the nodes of the power system, determine the mutual impedance between the currently traversed node and other nodes in the power system based on the nodal admittance matrix, and divide the nodes into the same synchronous network when the mutual impedance between two nodes meets the set condition until all nodes are traversed.

[0044] Specifically, the mutual impedance between any two nodes can be determined using the nodal admittance matrix constructed in the previous step in this step. Further, the nodal impedance matrix can be directly queried, and it can be directly determined whether two nodes belong to the same synchronous network based on the mutual impedance between the nodes. This is because the mutual impedance reflects the electrical coupling relationship between nodes. If the mutual impedance between two nodes is very small, it means that the admittance between them is very large, which usually indicates that the two nodes are connected by a line with a very low impedance and have strong electrical coupling. It can be considered that the two nodes belong to the same synchronous network based on this.

[0045] In a further embodiment, the set condition is set to that the mutual impedance between two nodes is less than a set threshold. In an example aspect, the set threshold can be set to a relatively low value. For example, it is considered that two nodes with a mutual impedance |Z| < 1 p.u. belong to the same synchronous network.

[0046] In a further embodiment, the traversal idea is adopted. The node division process in step S130 above includes:

[0047] Taking the node with the smallest current number as the currently traversed node, the remaining unpartitioned nodes except the currently traversed node as target nodes, determining the synchronous network where the currently traversed node is located, querying the mutual impedance between the currently traversed node and each target node in the nodal impedance matrix, and dividing the target nodes corresponding to the mutual impedance meeting the set condition into the synchronous network where the currently traversed node is located until all nodes in the power system are divided into several synchronous networks.

[0048] Exemplarily, starting from node 1, the synchronization network number where node 1 is located is network 1, and the remaining N - 1 nodes except node 1 are target nodes. If the mutual impedance magnitude between target node i and node 1 satisfies |Z| < 1 p.u., then the synchronization network where the target node is located is network 1, that is, node i ∈ network 1. If the mutual impedance magnitude between node i and node 1 satisfies |Z| ≥ 1 p.u., then node i ∈ network X, and the total number of all nodes belonging to network 1 is A. Repeat the above process for the nodes in the network X set. Starting from the node with the smallest number in network X, the synchronization network number where it is located is network 2, and the remaining N - A - 1 nodes except this node are target nodes. If the mutual impedance magnitude between the target node and this node satisfies |Z| < 1 p.u., then the synchronization network where the target node is located is network 2, that is, the target node ∈ network 2. After this round, the total number of all nodes belonging to network 2 is B, and the set network X is updated. Repeat the above node traversal and partitioning process until the number of nodes in the set network X is 0. At this time, each node is partitioned into several synchronization networks. In the further frequency analysis process, frequency time-domain simulation can be performed within a single synchronization network to calculate the frequencies of each synchronization network.

[0049] The above embodiments provide a method for partitioning a power system synchronization network based on mutual impedance. A simplified nodal admittance matrix of the power system is constructed, that is, only the line reactance and transformer reactance are considered when constructing the matrix, and given values are set for the line reactance and transformer reactance, without considering the parameters of other devices. The mutual impedance between any two nodes is determined based on the nodal admittance matrix, and the electrical coupling strength between the nodes is evaluated according to the mutual impedance, so as to partition each node into different synchronization networks. Compared with the prior art, the point-by-point search efficiency is higher, and it reflects the physical connectivity of the power grid, providing strong support in aspects such as system scheduling, stability analysis, and fault handling.

[0050] The above disclosed method can be implemented by devices in various forms. Therefore, the present invention also discloses a device corresponding to the above method, and specific embodiments are given below for detailed description.

[0051] As Figure 2 shown, an embodiment of the present invention provides a device for partitioning a power system synchronization network based on mutual impedance, including:

[0052] A parameter acquisition module 202, configured to acquire the node and branch parameters of the power system, where the branch parameters include line reactance and transformer reactance;

[0053] A matrix construction module 204, configured to construct a nodal admittance matrix of the power system according to the node and branch parameters;

[0054] The node division module 206 is configured to traverse the nodes of the power system, determine the mutual impedance between the currently traversed node and other nodes in the power system based on the node admittance matrix, and divide two nodes into the same synchronous network when the mutual impedance between them meets the set conditions until all nodes are traversed.

[0055] The device provided by the embodiments of the present application has the same implementation principle and technical effects as those of the foregoing method embodiments. For the sake of brief description, for the parts not mentioned in the device embodiments, reference may be made to the corresponding content in the foregoing method embodiments.

[0056] The methods and related devices mentioned in the above embodiments are described with reference to the method flowcharts and / or structural schematic diagrams provided by the embodiments of the present application. Specifically, they can be implemented by computer program instructions for each process and / or block in the method flowchart and / or structural schematic diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for implementing the functions specified in Figure 1 one process or multiple processes and / or structural schematic Figure 1 one block or multiple blocks. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction device, and the instruction device implements the functions specified in Figure 1 one process or multiple processes and / or structural schematic Figure 1 one block or multiple blocks. These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one process or multiple processes and / or structural schematic one block or multiple blocks.

[0057] The following embodiments are described by taking the application of the method to a computer device as an example. It can be understood that the computer device can be any device with computing and processing functions, and can be, but is not limited to, a server or a personal laptop computer, etc. In one of the embodiments, the computer device can be an application server, and the application server can be a server for running the application under test.

[0058] Refer to Figure 3, which shows a hardware structure block diagram of an electronic device. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present application described and / or claimed herein.

[0059] As Figure 3 shown, the electronic device includes: at least one processor 1, at least one communication interface 2, at least one memory 3, and at least one communication bus 4;

[0060] In the embodiment of the present application, the number of the processor 1, the communication interface 2, the memory 3, and the communication bus 4 is at least one, and the processor 1, the communication interface 2, and the memory 3 complete mutual communication through the communication bus 4;

[0061] The processor 1 may be a central processing unit CPU, or a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention, etc.;

[0062] The memory 3 may include high-speed RAM memory, and may also include non-volatile memory, etc., such as at least one disk memory;

[0063] Among them, the memory stores a program, and the processor can call the program stored in the memory. The program is used to: implement each processing flow of the foregoing power system synchronization network division scheme based on mutual impedance.

[0064] The embodiment of the present invention also provides a readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements each processing flow of the power system synchronization network division scheme based on mutual impedance provided by any possible implementation manner of the foregoing embodiment and / or the combined embodiment.

[0065] The above embodiments have described the present invention in particular detail with respect to possible scenarios, and those skilled in the art will recognize that the present invention can be practiced through other embodiments. The specific naming of components, the case of terms, attributes, data structures, or any other programming or structural aspects are not mandatory or significant. The mechanisms or features for implementing the present invention can have different names, forms, or procedures. The system can be implemented through a combination of hardware and software (as described), entirely through hardware elements, or entirely through software elements. The specific division of functions among the various system components described herein is merely exemplary and not mandatory; conversely, the functions performed by a single system component can be performed by multiple components, or the functions performed by multiple components can be performed by a single component.

[0066] Those skilled in the art should understand that each step of the above-disclosed method can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed across a network composed of multiple computing devices. Optionally, they can be implemented with program code executable by the computing device, so that they can be stored in a storage device and executed by the computing device, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. Thus, the disclosure of the embodiments of the present invention is not limited to any specific combination of hardware and software.

[0067] These programs executable by the computing device (also referred to as programs, software, software applications, or code) include machine instructions for a programmable processor and can be implemented using high-level procedural and / or object-oriented programming languages and / or assembly / machine languages. As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any computer program product, device, and / or apparatus (e.g., disk, optical disk, memory, programmable logic device (PLD)) for providing machine instructions and / or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term "machine-readable signal" refers to any signal for providing machine instructions and / or data to a programmable processor.

[0068] Certain aspects of the present invention include the process steps and instructions described herein in the form of an algorithm. It should be noted that the process steps and instructions of the present invention can be implemented in software, firmware, and / or hardware. When implemented in software, it can be downloaded and thus saved and operated on different platforms used by various operating systems.

[0069] Those skilled in the art can understand that the structures shown in the respective drawings are merely block diagrams of some structures related to the solution of the present application, and do not constitute a limitation on the terminal devices to which the solution of the present application is applied. The specific terminal devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0070] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "possible design", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0071] Finally, it should also be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, the element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0072] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for dividing a power system synchronization network based on mutual impedance, characterized in that: include: Acquiring node and branch parameters of the power system, wherein the branch parameters include line reactance and transformer reactance; Constructing a node admittance matrix of the power system according to the node and branch parameters; The nodes of the power system are traversed, and the mutual impedance between the current traversed node and other nodes in the power system is determined based on the node admittance matrix. When the mutual impedance of two nodes meets the set conditions, they are divided into the same synchronization network until all nodes are traversed.

2. The method according to claim 1, characterized in that The determining the mutual impedance between the current traversal node and other nodes in the power system based on the node admittance matrix includes: Inverse the node admittance matrix to obtain a node impedance matrix; The mutual impedance between the current traversed node and other nodes in the power system is determined according to the node impedance matrix.

3. The method according to claim 2, characterized in that The nodes of the power system are traversed, and the mutual impedance between the currently traversed node and other nodes in the power system is determined based on the node admittance matrix, and when the mutual impedance of two nodes meets the set conditions, they are divided into the same synchronization network until all nodes are traversed, including: The node with the smallest current number is taken as the current traversal node, and the remaining undivided nodes except the current traversal node are taken as target nodes. The synchronous network where the current traversal node is located is determined, and the mutual impedance between the current traversal node and each target node is queried in the node impedance matrix. The target nodes corresponding to the mutual impedance that meets the set conditions are divided into the synchronous network where the current traversal node is located, until all nodes in the power system are divided into several synchronous networks.

4. The method according to claim 1, characterized in that The obtaining of node and branch parameters of the power system comprises: Determine the node information of the power system and set given values ​​for the line reactance and transformer reactance between the nodes.

5. The method according to claim 4, characterized in that The setting of given values ​​for line reactance and transformer reactance between nodes includes: Set the line reactance and transformer reactance of the AC line to 10 -9 pu, the line reactance of the DC line is set to 10 9 pu.

6. The method according to claim 1, characterized in that The set condition is that the mutual impedance of the two nodes is less than a set threshold.

7. The method according to claim 1, characterized in that The setting condition is that the mutual impedance of the two nodes satisfies |Z|<1 pu.

8. A device for dividing a power system synchronization network based on mutual impedance, characterized in that: include: A parameter acquisition module, used to acquire node and branch parameters of the power system, wherein the branch parameters include line reactance and transformer reactance; A matrix construction module, used for constructing a node admittance matrix of the power system according to the node and branch parameters; The node division module is used to traverse the nodes of the power system, determine the mutual impedance between the currently traversed node and other nodes in the power system based on the node admittance matrix, and divide the two nodes into the same synchronous network when the mutual impedance meets the set conditions until all nodes are traversed.

9. An electronic device, characterized in that: The device comprises a memory storing computer executable instructions and a processor. When the computer executable instructions are executed by the processor, the device executes the method for dividing a synchronous network of a power system based on mutual impedance as described in any one of claims 1 to 7.

10. A readable storage medium, characterized in that: A computer executable program is stored, and when the program is executed, the method for dividing a synchronous network of a power system based on mutual impedance as described in any one of claims 1 to 7 can be implemented.

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