Capacitor detection circuit and power supply chip for linear voltage regulator

Abstract

Embodiments of the present disclosure provide a capacitance detection circuit and power supply chip for a linear regulator. The capacitance detection circuit includes a comparison module, a counting module, and a logic module. The comparison module can compare a reference voltage and a feedback voltage to obtain a comparison signal, where the feedback voltage is the product of the linear regulator's output voltage and a voltage divider coefficient. The counting module can count the number of consecutive flips of the comparison signal from a first level to a second level and, based on whether the number of consecutive flips of the comparison signal reaches a preset number, determine a capacitance connection state detection signal used to characterize the connection state of the output capacitor. This circuit can detect the connection state of the output capacitor in real time during operation of the linear regulator. After the linear regulator is powered on, the logic module controls whether the linear regulator operates based on the capacitance connection state detection signal, so that the linear regulator stops operating if the output capacitor connection is abnormal, thereby reducing safety risks caused by output capacitor abnormalities.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular to a capacitance detection circuit and a power supply chip of a linear regulator. Background Art

[0002] Linear regulators are common power supply chips with advantages such as simple structure, low cost, and low output voltage ripple. They are widely used in power supply systems in electronics, automotive, and aerospace industries. A large capacitor is typically installed at the output of a linear regulator to provide voltage stabilization and filtering. If the output capacitor becomes disconnected during operation, the linear regulator can become unstable, resulting in an output voltage exceeding the specified value and potentially damaging subsequent circuits. Therefore, it is necessary to monitor the output capacitor connection to improve the linear regulator's functional safety mechanisms.

[0003] A common practice is to check the output capacitor connection during chip power-up. If the output capacitor is properly connected, the linear regulator is enabled; if the output capacitor is not properly connected, the linear regulator is disabled. However, this method only checks when the chip is powered on and cannot detect abnormal output capacitor connections after the linear regulator is powered on and during normal use, posing a certain application safety risk. Summary of the Invention

[0004] The present disclosure provides a capacitance detection circuit and a power supply chip for a linear regulator, which can detect the connection status of the output capacitor in real time during the operation of the linear regulator, thereby reducing the safety risks caused by abnormal output capacitor connection.

[0005] In a first aspect, the present disclosure provides a capacitance detection circuit for a linear regulator, wherein the output of the linear regulator is grounded via an output capacitor. The capacitance detection circuit includes a comparison module, a counting module, and a logic module. A first input of the comparison module is connected to a reference voltage, a second input of the comparison module is connected to a feedback terminal of the linear regulator, an output of the comparison module is connected to an input of the logic module via the counting module, and an output of the logic module is connected to an enable terminal of the linear regulator.

[0006] The comparison module is configured to compare the reference voltage and the feedback voltage to generate a comparison signal, wherein the feedback voltage is the product of the output voltage of the linear regulator and the voltage divider coefficient. The counting module is configured to count the number of consecutive flips of the comparison signal from a first level to a second level, and determine a capacitor connection status detection signal based on whether the number of consecutive flips of the comparison signal reaches a preset number, wherein the capacitor connection status detection signal is used to indicate the connection status of the output capacitor. The logic module is configured to control whether the linear regulator operates based on the capacitor connection status detection signal after the linear regulator is powered on, so that the linear regulator stops operating when the output capacitor connection is abnormal and operates when the output capacitor connection is normal.

[0007] In some embodiments of the present disclosure, the comparison module includes a first high-speed comparator, the counting module includes a first counter, the positive input terminal of the first high-speed comparator is connected to the feedback terminal, the inverting input terminal of the first high-speed comparator is connected to a first reference voltage, the voltage value of the first reference voltage is less than the overvoltage threshold of the output voltage and the product of the voltage division coefficient and greater than the standard value of the output voltage and the product of the voltage division coefficient, and the output terminal of the first high-speed comparator is connected to the first input terminal of the logic module through the first counter.

[0008] The first counter is configured to determine that the first capacitor connection state detection signal is a capacitor connection abnormality signal when the number of consecutive flips of the first comparison signal reaches a first preset number, and to determine that the first capacitor connection state detection signal is a capacitor connection normal signal when the number of consecutive flips of the first comparison signal does not reach the first preset number.

[0009] In some embodiments of the present disclosure, the comparison module also includes a second high-speed comparator, the counting module also includes a second counter, the inverting input terminal of the second high-speed comparator is connected to the feedback terminal, the non-inverting input terminal of the second high-speed comparator is connected to a second reference voltage, the voltage value of the second reference voltage is less than the product of the standard value and the voltage division coefficient and greater than the undervoltage threshold of the output voltage and the product of the voltage division coefficient, and the output terminal of the second high-speed comparator is connected to the second input terminal of the logic module through the second counter.

[0010] The second counter is configured to, when the number of consecutive flips of the second comparison signal reaches a second preset number, determine that the second capacitor connection state detection signal is the capacitor connection abnormality signal; when the number of consecutive flips of the second comparison signal does not reach the second preset number, determine that the second capacitor connection state detection signal is the capacitor connection normal signal.

[0011] In some embodiments of the present disclosure, the first high-speed comparator includes a current generating unit, a pull-up unit, a pull-down unit and an output unit, the first input end of the current generating unit is connected to the first reference voltage, the second input end of the current generating unit is the feedback end, the first output end of the current generating unit is connected to the bias end of the pull-up unit, the second output end of the current generating unit is connected to the control end of the pull-down unit, and the connection point between the pull-up unit and the pull-down unit is connected to the input end of the first counter through the output unit.

[0012] The current generating unit is configured to, when the feedback voltage is greater than the first reference voltage, generate a dynamic bias current based on a voltage difference between the feedback voltage and the first reference voltage, wherein a current value of the dynamic bias current is proportional to the voltage difference. The pull-up unit is configured to, when the feedback voltage is greater than the first reference voltage, pull up a connection point voltage based on a constant bias current and the dynamic bias current.

[0013] The pull-down unit is configured to pull the connection point voltage down to ground when the feedback voltage is less than the first reference voltage. The output unit is configured to flip the first comparison signal from the first level to the second level when the connection point voltage rises to a first preset voltage, and flip the first comparison signal from the second level to the first level when the connection point voltage drops to a second preset voltage, wherein the first preset voltage is greater than the second preset voltage.

[0014] In some embodiments of the present disclosure, the current generating unit includes a current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first terminal of the first transistor and the first terminal of the second transistor are connected to a power supply voltage, the control terminal of the first transistor is connected to the second terminal of the first transistor, the control terminal of the second transistor, and the control terminal of the pull-up unit, the second terminal of the first transistor is grounded via the current source, and the second terminal of the second transistor is connected to the first terminal of the third transistor and the first terminal of the fourth transistor.

[0015] The control end of the third transistor is connected to the first reference voltage, the control end of the fourth transistor is connected to the feedback end, the second end of the third transistor is connected to the second end of the fifth transistor, the control end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor, the first end of the fifth transistor, the first end of the sixth transistor and the first end of the seventh transistor are grounded, the second end of the fourth transistor is connected to the second end of the sixth transistor and the control end of the pull-down unit, and the second end of the seventh transistor is connected to the bias end of the pull-up unit.

[0016] In some embodiments of the present disclosure, the pull-up unit includes an eighth transistor, a ninth transistor and a tenth transistor, the first end of the eighth transistor, the first end of the ninth transistor and the first end of the tenth transistor are connected to the power supply voltage, the control end of the eighth transistor is connected to the second end of the eighth transistor, the control end of the ninth transistor and the first output end of the current generating unit, the second end of the ninth transistor is connected to the connection point, the input end of the output unit and the second end of the tenth transistor, and the control end of the tenth transistor is connected to the bias end of the current generating unit.

[0017] In some embodiments of the present disclosure, the first high-speed comparator further includes a clamping unit, a first end of the clamping unit is connected to the control end of the pull-down unit, and a second end of the clamping unit is connected to the connection point.

[0018] The clamping unit is configured to limit a voltage drop between the control terminal of the pull-down unit and the connection point to not exceed a clamping voltage.

[0019] In some embodiments of the present disclosure, the first counter includes a start-up unit, a multi-stage D flip-flop unit, and a signal generating unit, wherein the input end of the start-up unit is connected to the output end of the first high-speed comparator, the output end of the start-up unit is connected to the set end of each D flip-flop in the multi-stage D flip-flop unit and the enable end of the signal generating unit, the output end of the multi-stage D flip-flop unit is connected to the input end of the signal generating unit, and the output end of the signal generating unit is connected to the first input end of the logic module.

[0020] For the multi-stage D flip-flop unit: the clock end of the first-stage D flip-flop is connected to the output end of the first high-speed comparator, the output end of the last-stage D flip-flop is connected to the input end of the signal generating unit, and the input end and inverting output end of the previous-stage D flip-flop in two adjacent stages of D flip-flops are connected to the clock end of the next-stage D flip-flop.

[0021] In some embodiments of the present disclosure, the logic module is further configured to, after the linear regulator is powered on, control the linear regulator to stop working when the first capacitor connection status detection signal or the second capacitor connection status detection signal is the capacitor connection abnormality signal, and control the linear regulator to work normally when the first capacitor connection status detection signal and the second capacitor connection status detection signal are the capacitor connection normal signals.

[0022] In a second aspect, the present disclosure provides a power supply chip, comprising any capacitance detection circuit provided in the first aspect.

[0023] The technical solution disclosed herein provides a capacitance detection circuit for a linear regulator, including a comparison module, a counting module, and a logic module. The comparison module can compare a reference voltage and a feedback voltage to obtain a comparison signal, where the feedback voltage is the product of the output voltage of the linear regulator and a voltage divider coefficient. The counting module can count the number of consecutive flips of the comparison signal from a first level to a second level, and determine a capacitance connection state detection signal for characterizing the connection state of the output capacitor based on whether the number of consecutive flips of the comparison signal reaches a preset number. The capacitance connection state can be detected in real time during the operation of the linear regulator. After the linear regulator is powered on, the logic module controls whether the linear regulator is operating based on the capacitance connection state detection signal, so that the linear regulator stops operating when the output capacitor connection is abnormal, thereby reducing the safety risks caused by the output capacitor abnormality. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. It should be noted that the drawings described below only relate to some embodiments of the present disclosure and are not intended to limit the present disclosure.

[0025] Figure 1 A schematic diagram of the structure of a power chip provided in an embodiment of the present disclosure.

[0026] Figure 2 A schematic diagram of the structure of a capacitance detection circuit provided in an embodiment of the present disclosure.

[0027] Figure 3 A schematic diagram of feedback voltage under different connection states provided by an embodiment of the present disclosure.

[0028] Figure 4 A circuit diagram of a capacitance detection circuit provided by an embodiment of the present disclosure.

[0029] Figure 5 A circuit diagram of a first counter provided in an embodiment of the present disclosure.

[0030] Figure 6 A circuit diagram of a first high-speed comparator provided in an embodiment of the present disclosure.

[0031] Figure 7 This is a simulation diagram of various signals in a first high-speed comparator provided in an embodiment of the present disclosure.

[0032] Figure 8 A circuit diagram of another first high-speed comparator provided by an embodiment of the present disclosure.

[0033] Figure 9 A circuit diagram of another capacitance detection circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0035] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal manner unless otherwise expressly defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that the parts are joined together either directly or through one or more intermediate components.

[0036] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase "embodiment" in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this disclosure may be combined with other embodiments.

[0037] In addition, the terms "first", "second", etc. in the description and claims of the present disclosure or the above-mentioned drawings are used to distinguish different objects rather than to describe a specific order, and may explicitly or implicitly include one or more such features.

[0038] In this disclosure, the term "and / or" simply describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the related objects are in an "or" relationship.

[0039] In the description of the present disclosure, unless otherwise specified, “multiple” and “at least two” mean more than two (including two). Similarly, “multiple groups” and “at least two groups” mean more than two (including two).

[0040] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0041] The linear regulator provided in the present disclosure may be a conventional linear regulator or a low dropout linear regulator (LDO), and the output capacitor provided in the present disclosure may be an off-chip capacitor or an on-chip capacitor.

[0042] Figure 1 A schematic diagram of the structure of a power chip provided in an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the power chip 10 includes a capacitance detection circuit 100 and a linear regulator 200. The output end of the linear regulator 200 is grounded through the output capacitor Cout, the input end of the capacitance detection circuit 100 is connected to the feedback end FB of the linear regulator 200, and the output end of the capacitance detection circuit 100 is connected to the enable end of the linear regulator 200.

[0043] Illustratively, the linear regulator 200 includes a loop comparator CMP_L, a power transistor M_Power, and a feedback network 210. The non-inverting input of the loop comparator CMP_L receives a reference voltage Vbg, and the inverting input of the loop comparator CMP_L is connected to the output of the feedback network 210, i.e., to the feedback terminal FB of the linear regulator 200, to receive the feedback voltage Vfb. The enable terminal of the loop comparator CMP_L is connected to the output of the capacitance detection circuit 100, and the output of the loop comparator CMP_L is connected to the control terminal of the power transistor M_Power. The loop comparator CMP_L can determine the control voltage of the power transistor M_Power based on the reference voltage Vbg and the feedback voltage Vfb.

[0044] The input end of the power transistor M_Power is connected to the input end of the linear regulator 200 to receive the input voltage Vin. The output end of the power transistor M_Power is connected to the input end of the feedback network 210 and the output end of the linear regulator 200. The power transistor M_Power can adjust the output voltage Vout of the linear regulator 200 according to the control voltage to suppress the ripple noise of the input voltage Vin and the impact of load changes on the output voltage Vout, thereby stabilizing the output voltage Vout.

[0045] The feedback network 210 includes a first feedback resistor R1 and a second feedback resistor R2. The first feedback resistor R1 and the second feedback resistor R2 are connected in series between the output terminal of the linear regulator 200 and ground. The connection terminal between the first feedback resistor R1 and the second feedback resistor R2 serves as a feedback terminal. The feedback voltage Vfb is a linearly divided voltage of the output voltage Vout. That is, the feedback voltage Vfb is the product of the output voltage Vout and a voltage division coefficient. The voltage division coefficient is the ratio of the resistance of the second feedback resistor R2 to the sum of the resistance of the second feedback resistor R2 and the resistance of the first feedback resistor R1.

[0046] The capacitance detection circuit provided by the present disclosure is described in detail below with reference to several specific embodiments.

[0047] Figure 2 A schematic diagram of a capacitance detection circuit according to an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the capacitance detection circuit 100 includes a comparison module 110, a counting module 120 and a logic module 130. The first input terminal of the comparison module 110 receives a reference voltage Vref, the second input terminal of the comparison module 110 is connected to the feedback terminal FB to receive the feedback voltage Vfb, the output terminal of the comparison module 110 is connected to the input terminal of the logic module 130 through the counting module 120, and the output terminal of the logic module 130 is connected to the enable terminal of the linear regulator 200.

[0048] The comparison module 110 is configured to compare the reference voltage Vref and the feedback voltage Vfb to obtain a comparison signal Vcmp. The counting module 120 is configured to count the number of consecutive flips of the comparison signal Vcmp from a first level to a second level and, based on whether the number of consecutive flips of the comparison signal Vcmp reaches a preset number, determine a capacitor connection state detection signal Det. The capacitor connection state detection signal Det is used to indicate the connection state of the output capacitor Cout.

[0049] The logic module 130 is configured to control whether the linear regulator 200 operates according to the capacitor connection state detection signal Det after the linear regulator 200 is powered on, so that the linear regulator 200 stops operating when the output capacitor Cout is abnormally connected and operates when the output capacitor Cout is normally connected.

[0050] Exemplarily, the connection status of the output capacitor Cout includes normal capacitor connection and abnormal capacitor connection, wherein the abnormal capacitor connection can be further divided into two situations, one is the abnormal capacitor connection caused by capacitor missing, and the other is the abnormal capacitor connection caused by capacitor mismatch, capacitance value offset and / or error in the internal loop of the linear regulator.

[0051] When the connection state of the output capacitor Cout is normal, during the operation of the linear regulator 200, the output voltage Vout and the feedback voltage Vfb ( Figure 3 The yellow line in the middle is stable, wherein the voltage value of the output voltage Vout is stable at the standard value SV, and the voltage value of the corresponding feedback voltage Vfb is stable at the product of the standard value SV and the voltage division coefficient, as shown in FIG. Figure 3 As shown, Figure 3 A schematic diagram of feedback voltage under different connection states provided by an embodiment of the present disclosure.

[0052] like Figure 3 As shown, when the connection state of the output capacitor Cout is abnormal due to capacitor missing, during the operation of the linear regulator 200, the output voltage Vout will oscillate around the standard value SV, and the maximum voltage value of the output voltage Vout will exceed the specified overvoltage threshold OV, and the corresponding feedback voltage Vfb ( Figure 3 The voltage value (shown by the black line in the middle) will oscillate around the product of the reference value SV and the voltage divider coefficient, and the maximum voltage of the feedback voltage Vfb will exceed the product of the overvoltage threshold OV and the voltage divider coefficient. To prevent false tripping, the overvoltage comparator within the power chip 10 is typically equipped with a hysteresis of tens of microseconds. However, the oscillation frequency of the output voltage Vout is generally above tens of kHz, making it unable to detect such high-frequency oscillations.

[0053] When the connection state of the output capacitor Cout is abnormal due to capacitance value deviation, internal loop error of the linear regulator, and / or capacitor mismatch, the output voltage Vout will oscillate around the standard value SV during the operation of the linear regulator 200. However, the maximum voltage value of the output voltage Vout does not exceed the overvoltage threshold value OV, and the minimum voltage value of the output voltage Vout does not fall below the undervoltage threshold value UV. That is, the output voltage Vout oscillates between the undervoltage threshold value UV and the overvoltage threshold value OV, and the corresponding feedback voltage Vfb oscillates between the product of the undervoltage threshold value UV and the voltage divider coefficient and the product of the overvoltage threshold value OV and the voltage divider coefficient.

[0054] Based on this, the feedback voltage Vfb continuously exceeding a certain voltage value can be used as a detection standard for indicating that the connection state of the output capacitor Cout is abnormal.

[0055] Figure 4 A circuit diagram of a capacitance detection circuit provided by an embodiment of the present disclosure is shown as follows: Figure 4As shown, the comparison module 110 includes a first high-speed comparator 111, the counting module 120 includes a first counter 121, the non-inverting input terminal of the first high-speed comparator 111 is connected to the feedback terminal FB, the inverting input terminal of the first high-speed comparator 111 receives the first reference voltage Vref1, and the output terminal of the first high-speed comparator 111 is connected to the first input terminal of the logic module 130 through the first counter 121.

[0056] The first high-speed comparator 111 can compare the feedback voltage Vfb and the first reference voltage Vref1, and when the feedback voltage Vfb is less than the first reference voltage Vref1, the output first comparison signal Vcmp1 is a low level, that is, a first level; when the feedback voltage Vfb is greater than the first reference voltage Vref1, the output first comparison signal Vcmp1 is a high level, that is, a second level.

[0057] Exemplarily, the voltage value of the first reference voltage Vref1 is less than the product of the overvoltage threshold OV and the voltage division coefficient and greater than the product of the standard value SV and the voltage division coefficient. For example, the first reference voltage Vref1 is 105% of the feedback voltage Vfb.

[0058] After the linear regulator 200 is powered on, the feedback voltage Vfb begins to rise. When the feedback voltage Vfb remains lower than the first reference voltage Vref1, the first comparison signal Vcmp1 maintains the first level and does not flip from the first level to the second level. The number of consecutive flips of the first comparison signal Vcmp1 from the first level to the second level counted by the first counter 121 is zero. The output first capacitor connection state detection signal Det1 then remains at a high level, i.e., the capacitor connection normal signal Cout_ok is maintained. At this point, the connection state of the output capacitor Cout is normal.

[0059] When the feedback voltage Vfb rises from less than the first reference voltage Vref1 to greater than the first reference voltage Vref1, the first comparison signal Vcmp1 flips from the first level to the second level, and as the feedback voltage Vfb continues to rise, the feedback voltage Vfb remains greater than the first reference voltage Vref1, and the first comparison signal Vcmp1 maintains the second level. Figure 3 Subsequently, the feedback voltage Vfb decreases from being greater than the first reference voltage Vref1 to being less than the first reference voltage Vref1, and the first comparison signal Vcmp1 flips from the second level to the first level. As the feedback voltage Vfb continues to decrease, the feedback voltage Vfb remains less than the first reference voltage Vref1, and the first comparison signal Vcmp1 maintains the first level.

[0060] Each time the first comparison signal Vcmp1 flips from the first level to the second level, the count value within the first counter 121 is incremented by one. Clearly, the first counter 121 can count the number of consecutive flips of the first comparison signal Vcmp1 from the first level to the second level. If the number of consecutive flips of the first comparison signal Vcmp1 from the first level to the second level does not reach the first preset number, this indicates that the current feedback voltage Vfb is experiencing a relatively low number of oscillations, i.e., the output voltage Vout is experiencing a relatively low number of oscillations, making it difficult to determine whether the output voltage Vout is oscillating at a high frequency. Therefore, at this point, the output first capacitor connection status detection signal Det1 remains the capacitor connection normal signal Cout_ok.

[0061] When the first comparison signal Vcmp1 switches from the first level to the second level continuously for a number of times reaching the first preset number, it indicates that the current output voltage Vout oscillates a lot, that is, the output voltage Vout is currently oscillating at a high frequency. At this time, the first capacitor connection state detection signal Det1 switches from a high level to a low level, that is, switches to a capacitor connection abnormality signal Cout_ng, such as Figure 3 As shown, it indicates that the connection state of the output capacitor Cout is abnormal.

[0062] Continue to see Figure 4 The logic module 130 includes an AND gate AND, a first input end of the AND gate AND is connected to the output end of the first counter 121, a second input end of the AND gate AND receives an enable signal EN of the linear regulator 200, and an output end of the AND gate AND is connected to the enable end of the linear regulator 200.

[0063] After the linear regulator 200 is powered on, the enable signal EN is at a high level. When the first capacitor connection state detection signal Det1 is a capacitor connection abnormality signal Cout_ng, the AND gate AND outputs a low level to disable the linear regulator 200, thereby stopping the linear regulator 200. When the first capacitor connection state detection signal Det1 is a capacitor connection normality signal Cout_ok, the AND gate AND outputs a high level to enable the linear regulator 200, thereby enabling the linear regulator 200.

[0064] In the embodiment of the present disclosure, the capacitor detection circuit includes a comparison module, a counting module and a logic module. The comparison module can compare the reference voltage and the feedback voltage to obtain a comparison signal. The feedback voltage is the product of the output voltage of the linear regulator and the voltage division coefficient. The counting module can count the number of consecutive flips of the comparison signal from the first level to the second level, and determine the capacitor connection status detection signal used to characterize the connection status of the output capacitor based on whether the number of consecutive flips of the comparison signal reaches a preset number. The connection status of the output capacitor can be detected in real time during the operation of the linear regulator. After the linear regulator is turned on, the logic module controls whether the linear regulator is working based on the capacitor connection status detection signal, so that the linear regulator stops working when the output capacitor connection is abnormal, which can reduce the safety risks caused by the output capacitor abnormality.

[0065] In some embodiments, Figure 5 A circuit diagram of a first counter provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the first counter 121 includes a starting unit 1211 , a multi-stage D flip-flop unit 1212 and a signal generating unit 1213 .

[0066] The input terminal of the start-up unit 1211 is connected to the output terminal of the first high-speed comparator 111. The output terminal of the start-up unit 1211 is connected to the set terminal set of each D flip-flop in the multi-stage D flip-flop unit 1212 and the enable terminal of the signal generating unit 1213. The output terminal of the multi-stage D flip-flop unit 1212 is connected to the input terminal of the signal generating unit 1213. The output terminal of the signal generating unit 1213 is connected to the first input terminal of the logic module 130. For the multi-stage D flip-flop unit 1212: the clock terminal clk of the first-stage D flip-flop is connected to the output terminal of the first high-speed comparator 111, the output terminal q of the last-stage D flip-flop is connected to the input terminal d of the signal generating unit 1213, and the input terminal d and the inverting output terminal of the previous-stage D flip-flop in the two adjacent stages are connected. The clock terminal clk of the next-stage D flip-flop is connected, and the number of D flip-flops in the multi-stage D flip-flop unit 1212 is related to the first preset number.

[0067] Exemplarily, the starting unit 1211 includes a first D flip-flop FF1, the clock terminal clk of the first D flip-flop FF1 is connected to the output terminal of the first high-speed comparator 111, the input terminal d and the set terminal set of the first D flip-flop FF1 are connected to the high level ONE, and the output terminal q of the first D flip-flop FF1 is connected to the set terminal set of each D flip-flop in the multi-stage D flip-flop unit 1212 and the enable terminal of the signal generating unit 1213.

[0068] After the linear regulator 200 is powered on, when the first comparison signal Vcmp1 switches from the first level to the second level for the first time, the output of the first D flip-flop FF1 switches from the low level to the high level, thereby enabling the signal generating unit 1213 and each D flip-flop in the multi-stage D flip-flop unit 1212. The inverting output terminal of the first stage D flip-flop in the multi-stage D flip-flop unit 1212 is switched to the inverting output terminal of the first stage D flip-flop. Output q of the first-stage D flip-flop outputs a low level, and the output terminal q of the first-stage D flip-flop outputs a high level, that is, the count value inside the first counter 121 is one, that is, the number of consecutive togglings of the first comparison signal Vcmp1 is one. Thereafter, each time the first comparison signal Vcmp1 toggles from the first level to the second level, the count value inside the first counter 121 is incremented by one, that is, the number of consecutive togglings of the first comparison signal Vcmp1 is incremented by one.

[0069] The signal generating unit 1213 includes a second D flip-flop FF2 and a first inverter INV1, the input terminal d of the second D flip-flop FF2 receives a high level ONE, the set terminal set of the second D flip-flop FF2 is connected to the output terminal q of the first D flip-flop FF1, the output terminal q of the second D flip-flop FF2 is connected to the first input terminal of the logic module 130 through the first inverter INV1, and the clock terminal clk of the second D flip-flop FF2 is connected to the output terminal q of the last stage D flip-flop in the multi-stage D flip-flop unit 1212.

[0070] When the first comparison signal Vcmp1 flips from the first level to the second level continuously for a number of times reaching a first preset number, the output of the last-stage D flip-flop in the multi-stage D flip-flop unit 1212 flips from a low level to a high level, and the second D flip-flop DFF2 outputs a high level. After being inverted by the first inverter INV1, the output first capacitor connection state detection signal Det1 is the capacitor connection abnormality signal Cout_ng.

[0071] In some embodiments, Figure 6 A circuit diagram of a first high-speed comparator provided by an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the first high-speed comparator 111 includes a current generating unit 1111 , a pull-up unit 1112 , a pull-down unit 1113 and an output unit 1114 .

[0072] Among them, the first input end of the current generating unit 1111 receives the first reference voltage Vref1, the second input end of the current generating unit 1111 is the feedback end FB, the first output end of the current generating unit 1111 is connected to the bias end of the pull-up unit 1112, the second output end of the current generating unit 1111 is connected to the control end of the pull-down unit 1113, and the connection point A between the pull-up unit 1112 and the pull-down unit 1113 is connected to the input end of the first counter 121 through the output unit 1114.

[0073] The current generating unit 1111 is configured to generate a dynamic bias current Ibias_dy according to a voltage difference Vfb-Vref1 between the feedback voltage Vfb and the first reference voltage Vref1 when the feedback voltage Vfb is greater than the first reference voltage Vref1, wherein the current value of the dynamic bias current Idrv_dy is proportional to the voltage difference Vfb-Vref1.

[0074] The pull-up unit 1112 is configured to, when the feedback voltage Vfb is greater than the first reference voltage Vref1, pull up the connection point voltage Va according to the constant bias current Ibias_cot and the dynamic bias current Ibias_dy. The pull-down unit 1113 is configured to, when the feedback voltage Vfb is less than the first reference voltage Vref1, pull down the connection point voltage Va to ground.

[0075] The output unit 1114 is configured to flip the first comparison signal Vcmp1 from the first level to the second level when the connection point voltage Va rises to the first preset voltage Vpre1, and to flip the first comparison signal Vcmp1 from the second level to the first level when the connection point voltage Va drops to the second preset voltage Vpre2, and the first preset voltage Vpre1 is greater than the second preset voltage Vpre2.

[0076] For example, Figure 6 As shown, the current generating unit 1111 includes a current source IB, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7. A first terminal of the first transistor M1 and a first terminal of the second transistor M2 are connected to a power supply voltage Vcc, a control terminal of the first transistor M1 is connected to a second terminal of the first transistor M1, a control terminal of the second transistor M2, and a control terminal of the pull-up unit 1112, a second terminal of the first transistor M1 is grounded via the current source IB, and a second terminal of the second transistor M2 is connected to a first terminal of the third transistor M3 and a first terminal of the fourth transistor M4.

[0077] A control end of the third transistor M3 receives a first reference voltage Vref1, a control end of the fourth transistor M4 is connected to the feedback end FB, a second end of the third transistor M3 is connected to the second end of the fifth transistor M5, the control end of the fifth transistor M5, the control end of the sixth transistor M6, and the control end of the seventh transistor M7, a first end of the fifth transistor M5, a first end of the sixth transistor M6, and a first end of the seventh transistor M7 are grounded, a second end of the fourth transistor M4 is connected to the second end of the sixth transistor M6 and the control end B of the pull-down unit 1113, and a second end of the seventh transistor M7 is connected to the bias end of the pull-up unit 1112.

[0078] The pull-up unit 1112 includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10. The first end of the eighth transistor M8, the first end of the ninth transistor M9, and the first end of the tenth transistor M10 are connected to the power supply voltage Vcc. The control end of the eighth transistor M8 is connected to the second end of the eighth transistor M8, the control end of the ninth transistor M9, and the first output end of the current generating unit 1111. The second end of the ninth transistor M9 is connected to the second end of the tenth transistor M10, the connection point A, and the input end of the output unit 1114. The control end of the tenth transistor M10 is connected to the bias end of the current generating unit 1111.

[0079] The pull-down unit 1113 includes an eleventh transistor M11, a first end of the eleventh transistor M11 is grounded, a control end of the eleventh transistor M11 is connected to the second output end of the voltage generating unit 1111, and a second end of the eleventh transistor M11 is connected to the input end of the output unit 1114 and the connection point A.

[0080] The output unit 1114 includes a Schmitt trigger SCHMITT, a second inverter INV2 and a third inverter INV3. The input end of the Schmitt trigger SCHMITT is connected to the connection point A, the output end of the Schmitt trigger SCHMITT is connected to the input end of the third inverter INV3 through the second inverter, and the output end of the third inverter INV3 is connected to the input end of the first counter 121.

[0081] The first transistor M1, the second transistor M2, and the tenth transistor M10 form a first current structure, and the third transistor M3 and the fourth transistor M4 form an input transistor pair. A current source IB provides a constant bias current Ibias_cot to the first current structure. The second transistor M2 mirrors the constant bias current Ibias_cot into a first current I1 and provides the first current I1 to the input transistor pair. The current flowing through the third transistor M3 is the second current I2, and the current flowing through the fourth transistor M4 is the third current I3. Thus, I1 = I2 + I3.

[0082] The fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eleventh transistor M11 form a second current mirror structure, and the eighth transistor M8 and the ninth transistor M9 form a third current mirror structure. The second current I2 serves as a bias current for the second current mirror structure. The sixth transistor M6 can mirror the second current into a third current I3. The seventh transistor M7 can mirror the second current I2 into a dynamic bias current Ibias_dy and provide it to the third current mirror structure.

[0083] The tenth transistor M10 mirrors the constant bias current Ibias_cot into a constant current Icot and provides it to the connection point A. The ninth transistor M9 can mirror the dynamic bias current Ibias_dy into a dynamic current Idy and provide it to the connection point A. Therefore, the current flowing into the connection point A is Idy+Icot.

[0084] Reference below Figure 7 The working process of the first high-speed comparator 111 is exemplarily described. Figure 7 This is a simulation diagram of various signals in a first high-speed comparator provided in an embodiment of the present disclosure.

[0085] After the linear regulator 200 is powered on, the feedback voltage Vfb begins to rise from zero, increasing the control voltage Vb of the pull-down unit 1113. This turns on the eleventh transistor M11, which can pull the connection point voltage Va down to ground. At this point, the second current I2 is much smaller than the third current I3, resulting in relatively small dynamic bias current Ibias_dy and dynamic current Idy. For example, Ibias_dy = 0.35 μA and dynamic current Idy = 1.05 μA, resulting in a relatively small current Idy + Icot flowing into the connection point A.

[0086] As the feedback voltage Vfb rises, the third current I3 slowly decreases, the second current I2 slowly increases, the dynamic current Idy slowly increases, and the current Idy + Icot flowing into the connection point A slowly increases. When the output capacitor Cout is in a normal connection state, the dynamic current Idy is small, and the current Idy + Icot flowing into the connection point A remains at a low level.

[0087] When the output capacitor Cout is in an abnormal connection state, the feedback voltage Vfb rises to a value greater than the first reference voltage Vref1. At this point, the second current I2 is greater than the third current I3, and the dynamic current Idy is relatively large. For example, Ibias_dy = 2 μA, and the dynamic current Idy = 6 μA. Consequently, a relatively large current Idy + Icot flows into the connection point A. This improves the pull-up capability of the pull-up unit 1112 at the connection point A, thereby increasing the response speed of the capacitance detection circuit 100.

[0088] The feedback voltage Vfb reaches a maximum value and then begins to decrease. When the feedback voltage Vfb decreases to be lower than the first reference voltage Vref1, the second current I2 decreases, and the current Idy+Icot flowing into the connection point A decreases, thereby reducing unnecessary losses and thus reducing the power consumption of the capacitance detection circuit 100.

[0089] During the rising process of the connection point voltage Va, when the connection point voltage Va does not reach the first preset voltage Vpre1, for example, the first preset voltage Vpre1 is 1.3V, the Schmitt trigger SCHMITT outputs the first level, and the first comparison signal Vcmp1 is the first level. When the connection point voltage Va rises to the first preset voltage Vpre1, the output of the Schmitt trigger SCHMITT flips from the first level to the second level, and the first comparison signal Vcmp1 flips from the first level to the second level.

[0090] During the process of the connection point voltage Va decreasing, when the connection point voltage Va does not reach the second preset voltage Vpre2, for example, the second preset voltage Vpre2 is 1.1V, the Schmitt trigger SCHMITT outputs the second level, and the first comparison signal Vcmp1 is the second level. When the connection point voltage Va decreases to the second preset voltage Vpre2, the output of the Schmitt trigger SCHMITT flips from the second level to the first level, and the first comparison signal Vcmp1 flips from the second level to the first level.

[0091] In the embodiment of the present disclosure, when the feedback voltage Vfb is greater than the first reference voltage Vref1, the current generating unit 1111 generates a dynamic bias current Ibias_dy, and the pull-up unit 1112 pulls up the connection point voltage Va according to the constant bias current Ibias_cot and the dynamic bias current Ibias_dy. When the feedback voltage Vfb is less than the first reference voltage Vref1, the pull-down unit 1113 pulls the connection point voltage Va to ground. When the capacitor connection is normal, real-time detection can be performed with lower power consumption. When the capacitor connection is abnormal and the feedback voltage Vfb is lower than the first reference voltage Vref1, real-time detection can be performed with lower power consumption. When the capacitor connection is abnormal and the feedback voltage Vfb is greater than the first reference voltage, real-time detection can be performed with higher power consumption, thereby improving the capacitor detection efficiency. Therefore, the requirements of high efficiency and low power consumption of capacitor detection can be met at the same time.

[0092] In some embodiments, Figure 8 A circuit diagram of another first high-speed comparator provided by an embodiment of the present disclosure is shown in FIG. Figure 8 As shown, the first high-speed comparator 111 further includes a clamping unit 1115 , a first end of the clamping unit 1115 is connected to the control end of the pull-down unit 1113 , and a second end of the clamping unit 1115 is connected to the connection point A.

[0093] For example, Figure 8As shown, the clamping unit 1115 includes a twelfth transistor M12 and a thirteenth transistor M13, the first end of the twelfth transistor M12 is connected to the second end of the thirteenth transistor M13, the control end of the thirteenth transistor M13, the second output end of the voltage generating unit 1111 and the control end of the pull-down unit 1113, the second end of the twelfth transistor M12 is connected to the power supply voltage Vcc, and the first end of the thirteenth transistor M13 is connected to the connection point A and the input end of the output unit 1114.

[0094] In the process of the feedback voltage Vfb rising from 0V to a value higher than the first reference voltage Vref1, when Vb-Va>Vclamp1, the thirteenth transistor M13 is turned on, and a first clamping voltage Vclamp1 is formed between the connection point A and the control terminal B, that is, Vb-Va=Vclamp1, so that the connection point voltage Va starts to rise from a larger voltage value and the control voltage Vb starts to fall from a smaller voltage value, thereby shortening the time it takes for the first high-speed comparator 111 to flip upward.

[0095] For example, when the feedback voltage Vfb rises from 0V to a value higher than the first reference voltage Vref1, without the thirteenth transistor M13, Va rises from 0V to 1.3V, Vb drops from 3V to 0.7V, and the first comparison signal Vcmp1 flips from the first level to the second level. If the thirteenth transistor M13 is provided, Va rises from 0.2V to 1.3V, and Vb drops from 0.9V to 0.7V, the upward flipping time of the first high-speed comparator 111 can be shortened, thereby improving the efficiency of capacitance detection.

[0096] In the process of the feedback voltage Vfb decreasing from being higher than the first reference voltage Vref1 to being lower than the first reference voltage Vref1, when Va-Vb>Vclamp2, the twelfth transistor M12 is turned on, and a second clamping voltage Vclamp2 is formed between the connection point A and the control terminal B, that is, Va-Vb=Vclamp2, so that the control voltage Vb starts to rise from a larger voltage value and the connection point voltage Va starts to fall from a smaller voltage value, thereby shortening the time it takes for the first high-speed comparator 111 to flip downward.

[0097] It should be noted that the first clamping voltage Vclamp1 and the second clamping voltage Vclamp2 may be the same or different, and the present disclosure does not impose any specific limitation on this.

[0098] In the embodiment of the present disclosure, the clamping unit 1115 can limit the voltage drop |Va-Vb| between the control terminal B and the connection point A of the pull-down unit 1113 to not exceed the clamping voltage Vclamp, which can shorten the time required for signal flipping and thus improve the capacitance detection efficiency.

[0099] In some embodiments, Figure 9 A circuit diagram of another capacitance detection circuit provided by an embodiment of the present disclosure is shown as follows: Figure 9 As shown, the comparison module 110 further includes a second high-speed comparator 112, and the counting module 120 further includes a second counter 122. An inverting input terminal of the second high-speed comparator 112 is connected to the feedback terminal FB, a non-inverting input terminal of the second high-speed comparator 112 is connected to the second reference voltage Vref2, and an output terminal of the second high-speed comparator 112 is connected to a second input terminal of the logic module 130 via the second counter 122.

[0100] For example, when the connection state of the output capacitor Cout is a capacitor connection abnormality caused by a missing capacitor, the maximum voltage value of the feedback voltage Vfb will exceed the product of the overvoltage threshold value OV and the voltage divider coefficient. Continuous exceeding of a certain voltage value by the feedback voltage Vfb can be used as a detection criterion for the connection state of the output capacitor Cout being a capacitor connection abnormality caused by a missing capacitor. When the connection state of the output capacitor Cout is a capacitor connection abnormality caused by a capacitance value deviation, an internal loop error of the linear regulator, and / or a capacitor mismatch, the feedback voltage Vfb oscillates between the product of the undervoltage threshold value UV and the voltage divider coefficient and the product of the overvoltage threshold value OV and the voltage divider coefficient. Continuous lowering of the feedback voltage Vfb below another voltage value can be used as a detection criterion for the connection state of the output capacitor Cout being a capacitor connection abnormality caused by a capacitance value deviation, an internal loop error of the linear regulator, and / or a capacitor mismatch.

[0101] The voltage value of the second reference voltage Vref2 is less than the product of the standard value SV and the voltage division coefficient and greater than the product of the undervoltage threshold UV and the voltage division coefficient. After the linear regulator 200 is powered on, when the feedback voltage Vfb continues to be greater than the second reference voltage Vref2, the second comparison signal Vcmp2 maintains the first level and does not flip from the first level to the second level. The number of consecutive flips of the second comparison signal Vcmp2 from the first level to the second level counted by the second counter 122 is zero, and the output second capacitor connection status detection signal Det2 maintains the capacitor connection normal signal Cout_ok. At this time, the connection status of the output capacitor Cout is the capacitor connection is normal.

[0102] When the feedback voltage Vfb drops from being greater than the second reference voltage Vref2 to being less than the second reference voltage Vref2, the second comparison signal Vcmp2 flips from the first level to the second level. As the feedback voltage Vfb continues to drop, the feedback voltage Vfb becomes less than the second reference voltage Vref2, and the second comparison signal Vcmp2 maintains the second level. Subsequently, when the feedback voltage Vfb rises from being less than the second reference voltage Vref2 to being greater than the second reference voltage Vref2, the second comparison signal Vcmp2 flips from the second level to the first level. As the feedback voltage Vfb continues to rise, the feedback voltage Vfb becomes greater than the second reference voltage Vref2.

[0103] Each time the second comparison signal Vcmp2 flips from the first level to the second level, the count value within the second counter 122 is incremented by one. Clearly, the second counter 122 can count the number of consecutive flips of the second comparison signal Vcmp2 from the first level to the second level. If the number of consecutive flips of the second comparison signal Vcmp2 from the first level to the second level does not reach the second predetermined number, this indicates that the current output voltage Vout is experiencing relatively few oscillations, making it difficult to determine whether the output voltage Vout is oscillating at a high frequency. Therefore, at this point, the output second capacitor connection status detection signal Det2 remains the capacitor connection normal signal Cout_ok.

[0104] When the second comparison signal Vcmp2 continuously flips from the first level to the second level a second predetermined number of times, it indicates that the current output voltage Vout is oscillating a large number of times, that is, the output voltage Vout is currently oscillating at a high frequency. At this time, the second capacitor connection state detection signal Det2 flips from a high level to a low level, that is, flips to a capacitor connection abnormality signal Cout_ng, indicating that the connection state of the output capacitor Cout is a capacitor connection abnormality caused by capacitance value deviation, internal loop error of the linear regulator, and / or capacitor mismatch.

[0105] The second high-speed comparator 112 has the same circuit structure as the first high-speed comparator 111, which will not be described in detail here. Compared with the first high-speed comparator 111, the second high-speed comparator 112 is different in that the control end of the third transistor M3 receives the feedback voltage Vfb, and the control end of the fourth transistor M4 receives the second reference voltage Vref2.

[0106] The second counter 122 has the same circuit structure as the first counter 121, which will not be further described here. A possible difference between the two is that the number of D flip-flops in the multi-stage D flip-flop unit in the second counter 122 and the first counter 121 is different, and the corresponding first preset number and second preset number are different. In other embodiments, the number of D flip-flops in the multi-stage D flip-flop unit in the second counter 122 and the first counter 121 is the same, and the first preset number is equal to the second preset number.

[0107] Continue to see Figure 9 The logic module 130 includes an AND gate AND, a first input end of the AND gate AND is connected to the output end of the first counter 121, a second input end of the AND gate AND is connected to the output end of the second counter 122, a third input end of the AND gate AND receives an enable signal EN of the linear regulator 200, and an output end of the AND gate AND is connected to the enable end of the linear regulator 200.

[0108] After the linear regulator 200 is powered on, the enable signal EN is at a high level. When the first capacitor connection state detection signal Det1 or the second capacitor connection state detection signal Det2 is the capacitor connection abnormality signal Cout_ng, the AND gate AND outputs a low level to disable the linear regulator 200, thereby stopping the linear regulator 200. When the first capacitor connection state detection signal Det1 or the second capacitor connection state detection signal Det2 is the capacitor connection normality signal Cout_ok, the AND gate AND outputs a high level to enable the linear regulator 200, thereby controlling the linear regulator 200 to operate normally.

[0109] In the embodiment of the present disclosure, it is possible to distinguish between capacitor connection abnormalities caused by capacitor missing, and capacitor connection abnormalities caused by capacitance value offset, internal loop error of the linear regulator and / or capacitor mismatch, providing support for subsequent abnormality troubleshooting of the output capacitor Cout and facilitating the positioning of the abnormal point of the output capacitor Cout.

[0110] Unless the context clearly indicates otherwise, as used herein and in the appended claims, the singular includes the plural, and vice versa. Thus, when referring to the singular, the plural of the corresponding term is generally included. Similarly, the words "include" and "comprising" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, the "example" is merely illustrative and should not be considered exclusive or comprehensive.

[0111] Several embodiments of the present disclosure have been described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A capacitance detection circuit for a linear regulator, characterized in that: The output end of the linear regulator is grounded via an output capacitor, and the capacitance detection circuit includes a comparison module, a counting module and a logic module; The first input terminal of the comparison module is connected to the reference voltage, the second input terminal of the comparison module is connected to the feedback terminal of the linear regulator, the output terminal of the comparison module is connected to the input terminal of the logic module through the counting module, and the output terminal of the logic module is connected to the enable terminal of the linear regulator; The comparison module is configured to, after the linear regulator is powered on, compare the reference voltage and the feedback voltage to obtain a comparison signal, wherein the feedback voltage is a product of the output voltage of the linear regulator and a voltage division coefficient, wherein the reference voltage includes a first reference voltage, and a voltage value of the first reference voltage is less than a product of an overvoltage threshold and the voltage division coefficient and greater than a standard value and a product of the voltage division coefficient; The counting module is configured to, after the linear regulator is powered on, count the number of consecutive flips of the comparison signal from the first level to the second level, and determine a capacitor connection state detection signal based on whether the number of consecutive flips of the comparison signal reaches a preset number, wherein the capacitor connection state detection signal is used to indicate the connection state of the output capacitor; The logic module is configured to control whether the linear regulator works according to the capacitor connection status detection signal after the linear regulator is turned on, so that the linear regulator stops working when the output capacitor connection is abnormal and works when the output capacitor connection is normal.

2. The capacitance detection circuit according to claim 1, wherein: The comparison module includes a first high-speed comparator, and the counting module includes a first counter; The non-inverting input terminal of the first high-speed comparator is connected to the feedback terminal, the inverting input terminal of the first high-speed comparator is connected to the first reference voltage, the voltage value of the first reference voltage is less than the product of the overvoltage threshold of the output voltage and the voltage division coefficient and greater than the product of the standard value of the output voltage and the voltage division coefficient, and the output terminal of the first high-speed comparator is connected to the first input terminal of the logic module through the first counter; The first counter is configured to determine that the first capacitor connection state detection signal is a capacitor connection abnormality signal when the number of consecutive flips of the first comparison signal reaches a first preset number, and to determine that the first capacitor connection state detection signal is a capacitor connection normal signal when the number of consecutive flips of the first comparison signal does not reach the first preset number.

3. The capacitance detection circuit according to claim 2, wherein: The comparison module further includes a second high-speed comparator, and the counting module further includes a second counter; an inverting input terminal of the second high-speed comparator connected to the feedback terminal, a non-inverting input terminal of the second high-speed comparator connected to a second reference voltage, a voltage value of the second reference voltage being less than a product of the standard value and the voltage division coefficient and greater than a product of an undervoltage threshold of the output voltage and the voltage division coefficient, and an output terminal of the second high-speed comparator connected to the second input terminal of the logic module via the second counter; The second counter is configured to, when the number of consecutive flips of the second comparison signal reaches a second preset number, determine that the second capacitor connection state detection signal is the capacitor connection abnormality signal; when the number of consecutive flips of the second comparison signal does not reach the second preset number, determine that the second capacitor connection state detection signal is the capacitor connection normal signal.

4. The capacitance detection circuit according to claim 2, wherein: The first high-speed comparator includes a current generating unit, a pull-up unit, a pull-down unit and an output unit; A first input terminal of the current generating unit is connected to the first reference voltage, a second input terminal of the current generating unit is connected to the feedback terminal, a first output terminal of the current generating unit is connected to the bias terminal of the pull-up unit, a second output terminal of the current generating unit is connected to the control terminal of the pull-down unit, and a connection point between the pull-up unit and the pull-down unit is connected to the input terminal of the first counter via the output unit; The current generating unit is configured to, when the feedback voltage is greater than the first reference voltage, generate a dynamic bias current according to a voltage difference between the feedback voltage and the first reference voltage, wherein a current value of the dynamic bias current is proportional to the voltage difference; The pull-up unit is configured to, when the feedback voltage is greater than the first reference voltage, pull up the connection point voltage according to the constant bias current and the dynamic bias current; The pull-down unit is configured to pull the connection point voltage down to ground when the feedback voltage is less than the first reference voltage; The output unit is configured to flip the first comparison signal from the first level to the second level when the connection point voltage rises to a first preset voltage, and to flip the first comparison signal from the second level to the first level when the connection point voltage drops to a second preset voltage, wherein the first preset voltage is greater than the second preset voltage.

5. The capacitance detection circuit according to claim 4, characterized in that: The current generating unit includes a current source, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; The first end of the first transistor and the first end of the second transistor are connected to a power supply voltage, the control end of the first transistor is connected to the second end of the first transistor, the control end of the second transistor and the control end of the pull-up unit, the second end of the first transistor is grounded through the current source, and the second end of the second transistor is connected to the first end of the third transistor and the first end of the fourth transistor; The control end of the third transistor is connected to the first reference voltage, the control end of the fourth transistor is connected to the feedback end, the second end of the third transistor is connected to the second end of the fifth transistor, the control end of the fifth transistor, the control end of the sixth transistor and the control end of the seventh transistor, the first end of the fifth transistor, the first end of the sixth transistor and the first end of the seventh transistor are grounded, the second end of the fourth transistor is connected to the second end of the sixth transistor and the control end of the pull-down unit, and the second end of the seventh transistor is connected to the bias end of the pull-up unit.

6. The capacitance detection circuit according to claim 4, characterized in that: The pull-up unit includes an eighth transistor, a ninth transistor, and a tenth transistor; The first end of the eighth transistor, the first end of the ninth transistor and the first end of the tenth transistor are connected to the power supply voltage, the control end of the eighth transistor is connected to the second end of the eighth transistor, the control end of the ninth transistor and the first output end of the current generating unit, the second end of the ninth transistor is connected to the connection point, the input end of the output unit and the second end of the tenth transistor, and the control end of the tenth transistor is connected to the bias end of the current generating unit.

7. The capacitance detection circuit according to claim 4, characterized in that: The first high-speed comparator further includes a clamping unit; The first end of the clamping unit is connected to the control end of the pull-down unit, and the second end of the clamping unit is connected to the connection point; The clamping unit is configured to limit a voltage drop between the control terminal of the pull-down unit and the connection point to not exceed a clamping voltage.

8. The capacitance detection circuit according to any one of claims 2 to 7, characterized in that: The first counter includes a start unit, a multi-stage D flip-flop unit and a signal generating unit; The input end of the startup unit is connected to the output end of the first high-speed comparator, the output end of the startup unit is connected to the set end of each D flip-flop in the multi-stage D flip-flop unit and the enable end of the signal generating unit, the output end of the multi-stage D flip-flop unit is connected to the input end of the signal generating unit, and the output end of the signal generating unit is connected to the first input end of the logic module; For the multi-stage D flip-flop unit: the clock end of the first-stage D flip-flop is connected to the output end of the first high-speed comparator, the output end of the last-stage D flip-flop is connected to the input end of the signal generating unit, and the input end and inverting output end of the previous-stage D flip-flop in two adjacent stages of D flip-flops are connected to the clock end of the next-stage D flip-flop.

9. The capacitance detection circuit according to claim 3, characterized in that: The logic module is further configured to, after the linear regulator is powered on, control the linear regulator to stop working when the first capacitor connection state detection signal or the second capacitor connection state detection signal is the capacitor connection abnormality signal, and control the linear regulator to work normally when the first capacitor connection state detection signal or the second capacitor connection state detection signal is the capacitor connection normal signal.

10. A power chip, characterized in that: The device comprises a linear regulator and the capacitance detection circuit according to any one of claims 1 to 9, wherein the output end of the linear regulator is grounded via an output capacitor.

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