Thyristor driving circuit and electrical equipment

Abstract

The invention is applicable to the technical field of electronic circuits, and provides a thyristor driving circuit and electrical equipment, and the circuit comprises a time-sharing wave sending module, a signal enhancement module and a driving output module. The thyristor driving circuit comprises a time-sharing wave sending module, a signal enhancement module and a driving output module, and the time-sharing wave sending module outputs a first driving signal, a second driving signal and a third driving signal in a time-sharing manner when receiving a driving control signal output by a processor. The first driving signal, the second driving signal and the third driving signal are averagely distributed in time, that is, the time proportions of the first driving signal, the second driving signal and the third driving signal are the same in a wave sending period. After the signals are enhanced by the signal enhancement module, the three-phase thyristor driving signals are respectively output to the thyristors of the corresponding phases through the driving output module, the implementation mode is simple and reliable, only the thyristor of one phase is driven at the same time, and the ripple current of the driving power supply is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and particularly relates to a thyristor drive circuit and an electrical device. Background Art

[0002] Existing thyristor drive circuit systems usually adopt two methods in the drive mode. The first is to use a simple unified carrier processing method, and the other is to adopt complex means to increase the instantaneous drive current provided by the drive circuit during the drive process. For the first method, since the high level (or low level) of the drive part corresponds to all drives at the same moment, the ripple current of the drive power supply is very large. For the second method, there are defects that the instantaneous drive current and the steady-state drive loss provided by the drive circuit during the thyristor drive process do not reach the optimum. Summary of the Invention

[0003] An embodiment of the present invention provides a thyristor drive circuit, aiming to solve the problems that the traditional thyristor drive circuit system is likely to cause excessive ripple current of the drive power supply and excessive instantaneous drive current and steady-state drive loss.

[0004] The embodiment of the present invention is implemented as follows. A thyristor drive circuit includes:

[0005] A time-sharing wave generation module, connected to a processor, for receiving a drive control signal output by the processor to output a first drive signal, a second drive signal, and a third drive signal in a time-sharing manner. In a wave generation cycle, the time ratios of the first drive signal, the second drive signal, and the third drive signal are the same;

[0006] A signal enhancement module, including three signal enhancement branches connected to the time-sharing wave generation module and the processor. The three signal enhancement branches are respectively used for receiving the first drive signal, the second drive signal, and the third drive signal, and combining and enhancing the drive control signal output by the processor with the first drive signal, the second drive signal, and the third drive signal respectively to obtain a first enhanced signal, a second enhanced signal, and a third enhanced signal and output them;

[0007] A drive output module, including three drive branches connected to the three signal enhancement branches in one-to-one correspondence. The three drive branches are also respectively connected to three-phase thyristors in one-to-one correspondence. The three drive branches are respectively used for outputting a first thyristor drive signal, a second thyristor drive signal, and a third thyristor drive signal to the three-phase thyristors when receiving the first enhanced signal, the second enhanced signal, and the third enhanced signal.

[0008] Furthermore, the thyristor drive circuit further includes a drive power supply monitoring module;

[0009] The drive power supply monitoring module is connected to the drive power supply and the time-sharing wave generation module, and is used to monitor the voltage value of the drive power supply and send the monitoring result to the time-sharing wave generation module.

[0010] Furthermore, the time-sharing wave generation module includes a first monostable chip, a second monostable chip, a third monostable chip, a first NAND gate, a second NAND gate, a third NAND gate, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor;

[0011] One input terminal of the first NAND gate is connected to the drive power supply monitoring module, the other input terminal is connected to the processor, and the output terminal is connected to the two input terminals of the second NAND gate;

[0012] The output terminal of the second NAND gate is connected to the first signal terminal;

[0013] The ninth pin of the first monostable chip is connected to one input terminal of the third NAND gate through the first resistor, the tenth pin is used to output the first drive signal, the eleventh pin is connected to the first voltage terminal through the second resistor, the twelfth pin is connected to the ninth pin of the third monostable chip through the third resistor, the thirteenth pin is connected to the first signal terminal through the fourth resistor, the fourteenth pin is connected to the first voltage terminal through the fifth resistor and is connected to one end of the first capacitor, and the fifteenth pin is grounded;

[0014] The other end of the first capacitor is connected to one end of the second capacitor and grounded;

[0015] The other end of the second capacitor is connected to the output terminal of the second NAND gate through the sixth resistor, and the other end of the second capacitor is also connected to the other input terminal of the third NAND gate;

[0016] The output terminal of the third NAND gate is connected to the fifth pin of the second monostable chip through the seventh resistor;

[0017] The third pin of the second monostable chip is connected to the first signal terminal through the eighth resistor, the first pin, the fourth pin, and the eighth pin are grounded, the second pin is connected to the first voltage terminal through the ninth resistor and grounded through the third capacitor, the sixth pin is used to output the second drive signal, the seventh pin is connected to the twelfth pin of the third monostable chip through the tenth resistor, and the sixteenth pin is connected to the first voltage terminal and grounded through the fourth capacitor;

[0018] The tenth pin of the third monostable chip is used to output the third drive signal, the eleventh pin is connected to the first voltage terminal, the thirteenth pin is connected to the first signal terminal through the eleventh resistor, the fourteenth pin is connected to the first voltage terminal through the twelfth resistor and grounded through the fifth capacitor, and the fifteenth pin is grounded.

[0019] Further, the signal enhancement module includes a first AND gate, a second AND gate, a third AND gate, a first triode, a second triode, a third triode, a fourth triode, a fifth triode, and a sixth triode;

[0020] Two input terminals of the first AND gate are respectively connected to the time-sharing wave generation module and the processor, and are respectively used for receiving a first driving signal and a driving control signal, and an output terminal thereof is connected to a first pole pin of the first triode and a first pole pin of the second triode;

[0021] The second pole pins of the first triode and the second triode are coupled to output a first enhancement signal;

[0022] Two input terminals of the second AND gate are respectively connected to the time-sharing wave generation module and the processor, and are respectively used for receiving a second driving signal and a driving control signal, and an output terminal thereof is connected to a first pole pin of the third triode and a first pole pin of the fourth triode;

[0023] The second pole pins of the third triode and the fourth triode are coupled to output a second enhancement signal;

[0024] Two input terminals of the third AND gate are respectively connected to the time-sharing wave generation module and the processor, and are respectively used for receiving a third driving signal and a driving control signal, and an output terminal thereof is connected to a first pole pin of the fifth triode and a first pole pin of the sixth triode;

[0025] The second pole pins of the fifth triode and the sixth triode are coupled to output a third enhancement signal;

[0026] The third pole pins of the first triode, the third triode, and the fifth triode are all connected to a first voltage terminal;

[0027] The third pole pins of the second triode, the fourth triode, and the sixth triode are all grounded.

[0028] Further, the drive output module includes three drive branches respectively corresponding to the thyristors of three phases, and each drive branch includes a MOS tube, a MOS tube drive absorption unit, a thyristor drive circuit enhancement unit, and a drive transformer output rectification unit;

[0029] The MOS tube drive absorption unit is connected to the signal enhancement module and the MOS tube, and is used for receiving the signal output by the signal enhancement module to drive the MOS tube and absorbing the electrical stress brought to the MOS tube;

[0030] The thyristor drive circuit enhancement unit is connected to the MOS tube and the drive transformer, and is used for outputting an enhanced electrical signal for driving the thyristor in the early stage of the conduction of the MOS tube;

[0031] The drive transformer output rectification unit is connected to the MOS transistor drive absorption unit, the thyristor drive circuit enhancement unit, and the thyristor of the corresponding phase, and is used to convert the electrical signal output by the thyristor drive circuit enhancement unit into the drive current of the thyristor of the corresponding phase and output it.

[0032] Furthermore, the MOS transistor drive absorption unit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first diode, a voltage regulator diode, a sixth capacitor, and a seventh capacitor;

[0033] One end of the thirteenth resistor is connected to the gate of the MOS transistor and one end of the fourteenth resistor, and the other end is connected to one path of the output of the signal enhancement module;

[0034] The source of the MOS transistor and the other end of the fourteenth resistor are grounded, and the drain of the MOS transistor is connected to the thyristor drive circuit enhancement unit, the anode of the first diode, and one end of the sixth capacitor;

[0035] The cathode of the first diode is connected to the cathode of the voltage regulator diode, and the anode of the voltage regulator diode is connected to the drive power supply;

[0036] The other end of the sixth capacitor is grounded through the fifteenth resistor;

[0037] The seventh capacitor is connected in parallel with the fourteenth resistor.

[0038] Furthermore, the thyristor drive circuit enhancement unit includes a resistor parallel body composed of a plurality of resistors connected in parallel, and a capacitor parallel body composed of a plurality of capacitors connected in parallel;

[0039] One end of the resistor parallel body is connected to the drive power supply (the anode of the voltage regulator diode), and the other end of the resistor parallel body is connected to the drive transformer, that is, the other end of the resistor parallel body is connected to an input end of the drive transformer output rectification unit and one end of the capacitor parallel body;

[0040] The other input end of the drive transformer output rectification unit is connected to the drain of the MOS transistor;

[0041] The other end of the capacitor parallel body is grounded.

[0042] Furthermore, the drive transformer output rectification unit includes a drive transformer, a second diode, a third diode, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, an eighth capacitor, and a ninth capacitor;

[0043] The drive transformer includes a primary winding, a first secondary winding, and a second secondary winding. The primary winding is connected to the thyristor drive circuit enhancement unit. One output terminal of the first secondary winding is connected to the anode of the second diode, and the other output terminal of the first secondary winding is used to output the first thyristor signal. One output terminal of the second secondary winding is connected to the anode of the third diode, and the other output terminal of the second secondary winding is used to output the second thyristor signal in the same phase;

[0044] The cathode of the second diode is connected to one end of the sixteenth resistor, and the other end of the sixteenth resistor is used to output the third thyristor signal in the same phase. The other end of the sixteenth resistor is connected to the other output terminal of the first secondary winding through the seventeenth resistor;

[0045] The eighteenth resistor is connected in parallel with the sixteenth resistor, and the eighth capacitor is connected in parallel with the seventeenth resistor;

[0046] The cathode of the third diode is connected to one end of the nineteenth resistor, and the other end of the nineteenth resistor is used to output the fourth thyristor signal in the same phase. The other end of the nineteenth resistor is connected to the other output terminal of the second secondary winding through the twentieth resistor;

[0047] The twenty-first resistor is connected in parallel with the nineteenth resistor, and the ninth capacitor is connected in parallel with the twentieth resistor.

[0048] Furthermore, the drive power supply monitoring module includes a detection chip, a seventh triode, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a tenth capacitor, an eleventh capacitor, and a twelfth capacitor;

[0049] The first terminal of the detection chip is connected to one end of the twenty-second resistor, one end of the twenty-third resistor, and one end of the tenth capacitor. The second terminal is connected to one end of the twenty-fourth resistor, and the third terminal is grounded;

[0050] The other end of the twenty-second resistor is connected to the drive power supply and one end of the eleventh capacitor;

[0051] The other end of the twenty-fourth resistor is connected to one end of the twenty-fifth resistor, one end of the twelfth capacitor, and the first pole pin of the seventh triode;

[0052] The other end of the twenty-fifth resistor, the other end of the twelfth capacitor, and the second pole pin of the seventh triode are all connected to the first voltage terminal;

[0053] The third pole pin of the seventh triode is connected to one end of the twenty-sixth resistor and the time-sharing wave generation module;

[0054] The other end of the twenty-third resistor, the other end of the tenth capacitor, the other end of the eleventh capacitor, and the other end of the twenty-sixth resistor are all grounded.

[0055] In a second aspect, the present application further provides an electrical device, including the thyristor drive circuit as described above.

[0056] The beneficial effects achieved by the present invention are as follows. The thyristor drive circuit includes a time-sharing wave generation module, a signal enhancement module, and a drive output module. Since the time-sharing wave generation module outputs a first drive signal, a second drive signal, and a third drive signal in a time-sharing manner when receiving the drive control signal output by the processor, within one wave generation cycle, the time ratios of the first drive signal, the second drive signal, and the third drive signal are the same, that is, the first drive signal, the second drive signal, and the third drive signal are evenly distributed in time. These signals are then enhanced by the signal enhancement module to obtain a first enhanced signal, a second enhanced signal, and a third enhanced signal. The drive output module outputs a first thyristor drive signal, a second thyristor drive signal, and a third thyristor drive signal to the thyristors of three phases respectively according to the first enhanced signal, the second enhanced signal, and the third enhanced signal. The implementation method is simple and reliable. Only one phase of thyristors is driven at the same moment, reducing the ripple current of the drive power supply. Description of the Drawings

[0057] Figure 1 is a schematic diagram of a module of an embodiment of the thyristor drive circuit provided by the present application;

[0058] Figure 2 is a schematic diagram of a module of another embodiment of the thyristor drive circuit provided by the present application;

[0059] Figure 3 is a schematic diagram of the circuit structure of the time-sharing wave generation module of an embodiment of the thyristor drive circuit provided by the present application;

[0060] Figure 4 is a schematic diagram of the circuit structure of the signal enhancement module of an embodiment of the thyristor drive circuit provided by the present application;

[0061] Figure 5 is a schematic diagram of the drive branch corresponding to the thyristor of phase A of the drive output module of an embodiment of the thyristor drive circuit provided by the present application;

[0062] Figure 6 is a schematic diagram of the drive branch corresponding to the thyristor of phase B of the drive output module of an embodiment of the thyristor drive circuit provided by the present application;

[0063] Figure 7 is a schematic diagram of the drive branch corresponding to the thyristor of phase C of the drive output module of an embodiment of the thyristor drive circuit provided by the present application;

[0064] Figure 8 is a schematic diagram of the thyristor circuit of an embodiment of the thyristor drive circuit provided by the present application;

[0065] Figure 9 It is a schematic circuit diagram of a drive power detection module in an embodiment of the thyristor drive circuit provided by this application;

[0066] Figure 10 It is a waveform schematic diagram of the first drive signal, the second drive signal, and the third drive signal in an embodiment of the thyristor drive circuit provided by this application. Detailed implementation manners

[0067] In order to make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0068] Since the time-sharing wave generation module in this application will output the first drive signal, the second drive signal, and the third drive signal in a time-sharing manner when receiving the drive control signal output by the processor, and evenly distribute them in time to drive the thyristor. The implementation method is simple and reliable. Only one phase of thyristor is driven at the same moment, reducing the ripple current of the drive power supply.

[0069] Embodiment 1

[0070] As Figures 1 to 10 shown, this embodiment provides a thyristor drive circuit, including:

[0071] A time-sharing wave generation module 100, connected to the processor MCU, for receiving the drive control signal DRV_SCR output by the processor MCU, and outputting the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 in a time-sharing manner. In a wave generation cycle, the time ratios of the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 are the same;

[0072] A signal enhancement module 200, including three signal enhancement branches connected to the time-sharing wave generation module 100 and the processor MCU. The three signal enhancement branches are respectively used to receive the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3, and combine and enhance the drive control signal DRV_SCR output by the processor MCU with the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 respectively to obtain the first enhanced signal DRV_SCR_A, the second enhanced signal DRV_SCR_B, and the third enhanced signal DRV_SCR_C and output them;

[0073] The drive output module 300 includes three drive branches respectively connected to three signal enhancement branches in one-to-one correspondence. The three drive branches are also respectively connected to three-phase thyristors in one-to-one correspondence. The three drive branches are respectively used for generating a first thyristor drive signal, a second thyristor drive signal, and a third thyristor drive signal to the three-phase thyristors after receiving a first enhancement signal DRV_SCR_A, a second enhancement signal DRV_SCR_B, and a third enhancement signal DRV_SCR_C.

[0074] In implementation, the thyristor drive circuit provided by this application is used to drive thyristors. The thyristors include three-phase thyristors. Exemplarily, the three-phase thyristors are respectively an A-phase thyristor, a B-phase thyristor, and a C-phase thyristor. In high-power applications, each phase of thyristors is respectively composed of 2 reverse-parallel unidirectional thyristors. The three drive branches of the drive output module 300 respectively generate a first thyristor drive signal, a second thyristor drive signal, and a third thyristor drive signal to the A-phase thyristor, B-phase thyristor, and C-phase thyristor. For example, the first thyristor drive signal is output to the A-phase thyristor, the second thyristor drive signal is output to the B-phase thyristor, and the third thyristor drive signal is output to the C-phase thyristor.

[0075] Optionally, when the system is stable, the time-sharing wave generation module 100 receives the drive control signal DRV_SCR output by the processor MCU, and then the time-sharing wave generation module 100 outputs a first drive signal SCR_PWM1, a second drive signal SCR_PWM2, and a third drive signal SCR_PWM3 in a time-sharing manner. Time-sharing output means that the time-sharing wave generation module 100 sequentially outputs the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 in a periodic cycle. That is, within one wave generation cycle, the time ratios of the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 are the same. In other words, the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 are evenly distributed in time.

[0076] Exemplarily, within one wave generation cycle, the wave generation cycle is evenly divided into three time periods. Taking the wave generation cycle time being 3 milliseconds as an example, the three time periods are 0 - 1, 1 - 2, and 2 - 3, with the unit being milliseconds. The first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 as described above can be output respectively during these three time periods. For example, the first drive signal SCR_PWM1 can be output during 0 - 1, the second drive signal SCR_PWM2 can be output during 1 - 2, and the third drive signal SCR_PWM3 can be output during 2 - 3. Or the second drive signal SCR_PWM2 can be output during 0 - 1, the third drive signal SCR_PWM3 can be output during 1 - 2, and the first drive signal SCR_PWM1 can be output during 2 - 3. Or the third drive signal SCR_PWM3 can be output during 0 - 1, the first drive signal SCR_PWM1 can be output during 1 - 2, and the second drive signal SCR_PWM2 can be output during 2 - 3. There is no limitation.

[0077] Optionally, the first signal enhancement branch of the signal enhancement module 200 is used to receive the first drive signal SCR_PWM1, and when the first drive signal SCR_PWM1 is received, the drive control signal DRV_SCR and the first drive signal SCR_PWM1 are combined and enhanced to obtain the first enhanced signal DRV_SCR_A, which is output to the first drive branch of the drive output module 300. After receiving the first enhanced signal DRV_SCR_A, the first drive branch outputs the first thyristor drive signal to the thyristor of phase A according to the first enhanced signal DRV_SCR_A.

[0078] Similarly, the second signal enhancement branch of the signal enhancement module 200 is used to receive the second drive signal SCR_PWM2, and when the second drive signal SCR_PWM2 is received, the drive control signal DRV_SCR and the second drive signal SCR_PWM2 are combined and enhanced to obtain the second enhanced signal DRV_SCR_B, which is output to the second drive branch of the drive output module 300. After receiving the second enhanced signal DRV_SCR_B, the second drive branch outputs the second thyristor drive signal to the thyristor of phase B according to the second enhanced signal DRV_SCR_B.

[0079] The third signal enhancement branch of the signal enhancement module 200 is used to receive the third driving signal SCR_PWM3. When the third driving signal SCR_PWM3 is received, the driving control signal DRV_SCR is combined with the third driving signal SCR_PWM3 and enhanced to obtain the third enhanced signal DRV_SCR_C, which is output to the third driving branch of the driving output module 300. After receiving the third enhanced signal DRV_SCR_C, the third driving branch outputs the third thyristor driving signal to the C-phase thyristor.

[0080] Since the first driving signal SCR_PWM1, the second driving signal SCR_PWM2, and the third driving signal SCR_PWM3 are sent in a time-sharing manner, it is ensured that only one of the A-phase thyristor, B-phase thyristor, and C-phase thyristor is driven at the same time, ensuring the smoothness of the power supply and reducing the ripple current of the driving power supply.

[0081] In this application, since the time-sharing wave generation module 100 outputs the first driving signal SCR_PWM1, the second driving signal SCR_PWM2, and the third driving signal SCR_PWM3 in a time-sharing manner when receiving the driving control signal DRV_SCR output by the processor MCU, within one wave generation cycle, the time ratios of the first driving signal SCR_PWM1, the second driving signal SCR_PWM2, and the third driving signal SCR_PWM3 are the same, that is, the first driving signal SCR_PWM1, the second driving signal SCR_PWM2, and the third driving signal SCR_PWM3 are evenly distributed in time. These signals are then enhanced by the signal enhancement module 200 to obtain the first enhanced signal DRV_SCR_A, the second enhanced signal DRV_SCR_B, and the third enhanced signal DRV_SCR_C. The driving output module 300 outputs the first thyristor driving signal, the second thyristor driving signal, and the third thyristor driving signal to the A-phase thyristor, B-phase thyristor, and C-phase thyristor respectively according to the first enhanced signal DRV_SCR_A, the second enhanced signal DRV_SCR_B, and the third enhanced signal DRV_SCR_C. The implementation method is simple and reliable. Only one phase of thyristor is driven at the same moment, reducing the ripple current of the driving power supply.

[0082] Embodiment 2

[0083] In some alternative embodiments, the thyristor driving circuit provided by this application further includes a driving power supply monitoring module 400;

[0084] The driving power supply monitoring module 400 is connected to the driving power supply VDD and the time-sharing wave generation module 100, and is used to monitor the voltage value of the driving power supply VDD and send the monitoring result PW_Rst to the time-sharing wave generation module 100.

[0085] Optionally, the driving power supply VDD can be used to output voltages higher than +12V, such as +15V, +18V, +24V, +36V, and +48V, etc., which can be selected or set according to requirements and circuit parameters without limitation.

[0086] When the system is just powered on and started, the driving power supply VDD is not yet stable. At this time, the subsequent circuit operation can be paused first, and after the driving power supply VDD is stable, the subsequent circuit is allowed to work. Specifically, the driving power supply monitoring module 400 is used to monitor the voltage value of the driving power supply VDD, and the obtained monitoring result PW_Rst can represent two states of the driving power supply VDD. For example, when the system is just powered on and started and the driving power supply VDD is not yet stable, the monitoring result PW_Rst can be represented as 0, and when the driving power supply VDD is stable, the monitoring result PW_Rst can be represented as 1, so that the time-sharing wave generation module 100 makes corresponding actions according to the detection result. For example, when the monitoring result PW_Rst is 0, the time-sharing wave generation module 100 and the subsequent circuit stop working and wave generation is prohibited to protect the subsequent circuit. When the monitoring result PW_Rst is 1, the time-sharing wave generation module 100 and the subsequent circuit are allowed to start working.

[0087] Optionally, the above monitoring result PW_Rst being 0 or 1 is an example in an embodiment of the present application, rather than a specific limitation on the present application. In some other embodiments, the detection result can also adopt other forms, such as the form of high and low levels. That is, when the driving power supply VDD is unstable, the driving power supply monitoring module 400 outputs a low-level signal to stop the subsequent circuit from working and protect the circuit. When the driving power supply VDD is stable, the driving power supply monitoring module 400 outputs a high-level signal to allow the subsequent circuit to start working.

[0088] It should be noted that the level signal in the embodiment of the present application refers to that in a digital logic circuit, the low level represents 0 and the high level represents 1. From the perspective of the signal level, it is generally stipulated that the low-level voltage is less than 30% of VCC, and the high-level voltage is greater than 70% of VCC.

[0089] Embodiment III

[0090] Furthermore, the time-sharing wave generation module 100 includes a first monostable chip U1, a second monostable chip U2, a third monostable chip U3, a first NAND gate U4, a second NAND gate U5, a third NAND gate U6, a first resistor R39, a second resistor R37, a third resistor R38, a fourth resistor R31, a fifth resistor R34, a sixth resistor R42, a seventh resistor R32, an eighth resistor R40, a ninth resistor R35, a tenth resistor R41, an eleventh resistor R33, a twelfth resistor R36, a first capacitor C12, a second capacitor C15, a third capacitor C13, a fourth capacitor C11, and a fifth capacitor C14;

[0091] One input terminal of the first NAND gate U4 is connected to the drive power monitoring module 400, another input terminal of the first NAND gate U4 is connected to the processor MCU, and the output terminal of the first NAND gate U4 is connected to two input terminals of the second NAND gate U5;

[0092] The output terminal of the second NAND gate U5 is connected to the first signal terminal PWM_nRST;

[0093] The ninth pin of the first monostable chip U1 is connected to one input terminal of the third NAND gate U6 through the first resistor R39. The tenth pin of the first monostable chip U1 is used to output the first drive signal SCR_PWM1. The eleventh pin of the first monostable chip U1 is connected to the first voltage terminal VCC through the second resistor R37. The twelfth pin of the first monostable chip U1 is connected to the ninth pin of the third monostable chip U3 through the third resistor R38. The thirteenth pin of the first monostable chip U1 is connected to the first signal terminal PWM_nRST through the fourth resistor R31. The fourteenth pin of the first monostable chip U1 is connected to the first voltage terminal VCC through the fifth resistor R34 and is connected to one end of the first capacitor C12. The fifteenth pin of the first monostable chip U1 is grounded;

[0094] The other end of the first capacitor C12 is connected to one end of the second capacitor C15 and is grounded;

[0095] The other end of the second capacitor C15 is connected to the output terminal of the second NAND gate U5 through the sixth resistor R42. The other end of the second capacitor C15 is also connected to the other input terminal of the third NAND gate U6;

[0096] The output terminal of the third NAND gate U6 is connected to the fifth pin of the second monostable chip U2 through the seventh resistor R32;

[0097] The third pin of the second monostable chip U2 is connected to the first signal terminal PWM_nRST through the eighth resistor R40. The first pin, the fourth pin, and the eighth pin of the second monostable chip U2 are grounded. The second pin of the second monostable chip U2 is connected to the first voltage terminal VCC through the ninth resistor R35 and is grounded through the third capacitor C13. The sixth pin of the second monostable chip U2 is used to output the second drive signal SCR_PWM2. The seventh pin of the second monostable chip U2 is connected to the twelfth pin of the third monostable chip U3 through the tenth resistor R41. The sixteenth pin of the second monostable chip U2 is connected to the first voltage terminal VCC and is grounded through the fourth capacitor C11;

[0098] The tenth pin of the third monostable chip U3 is used to output the third drive signal SCR_PWM3. The eleventh pin of the third monostable chip U3 is connected to the first voltage terminal VCC. The thirteenth pin of the third monostable chip U3 is connected to the first signal terminal PWM_nRST through the eleventh resistor R33. The fourteenth pin of the third monostable chip U3 is connected to the first voltage terminal VCC through the twelfth resistor R36 and grounded through the fifth capacitor C14. The fifteenth pin of the third monostable chip U3 is grounded.

[0099] Further, the signal enhancement module 200 includes a first AND gate U7, a second AND gate U8, a third AND gate U9, a first triode Q10, a second triode Q6, a third triode Q4, a fourth triode Q7, a fifth triode Q5, and a sixth triode Q8;

[0100] Two input terminals of the first AND gate U7 are respectively connected to the time-sharing wave generation module 100 and the processor MCU, and are respectively used to receive the first drive signal SCR_PWM1 and the drive control signal DRV_SCR. The output terminal of the first AND gate U7 is connected to the first pole pin of the first triode Q10 and the first pole pin of the second triode Q6;

[0101] The second pole pins of the first triode Q10 and the second triode Q6 are coupled to output a first enhanced signal DRV_SCR_A;

[0102] Two input terminals of the second AND gate U8 are respectively connected to the time-sharing wave generation module 100 and the processor MCU, and are respectively used to receive the second drive signal SCR_PWM2 and the drive control signal DRV_SCR. The output terminal of the second AND gate U8 is connected to the first pole pin of the third triode Q4 and the first pole pin of the fourth triode Q7;

[0103] The second pole pins of the third triode Q4 and the fourth triode Q7 are coupled to output a second enhanced signal DRV_SCR_B;

[0104] Two input terminals of the third AND gate U9 are respectively connected to the time-sharing wave generation module 100 and the processor MCU, and are respectively used to receive the third drive signal SCR_PWM3 and the drive control signal DRV_SCR. The output terminal of the third AND gate U9 is connected to the first pole pin of the fifth triode Q5 and the first pole pin of the sixth triode Q8;

[0105] The second pole pins of the fifth triode Q5 and the sixth triode Q8 are coupled to output a third enhanced signal DRV_SCR_C;

[0106] The third pole pins of the first triode Q10, the third pole pins of the third triode Q4, and the third pole pins of the fifth triode Q5 are all connected to the first voltage terminal VCC;

[0107] The third pole pins of the second triode Q6, the third pole pins of the fourth triode Q7, and the third pole pins of the sixth triode Q8 are all grounded.

[0108] During implementation, the signal enhancement module includes three signal enhancement branches. Among them, the first signal enhancement branch includes the first AND gate U7, the first triode Q10, and the second triode Q6. The second signal enhancement branch includes the second AND gate U8, the third triode Q4, and the fourth triode Q7. The third signal enhancement branch includes the third AND gate U9, the fifth triode Q5, and the sixth triode Q8.

[0109] In some embodiments, the first triode Q10, the second triode Q6, the third triode Q4, the fourth triode Q7, the fifth triode Q5, and the sixth triode Q8 can be triodes. Among them, the first pole pin, the second pole pin, and the third pole pin of each triode are the base, emitter, and collector of the triode respectively.

[0110] Furthermore, each drive branch includes a MOS transistor, a MOS transistor drive absorption unit, a thyristor drive circuit enhancement unit, and a drive transformer output rectification unit;

[0111] The MOS transistor drive absorption unit is connected to the signal enhancement module 200 and the MOS transistor, and is used to receive the signal output by the signal enhancement module 200 to drive the MOS transistor and absorb the electrical stress brought to the MOS transistor;

[0112] The thyristor drive circuit enhancement unit is connected to the MOS transistor and the drive transformer, and is used to output or stop outputting the enhanced thyristor drive electrical signal according to the state of the MOS transistor;

[0113] The drive transformer output rectification unit is connected to the MOS transistor drive absorption unit, the thyristor drive circuit enhancement unit, and the thyristor of the corresponding phase, and is used to convert the electrical signal output by the thyristor drive circuit enhancement unit into the drive current of the thyristor of the corresponding phase and output it.

[0114] In some implementations, the present application takes the drive branch of the A-phase thyristor as an example for illustration, as Figure 5 shown, the drive branch of the A-phase thyristor includes the MOS transistor Q1, the MOS transistor drive absorption unit, the thyristor drive circuit enhancement unit, and the drive transformer output rectification unit;

[0115] The MOS transistor drive absorption unit includes the thirteenth resistor R19, the fourteenth resistor R10, the fifteenth resistor R9, the first diode D3, the voltage regulator diode D4, the sixth capacitor C5, and the seventh capacitor C6;

[0116] One end of the thirteenth resistor R19 is connected to the gate of the MOS transistor Q1 and one end of the fourteenth resistor R10, and the other end of the thirteenth resistor R19 is connected to an output end of the signal enhancement module 200. Understandably, since the drive branch corresponds to the thyristor of phase A, the other end of the thirteenth resistor R19 is connected to the first enhancement signal DRV_SCR_A. Similarly, when the drive branch corresponds to the thyristor of phase B, the other end of the thirteenth resistor R19 is connected to the second enhancement signal DRV_SCR_B, and when the drive branch corresponds to the thyristor of phase C, the other end of the thirteenth resistor R19 is connected to the third enhancement signal DRV_SCR_C.

[0117] The source of the MOS transistor Q1 and the other end of the fourteenth resistor R10 are grounded, and the drain of the MOS transistor Q1 is connected to the thyristor drive circuit enhancement unit, the anode of the first diode D3, and one end of the sixth capacitor C5;

[0118] The cathode of the first diode D3 is connected to the cathode of the voltage regulator diode D4, and the anode of the voltage regulator diode D4 is connected to the drive power supply VDD;

[0119] The other end of the sixth capacitor C5 is grounded through the fifteenth resistor R9;

[0120] The seventh capacitor C6 is connected in parallel with the fourteenth resistor R10.

[0121] Furthermore, the thyristor drive circuit enhancement unit includes a resistor parallel body composed of a plurality of resistors connected in parallel and a capacitor parallel body composed of a plurality of capacitors connected in parallel. Optionally, in this application, taking the resistor parallel body composed of the resistor R1, the resistor R2, and the resistor R3 and the capacitor parallel body composed of the capacitor C2, the capacitor C3, and the capacitor C4 as examples, the method of connecting a plurality of resistors in parallel can improve the heat dissipation capacity of the resistors and achieve redundancy to improve reliability; connecting a plurality of capacitors in parallel and using capacitors with different capacitance values can achieve better EMC (Electromagnetic Compatibility) performance.

[0122] It should be noted that the number of resistors and capacitors in the above resistor parallel body and capacitor parallel body is an example of an embodiment of this application and is not a specific limitation of this application. In some other embodiments, the number of resistors forming the resistor parallel body and the number of capacitors forming the capacitor parallel body can be specifically set according to requirements without limitation.

[0123] One end of the resistor parallel body is connected to the drive power supply VDD and is connected to the anode of the voltage regulator diode D4, and the other end of the resistor parallel body is connected to the drive transformer, that is, the other end of the resistor parallel body is connected to an input end of the drive transformer output rectification unit and one end of the capacitor parallel body;

[0124] Another input end of the driving transformer output rectifying unit is connected to the drain of the MOS transistor Q1;

[0125] The other end of the capacitor parallel body is grounded.

[0126] In some embodiments, the thyristor driving circuit enhancement unit may further include a capacitor CA1 and a capacitor CA3. One end of the capacitor CA1 is connected to the anode of the voltage stabilizing diode D4, the other end of the capacitor CA1 is grounded, and the capacitor CA3 is in parallel with the capacitor CA1. The capacitor CA1 and the capacitor CA3 filter out the clutter in the circuit to improve the circuit stability.

[0127] Furthermore, each phase of thyristor corresponds to a driving transformer output rectifying unit, and each driving transformer output rectifying unit can output two thyristor driving signals to drive the two thyristors of each phase. Specifically, the driving transformer output rectifying unit includes a driving transformer T1, a second diode D1, a third diode D2, a sixteenth resistor R12, a seventeenth resistor R17, an eighteenth resistor R11, a nineteenth resistor R15, a twentieth resistor R18, a twenty-first resistor R14, an eighth capacitor C7, and a ninth capacitor C8;

[0128] The driving transformer T1 includes a primary winding, a first secondary winding, and a second secondary winding. The primary winding is connected to the thyristor driving circuit enhancement unit. For example, one end of the primary winding is connected to the other end of the resistor parallel body, and the other end of the primary winding is connected to the drain of the MOS transistor Q1. One output end of the first secondary winding is connected to the anode of the second diode D1, and the other output end of the first secondary winding is used to output the thyristor driving signal SCR_A1_K. One output end of the second secondary winding is connected to the anode of the third diode D2, and the other output end of the second secondary winding is used to output the in-phase thyristor driving signal SCR_A2_K;

[0129] The cathode of the second diode D1 is connected to one end of the sixteenth resistor R12, and the other end of the sixteenth resistor R12 is used to output the thyristor driving signal SCR_A1_G. The other end of the sixteenth resistor R12 is connected to the other output end of the first secondary winding through the seventeenth resistor R17;

[0130] The eighteenth resistor R11 is in parallel with the sixteenth resistor R12, and the eighth capacitor C7 is in parallel with the seventeenth resistor R17;

[0131] The cathode of the third diode D2 is connected to one end of the nineteenth resistor R15, and the other end of the nineteenth resistor R15 is used to output the thyristor driving signal SCR_A2_G. The other end of the nineteenth resistor R15 is connected to the other output end of the second secondary winding through the twentieth resistor R18;

[0132] The twenty - first resistor R14 is in parallel with the nineteenth resistor R15, and the ninth capacitor C8 is in parallel with the twentieth resistor R18.

[0133] Furthermore, the drive power monitoring module 400 includes a detection chip U10, a seventh triode Q9, a twenty - second resistor R21, a twenty - third resistor R22, a twenty - fourth resistor R24, a twenty - fifth resistor R23, a twenty - sixth resistor R25, a tenth capacitor C9, an eleventh capacitor CA2, and a twelfth capacitor C10;

[0134] The first terminal of the detection chip U10 is connected to one end of the twenty - second resistor R21, one end of the twenty - third resistor R22, and one end of the tenth capacitor C9. The second terminal of the detection chip U10 is connected to one end of the twenty - fourth resistor R24, and the third terminal of the detection chip U10 is grounded;

[0135] The other end of the twenty - second resistor R21 is connected to the drive power supply VDD and one end of the eleventh capacitor CA2;

[0136] The other end of the twenty - fourth resistor R24 is connected to one end of the twenty - fifth resistor R23, one end of the twelfth capacitor C10, and the first pole pin of the seventh triode Q9;

[0137] The other end of the twenty - fifth resistor R23, the other end of the twelfth capacitor C10, and the second pole pin of the seventh triode Q9 are all connected to the first voltage terminal VCC;

[0138] The third pole pin of the seventh triode Q9 is connected to one end of the twenty - sixth resistor R25 and the time - sharing wave - emitting module 100;

[0139] The other end of the twenty - third resistor R22, the other end of the tenth capacitor C9, the other end of the eleventh capacitor CA2, and the other end of the twenty - sixth resistor R25 are all grounded.

[0140] Optionally, the circuit structures of the drive branches of the B - phase thyristor and the C - phase thyristor are the same as that of the drive branch of the A - phase thyristor. The markings of each component are as Figure 6 and Figure 7 shown, and will not be elaborated here.

[0141] Furthermore, the A - phase thyristor includes thyristor A1 and thyristor A2, the B - phase thyristor includes thyristor B1 and thyristor B2, and the C - phase thyristor includes thyristor C1 and thyristor C2.

[0142] The A - phase thyristor circuit is connected to the A - phase input end VA_In and the A - phase output end VA_Out of the power loop. The drive signals of its corresponding thyristor A1 are SCR_A1_G and SCR_A1_K, and the drive signals of thyristor A2 are SCR_A2_G and SCR_A2_K.

[0143] The thyristor circuit of phase B is connected to the input terminal VB_In and the output terminal VB_Out of the power circuit of phase B. The driving signals of the corresponding thyristors B1 are SCR_B1_G and SCR_B1_K, and the driving signals of the thyristor B2 are SCR_B2_G and SCR_B2_K.

[0144] The thyristor circuit of phase C is connected to the input terminal VC_In and the output terminal VC_Out of the power circuit of phase C. The driving signals of the corresponding thyristors C1 are SCR_C1_G and SCR_C1_K, and the driving signals of the thyristor C2 are SCR_C2_G and SCR_C2_K.

[0145] During implementation, the first monostable chip U1, the second monostable chip U2, and the third monostable chip U3 can use chips such as CD4098 or 74HC123. The model of the monostable chip can be selected according to the actual application situation without limitation.

[0146] Optionally, the first NAND gate U4, the second NAND gate U5, and the third NAND gate U6 can use CD4093 or 74HC00, etc., and the AND gate can use CD4081 or 74HC08, etc. The models of the NAND gate and the AND gate can be selected according to the actual application situation without limitation.

[0147] During implementation, as Figure 3 shown, the ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth pins of the first monostable chip U1 are Q2-, Q2, TR-2, TR+2, RESET2, RxCx2, and Cx2 respectively. The first, second, third, fourth, fifth, sixth, seventh, eighth, and sixteenth pins of the second monostable chip U2 are Cx1, RxCx 1, RESET 1, TR+1, TR-1, Q1, Q1-, VSS, and VDD respectively. The ninth, tenth, eleventh, twelfth, thirteenth, fourteenth, and fifteenth pins of the third monostable chip U3 are Q2-, Q2, TR-2, TR+2, RESET2, RxCx2, and Cx2 respectively.

[0148] The third pole pin of the seventh triode Q9 can be regarded as the connection of the output monitoring result PW_Rst to the time-sharing wave generation module 100. The drive power supply in the drive power supply monitoring module 400 is VDD, and VCC is the control power supply. When the drive power supply VDD is lower than the detection value, the detection chip U10 outputs a high level, the first triode Q10 is turned off, the monitoring result PW_Rst is at a low level, the control drive signal output is 0, and the protection circuit is protected. When the drive power supply VDD is higher than the detection value, the detection chip U10 outputs a low level, the seventh triode Q9 is turned on, the monitoring result PW_Rst is at a high level, and the subsequent circuit is allowed to start working.

[0149] The working process and principle of the time-sharing wave generation module 100 are as follows:

[0150] 1. Before the drive power supply VDD is normal, the drive power supply monitoring module 400 outputs a low level. At this time, the monitoring result PW_Rst can be regarded as 0, so that the signal output by the first signal terminal PWM_nRST is 0. In this way, the Reset terminals (the above RESET1 and RESET2) of the three monostable chips are all 0, and the monostable chip circuits are all reset, and the outputs are all 0, ensuring the reliable operation of the circuit.

[0151] 2. After the drive power supply VDD is normal, the drive power supply monitoring module 400 outputs a high level. At this time, the monitoring result PW_Rst can be regarded as 1, and the time-sharing wave generation module 100 starts to be controlled by the drive control signal DRV_SCR: when the drive control signal DRV_SCR is 0, the first signal terminal PWM_nRST continues to be 0, blocking the monostable circuit, and the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 are all 0, the thyristor is turned off, and the ninth pin output of the first monostable chip U1 is 1, which does not affect the start-up circuit of the third NAND gate U6; when the drive control signal DRV_SCR changes from 0 to 1, the following process occurs:

[0152] 2.1. The first signal terminal PWM_nRST generates a rising edge signal and maintains it at a high level. The high level of the first signal terminal PWM_nRST wakes up all the monostable circuits; the rising edge signal of the first signal terminal PWM_nRST causes a falling edge signal to be generated at the output terminal of the third NAND gate U6, prompting the second monostable chip U2 circuit to be activated and output an effective second drive signal SCR_PWM2 to turn on the B-phase thyristor.

[0153] 2.2 After the monostable delay time has elapsed, the second drive signal SCR_PWM2 flips to 0, turning off the B-phase thyristor, and a rising edge signal is generated at the seventh pin of the second monostable chip U2, triggering the third monostable chip U3 circuit to start working and outputting a valid third drive signal SCR_PWM3 to turn on the C-phase thyristor.

[0154] 2.3 And so on. When the monostable delay time has elapsed and the third drive signal SCR_PWM3 flips to 0 to turn off the C-phase thyristor, the first drive signal SCR_PWM1 flips to 1 to turn on the A-phase thyristor. When the first drive signal SCR_PWM1 flips to 0, a rising edge signal is generated at the ninth pin of the first monostable chip U1, which is output from the output terminal of the third NAND gate U6 by flipping to a falling edge signal, completing a cycle. In this way, it repeats cyclically, periodically outputting the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3.

[0155] 3. Turn off the wave generation signal: The drive control signal DRV_SCR flips to 0, the signal of the first signal terminal PWM_nRST is 0, turning off all monostable chip circuits, and the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 are all 0.

[0156] In some possible embodiments, on the premise that the drive power supply VDD is stable, the first NAND gate U4 and the second NAND gate U5 can be omitted, or both input terminals of the first NAND gate U4 are connected to the drive control signal DRV_SCR. In other words, the signal output by the first signal terminal PWM_nRST is equal to the drive control signal DRV_SCR. Exemplarily, when the drive control signal DRV_SCR is 0, the first signal terminal PWM_nRST outputs 0, blocking the monostable circuit, and the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3 are all 0, and the thyristor is turned off. When the drive control signal DRV_SCR changes from 0 to 1, the first signal terminal PWM_nRST outputs 1. For the specific working process and principle of the above-mentioned time-sharing wave generation module 100, no further description will be given.

[0157] As Figure 8 shown, the upper, middle, and lower three waveforms respectively correspond to the first drive signal SCR_PWM1, the second drive signal SCR_PWM2, and the third drive signal SCR_PWM3. From the waveforms, the three drive signals are evenly distributed in time. On the power supply side: the output current of the power supply will not cause current fluctuations due to waveform collapse, and such current is stable, which can effectively reduce the current ripple.

[0158] After the first driving signal SCR_PWM1, the second driving signal SCR_PWM2, and the third driving signal SCR_PWM3 output by the time-sharing wave generating module 100 are combined with the driving control signal DRV_SCR, they pass through the signal enhancement module 200 to drive the MOS transistor QTMOS of the thyristor driving circuit, so as to improve the load-carrying capacity and enhance the system reliability.

[0159] The working process and principle of the driving output module 300 are as follows:

[0160] 1. Taking the driving branch of the thyristor of phase A as an example, the thirteenth resistor R19 and the fourteenth resistor R10 of the driving absorption unit are the driving resistor and the protection resistor respectively, and the seventh capacitor C6 is the filtering capacitor to realize the driving of the G pole of the MOS transistor Q1; the first diode D3 and the voltage stabilizing diode D4 realize the absorption of the spike, and the sixth capacitor C5 and the fifteenth resistor R9 realize the absorption of the oscillation.

[0161] 2. The thyristor driving circuit enhancement unit is completed by the cooperation of the resistor parallel body and the capacitor parallel body: at the moment when the MOS transistor is turned on, the energy on the capacitor parallel body is directly transmitted to the outside through the driving transformer T1, increasing the spike current of the thyristor driving. The simple capacitor energy storage structure ensures that the current at the moment when the thyristor is turned on meets the requirements and reduces the driving loss. After the voltage of the capacitor parallel body drops, the driving transformer T1 provides energy through the resistor parallel body.

[0162] 3. When the MOS transistor is turned off, the driving power supply VDD charges the capacitor parallel body through the resistor parallel body. By using the method of parallel connection of multiple resistors, the heat dissipation capacity of the resistor can be improved, redundancy can be achieved, and the reliability can be improved; for the parallel connection of multiple capacitors, capacitors with different capacitance values can be used to achieve better EMC performance.

[0163] 4. The driving transformer output rectifying unit is composed of a diode + the corresponding resistor and capacitor. On the output channel, the driving transformer T1 has 2 output connections, and each secondary winding corresponds to one output connection to drive the thyristor of phase A.

[0164] Similarly, the circuits of the thyristors of phase B and phase C are the same as the circuit of the thyristor of phase A above. Therefore, three identical circuits are required to complete the three-phase thyristors, which will not be elaborated here.

[0165] Since the time difference of the driving signals of each phase is the same and the driving duty cycle is 1 / 3, it ensures that the power supply is stable, thereby reducing the ripple current of the driving power supply.

[0166] Embodiment 4

[0167] In some possible embodiments, the present application further provides an electrical device including the thyristor driving circuit as described above.

[0168] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the structures and implementation principles of the electrical equipment described above can refer to the corresponding structures and implementation principles in the foregoing First to Third Embodiments, and will not be elaborated herein.

[0169] The thyristor drive circuit of the present application includes a time-sharing wave generation module 100, a signal enhancement module 200, and a drive output module 300. Since the time-sharing wave generation module 100 outputs a first drive signal SCR_PWM1, a second drive signal SCR_PWM2, and a third drive signal SCR_PWM3 in a time-sharing manner when receiving the drive control signal DRV_SCR output by the processor MCU, these signals are then enhanced by the signal enhancement module 200 to obtain a first enhanced signal DRV_SCR_A, a second enhanced signal DRV_SCR_B, and a third enhanced signal DRV_SCR_C. The drive output module 300 evenly distributes the first enhanced signal DRV_SCR_A, the second enhanced signal DRV_SCR_B, and the third enhanced signal DRV_SCR_C in time to respectively output three-phase thyristor drive signals to the thyristors of the corresponding phases. The implementation method is simple and reliable. Only one phase of thyristors is driven at the same moment, reducing the ripple current of the drive power supply.

[0170] It can be understood that those skilled in the art can, under the guidance of the above embodiments, combine various implementation manners in the above various embodiments. For example, the First Embodiment and the Second Embodiment are combined to obtain technical solutions of various implementation manners.

[0171] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A thyristor drive circuit, characterized in that, it includes: A time-sharing wave generation module, connected to the processor, for receiving the drive control signal output by the processor, and outputting a first drive signal, a second drive signal, and a third drive signal in a time-sharing manner. In one wave generation cycle, the time ratios of the first drive signal, the second drive signal, and the third drive signal are the same; A signal enhancement module, including three signal enhancement branches connected to the time-sharing wave generation module and the processor. The three signal enhancement branches are respectively used to receive the first drive signal, the second drive signal, and the third drive signal, and combine and enhance the drive control signal output by the processor with the first drive signal, the second drive signal, and the third drive signal respectively to obtain a first enhanced signal, a second enhanced signal, and a third enhanced signal and output them; A drive output module, including three drive branches connected to the three signal enhancement branches in one-to-one correspondence. The three drive branches are also respectively connected to three-phase thyristors in one-to-one correspondence. The three drive branches are respectively used to output a first thyristor drive signal, a second thyristor drive signal, and a third thyristor drive signal to the three-phase thyristors when receiving the first enhanced signal, the second enhanced signal, and the third enhanced signal.

2. The thyristor drive circuit according to claim 1, characterized in that, the thyristor drive circuit further includes a drive power supply monitoring module; the drive power supply monitoring module is connected to the drive power supply and the time-sharing wave generation module, and is used to monitor the voltage value of the drive power supply and send the monitoring result to the time-sharing wave generation module.

3. The thyristor drive circuit according to claim 2, characterized in that, the time-sharing wave generation module includes a first monostable chip, a second monostable chip, a third monostable chip, a first NAND gate, a second NAND gate, a third NAND gate, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a fifth capacitor; one input terminal of the first NAND gate is connected to the drive power supply monitoring module, the other input terminal is connected to the processor, and the output terminal is connected to the two input terminals of the second NAND gate; the output terminal of the second NAND gate is connected to a first signal terminal; the ninth pin of the first monostable chip is connected to one input terminal of the third NAND gate through the first resistor, the tenth pin is used to output the first drive signal, the eleventh pin is connected to a first voltage terminal through the second resistor, the twelfth pin is connected to the ninth pin of the third monostable chip through the third resistor, the thirteenth pin is connected to the first signal terminal through the fourth resistor, the fourteenth pin is connected to the first voltage terminal through the fifth resistor and is connected to one end of the first capacitor, and the fifteenth pin is grounded; the other end of the first capacitor is connected to one end of the second capacitor and is grounded; The other end of the second capacitor is connected to the output end of the second NAND gate through the sixth resistor, and the other end of the second capacitor is also connected to the other input end of the third NAND gate; The output end of the third NAND gate is connected to the fifth pin of the second monostable chip through the seventh resistor; The third pin of the second monostable chip is connected to the first signal terminal through the eighth resistor, the first pin, the fourth pin and the eighth pin are grounded, the second pin is connected to the first voltage terminal through the ninth resistor and grounded through the third capacitor, the sixth pin is used to output the second driving signal, the seventh pin is connected to the twelfth pin of the third monostable chip through the tenth resistor, and the sixteenth pin is connected to the first voltage terminal and grounded through the fourth capacitor; The tenth pin of the third monostable chip is used to output the third driving signal, the eleventh pin is connected to the first voltage terminal, the thirteenth pin is connected to the first signal terminal through the eleventh resistor, the fourteenth pin is connected to the first voltage terminal through the twelfth resistor and grounded through the fifth capacitor, and the fifteenth pin is grounded.

4. The thyristor drive circuit according to claim 1, characterized in that, the signal enhancement module includes a first AND gate, a second AND gate, a third AND gate, a first triode, a second triode, a third triode, a fourth triode, a fifth triode and a sixth triode; The two input ends of the first AND gate are respectively connected to the time-sharing wave generation module and the processor, and are respectively used to receive the first driving signal and the drive control signal, and the output end is connected to the first pole pin of the first triode and the first pole pin of the second triode; The second pole pins of the first triode and the second triode are coupled to output the first enhancement signal; The two input ends of the second AND gate are respectively connected to the time-sharing wave generation module and the processor, and are respectively used to receive the second driving signal and the drive control signal, and the output end is connected to the first pole pin of the third triode and the first pole pin of the fourth triode; The second pole pins of the third triode and the fourth triode are coupled to output the second enhancement signal; The two input ends of the third AND gate are respectively connected to the time-sharing wave generation module and the processor, and are respectively used to receive the third driving signal and the drive control signal, and the output end is connected to the first pole pin of the fifth triode and the first pole pin of the sixth triode; The second pole pins of the fifth triode and the sixth triode are coupled to output the third enhancement signal; The third pole pins of the first triode, the third triode and the fifth triode are all connected to the first voltage terminal; The third pole pins of the second triode, the fourth triode and the sixth triode are all grounded.

5. The thyristor drive circuit according to claim 1, characterized in that, Each of the driving branches includes a MOS transistor, a MOS transistor driving absorption unit, a thyristor driving circuit enhancement unit, and a driving transformer output rectification unit; The MOS transistor driving absorption unit is connected to the signal enhancement module and the MOS transistor, and is configured to receive the signal output by the signal enhancement module to drive the MOS transistor and absorb the electrical stress brought to the MOS transistor; The thyristor driving circuit enhancement unit is connected to the MOS transistor and the driving transformer, and is configured to output an enhanced electrical signal for driving the thyristor in the early stage of the conduction of the MOS transistor; The driving transformer output rectification unit is connected to the MOS transistor driving absorption unit, the thyristor driving circuit enhancement unit, and the thyristor of the corresponding phase, and is configured to convert the electrical signal output by the thyristor driving circuit enhancement unit into a driving current for the thyristor of the corresponding phase and output it.

6. The thyristor driving circuit according to claim 5, wherein, The MOS transistor driving absorption unit includes a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a first diode, a voltage stabilizing diode, a sixth capacitor, and a seventh capacitor; One end of the thirteenth resistor is connected to the gate of the MOS transistor and one end of the fourteenth resistor, and the other end is connected to a corresponding output terminal of the signal enhancement module; The source of the MOS transistor and the other end of the fourteenth resistor are grounded, and the drain of the MOS transistor is connected to the thyristor driving circuit enhancement unit, the anode of the first diode, and one end of the sixth capacitor; The cathode of the first diode is connected to the cathode of the voltage stabilizing diode, and the anode of the voltage stabilizing diode is connected to the driving power supply; The other end of the sixth capacitor is grounded through the fifteenth resistor; The seventh capacitor is connected in parallel with the fourteenth resistor.

7. The thyristor driving circuit according to claim 6, wherein, The thyristor driving circuit enhancement unit includes a resistor parallel body composed of a plurality of resistors connected in parallel, and a capacitor parallel body composed of a plurality of capacitors connected in parallel; One end of the resistor parallel body is connected to the driving power supply and is connected to the anode of the voltage stabilizing diode, and the other end of the resistor parallel body is connected to an input terminal of the driving transformer output rectification unit and is connected to one end of the capacitor parallel body; The other input terminal of the driving transformer is connected to the drain of the MOS transistor; The other end of the capacitor parallel body is grounded.

8. The thyristor driving circuit according to claim 7, wherein, The driving transformer output rectification unit includes a driving transformer, a second diode, a third diode, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, an eighth capacitor, and a ninth capacitor; The driving transformer includes a primary winding, a first secondary winding, and a second secondary winding. The primary winding is connected to the thyristor driving circuit enhancement unit. One output terminal of the first secondary winding is connected to the anode of the second diode, and the other output terminal of the first secondary winding is used to output a first thyristor signal. One output terminal of the second secondary winding is connected to the anode of the third diode, and the other output terminal of the second secondary winding is used to output a second thyristor signal in the same phase; The cathode of the second diode is connected to one end of the sixteenth resistor, and the other end of the sixteenth resistor is used to output a third thyristor signal in the same phase. The other end of the sixteenth resistor is connected to the other output terminal of the first secondary winding through the seventeenth resistor; The eighteenth resistor is connected in parallel with the sixteenth resistor, and the eighth capacitor is connected in parallel with the seventeenth resistor; The cathode of the third diode is connected to one end of the nineteenth resistor, and the other end of the nineteenth resistor is used to output a fourth thyristor signal in the same phase. The other end of the nineteenth resistor is connected to the other output terminal of the second secondary winding through the twentieth resistor; The twenty-first resistor is connected in parallel with the nineteenth resistor, and the ninth capacitor is connected in parallel with the twentieth resistor.

9. The thyristor driving circuit according to claim 2, characterized in that, the driving power supply monitoring module includes a detection chip, a seventh triode, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a twenty-sixth resistor, a tenth capacitor, an eleventh capacitor, and a twelfth capacitor; The first terminal of the detection chip is connected to one end of the twenty-second resistor, one end of the twenty-third resistor, and one end of the tenth capacitor. The second terminal is connected to one end of the twenty-fourth resistor, and the third terminal is grounded; The other end of the twenty-second resistor is connected to the driving power supply and one end of the eleventh capacitor; The other end of the twenty-fourth resistor is connected to one end of the twenty-fifth resistor, one end of the twelfth capacitor, and the first pole pin of the seventh triode; The other end of the twenty-fifth resistor, the other end of the twelfth capacitor, and the second pole pin of the seventh triode are all connected to the first voltage terminal; The third pole pin of the seventh triode is connected to one end of the twenty-sixth resistor and the time-sharing wave generation module; The other end of the twenty-third resistor, the other end of the tenth capacitor, the other end of the eleventh capacitor, and the other end of the twenty-sixth resistor are all grounded.

10. An electrical equipment, characterized in that, it includes the thyristor driving circuit according to any one of claims 1 to 9.

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