Half-bridge D-Mode GaN drive dead zone control detection circuit

Abstract

The invention discloses a half-bridge D-Mode GaN drive dead zone control detection circuit, which comprises a bias generation circuit, a common half-bridge D-Mode GaN circuit and a half-bridge D-Mode GaN drive dead zone time detection circuit, and is characterized in that the bias generation circuit provides bias voltage and bias current for subsequent circuits, the common half-bridge D-Mode GaN circuit adopts an LLC resonant converter circuit topological structure, and the common half-bridge D-Mode GaN drive dead zone time detection circuit adopts an LLC resonant converter circuit topological structure; the input end of the half-bridge D-Mode GaN driving dead-zone time detection circuit is connected with the source end of an L-DMOS at the lower part of D-Mode GaN to detect the change of the voltage of the source end of the L-DMOS, and the input end of the Schmidt trigger circuit is connected with the output end of the half-bridge D-Mode GaN driving dead-zone time detection circuit to adjust the voltage threshold when the dead-zone time comes and have certain voltage margin to resist noise interference; through accurate capture of the dead zone time, excellent detection precision can be maintained even in a complex and changeable working condition environment, and the method has accurate dead zone time detection capability and anti-interference capability.

Description

Technical Field

[0001] The present invention relates to the technical field of detection circuits, and particularly to a half-bridge D-Mode GaN drive dead-time control detection circuit. Background Art

[0002] With the continuous development trend of switching power supply technology towards higher power density, smaller and lighter systems, the third-generation wide-bandgap semiconductor material - gallium nitride (GaN) has become a recognized new development direction in the industry due to a series of unique advantages such as its high breakdown electric field, excellent high electron mobility, and remarkable high electron saturation velocity. These characteristics of GaN devices enable them to exhibit extraordinary potential in high-frequency applications.

[0003] Since the operating frequency of GaN devices can be significantly increased to far exceed that of traditional semiconductor materials, this characteristic extremely crucially promotes a substantial reduction in the volume of passive devices in the system - such as inductors and capacitors, thereby providing strong technical support for the miniaturization of switching power supplies. At the same time, due to the significant increase in the operating frequency of GaN devices, in order to more effectively reduce power losses, GaN power devices often need to be designed to operate under the conditions of zero-voltage switching (ZVS) and zero-current switching (ZCS) in practical applications. These two switching modes can minimize the energy loss during the switching process, thereby further improving the overall efficiency of the system.

[0004] However, in the application process of GaN power devices, an issue that cannot be ignored is to prevent the shoot-through phenomenon between the upper and lower transistors. Once shoot-through occurs between the upper and lower transistors, it will lead to a sharp increase in system losses, seriously affecting the stability and reliability of the system. To avoid this problem, the dead time must be carefully set. The setting of the dead time is aimed at ensuring that there is sufficient time interval during the switching process of the upper and lower transistors to prevent them from conducting simultaneously. However, it should be noted that if the dead time is too long, it will also lead to an increase in reverse conduction loss, which also has an adverse impact on the overall efficiency of the system.

[0005] Therefore, the precise detection of the dead-time arrival moment is particularly important. Through high-precision detection technology, the start and end points of the dead time can be monitored in real time and accurately judged, so as to optimize the setting of the dead time as much as possible on the premise of ensuring the safe and stable operation of the system, in order to achieve the best balance state of preventing shoot-through between the upper and lower transistors and reducing reverse conduction loss. This is of crucial significance for improving the overall performance of switching power supplies and promoting their development to a higher level. Summary of the Invention

[0006] The purpose of the present invention is to provide a half-bridge D-Mode GaN drive dead-time control detection circuit to solve the problems raised in the above background art.

[0007] To achieve the above object, the present invention provides the following technical solution: a half-bridge D-Mode GaN drive dead-time control detection circuit, including a bias generation circuit, a common half-bridge D-Mode GaN circuit, and a half-bridge D-Mode GaN drive dead-time detection circuit. The bias generation circuit provides a bias voltage and a bias current for the subsequent circuits. The common half-bridge D-Mode GaN circuit adopts the LLC resonant converter circuit topology. The input end of the half-bridge D-Mode GaN drive dead-time detection circuit is connected to the source terminal of the lower L-DMOS of D-Mode GaN to detect the change in the source voltage of the L-DMOS.

[0008] Preferably, the half-bridge D-Mode GaN drive dead-time detection circuit includes a D-Mode GaN half-bridge LLC resonant circuit, a high-side drive dead-time control detection, and a low-side drive dead-time control detection.

[0009] Preferably, the high and low side drive dead-time control detection includes a bias generation circuit, a drive dead-time generation circuit, and a Schmitt trigger circuit. The input end of the Schmitt trigger circuit is connected to the output end of the half-bridge D-Mode GaN drive dead-time detection circuit, which is used to adjust the voltage threshold when the detection dead-time comes and has a certain voltage margin to resist noise interference.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows: by adaptively adjusting the dead-time, the present invention significantly improves the stability and efficiency of the half-bridge D-Mode GaN drive system, effectively reduces the system loss. In the traditional fixed dead-time setting, it is often difficult to balance the system requirements under different working conditions, resulting in too long dead-time in some cases, increasing the reverse conduction loss, while in other cases, the dead-time is too short, which may cause the risk of upper and lower transistor breakdown. The present invention introduces an adaptive adjustment mechanism, which can dynamically adjust the dead-time according to the change of the actual application environment to ensure that it can maintain the optimal state under various working conditions, thus maximizing the system performance.

[0011] As the core part of the present invention, the dead-time detection circuit can real-time monitor the state change of the dead-time and trigger the protection mechanism in time when an abnormality is detected. This function is crucial for ensuring the safe and stable operation of the system. In the half-bridge D-Mode GaN drive system, the accurate control of the dead-time is the key to preventing the upper and lower transistor breakdown and avoiding excessive system loss. The dead-time detection circuit can accurately judge the start and end points of the dead-time through high-precision monitoring means. Once it detects that the dead-time deviates from the preset range, it immediately takes corresponding protection measures, such as blocking the drive signal, cutting off the power supply, etc., thus effectively avoiding the occurrence of system failures and enhancing the reliability of the system.

[0012] In addition, the present invention also has the characteristics of simple structure and easy implementation. The entire dead zone control detection circuit adopts a modular design, with tight connections and clear logic between modules, making it easy to integrate into the existing half-bridge D-Mode GaN drive system. At the same time, the components used in the present invention are all common devices and do not require special customization, reducing the production cost and R & D difficulty. This enables the present invention to have a wide range of application prospects in various half-bridge D-Mode GaN drive systems. Whether in the fields of communication power supplies, data center power supplies, or electric vehicle chargers, etc., it can play its unique advantages and provide strong support for improving the performance and ensuring the reliability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic flowchart diagram of the present invention.

[0014] Figure 2 It is a circuit operation diagram of the half-bridge D-Mode GaN circuit when the detection circuit of the present invention works normally.

[0015] Figure 3 It is a circuit operation diagram of the half-bridge D-Mode GaN circuit when detecting leakage electricity of the present invention.

[0016] Figure 4 It is a circuit operation diagram of the bias generation circuit of the present invention.

[0017] Figure 5 It is a circuit operation diagram of the half-bridge D-Mode GaN drive dead time detection circuit of the present invention.

[0018] Figure 6 It is a circuit operation diagram of the Schmidt trigger circuit of the present invention.

[0019] Figure 7 It is a schematic diagram of the signal voltage change for detecting the dead time of the high-side drive and the dead time of the low-side drive of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0021] Please refer to Figures 1 - 7, the present invention provides a technical solution: a half-bridge D-Mode GaN drive dead-time control detection circuit, including a bias generation circuit, a common half-bridge D-Mode GaN circuit, and a half-bridge D-Mode GaN drive dead-time detection circuit. The bias generation circuit provides bias voltage and bias current for the subsequent circuits. The common half-bridge D-Mode GaN circuit adopts the LLC resonant converter circuit topology. The input end of the half-bridge D-Mode GaN drive dead-time detection circuit is connected to the source end of the lower L-DMOS of D-Mode GaN to detect the change of the source voltage of L-DMOS. The half-bridge D-Mode GaN drive dead-time detection circuit includes a D-Mode GaN half-bridge LLC resonant circuit, a high-side drive dead-time control detection, and a low-side drive dead-time control detection. The high and low side drive dead-time control detection includes a bias generation circuit, a drive dead-time generation circuit, and a Schmitt trigger circuit. The input end of the Schmitt trigger circuit is connected to the output end of the half-bridge D-Mode GaN drive dead-time detection circuit, which is used to adjust the voltage threshold when the detection dead-time comes and has a certain voltage margin to resist noise interference.

[0022] The working principle of the above technical solution: When the D-Mode GaN half-bridge LLC resonant circuit is working normally, as Figure 2 shown, when the upper transistor S1 is turned on and the lower transistor S2 is turned off, the current flows from V BUS through the S1 GaN power device L R inductor C R capacitor to ground. At the next moment, when the upper transistor S1 is turned off and the lower transistor S2 is also turned off, the dead-time comes. Since the current in the inductor cannot change suddenly, it can only gradually decrease along the original current direction. Due to the existence of the LDMOS body diode, the current can only flow from the ground along the body diode of the lower LDMOS. Since there is current flowing through the body diode, it will cause the drain voltage (voltage at point B) of the LDMOS to be lower than the source voltage (ground voltage). Similarly, for the upper transistor, only when both the upper and lower transistors are turned off (i.e., the dead-time comes), due to the body diode freewheeling, the drain voltage will be lower than the source voltage. Therefore, only by detecting the source-drain voltage difference of the LDMOS can the arrival of the dead-time be judged. Since the ground VS in the high-side drive dead-time control detection circuit is connected to the floating voltage terminal VS of the LLC topology circuit, a bootstrap diode and capacitor are required to provide the power supply VDDA for the high-side detection circuit. As Figure 4 shown, the bias generation circuit generates a bias current independent of the power supply voltage by the connection method of the MP7, MP8, MN1, and MN2 double current mirrors: By adjusting the sizes of MN1 and MN2 and the resistor R1, a fixed - sized bias current is generated. Selecting a resistor with an appropriate temperature coefficient can even generate a current with a low temperature drift coefficient. The startup circuit composed of MP1, MP2, MP3, MP4, MP5, and MP6 is used to break the degeneracy point where the bias circuit does not work, as Figure 5 shown. The gates of MP9, MP10, and MP11 that drive the dead - time generation circuit are connected to the gate Vp of the bias circuit. By adjusting the aspect ratio, the magnitude of the bias current can be adjusted. If the same aspect ratio is set, the currents flowing through the P - type transistors in these three branches are the same. Also, since the gates of MN3 and MN4 are connected to the same potential, when the potential at point A is higher than the potential at VS, the current flowing through MN4 is less than the current flowing through MN3, that is, the current of MP10. Therefore, the gate potential of MN5 is pulled up, and the current flowing through MN5 is greater than the current of MP11, and the potential of the output out is pulled down. Only when the dead - time comes, the drain potential of the LDMOS will be greater than the source potential. Therefore, when the output out becomes low - potential, it is the moment when the dead - time comes. Thus, this circuit can detect the moment when the dead - time comes, as Figure 6 shown. For the Schmitt trigger circuit, the threshold of the Schmitt circuit flip and the voltage range of the hysteresis can be adjusted by adjusting the size of the Schmitt trigger circuit to prevent false triggering caused by noise interference, which may affect the misjudgment of the moment when the dead - time comes. When the voltage at the VS terminal changes, the signal voltage change conditions of the high - side drive dead - time detection and the low - side drive dead - time detection are as Figure 7 shown.

[0023] Working principle: When the D - Mode GaN half - bridge LLC resonant circuit is working normally, as Figure 2 shown, when the upper switch S1 is turned on and the lower switch S2 is turned off, the current flows from V BUS through the S1 GaN power device L R inductor C R capacitor to ground. At the next moment, when the upper switch S1 is turned off and the lower switch S2 is also turned off, the dead - time comes. Since the current in the inductor cannot change suddenly, it can only gradually decrease along the original current direction. Due to the existence of the LDMOS body diode, the current can only flow from the ground through the body diode of the lower - side LDMOS. Since there is current flowing through the body diode, the drain voltage (voltage at point B) of the LDMOS will be lower than the source voltage (ground voltage); similarly, for the upper switch, only when both the upper and lower switches are turned off (i.e., the dead - time comes), due to the body - diode free - wheeling, the drain voltage will be lower than the source voltage. Therefore, by detecting the source - drain voltage difference of the LDMOS, the arrival of the dead - time can be judged. Since the ground VS in the high - side drive dead - time control detection circuit is connected to the floating voltage terminal VS of the LLC topology circuit, a bootstrap diode and capacitor are required to provide the power supply VDDA for the high - side detection circuit, as Figure 4The bias generation circuit shown generates a bias current independent of the power supply voltage through the connection mode of the double current mirrors of MP7, MP8, MN1, and MN2: By adjusting the sizes of MN1 and MN2 and the resistor R1, a fixed - sized bias current can be generated. Selecting a resistor with an appropriate temperature coefficient can even generate a current with a low temperature drift coefficient. The start - up circuit composed of MP1, MP2, MP3, MP4, MP5, and MP6 is used to break the degeneracy point where the bias circuit does not work, as Figure 5 shown. The gates of MP9, MP10, and MP11 in the driving dead - time generation circuit are connected to the gate Vp of the bias circuit. By adjusting the aspect ratio, the magnitude of the bias current can be adjusted. If the same aspect ratio is set, the currents flowing through the P - type transistors in these three branches are the same. Also, since the gates of MN3 and MN4 are connected to the same potential, when the potential at point A is higher than the potential at VS, the current flowing through MN4 is less than the current flowing through MN3, that is, the current of MP10. Therefore, the gate potential of MN5 is pulled up, the current flowing through MN5 is greater than the current of MP11, and the potential of the output out is pulled down. Only when the dead - time comes, the drain potential of the LDMOS will be greater than the source potential. Therefore, when the output out becomes low - potential, it is the moment when the dead - time comes. Thus, this circuit can detect the moment when the dead - time comes, as Figure 6 shown. For the Schmitt trigger circuit, the threshold of the Schmitt circuit flip and the hysteresis voltage range can be adjusted by adjusting the size of the Schmitt trigger circuit to prevent false triggering caused by noise interference, which may affect the misjudgment of the dead - time arrival. As the voltage at the VS terminal changes, the signal voltage change conditions of the high - side driving dead - time detection and the low - side driving dead - time detection are as Figure 7As shown, by adaptively adjusting the dead time, the present invention significantly improves the stability and efficiency of the half-bridge D-Mode GaN drive system, effectively reduces system losses. In the traditional fixed dead time setting, it is often difficult to balance the system requirements under different working conditions, resulting in too long dead time in some cases, increasing the reverse conduction loss, while in other cases, the dead time is too short, which may trigger the risk of shoot-through of the upper and lower switches. However, the present invention can dynamically adjust the dead time according to the changes in the actual application environment by introducing an adaptive adjustment mechanism, ensuring that it can maintain the optimal state under various working conditions, thus achieving the maximization of system performance. The dead time detection circuit, as the core part of the present invention, can monitor the state change of the dead time in real time and trigger the protection mechanism in time when an abnormality is detected. This function is crucial for ensuring the safe and stable operation of the system. In the half-bridge D-Mode GaN drive system, the accurate control of the dead time is the key to preventing shoot-through of the upper and lower switches and avoiding excessive system losses. The dead time detection circuit can accurately judge the start and end points of the dead time through high-precision monitoring means. Once it detects that the dead time deviates from the preset range, it immediately takes corresponding protection measures, such as blocking the drive signal, cutting off the power supply, etc., thus effectively avoiding the occurrence of system failures and enhancing the reliability of the system. In addition, the present invention also has the characteristics of simple structure and easy implementation. The entire dead time control and detection circuit adopts a modular design, with tight connections and clear logic between modules, which is easy to be integrated into the existing half-bridge D-Mode GaN drive system. At the same time, the components used in the present invention are all common devices, without special customization, reducing the production cost and R & D difficulty. This makes the present invention have a wide application prospect in various half-bridge D-Mode GaN drive systems. Whether in the fields of communication power supplies, data center power supplies or electric vehicle chargers, etc., it can play its unique advantages and provide strong support for the improvement of system performance and the guarantee of reliability.

[0024] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions and variations can be made therein without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A half-bridge D-Mode GaN driving dead zone control detection circuit, comprising a bias generation circuit, a common half-bridge D-Mode GaN circuit and a half-bridge D-Mode GaN driving dead zone time detection circuit, characterized in that: The bias generating circuit provides bias voltage and bias current for subsequent circuits. The common half-bridge D-Mode GaN circuit adopts an LLC resonant converter circuit topology. The input end of the half-bridge D-Mode GaN driving dead time detection circuit is connected to the source end of the L-DMOS in the lower part of the D-Mode GaN to detect changes in the source end voltage of the L-DMOS.

2. A half-bridge D-Mode GaN driving dead zone control detection circuit according to claim 1, characterized in that: The half-bridge D-Mode GaN driving dead zone time detection circuit includes a D-Mode GaN half-bridge LLC resonant circuit, a high-side driving dead zone control detection and a low-side driving dead zone control detection.

3. A half-bridge D-Mode GaN driving dead zone control detection circuit according to claim 2, characterized in that: The high-side and low-side drive dead zone control detection includes a bias generation circuit, a drive dead zone moment generation circuit and a Schmitt trigger circuit. The input end of the Schmitt trigger circuit is connected to the output end of the half-bridge D-Mode GaN drive dead zone moment detection circuit, which is used to adjust the voltage threshold when the dead zone moment arrives and have a certain voltage margin to resist noise interference.

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