High-speed motor controller and control system applied to high-temperature environment

Abstract

The invention discloses a high-speed motor controller applied to a high-temperature environment and a control system. The high-speed motor controller applied to the high-temperature environment comprises a control circuit, a gate drive circuit and a three-phase inverter circuit, the control circuit is used for outputting a control signal for controlling the high-speed motor to operate; the gate driving circuit is used for converting the control signal into a driving signal for driving the silicon carbide power semiconductor device; each phase bridge arm of the three-phase inverter circuit comprises two silicon carbide power semiconductor devices, and the three-phase inverter circuit is used for generating three-phase sine wave current under the action of the driving signal so as to drive the high-speed motor to operate. The high-speed motor controller disclosed by the invention has high-temperature resistance, and can realize rapid, safe and stable control of a high-speed motor.

Description

Technical Field

[0001] The present invention relates to the technical field of motor control, and in particular, to a high-speed motor controller and a control system applied to a high-temperature environment. Background Art

[0002] With the continuous in-depth research and application of high-speed motors, higher requirements are put forward for the design of high-speed motor controllers. Traditional motor controllers often use insulated gate bipolar transistors as power semiconductor devices. Their own characteristics lead to problems such as slow switching speed, large switching losses and conduction losses, resulting in excessive temperature rise. At the same time, their maximum operating junction temperature is relatively low, making it difficult to be applied to the control of high-speed motors in high-temperature environments.

[0003] Wide bandgap semiconductor devices represented by silicon carbide devices have advantages such as fast switching speed, small switching losses, higher working junction temperature, small conduction losses, and lower average temperature rise compared with silicon semiconductor power devices represented by insulated gate bipolar transistors. Therefore, silicon carbide metal oxide semiconductor field effect transistors as power semiconductor devices are more conducive to the high-speed motor controller working under high-temperature conditions. Therefore, it is necessary to provide a high-speed motor control scheme based on silicon carbide devices that can be applied to high-temperature environments. Summary of the Invention

[0004] The present invention aims to solve at least to some extent the technical problems in the related art. For this purpose, the first object of the present invention is to provide a high-speed motor controller applied to a high-temperature environment, which can provide high-temperature resistance and can achieve fast, safe and stable control of a high-speed motor.

[0005] The second object of the present invention is to provide a high-speed motor control system applied to a high-temperature environment.

[0006] To achieve the above object, the present invention is realized through the following technical solutions:

[0007] A high-speed motor controller applied to a high-temperature environment includes:

[0008] A control circuit for outputting a control signal for controlling the operation of a high-speed motor;

[0009] A gate drive circuit connected to the control circuit, the gate drive circuit is used to convert the control signal into a drive signal for driving a silicon carbide power semiconductor device;

[0010] A three-phase inverter circuit is respectively connected to the gate drive circuit and the high-speed motor. Each phase bridge arm of the three-phase inverter circuit includes two silicon carbide power semiconductor devices. The three-phase inverter circuit is used to generate three-phase sinusoidal current under the action of the drive signal to drive the high-speed motor to operate.

[0011] Preferably, the high-speed motor controller further includes: a current sampling circuit, which is respectively connected to the three-phase inverter circuit and the control circuit. The current sampling circuit is used to sample the three-phase current in the three-phase inverter circuit and feedback it to the control circuit, so as to realize the closed-loop feedback control of the high-speed motor.

[0012] Preferably, the high-speed motor controller further includes: a communication circuit, which is respectively connected to the host computer and the control circuit. The communication circuit is used to realize the interactive communication between the host computer and the control circuit.

[0013] Preferably, the three-phase inverter circuit specifically includes:

[0014] A first capacitor, which is connected in parallel between the positive and negative terminals of the DC bus;

[0015] The first to sixth switching tubes, wherein the first switching tube and the fourth switching tube are connected in series on the A-phase bridge arm; the third switching tube and the sixth switching tube are connected in series on the B-phase bridge arm; the fifth switching tube and the second switching tube are connected in series on the C-phase bridge arm; the three-phase bridge arms are connected in parallel with the first capacitor; the midpoint of the three-phase bridge arms is connected to the high-speed motor; wherein, the first to sixth switching tubes are all silicon carbide power semiconductor devices;

[0016] The first to third sampling resistors, which are respectively connected in series on the lower bridge arms of the three-phase bridge arms, so as to facilitate the three-phase current sampling.

[0017] Preferably, the gate drive circuit includes:

[0018] A first gate drive chip, and the first gate drive chip is a IVCO1412 type drive chip;

[0019] The second to fifth capacitors, the VCC1 pin of the first gate drive chip is grounded through the second capacitor; the IN pin of the first gate drive chip is connected to the control circuit; the OUT pin of the first gate drive chip is connected to its own NEG pin through the third capacitor; the VCC2 pin of the first gate drive chip is connected to its own VEE2 pin through the fifth capacitor; the VEE2 pin of the first gate drive chip is connected to the source electrode of the switching tube on the upper bridge arm of the corresponding phase;

[0020] The fourth to sixth resistors and the first diode, the VCC1 pin of the first gate drive chip is also connected to its own FO pin through the fourth resistor; the VEE2 pin of the first gate drive chip is also connected to the power supply through the fourth capacitor, the first diode and the fifth resistor; the NEG pin of the first gate drive chip is connected to the gate of the switching tube on the upper bridge arm of the corresponding phase through the sixth resistor;

[0021] Among them, the fifth resistor, the first diode and the fourth capacitor form a bootstrap circuit.

[0022] Preferably, the gate drive circuit further includes:

[0023] A second gate drive chip, which is an IVCR1401 type drive chip;

[0024] The sixth to tenth capacitors, the VCC pin of the second gate drive chip is grounded through the seventh capacitor and the eighth capacitor respectively, and is connected to the power supply; the 5VREF pin of the second gate drive chip is grounded through the sixth capacitor and is connected to the VCC1 pin of the first gate drive chip; the IN pin of the second gate drive chip is connected to the control circuit; the OUT pin of the second gate drive chip is connected to its own NEG pin through the ninth capacitor; the DESAT pin of the second gate drive chip is grounded through the tenth capacitor;

[0025] The seventh to ninth resistors, and the second and third diodes, the 5VREF pin of the second gate drive chip is also connected to its own FAULT pin through the seventh resistor; the DESAT pin of the second gate drive chip is also connected to the source of the upper bridge arm and the drain of the lower bridge arm of the corresponding phase through the eighth resistor and the second diode respectively; the NEG pin of the second gate drive chip is also connected to the gate of the lower bridge arm of the corresponding phase through the ninth resistor;

[0026] The FO pin of the first gate drive chip and the FAULT pin of the second gate drive chip are both connected to the control circuit through the third diode;

[0027] Among them, the tenth capacitor, the eighth resistor and the second diode form a desaturation detection circuit.

[0028] Preferably, the current sampling circuit adopts a differential amplifier circuit and is composed of a differential operational amplifier and a voltage follower.

[0029] Preferably, the communication circuit includes a CAN transceiver, the CAN transceiver is an SN65HVD230DR type transceiver, the D end and the R end of the CAN transceiver are respectively connected to the control circuit; the CANH end and the CANL end of the CAN transceiver are respectively connected to the upper computer through a first-order RC filter circuit, a common-mode filter and an anti-static surge protection diode.

[0030] Preferably, the high-speed motor controller further includes a power supply circuit, which is respectively connected to the gate drive circuit, the current sampling circuit, the control circuit and the communication circuit for supplying power to each circuit module.

[0031] To achieve the above object, a second aspect of the present invention provides a high-speed motor control system applied to a high-temperature environment, including the above-mentioned high-speed motor controller, a host computer, and a high-speed motor; the host computer communicates with the high-speed motor controller to achieve the operation control of the high-speed motor.

[0032] The present invention has at least the following technical effects:

[0033] (1) The present invention provides a high-speed motor controller applied to a high-temperature environment, which uses a silicon carbide metal oxide semiconductor field effect transistor as a power semiconductor device, and can solve the problems of large losses of traditional high-speed motor controllers, high harmonic components in the motor phase current, and high temperature rise of the controller during the operation of high-speed motors, and improves the high-temperature resistance ability of the high-speed motor controller.

[0034] (2) The present invention provides a novel structure of a high-speed motor controller. Among them, the gate drive circuit includes two gate drive chips, a bootstrap circuit, and a desaturation detection circuit, and can convert the PWM signal output by the control circuit, that is, the control signal, into a drive signal suitable for silicon carbide power semiconductor devices through the provided complex structure, so that the silicon carbide power semiconductor devices can be turned on and off quickly, and further can ensure the fast, safe, and stable control of high-speed motors; among them, the current sampling circuit can achieve the closed-loop feedback control of high-speed motors; the communication circuit can achieve stable communication with the host computer and the control circuit through a CAN transceiver, a first-order RC filter circuit, a common-mode filter, and an anti-static surge protection diode. The communication between the communication circuit and the host computer can achieve the control of starting, stopping, speed, forward and reverse rotation, overcurrent protection, etc. of high-speed motors.

[0035] Additional aspects and advantages of the present invention will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of the present invention. Description of the Drawings

[0036] Figure 1 It is a schematic diagram of the overall design of the high-speed motor controller applied to a high-temperature environment according to an embodiment of the present invention.

[0037] Figure 2 It is a schematic diagram of the structure of the three-phase inverter circuit according to an embodiment of the present invention.

[0038] Figure 3 It is a schematic diagram of the structure of the gate drive circuit according to an embodiment of the present invention.

[0039] Figure 4 It is a schematic diagram of the structure of the control circuit according to an embodiment of the present invention.

[0040] Figure 5 It is a schematic diagram of the structure of the current sampling circuit according to an embodiment of the present invention.

[0041] Figure 6 Schematic diagram of the communication circuit structure according to an embodiment of the present invention.

[0042] Figure 7 Schematic diagram of the power supply circuit structure according to an embodiment of the present invention. Detailed implementation manners

[0043] The following details this embodiment. Examples of the embodiment are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present invention and should not be construed as limiting the present invention.

[0044] The following describes the high-speed motor controller and control system applied to high-temperature environments according to this embodiment with reference to the accompanying drawings.

[0045] Figure 1 Overall design schematic diagram of the high-speed motor controller applied to high-temperature environments according to an embodiment of the present invention. As Figure 1 shown, the high-speed motor controller applied to high-temperature environments includes a three-phase inverter circuit, a gate drive circuit, a control circuit, a current sampling circuit, a communication circuit, and a power supply circuit.

[0046] Among them, the control circuit, the gate drive circuit, the three-phase inverter circuit, and the high-speed motor are connected in sequence. The current sampling circuit is respectively connected to the three-phase inverter circuit and the control circuit. The communication circuit is respectively connected to the control circuit and an external host computer. The power supply circuit is respectively connected to each circuit module.

[0047] In this embodiment, the three-phase inverter circuit adopts SVPWM (Space Vector Pulse Width Modulation) modulation technology to generate sinusoidal current with a 120° electrical angle difference between three phases to drive the high-speed motor. Each phase leg of the three-phase inverter circuit in this embodiment includes two silicon carbide power semiconductor devices. The gate drive circuit converts the PWM (Pulse Width Modulation) signal output by the control circuit, that is, the control signal, into a drive signal suitable for the silicon carbide power semiconductor device, so that the silicon carbide power semiconductor device can be quickly turned on and off. The control circuit is used to output a control signal for controlling the operation of the high-speed motor to drive the high-speed motor through the gate drive circuit and the three-phase inverter circuit. The current sampling circuit is used to collect voltage signals from the three-phase sampling resistors, and after amplification and filtering, output them to the control circuit to obtain the magnitudes of the three-phase currents, so as to facilitate the control circuit to achieve closed-loop feedback control of the high-speed motor through the three-phase currents. The communication circuit mainly realizes the interactive communication between the host computer and the control circuit, and is mainly used for controlling the start, stop, speed, forward and reverse rotation, overcurrent protection, etc. of the high-speed motor. The power supply circuit is used to supply power to the gate drive circuit, the control circuit, the current sampling circuit, and the communication circuit.

[0048] Figure 2 The structural schematic diagram of the three - phase inverter circuit according to the embodiment of the present invention is as follows. As Figure 2 shown, the three - phase inverter circuit specifically includes a first capacitor C1, first to sixth switching transistors Q1 - Q6, and first to third sampling resistors R1 - R3. Among them, the first capacitor C1 is connected in parallel across the positive and negative terminals of the DC bus; the first switching transistor Q1 and the fourth switching transistor Q4 are connected in series on the A - phase bridge arm; the third switching transistor Q3 and the sixth switching transistor Q6 are connected in series on the B - phase bridge arm; the fifth switching transistor Q5 and the second switching transistor Q2 are connected in series on the C - phase bridge arm; the three - phase bridge arms are connected in parallel with the first capacitor C1; the mid - point of the three - phase bridge arms is connected to the high - speed motor M. Among them, the first to sixth switching transistors Q1 - Q6 are all silicon carbide power semiconductor devices. The first to third sampling resistors R1 - R3 are respectively connected in series on the lower bridge arms of the three - phase bridge arms to facilitate three - phase current sampling.

[0049] Specifically, Figure 2 Udc in [[ ]] is the DC bus voltage with a rated value of 600V, and C1 is the DC bus capacitor connected in parallel across the DC bus voltage to stabilize the DC bus voltage.

[0050] Each of the three - phase bridge arms is composed of two silicon carbide power semiconductor devices, namely Q1, Q4, Q3, Q6, Q5, Q2. Each phase bridge arm is connected in parallel across the DC bus voltage. The model of the silicon carbide power semiconductor device is G3R45MT17D, with a breakdown voltage of 1700V, a conduction resistance of 45mΩ, and a maximum continuous current that can be tolerated at 100°C of 37A.

[0051] The sampling resistors R1, R2, and R3 are 10mΩ resistors connected in series between the silicon carbide power semiconductor devices on the lower bridge arms of the three - phases and the negative terminal of the DC bus voltage for current sampling.

[0052] Figure 3 The structural schematic diagram of the gate - drive circuit according to the embodiment of the present invention is as follows. As Figure 3 shown, the gate - drive circuit includes a first gate - drive chip U1A, a second gate - drive chip U2A, second to tenth capacitors C2 - C10, fourth to ninth resistors R4 - R9, and first to third diodes D1 - D3.

[0053] Among them, the first gate driver chip is a driver chip of type IVCO1412; the VCC1 pin of the first gate driver chip is grounded through the second capacitor C2; the IN pin of the first gate driver chip is connected to the control circuit; the OUT pin of the first gate driver chip is connected to its own NEG pin through the third capacitor C3; the VCC2 pin of the first gate driver chip is connected to its own VEE2 pin through the fifth capacitor C5; the VEE2 pin of the first gate driver chip is connected to the source of the switching transistor of the corresponding phase upper bridge arm; the VCC1 pin of the first gate driver chip is also connected to its own FO pin through the fourth resistor R4; the VEE2 pin of the first gate driver chip is also connected to the power supply, i.e., the 18V power supply, through the fourth capacitor C4, the first diode D1, and the fifth resistor R5; the NEG pin of the first gate driver chip is connected to the gate of the switching transistor of the corresponding phase upper bridge arm through the sixth resistor R6; among them, the fifth resistor R5, the first diode D1, and the fourth capacitor C4 form a bootstrap circuit.

[0054] The second gate driver chip is a driver chip of type IVCR1401; the VCC pin of the second gate driver chip is grounded through the seventh capacitor C7 and the eighth capacitor C8 respectively, and is connected to the power supply; the 5VREF pin of the second gate driver chip is grounded through the sixth capacitor C6 and is connected to the VCC1 pin of the first gate driver chip; the IN pin of the second gate driver chip is connected to the control circuit; the OUT pin of the second gate driver chip is connected to its own NEG pin through the ninth capacitor C9; the DESAT pin of the second gate driver chip is grounded through the tenth capacitor C10; the 5VREF pin of the second gate driver chip is also connected to its own FAULT pin through the seventh resistor R7; the DESAT pin of the second gate driver chip is also connected to the source of the corresponding phase upper bridge arm and the drain of the lower bridge arm through the eighth resistor R8 and the second diode D2 respectively; the NEG pin of the second gate driver chip is also connected to the gate of the corresponding phase lower bridge arm through the ninth resistor R9; the FO pin of the first gate driver chip and the FAULT pin of the second gate driver chip are both connected to the control circuit through the third diode D3; among them, the tenth capacitor C10, the eighth resistor R8, and the second diode D2 form a desaturation detection circuit.

[0055] Specifically, taking the gate driver circuit of the A-phase bridge arm as an example, the gate driver circuits of the B-phase and C-phase are the same, and the gate driver circuit includes:

[0056] The gate driver circuit uses two gate driver chips of different models to drive the silicon carbide power semiconductor devices of the upper bridge arm and the lower bridge arm respectively. Among them, Figure 3The medium - low side gate driver chip, i.e., the second gate driver chip, is model IVCR1401, which is a 4 - ampere single - channel high - speed intelligent driver. For the high side, it is necessary to consider isolating the high - voltage signal from the digital signal. The high - side gate driver chip, i.e., the first gate driver chip, is model IVCO1412, which is a 4 - ampere single - channel isolated gate driver with an isolation voltage of 5.7 kV.

[0057] D3 is a Schottky diode, which is connected to the FO pin of the high - side gate driver chip and the FAULT pin of the low - side gate driver chip respectively. When one of the two chips detects a fault, the FO pin or the FAULT pin will be pulled low to a low level, and D3 will conduct. The fault output will be input into the control circuit through the FAULT signal, thereby triggering protection, stopping the high - speed motor, and then realizing the safe operation of the high - speed motor.

[0058] The 5VREF pin of the low - side gate driver chip outputs + 5VREF voltage, which is used to supply power to the input end of the high - side gate driver chip. C2 and C6 are filter capacitors, which play a role in filtering out high - frequency interference. R4 and R7 are voltage - regulating resistors. The chip has an undervoltage protection function. If the supply voltage of the chip is lower than the set value, the output of the chip remains low - level. The undervoltage protection value is set by setting the resistance value of the voltage - regulating resistor.

[0059] The supply voltage of the low - side gate driver chip and the output power supply voltage of the high - side gate driver chip are both + 18V. Among them, C5, C7, and C8 are all filter capacitors, which play a role in filtering out high - frequency interference.

[0060] R5, D1, and C4 form a bootstrap circuit. Among them, R5 is the bootstrap resistor, D1 is the bootstrap diode, and C4 is the bootstrap capacitor. The function of the bootstrap resistor is to limit the peak current on the bootstrap diode during startup and form a first - order RC circuit with the bootstrap capacitor, making the charging of the bootstrap capacitor more gentle. The bootstrap diode selects a Schottky diode with a low forward voltage drop, model US1NWF - 7, which can effectively reduce the risk of power feedback charge from the bootstrap capacitor to the gate driver chip and minimize the leakage current to the greatest extent. The bootstrap capacitor is used to store charge to ensure sufficient energy to drive the gate of the high - side silicon carbide power semiconductor device. The bootstrap circuit of this embodiment can ensure the safe and stable operation of the high - speed motor controller.

[0061] C3 and C9 are the negative voltage capacitors of the high-side and low-side gate driver chips respectively, connected between the OUT pin and the NEG pin. When the gate driver chip starts up, the NEG output is pulled to low level, thus charging the external negative voltage capacitor through the OUT pin. Before the negative voltage capacitor is fully charged, regardless of the logic level of IN, FAULT remains low level. After the negative voltage is established, both the NEG pin and the FAULT pin are released, and OUT starts to follow the input signal of the IN pin. After that, the gate drive signal NEG switches between -3V and -3V.

[0062] The DESAT pin of the low-side gate driver chip is the desaturation detection input pin, which forms a desaturation detection circuit with C10, R8, and D2. Among them, C10 is the blanking capacitor, R8 is the current-limiting resistor, and D2 is a Schottky diode with a low forward conduction voltage drop. When a short circuit or overcurrent occurs, the drain current of the silicon carbide power semiconductor device may increase to a very high value. After the DESAT pin detects a high drain current, it controls the silicon carbide power semiconductor device to exit the saturation state, thereby ensuring the safe operation of the high-speed motor controller.

[0063] R6 and R9 are gate resistors. On the one hand, the gate resistors can limit the magnitude of the gate current to prevent damage to the silicon carbide power semiconductor device due to excessive gate current. On the other hand, due to the existence of parasitic inductance and parasitic capacitance in the circuit, it may cause oscillation in the gate loop. The gate resistors can increase the damping of the gate loop, thereby playing a role in suppressing circuit oscillation.

[0064] Figure 4 is a schematic structural diagram of the control circuit of the embodiment of the present invention. As Figure 4 shown, the main control chip of the control circuit selects TMS320280037 in the C2000 real-time microcontroller series of TI Company. This chip supports a maximum clock frequency of 120MHz and has 16 ePWM channels and 3 12-bit analog-to-digital converters (ADCs), namely ADC_A, ADC_B, and ADC_C. Each ADC has 16 sampling channels. 6 PWM signals PWMH_A, PWML_A, PWMH_B, PWML_B, PWMH_C, and PWML_C are connected to the corresponding pins of the main control chip. When the program runs, the PWM signals are sent from the main control chip to the gate driver chip. When there is no PWM signal output, to avoid the situation that the pins are in a floating state and may cause the upper and lower tubes of the driving half-bridge to conduct simultaneously, a pull-down resistor is connected to each pin to make the pin state default to low level. 3 current signals ADC_IA, ADC_IB, and ADC_IC are each sampled by three sampling channels, and then the sampled values are averaged to improve the accuracy of the sampling result.

[0065] CAN_TXD and CAN_RXD are respectively for CAN (a serial communication protocol) to send data and receive data. The main control chip is connected to the CAN transceiver through CAN_TXD and CAN_RXD.

[0066] FAULT is the fault output signal, connected to GP1O16, with an external pull-up resistor to make the default state of GPIO16 high level. When the gate driver chip detects desaturation and undervoltage, the FAULT signal is at low level. The main control chip reads the state of GPIO16 and triggers overcurrent protection through the program.

[0067] Figure 5 It is the schematic diagram of the current sampling circuit structure of the embodiment of the present invention. As Figure 5 shown, the current sampling circuit uses a differential amplifier circuit with an amplification factor of 25 times. The model of the operational amplifier is COS8054, which is a four-channel rail-to-rail input and output operational amplifier with a gain-bandwidth product of 100MHz and a slew rate of 150V / us.

[0068] R1 is the sampling resistor for phase A. After the three-phase current flows through the sampling resistor, a voltage drop will be generated across the resistor. The resistor is connected to both ends of the differential operational amplifier for amplification. C11 is a filter capacitor used to filter out high-frequency interference across the sampling resistor.

[0069] R17 and R18 are input resistors, R19 is a balancing resistor, and R20 is a feedback resistor. Among them, R17 is connected to the positive end of the sampling resistor and the inverting input terminal of the differential operational amplifier, R18 is connected to the negative end of the sampling resistor and the non-inverting input terminal of the differential operational amplifier, R19 is connected to the non-inverting input terminal and +2.5VREF, and +2.5VREF is the DC bias voltage used to raise the amplified voltage by 2.5V. R20 is connected to the inverting input terminal and the output terminal. R17 is equal to R18, and R19 is equal to R20. The amplification factor is the ratio of R20 to R17. C13 is in parallel with R20, and C12 is in parallel with R19, respectively forming a first-order RC filter circuit to make the sampling bandwidth greater than 1MHz.

[0070] After the output voltage of the differential operational amplifier is divided by R21 and R22, the voltage range is 0 - 3V. The parallel combination of the resistors and the capacitor C14 form a first-order RC filter circuit with a cut-off frequency of 1Mhz.

[0071] The filtered voltage signal is input to the non-inverting input terminal of the voltage follower and then fed back to the output terminal through the inverting input terminal, and the voltage magnitude remains unchanged. The output resistance of the voltage follower is small and is used to provide sufficient current for the load.

[0072] D4 is a switching diode used to clamp the voltage signal output from the voltage follower, so that the voltage signal is clamped between 0 and 3.3V to prevent damage to the main control chip due to excessive voltage.

[0073] In this embodiment, the current sampling circuit sampling three-phase current can achieve the following functions, namely vector control, current loop feedback, short circuit or overload protection, temperature management, harmonic suppression, efficiency maximization, phase current balance monitoring, fault-tolerant operation and load mutation response, etc.

[0074] For example, for vector control, the instantaneous values of the three-phase current can be obtained in real time and converted into direct-axis and quadrature-axis components, so as to accurately control the torque and magnetic field of the high-speed motor. Without current feedback, dynamic decoupling control cannot be achieved. For current loop feedback, the current loop is the core inner loop of motor control. By adjusting the PWM duty cycle of the inverter in real time, it ensures that the actual current tracks the target current value, thereby improving the dynamic response and anti-interference ability. For short circuit or overload protection, when the motor is blocked, the load suddenly changes or the circuit fails, the current may rise sharply. Current sampling can detect abnormal current in real time and trigger protection (such as turning off the PWM output) to prevent the power device from burning out. For temperature management, the temperature rise of the high-speed motor and the inverter can be indirectly evaluated through current monitoring to avoid overheating damage. For harmonic suppression, the PWM voltage output by the inverter contains high-order harmonics, resulting in current distortion. Current sampling can be used for harmonic compensation (such as dead-time compensation, harmonic closed-loop suppression) to reduce losses and noise. For efficiency maximization, the ratio of electromagnetic torque to current can be optimized to improve energy efficiency. For phase current balance monitoring, unbalanced three-phase current may indicate motor winding failure, inverter bridge arm damage or sensor abnormality. Thus, faults (such as open phase, phase-to-phase short circuit) can be quickly identified through current sampling. For fault-tolerant operation, current feedback can support reconfiguration control after a fault (such as disabling the faulty phase, switching the topology). For load mutation response, when the load of the high-speed motor suddenly changes, current feedback can assist the controller to quickly adjust the output to avoid speed fluctuation or out-of-step.

[0075] Figure 6 It is a schematic diagram of the communication circuit structure of the embodiment of the present invention. As Figure 6 shown, the communication circuit uses CAN communication as the communication protocol, the model of the CAN transceiver is SN65HVD230DR, the data transmission rate can reach 1Mbps, and different working modes can be set, including high-speed mode, slope control mode, and low-power mode.

[0076] CAN_TXD and CAN_RXD are respectively connected to D and R of the CAN transceiver, where D is the CAN transmission data input and R represents the CAN received data output.

[0077] The CAN transceiver is powered by +3.3V. C16 and C17 are filtering capacitors used to filter out high-frequency interference.

[0078] R25 and C18, as well as R26 and C19, form a first-order RC filtering circuit to filter out high-frequency interference signals at both ends of CANH and CANL.

[0079] The CAN transceiver sets different operating modes through the RS pin. This circuit adopts the slope control mode, that is, the rate of CAN communication is controlled by controlling the on and off rates of the transistor. It can be adjusted by connecting a resistor in series between the RS pin and the ground. The slope is proportional to the output current of the pin. The resistance value of R24 is 4.7k. It can be known from the data sheet that the slew rate corresponding to a resistance value of 4.7k is 18V / us.

[0080] R27 and R28 are pull-down resistors. Since the internal pull-down bias of the CAN transceiver is very weak for floating pins, external pull-down resistors are needed to more strongly bias the pin state during transient events to resist noise.

[0081] L1 is a common-mode filter used to prevent interference caused by common-mode signals. D5 and D6 are anti-static surge protection diodes (TVS). When there is a voltage surge, the TVS tube will clamp the voltage to prevent the device from being damaged.

[0082] F1 and F2 are self-resetting fuses. When there is an overcurrent in the circuit, the resistance value of the self-resetting fuse will increase rapidly, reducing the current in the circuit and thus protecting other devices.

[0083] R34 is a 120-ohm terminating resistor. The terminating resistor matches the characteristic impedance of the bus, which can eliminate signal reflection at both ends of the bus. In addition, it is beneficial to form a recessive level with a voltage drop of 0V at both ends of the bus, thus ensuring that the bus is in a recessive state when there is no data transmission.

[0084] Figure 7 This is the structural schematic diagram of the power supply circuit of the embodiment of the present invention. As Figure 7 shown, the power supply circuit includes +18V accessed from the outside. +18V is stepped down to +5V through the buck chip SCT2400. +5V is stepped down to +3.3V through the linear voltage regulator AMS1117-3.3V. The digital voltage +5V and the analog voltage +A5V are isolated through a 1uH inductor. +A5V is stepped down to +2.5VREF through the voltage reference chip TL431.

[0085] The externally connected +18V voltage is stepped down to +5V by the buck chip SCT2400. C20, C21, and C22 are input capacitors, and C23, C24, and C25 are output capacitors, which are used for voltage regulation and filtering. EN is the enable pin of the buck chip, and an external pull-up resistor of 100K is connected to enable the input voltage of the chip to reach 18V. L2 is an inductor. When the internal switch of the chip is turned on, L2 can convert electrical energy into magnetic energy and store it. When the internal switch of the chip is turned off, L2 releases the stored energy, keeping the current continuous and stable and reducing the ripple of the output voltage. R30 and R31 are voltage-dividing resistors that affect the magnitude of the output voltage. The feedback voltage value of the FB pin is 0.81V. When the output voltage is +5V, R30 is 105K and R31 is 20K.

[0086] +5V is stepped down to +3.3V by the linear voltage regulator AMS1117-3.3V. C26, C27, and C28 are all filter capacitors, which are used to filter out high-frequency interference.

[0087] The digital voltage +5V and the analog voltage +A5V are isolated by an inductor L3 of 1uH. The digital ground GND and the analog ground AGND are isolated by a 0-ohm resistor R32.

[0088] The internal reference voltage of TL431 is 2.5V. +A5V is stepped down to +2.5VREF by the voltage reference chip TL431. C31, C32, C33, and C34 are filter capacitors, which are used for voltage regulation and filtering. R33 is a current-limiting resistor, which is used to prevent excessive current from damaging the voltage reference chip.

[0089] Furthermore, the present invention also provides a high-speed motor control system applied to a high-temperature environment, including the above-mentioned high-speed motor controller, upper computer, and high-speed motor. In this embodiment, the upper computer communicates with the high-speed motor controller interactively, and can realize the operation control of the high-speed motor.

[0090] In summary, the present invention provides a high-speed motor controller applied to high-temperature environments. It uses silicon carbide metal-oxide-semiconductor field-effect transistors as power semiconductor devices, which can solve problems such as large losses in traditional high-speed motor controllers, high harmonic components in motor phase currents, and high temperature rise of the controller during the operation of high-speed motors. It improves the high-temperature resistance ability of the high-speed motor controller; the present invention provides a novel structure of a high-speed motor controller. Among them, the gate drive circuit includes two gate drive chips, a bootstrap circuit, and a desaturation detection circuit, and through the provided complex structure, the PWM signal output by the control circuit, that is, the control signal, can be converted into a drive signal suitable for silicon carbide power semiconductor devices, enabling the silicon carbide power semiconductor devices to conduct and turn off quickly, thereby ensuring the fast, safe, and stable control of high-speed motors; among them, the current sampling circuit can achieve closed-loop feedback control of high-speed motors; the communication circuit can achieve stable communication with the host computer and the control circuit through a CAN transceiver, a first-order RC filter circuit, a common-mode filter, and an anti-static surge protection diode. The communication between the communication circuit and the host computer can achieve control of starting, stopping, speed, forward and reverse rotation, overcurrent protection, etc. of high-speed motors.

[0091] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without more limitations, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0092] Although the content of the present invention has been introduced in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and substitutions to the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A high-speed motor controller for use in a high-temperature environment, characterized in that: include: A control circuit, used for outputting a control signal for controlling the operation of the high-speed motor; A gate drive circuit connected to the control circuit, the gate drive circuit is used to convert the control signal into a drive signal for driving the silicon carbide power semiconductor device; A three-phase inverter circuit is respectively connected to the gate drive circuit and the high-speed motor. Each phase bridge arm of the three-phase inverter circuit includes two silicon carbide power semiconductor devices. The three-phase inverter circuit is used to generate a three-phase sinusoidal current under the action of the drive signal to drive the high-speed motor to operate.

2. The high-speed motor controller according to claim 1, characterized in that: Also includes: The current sampling circuit is connected to the three-phase inverter circuit and the control circuit respectively. The current sampling circuit is used to sample the three-phase current in the three-phase inverter circuit and feed it back to the control circuit so as to realize closed-loop feedback control of the high-speed motor.

3. The high-speed motor controller according to claim 1, characterized in that: Also includes: The communication circuit is connected to the host computer and the control circuit respectively, and the communication circuit is used to realize interactive communication between the host computer and the control circuit.

4. The high-speed motor controller according to claim 1, characterized in that: The three-phase inverter circuit specifically includes: A first capacitor is connected in parallel to the positive and negative ends of the DC bus; The first to sixth switch tubes, wherein the first switch tube and the fourth switch tube are connected in series on the A-phase bridge arm; the third switch tube and the sixth switch tube are connected in series on the B-phase bridge arm; the fifth switch tube and the second switch tube are connected in series on the C-phase bridge arm; the three-phase bridge arm is connected in parallel with the first capacitor; the midpoint of the three-phase bridge arm is connected to the high-speed motor; wherein the first to sixth switch tubes are all silicon carbide power semiconductor devices; The first to third sampling resistors are respectively connected in series to the lower bridge arms of the three-phase bridge arms to facilitate three-phase current sampling.

5. The high-speed motor controller according to claim 4, characterized in that: The gate drive circuit comprises: A first gate driving chip, wherein the first gate driving chip is an IVCO1412 type driving chip; The second capacitor to the fifth capacitor, the VCC1 pin of the first gate driver chip is grounded through the second capacitor; the IN pin of the first gate driver chip is connected to the control circuit; the OUT pin of the first gate driver chip is connected to its own NEG pin through the third capacitor; the VCC2 pin of the first gate driver chip is connected to its own VEE2 pin through the fifth capacitor; the VEE2 pin of the first gate driver chip is connected to the source of the corresponding phase upper bridge arm switch tube; The fourth to sixth resistors and the first diode, the VCC1 pin of the first gate driver chip is also connected to its own FO pin through the fourth resistor; the VEE2 pin of the first gate driver chip is also connected to the power supply through the fourth capacitor, the first diode and the fifth resistor; the NEG pin of the first gate driver chip is connected to the gate of the corresponding phase upper bridge arm switch tube through the sixth resistor; The fifth resistor, the first diode and the fourth capacitor constitute a bootstrap circuit.

6. The high-speed motor controller according to claim 5, characterized in that: The gate drive circuit further includes: A second gate drive chip, wherein the second gate drive chip is an IVCR1401 drive chip; The sixth capacitor to the tenth capacitor, the VCC pin of the second gate drive chip is grounded through the seventh capacitor and the eighth capacitor respectively, and is connected to the power supply; the 5VREF pin of the second gate drive chip is grounded through the sixth capacitor, and is connected to the VCC1 pin of the first gate drive chip; the IN pin of the second gate drive chip is connected to the control circuit; the OUT pin of the second gate drive chip is connected to its own NEG pin through the ninth capacitor; the DESAT pin of the second gate drive chip is grounded through the tenth capacitor; The seventh to ninth resistors and the second and third diodes, the 5VREF pin of the second gate driver chip is also connected to its own FAULT pin through the seventh resistor; the DESAT pin of the second gate driver chip is also connected to the source of the upper bridge arm and the drain of the lower bridge arm of the corresponding phase through the eighth resistor and the second diode respectively; the NEG pin of the second gate driver chip is also connected to the gate of the lower bridge arm of the corresponding phase through the ninth resistor; The FO pin of the first gate driving chip and the FAULT pin of the second gate driving chip are both connected to the control circuit through a third diode; The tenth capacitor, the eighth resistor and the second diode constitute a desaturation detection circuit.

7. The high-speed motor controller according to claim 2, characterized in that: The current sampling circuit adopts a differential amplifier circuit, and is composed of a differential operational amplifier and a voltage follower.

8. The high-speed motor controller according to claim 3, characterized in that: The communication circuit includes a CAN transceiver, which is a SN65HVD230DR transceiver. The D end and the R end of the CAN transceiver are respectively connected to the control circuit; the CANH end and the CANL end of the CAN transceiver are respectively connected to the host computer through a first-order RC filter circuit, a common mode filter and an anti-static surge protection diode.

9. The high-speed motor controller according to claim 2, characterized in that: It also includes a power supply circuit, which is respectively connected to the gate drive circuit, the current sampling circuit, the control circuit and the communication circuit, and is used to supply power to each circuit module.

10. A high-speed motor control system used in a high-temperature environment, characterized in that: It comprises a high-speed motor controller, a host computer and a high-speed motor as described in any one of claims 1 to 9; the host computer interacts and communicates with the high-speed motor controller to realize operation control of the high-speed motor.

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