High-efficiency frequency tripler for optimizing common-mode impedance based on transformer tap inductance

Abstract

The invention provides a high-efficiency frequency tripler for optimizing common-mode impedance based on transformer tap inductance, which belongs to the field of radio frequency integrated circuits and comprises an input matching network, a frequency tripling unit, an interstage matching network, a buffer amplification monocular and an output matching network. Wherein the inter-stage matching network is connected in series with an 8-shaped inductor at a center tap of a primary coil, so that common-mode impedance can be adjusted and optimized on the premise of not obviously influencing differential-mode impedance, the efficiency of the frequency tripler is improved, and the sensitivity of a frequency tripling unit to the common-mode impedance is inhibited. In addition, due to the fact that the inductors connected with the center tap in series are symmetrically wound in an 8-shaped mode, extra area is not needed when the tap inductors are added.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency integrated circuits, and particularly relates to a high-efficiency tripler based on optimizing the common-mode impedance with a tapped inductor of a transformer. Background Art

[0002] With the development of communication technologies, the millimeter-wave band (30 GHz - 300 GHz) has become crucial for realizing high-speed wireless communication data transmission due to its high frequency and abundant bandwidth resources. As the core part of a high-speed wireless transceiver, the millimeter-wave frequency source has a vital impact on the performance of the entire system in terms of power consumption, output power, phase noise, etc. In addition, there is a wide demand for high-performance millimeter-wave frequency sources in the fields of high-precision radar and high-precision imaging.

[0003] In the millimeter-wave band, there are mainly two schemes for generating a frequency source. One scheme is to directly generate a millimeter-wave signal with an oscillator. However, as the frequency increases, the directly generated frequency has the disadvantage of poor noise performance. The other scheme is to first generate a fundamental wave with a low-frequency oscillator and then provide a local oscillator output at the target frequency through a tripler. This scheme avoids directly designing an oscillator in the millimeter-wave band and reduces the design difficulty, thus becoming a common frequency source scheme.

[0004] The introduction of a tripler will increase the area and power consumption overhead. The common tripler implemented with a transistor differential pair has the problem of low efficiency. Improving the conversion efficiency of the tripler has become a hot issue in tripler design. Summary of the Invention

[0005] The purpose of the present invention is to propose a high-efficiency tripler circuit based on optimizing the common-mode impedance with a tapped inductor of a transformer to improve the efficiency of the tripler.

[0006] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0007] A high-efficiency tripler based on optimizing the common-mode impedance with a tapped inductor of a transformer, characterized by comprising: an input matching network, a tripling unit, an inter-stage matching network, a buffer amplification unit, and an output matching network.

[0008] Further, the input matching network is composed of a first transformer, a first capacitor, a second capacitor, a first inductor, a second inductor, and a first resistor; one end of the primary coil of the first transformer is connected to the input end of the tripler, and the other end is grounded. The first capacitor is connected in parallel across the primary coil of the first transformer; one end of the first resistor is connected to the center tap of the secondary coil of the first transformer, and the other end is connected to the first bias voltage. The second capacitor is connected in parallel across the secondary coil of the first transformer; one end of the first inductor and the second inductor are respectively connected to both ends of the secondary coil of the first transformer. The other end of the first inductor is connected to the gate of the first transistor, and the other end of the second inductor is connected to the gate of the second transistor.

[0009] Further, the tripler unit is composed of a first transistor, a second transistor, a first neutralizing capacitor, and a second neutralizing capacitor; the sources of the first transistor and the second transistor are grounded. The drains of the first transistor and the second transistor are respectively connected to both ends of the primary coil of the second transformer; one end of the first neutralizing capacitor is connected to the gate of the first transistor, and the other end is connected to the drain of the second transistor; one end of the second neutralizing capacitor is connected to the gate of the second transistor, and the other end is connected to the drain of the first transistor.

[0010] Further, the inter-stage matching network is composed of a second transformer, a second resistor, and a tapped inductor; both ends of the secondary coil of the second transformer are respectively connected to the third transistor and the fourth transistor; one end of the tapped inductor is connected to the center tap of the primary coil of the second transformer, and the other end is connected to the power supply; one end of the second resistor is connected to the center tap of the secondary coil of the second transformer, and the other end is connected to the second bias voltage.

[0011] Further, the buffer amplifier unit is composed of a third transistor, a fourth transistor, a third neutralizing capacitor, and a fourth neutralizing capacitor; the sources of the third transistor and the fourth transistor are grounded. The drains of the third transistor and the fourth transistor are respectively connected to both ends of the primary coil of the third transformer; one end of the third neutralizing capacitor is connected to the gate of the third transistor, and the other end is connected to the drain of the fourth transistor; one end of the fourth neutralizing capacitor is connected to the gate of the fourth transistor, and the other end is connected to the drain of the third transistor.

[0012] Further, the output matching network is composed of a third transformer, a third capacitor, and a fourth capacitor; the third capacitor is connected in parallel across the primary coil of the third transformer. The center tap of the primary coil of the third transformer is connected to the power supply. The fourth capacitor is connected in parallel across the secondary coil of the third transformer. One end of the secondary coil of the third transformer is connected to the output end of the tripler, and the other end is grounded.

[0013] Further, one end of the tapped inductor is connected to the center tap of the primary coil of the second transformer, and the other end is connected to the power supply. The tapped inductor can adjust the common-mode impedance of the inter-stage matching network without significantly affecting the differential-mode impedance of the inter-stage matching network.

[0014] Furthermore, the tapped inductor can be realized in a symmetric winding form near the second transformer starting from the center tap of the primary coil of the second transformer, and then connected to the power supply (Vsupply).

[0015] Furthermore, the first bias voltage is connected to the center tap of the secondary coil of the first transformer via the first resistor, and directly provides DC bias for the gates of the first transistor and the second transistor through the first inductor and the second inductor. The first bias voltage is selected as the DC voltage when the triple-frequency unit outputs the maximum third-harmonic current at the corresponding input signal amplitude.

[0016] Furthermore, the second bias voltage is connected to the center tap of the secondary coil of the second transformer via the second resistor, and directly provides DC bias for the gates of the third transistor and the fourth transistor. The second bias voltage is selected as the DC voltage when the gain of the buffer amplification unit is maximum.

[0017] Furthermore, the first neutralization capacitor (Cn1) and the second neutralization capacitor (Cn2) are selected with capacitance values when the stability of the triple-frequency unit is the highest.

[0018] Furthermore, the third neutralization capacitor (Cn3) and the fourth neutralization capacitor (Cn4) are selected with capacitance values when the stability of the buffer amplification unit is the highest.

[0019] The beneficial effects of the present invention are as follows:

[0020] Different from the traditional transistor differential pair triple-frequency multiplier, the present invention considers adjusting the common-mode impedance of the triple-frequency unit to improve the efficiency of the triple-frequency multiplier and suppress the sensitivity of the triple-frequency unit to the common-mode impedance. A tapped inductor is added between the center tap of the primary coil of the load transformer of the triple-frequency unit and the power supply to avoid affecting the differential-mode impedance as much as possible when adjusting the common-mode impedance, so that the load differential-mode impedance and common-mode impedance of the triple-frequency unit can be independently designed and optimized. The tapped inductor is realized in a symmetric winding form near the transformer, thus avoiding additional area requirements while improving the efficiency of the triple-frequency multiplier. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic structural diagram of the triple-frequency multiplier and a layout schematic diagram of the inter-stage matching network in the present invention.

[0022] Figure 2 It is a layout schematic diagram of the inter-stage matching network of the traditional triple-frequency multiplier without a tapped inductor.

[0023] Figure 3 It is a comparison diagram of the efficiency between the triple-frequency multiplier of the present invention and the traditional triple-frequency multiplier.

[0024] Figure 4Layout schematic diagram of a tapped inductor using a traditional layout. Detailed implementation manners

[0025] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described below in conjunction with the following specific embodiments and with reference to the accompanying drawings.

[0026] The following non-limiting embodiments can enable those of ordinary skill in the art to more comprehensively understand the present invention, but do not limit the present invention in any way.

[0027] Embodiment 1

[0028] In this embodiment, the triple-frequency multiplier refers to Figure 1 the structural schematic diagram, and is composed of an input matching network, a triple-frequency unit, an inter-stage matching network, a buffer amplification unit and an output matching network.

[0029] The input matching network is composed of a first transformer XFMR1, a first capacitor C1, a second capacitor C2, a first inductor L1, a second inductor L2 and a first resistor R1; one end of the primary coil of the first transformer XFMR1 is connected to the input end Input of the triple-frequency multiplier, and the other end is grounded. The first capacitor C1 is connected in parallel across the primary coil of the first transformer XFMR1; one end of the first resistor R1 is connected to the center tap of the secondary coil of the first transformer XFMR1, and the other end is connected to the first bias voltage Vbias1. The second capacitor C2 is connected in parallel across the secondary coil of the first transformer XFMR1; one end of the first inductor L1 and the second inductor L2 are respectively connected to both ends of the secondary coil of the first transformer XFMR1. The other end of the first inductor L1 is connected to the gate of the first transistor M1, and the other end of the second inductor L2 is connected to the gate of the second transistor M2;

[0030] The triple-frequency unit is composed of a first transistor M1, a second transistor M2, a first neutralizing capacitor Cn1 and a second neutralizing capacitor Cn2; the sources of the first transistor M1 and the second transistor M2 are grounded. The drains of the first transistor M1 and the second transistor M2 are respectively connected to both ends of the primary coil of the second transformer XFMR2; one end of the first neutralizing capacitor Cn1 is connected to the gate of the first transistor M1, and the other end is connected to the drain of the second transistor M2; one end of the second neutralizing capacitor Cn2 is connected to the gate of the second transistor M2, and the other end is connected to the drain of the first transistor M1;

[0031] The inter-stage matching network consists of a second transformer XFMR2, a second resistor R2, and a tapped inductor Lt; both ends of the secondary coil of the second transformer XFMR2 are respectively connected to a third transistor M3 and a fourth transistor M4; one end of the tapped inductor Lt is connected to the center tap of the primary coil of the second transformer XFMR2, and the other end is connected to the power supply Vsupply; one end of the second resistor R2 is connected to the center tap of the secondary coil of the second transformer XFMR2, and the other end is connected to the second bias voltage Vbias2;

[0032] The buffer amplifier unit consists of a third transistor M3, a fourth transistor M4, a third neutralizing capacitor Cn3, and a fourth neutralizing capacitor Cn4; the sources of the third transistor M3 and the fourth transistor M4 are grounded, and the drains of the third transistor M3 and the fourth transistor M4 are respectively connected to both ends of the primary coil of a third transformer XFMR3; one end of the third neutralizing capacitor Cn3 is connected to the gate of the third transistor M3, and the other end is connected to the drain of the fourth transistor M4; one end of the fourth neutralizing capacitor Cn4 is connected to the gate of the fourth transistor M4, and the other end is connected to the drain of the third transistor M3;

[0033] The output matching network consists of a third transformer XFMR3, a third capacitor C3, and a fourth capacitor C4; the third capacitor C3 is connected in parallel across both ends of the primary coil of the third transformer XFMR3, the center tap of the primary coil of the third transformer XFMR3 is connected to the power supply Vsupply, the fourth capacitor C4 is connected in parallel across both ends of the secondary coil of the third transformer XFMR3, and one end of the secondary coil of the third transformer XFMR3 is connected to the output end Output of the frequency tripler, and the other end is grounded.

[0034] Among them, as Figure 1 shown in the layout schematic diagram, the tapped inductor of the inter-stage matching network is realized in the form of symmetric winding near the second transformer starting from the center tap of the primary coil of the second transformer, and then is led out from one side and connected to the power supply. Since the current directions of the two windings are opposite and the magnetic flux directions generated are opposite, the coupling between the tapped inductor and the primary coil and the secondary coil of the second transformer is very small. The common-mode impedance of the inter-stage matching network can be adjusted without significantly affecting the differential-mode impedance of the inter-stage matching network. By adjusting and optimizing the common-mode impedance of the inter-stage matching network, the efficiency of the frequency tripler is improved.

[0035] Based on the above working principle, the design and simulation of the frequency tripler are carried out in this embodiment, and the practicability of the present invention is verified.

[0036] Figure 3 shows a traditional frequency tripler without a tapped inductor (i.e., Figure 2 shown) and the frequency tripler proposed by the present invention with a tapped inductor (i.e., Figure 1Comparison of the conversion efficiency of the tripler (as shown), it can be seen from the figure that adding a certain tap inductance between the center tap of the primary coil of the second transformer and the power supply can improve the efficiency of the tripler.

[0037] Figure 4 The inter-stage matching network with the traditional tap inductance layout is given. Comparison Figure 1 and Figure 4 It can be seen that by adopting the stacked winding form, the tap inductance can be realized without additional area, saving more than 40% of the area of the inter-stage matching network.

[0038] As mentioned above, it is only the specific implementation manner of the present invention. For those of ordinary skill in the art, without departing from the principle of the present invention, the changes and modifications made should also be regarded as the protection scope of the present invention.

Claims

1. A high-efficiency frequency tripler based on transformer tap inductance optimization of common-mode impedance, characterized in that: include: An input matching network, a frequency tripler unit, an inter-stage matching network, a buffer amplifier unit and an output matching network; wherein the input matching network is composed of a first transformer (XFMR1), a first capacitor (C1), a second capacitor (C2), a first inductor (L1), a second inductor (L2) and a first resistor (R1); one end of the primary coil of the first transformer (XFMR1) is connected to the input end (Input) of the frequency tripler, and the other end is grounded, and the first capacitor (C1) is connected in parallel to both ends of the primary coil of the first transformer (XFMR1); one end of the first resistor (R1) is connected to the center tap of the secondary coil of the first transformer (XFMR1), and the other end is connected to the first bias voltage (Vbias1), and the second capacitor (C2) is connected in parallel to the first two ends of a secondary coil of a transformer (XFMR1); one end of a first inductor (L1) and one end of a second inductor (L2) are respectively connected to the two ends of the secondary coil of the first transformer (XFMR1), the other end of the first inductor (L1) is connected to the gate of the first transistor (M1), and the other end of the second inductor (L2) is connected to the gate of the second transistor (M2); the triple frequency unit is composed of a first transistor (M1), a second transistor (M2), a first neutralization capacitor (Cn1) and a second neutralization capacitor (Cn2); the source electrodes of the first transistor (M1) and the second transistor (M2) are grounded, and the drain electrodes of the first transistor (M1) and the second transistor (M2) are respectively connected to the two ends of the primary coil of the second transformer (XFMR2); the first One end of the neutralizing capacitor (Cn1) is connected to the gate of the first transistor (M1), and the other end is connected to the drain of the second transistor (M2); one end of the second neutralizing capacitor (Cn2) is connected to the gate of the second transistor (M2), and the other end is connected to the drain of the first transistor (M1); the inter-stage matching network is composed of a second transformer (XFMR2), a second resistor (R2) and a tapped inductor (Lt); two ends of the secondary coil of the second transformer (XFMR2) are respectively connected to the third transistor (M3) and the fourth transistor (M4); one end of the tapped inductor (Lt) is connected to the center tap of the primary coil of the second transformer (XFMR2), and the other end is connected to the power supply (Vsupply); one end of the second resistor (R2) is connected to the second transformer (XFMR2); 2) a center tap of the secondary coil, and the other end is connected to a second bias voltage (Vbias2); the buffer amplifier unit is composed of a third transistor (M3), a fourth transistor (M4), a third neutralization capacitor (Cn3) and a fourth neutralization capacitor (Cn4); the source electrodes of the third transistor (M3) and the fourth transistor (M4) are grounded, and the drain electrodes of the third transistor (M3) and the fourth transistor (M4) are respectively connected to the two ends of the primary coil of the third transformer (XFMR3); one end of the third neutralization capacitor (Cn3) is connected to the gate electrode of the third transistor (M3), and the other end is connected to the drain electrode of the fourth transistor (M4); one end of the fourth neutralization capacitor (Cn4) is connected to the gate electrode of the fourth transistor (M4), and the other end is connected to the drain electrode of the third transistor (M3);The output matching network is composed of a third transformer (XFMR3), a third capacitor (C3) and a fourth capacitor (C4); the third capacitor (C3) is connected in parallel to both ends of the primary coil of the third transformer (XFMR3), the center tap of the primary coil of the third transformer (XFMR3) is connected to the power supply (Vsupply), the fourth capacitor (C4) is connected in parallel to both ends of the secondary coil of the third transformer (XFMR3), one end of the secondary coil of the third transformer (XFMR3) is connected to the output end (Output) of the tripler, and the other end is grounded. ; 2. The high efficiency tripler according to claim 1, characterized in that: One end of the tapped inductor (Lt) is connected to the center tap of the primary coil of the second transformer (XFMR2), and the other end is connected to the power supply (Vsupply). The tapped inductor (Lt) can adjust the common-mode impedance of the inter-stage matching network without significantly affecting the differential-mode impedance of the inter-stage matching network.

3. The high efficiency tripler according to claim 1, characterized in that: The tapped inductor (Lt) is implemented in the form of a symmetrical 8-shaped winding near the second transformer (XFMR2) starting from the center tap of the primary coil of the second transformer (XFMR2) and then connected to the power supply (Vsupply).

4. The high efficiency tripler according to claim 1, characterized in that: The first bias voltage (Vbias1) is connected to the center tap of the secondary coil of the first transformer (XFMR1) via the first resistor (R1), and directly provides a DC bias for the gates of the first transistor (M1) and the second transistor (M2) through the first inductor (L1) and the second inductor (L2). The first bias voltage (Vbias1) is selected as a DC voltage when the triple frequency unit outputs a maximum third harmonic current under the corresponding input signal amplitude.

5. The high efficiency frequency tripler according to claim 1, characterized in that: The second bias voltage (Vbias2) is connected to the center tap of the secondary coil of the second transformer (XFMR2) via the second resistor (R2), directly providing a DC bias for the gates of the third transistor (M3) and the fourth transistor (M4). The second bias voltage (Vbias2) is selected as a DC voltage that maximizes the gain of the buffer amplifier unit.

6. The high efficiency tripler according to claim 1, characterized in that: The first neutralizing capacitor (Cn1) and the second neutralizing capacitor (Cn2) are selected to have capacitance values ​​when the stability of the triple frequency unit is the highest.

7. The high efficiency tripler according to claim 1, characterized in that: The third neutralizing capacitor (Cn3) and the fourth neutralizing capacitor (Cn4) are selected to have capacitance values ​​when the stability of the buffer amplifier unit is the highest.

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