Semiconductor device

Abstract

A semiconductor device includes a first set of transistors and a second set of transistors. The first set of transistors includes a first terminal, a second terminal, a control terminal, and a base terminal, wherein the base terminal of the first set of transistors is in floating connection. The second group of transistors includes a first terminal, a second terminal, a control terminal, and a base terminal. The first terminal, the second terminal, and the control terminal of the second group of transistors are respectively coupled to the first terminal, the second terminal, and the control terminal of the first group of transistors. The base ends of the second group of transistors are selectively and electrically connected or disconnected with the bias voltage end. When the semiconductor device is in a steady state, the base terminals of the second set of transistors are electrically disconnected from the bias voltage terminal, and when the semiconductor device is in a transient state, the base terminals of the second set of transistors are electrically connected with the bias voltage terminal.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an improved Noise Figure and a better Transient response, which can be used in power amplifiers, low-noise amplifiers, switch modules, etc. Background Art

[0002] Semiconductor devices such as power amplifiers (hereinafter referred to as PAs), low-noise amplifiers (hereinafter referred to as LNAs), and switch modules can be implemented by various types of transistors. For example, the LNA plays a key role in many applications such as wireless communication, radar, and satellite communication. It can be used to amplify weak signals and minimize the noise of the signals during the amplification process. In some applications, it is desirable for the semiconductor device to have an improved Noise Figure and / or a better Transient response. Summary of the Invention

[0003] An embodiment of the present invention discloses a semiconductor device, including a first group of transistors and a second group of transistors. The first group of transistors includes a first end, a second end, a control end, and a base end, wherein the base end of the first group of transistors is floating. The second group of transistors includes a first end, a second end, a control end, and a base end. The first end, the second end, and the control end of the second group of transistors are respectively coupled to the first end, the second end, and the control end of the first group of transistors. The base end of the second group of transistors is selectively electrically connected or disconnected from the bias voltage terminal. When the semiconductor device is in a steady state, the base end of the second group of transistors is electrically disconnected from the bias voltage terminal, and when the semiconductor device is in a transient state, the base end of the second group of transistors is electrically connected to the bias voltage terminal. Brief Description of the Drawings

[0004] Figures 1 to 2 It is a circuit schematic diagram of the semiconductor device according to an embodiment of the present invention.

[0005] Figures 3 to 6 It is a layout schematic diagram of the semiconductor device according to an embodiment of the present invention.

[0006] Symbol Description:

[0007] 100 to 600: Semiconductor device

[0008] 10: First group of transistors

[0009] 12: Second group of transistors

[0010] 13: Third group of transistors

[0011] AA, AA1, AA2: Active region

[0012] BB2, BB1-1, BB1-2: Base region

[0013] B1, B2, B3: Base terminal

[0014] CB: Base contact

[0015] CD: Drain contact

[0016] CG: Gate contact

[0017] D1, D2, D3: First terminal

[0018] DD1-1, DD1-2, DD2: Drain region

[0019] S1, S2, S3: Second terminal

[0020] SS1-1, SS1-2, SS2: Source region

[0021] G1, G2, G3: Control terminal

[0022] GG1-1, GG1-2, GG2: Gate region

[0023] L1, L2: Inductor

[0024] Nr: Bias voltage terminal

[0025] ND, NS, NG: Node

[0026] SW: Switch element

[0027] R1: Resistor element

[0028] T1: First transistor

[0029] T2: Second transistor

[0030] Vc: Control voltage

[0031] Vin: Input signal

[0032] Vout: Output signal

[0033] VSS: Reference voltage

[0034] VDD: System voltage

[0035] VB: Bias signal Detailed implementation manners

[0036] Figures 1 to 2 It is a circuit schematic diagram of semiconductor devices 100 and 200 in the embodiments of the present invention.

[0037] As Figure 1 shown, the semiconductor device 100 may include a first set of transistors 10 and a second set of transistors 12. The first set of transistors 10 may include a first terminal D1, a second terminal S1, a control terminal G1, and a body / bulk terminal B1, and the second set of transistors 12 may similarly include a first terminal D2, a second terminal S2, a control terminal G2, and a body / bulk terminal B2. The first terminal D2, the second terminal S2, and the control terminal G2 of the second set of transistors 12 are respectively coupled to the first terminal D1, the second terminal S1, and the control terminal G1 of the first set of transistors 10, thereby forming nodes ND, NS, and NG respectively. In some embodiments, the body / bulk terminal B1 of the first set of transistors 10 may be floating, and the body / bulk terminal B2 of the second set of transistors 12 may be selectively coupled to a bias voltage terminal Nr. In some cases, the first set of transistors 10 may be referred to as a floating body transistor, for example, and the second set of transistors 12 may be referred to as a non-floating body transistor, for example. In other embodiments, the second set of transistors may also be referred to as a body contact or body tie transistor.

[0038] For example, the first set of transistors 10 and / or the second set of transistors 12 may include a field-effect transistor (FET) or a bipolar junction transistor (BJT). In the case of a field-effect transistor (FET), the first terminal of the transistor may be a drain, the second terminal may be a source, and the control terminal may be a gate. In addition, in the case of a bipolar junction transistor (BJT), the first terminal of the transistor may be a collector, the second terminal may be an emitter, and the control terminal may be a base. For example, the semiconductor device 100 may be applied to a low noise amplifier (LNA), as described below with reference to Figure 2 described.

[0039] As Figure 2As shown, the semiconductor device 200 may include a first group of transistors 10, a second group of transistors 12, and a third group of transistors 13, wherein the arrangements of the first group of transistors 10 and the second group of transistors 12 are similar to their counterparts in the semiconductor device 100. The third group of transistors 13 may include a first terminal D3, a second terminal S3, and a control terminal G3, and may further include a base terminal B3 (not shown). The second terminal S3 of the third group of transistors 13 may be coupled to the node ND, and the first terminal D3 may receive the system voltage VDD via other elements (e.g., an inductor L1). In addition, the control terminal G3 of the third group of transistors 13 may be coupled to a bias circuit (not shown). As Figure 2 shown, the node NS may receive a reference voltage VSS via other elements (e.g., an inductor L2), and the reference voltage VSS may have a fixed voltage level, such as 0V.

[0040] In this embodiment, the semiconductor device 200 may receive an input signal Vin via the node NG and provide an amplified output voltage Vout via the first terminal D3 of the third group of transistors 13. For example, both the input signal Vin and the output voltage Vout may be radio frequency signals. Only exemplary descriptions of the applications of the semiconductor device 200 are provided herein, but the present invention is not limited thereto. In other embodiments, the semiconductor device 200 may also be implemented in devices such as power amplifiers and switch modules.

[0041] In the above embodiments, the semiconductor device 100 and / or 200 may operate in a transient state and a steady state, and may provide an improved noise figure and / or a better transient response.

[0042] Return Figure 1 , the semiconductor device 100 may further include a resistive element R1 and a switching element SW. The resistive element may include a first terminal and a second terminal. Its first terminal may be coupled to the base terminal B2 of the second group of transistors 12, and the second terminal may be coupled to the switching element SW. The switching element SW may include a first terminal, a second terminal, and a control terminal. Its first terminal may be coupled to the second terminal of the resistive element R1, and the second terminal may be coupled to a bias voltage terminal Nr, where the bias voltage terminal Nr may be used to provide a bias signal VB. In this embodiment, the resistance value of the resistor R1 may be, for example, about 100 k ohms to substantially isolate unwanted noise coupling. The bias signal VB may have a fixed voltage level, such as 0V. Further, the control terminal of the switching element SW may receive a control voltage Vc to control the conduction and cutoff of the switching element SW. By means of the switching element SW, the base terminal B2 of the second group of transistors 12 may be selectively electrically connected or disconnected from the bias voltage terminal Nr. In this embodiment, only exemplary descriptions of the configurations of the resistive element R1 and the switching element SW are provided, but the present invention is not limited thereto. In other embodiments, the positions of the resistive element R1 and the switching element SW may be interchanged.

[0043] In some embodiments, as described above, the semiconductor device 100 / 200 can operate in a steady state and a transient state. In the steady state, it is desirable for the semiconductor device 100 / 200 to have an improved noise figure, and in the transient state, it is desirable for the semiconductor device 100 / 200 to have a better transient response.

[0044] Specifically, in Figure 1 the illustrated embodiment, when the semiconductor device 100 operates in the steady state, the switching element SW can be turned off based on the control voltage Vc, such that the base terminal B2 of the second group of transistors 12 is electrically disconnected from the bias voltage terminal Nr, thereby making the base terminal B2 of the second group of transistors 12 floating. In this case, both the base terminal B1 of the first group of transistors 10 and the base terminal B2 of the second group of transistors 12 are floating, thereby providing an improved noise figure to reduce the noise in the output signal Vout. In addition, when the semiconductor device 100 undergoes a state transition, i.e., in the transient state, the switching element SW can be turned on based on the control voltage Vc, such that the base terminal B2 of the second group of transistors 12 is electrically connected to the bias voltage terminal Nr, thereby enabling the base terminal B2 of the second group of transistors 12 to receive the bias signal VB provided by the reference voltage terminal Nr. In this case, the base terminal B2 of the second group of transistors 12 can be at a fixed voltage level, and the semiconductor device 100 can provide a better transient response, thereby completing the state transition of the semiconductor state 100 more quickly. In the above embodiment, regardless of whether the semiconductor device 100 is in the steady state or the transient state, the base terminal B1 of the first group of transistors 10 is floating. For related descriptions, please refer to the following content.

[0045] In some embodiments, the first group of transistors 10, the second group of transistors 12, and / or the switching element SW can be implemented by, for example, N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), but the present invention is not limited thereto. In other embodiments, the first group of transistors 10, the second group of transistors 12, and / or the switching element SW can also be implemented by P-type MOSFETs or other types of transistors.

[0046] Although Figure 1It is shown that the first set of transistors 10 includes one first transistor T1 and the second set of transistors 12 includes one second transistor T2. However, those skilled in the art can change the number of transistors in the first set of transistors 10 and / or the second set of transistors 12 according to actual needs without departing from the spirit of the embodiments of the present invention. In some embodiments, the first set of transistors 10 may include m first transistors T1, and the second set of transistors 12 includes n second transistors T2, where m and n may be integers. In further embodiments, the integers m and n can be configured such that m is equal to or greater than n. For example, the integers m and n can be configured to be approximately m:n = 200:1, 199:1, 100:1, 99:1, 49:1, 3:1, 2:1, or 1:1, as described further below. It should be understood that the numerical values mentioned herein are for illustrative purposes only and may be approximate values. This case includes the ranges of the mentioned numerical values, such as ±10%.

[0047] Figures 3 to 6 It is a layout schematic diagram of semiconductor devices 300 to 600 according to the embodiments of the present invention. Taking a MOSFET as an example, a transistor can be defined as including a drain region, a source region, a gate region, and a base region. From the layout view, the gate region can be located between the drain region and the source region, and two adjacent transistors can share a drain region or a source region. From the cross-sectional view, the base region can be located below the gate region. The manufacturing method of the transistor can include many processes, such as the SOI (silicon on insulator) process.

[0048] As Figure 3 shown, the semiconductor device 300 includes a first set of transistors 10 and a second set of transistors 12, both of which are substantially disposed within the range of the active area AA. In some applications, the active area AA is also referred to as the oxide diffusion region ODr (oxide diffusion region). For ease of description, the active area AA is used hereinafter for description.

[0049] The first group of transistors 10 may include a plurality of first transistors T1 (e.g., 199), and the second group of transistors 12 may include, for example, one second transistor T2. For example, the second transistor T2 may include a drain region DD2, a source region SS2, a gate region GG2, and a base region BB2 located below the gate region GG2. A first transistor T1 may include a drain region DD1-1, a source region SS1-1, a gate region GG1-1 located between the drain region DD1-1 and the source region SS1-1, and a base region BB1-1 located below the gate region GG1-1. Another first transistor T1 may include a drain region DD1-2, a source region SS1-1, a gate region GG1-2 located between the drain region DD1-2 and the source region SS1-1, and a base region BB1-2 located below the gate region GG1-2. As shown in the figure, two adjacent first transistors T1 may share the source region SS1-1. However, the present invention is not limited thereto. In other embodiments, two adjacent first transistors T1 may share the drain region.

[0050] In the above embodiments, the drain regions DD1-1, DD1-2,... of the plurality of first transistors T1 may be connected together via, for example, a first metal layer (not shown). For the sake of convenience of description, they are collectively referred to as the drain region DD1. Similarly, the source regions SS1-1, SS1-2,... of the plurality of first transistors T1 may be connected together via, for example, a second metal layer, which is collectively referred to as the source region SS1, and the gate regions GG1-1, GG1-2,... of the plurality of first transistors T1 may be connected together via, for example, a third metal layer, which is collectively referred to as the gate region GG1.

[0051] In some embodiments, taking the second transistor T2 as an example, it may further include a drain contact CD, a source contact CS, and a gate contact CG, which are respectively used to achieve the connection of the drain region DD2, the source region SS2, and the gate region GG2 to other components (e.g., metal layers). The second transistor T2 may additionally include a base contact CB, which is used to achieve the connection of the base region BB2 to other components, for example, to ground the base region BB2. Furthermore, for the first transistor T1, its base region may be floating, so the first transistor T1 may not include a base contact. The positions and numbers of the nodes shown in the figure are only for the purpose of explanation and are not used to limit the present invention. Those skilled in the relevant art may increase or decrease the number of contacts at appropriate places according to actual needs without departing from the spirit of this case.

[0052] In the above embodiments, with reference to Figure 1 or Figure 2, the drain region DD2 of the second transistor T2 can be coupled to the drain region DD1 of the first transistor T1 to form the node ND mentioned above. The source region SS2 of the second transistor T2 can be coupled to the source region SS1 of the first transistor T1 to form the node NS mentioned above. Further, the node NS can be further coupled to a reference voltage terminal to receive, for example, the reference voltage VSS. The gate region GG2 of the second transistor T2 can be coupled to the gate region GG1 of the first transistor T1 to form the node NG mentioned above.

[0053] Return to Figure 3 , which illustrates an embodiment where, for example, m:n = 199:1. In this embodiment, the number m of the first transistors T1 is, for example, 199, and the number n of the second transistors T2 is, for example, 1. As shown, the second transistor T2 is disposed at a side position of a plurality of first transistors T1. However, the present invention is not limited thereto. In other embodiments, the second transistor T2 is disposed at an intermediate position among a plurality of first transistors T1. That is, half of the number of the first transistors T1 are distributed on the left side of the second transistor T2, and the other half of the number of the first transistors T1 are distributed on the right side of the second transistor T2, as Figure 4 shown in the semiconductor device 400.

[0054] Please refer to Figure 5 , the semiconductor device 500 is similar to the semiconductor device 300, and its main difference is that the second group of transistors 12 includes 2 second transistors T2, that is, n = 2. As shown, the 2 second transistors T2 are respectively disposed at a first side position (for example, the left side) and a second side position (for example, the right side) of a plurality of first transistors T1. In other words, all of the plurality of first transistors T2 are disposed at positions between the two second transistors T2.

[0055] In other embodiments, for example, the first group of transistors 10 can include a plurality of first transistors T1, and the second group of transistors 12 can include a plurality of second transistors T2. Relative to the plurality of first transistors T1, the plurality of second transistors T2 can be evenly distributed among the many first transistors T1. For example, the number of first transistors T1 disposed between every two second transistors T2 can be the same. For example, the second group of transistors 12 can include 3 second transistors T2, which are respectively distributed at two side positions and an intermediate position of the plurality of first transistors T1.

[0056] Please refer to Figure 6, the semiconductor device 600 includes a first set of transistors 10 and a second set of transistors 12, which are substantially disposed within the scope of the active region AA1. The semiconductor device 600 may further include a first set of transistors 10' and a second set of transistors 12', which are substantially disposed within the scope of the active region AA2. In the active region AA2, the configurations of the first set of transistors 10' and the second set of transistors 12' are respectively similar to the first set of transistors 10 and the second set of transistors 12 described above, and will not be elaborated herein. Figure 3 The first set of transistors 10 and the second set of transistors 12 described above, and will not be elaborated herein.

[0057] In at least one embodiment, the semiconductor device includes a first set of transistors and a second set of transistors, wherein the base terminals of the first set of transistors may be floating, and the base terminals of the second set of transistors may be selectively coupled to a bias voltage terminal. The first set of transistors with floating base terminals may provide an improved noise figure, and the second set of transistors with non-floating base terminals may provide a better transient response during transients. For example, the noise figure of the first set of transistors may be actually characterized as 1.5 dB, and the noise figure of the second set of transistors may be actually characterized as 3 dB. Embodiments of the present invention further provide an improved noise figure and a better transient response by appropriate operation of the first set of transistors and the second set of transistors.

[0058] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims

1. A semiconductor device, characterized in that, comprising: a first group of transistors, including a first end, a second end, a control end, and a base end, wherein the base end of the first group of transistors is floating; and a second group of transistors, including a first end, a second end, a control end, and a base end, the first end, the second end, and the control end of the second group of transistors are respectively coupled to the first end, the second end, and the control end of the first group of transistors, wherein the base end of the second group of transistors is selectively electrically connected or disconnected from a bias voltage terminal, wherein, when the semiconductor device is in a steady state, the base end of the second group of transistors is electrically disconnected from the bias voltage terminal; when the semiconductor device is in a transient state, the base end of the second group of transistors is electrically connected to the bias voltage terminal.

2. The semiconductor device according to claim 1, characterized in that, further comprising: a switching element, coupled between the base end of the second group of transistors and the bias voltage terminal, wherein when the semiconductor device is in the steady state, the switching element is turned off; and when the semiconductor device is in the transient state, the switching element is turned on, such that the base end of the second group of transistors receives a bias voltage signal provided by the bias voltage terminal.

3. The semiconductor device according to claim 2, characterized in that, further comprising: a resistance element, coupled between the base end of the second group of transistors and the switching element, or coupled between the switching element and the bias voltage terminal.

4. The semiconductor device according to claim 3, characterized in that, wherein the resistance value of the resistance element is 100 k ohms.

5. The semiconductor device according to claim 1, characterized in that, wherein the first group of transistors and the second group of transistors are disposed in a first active region.

6. The semiconductor device according to claim 1, characterized in that, wherein the semiconductor device is for a power amplifier, a low noise amplifier, or a switching module.

7. The semiconductor device according to claim 1, characterized in that, wherein the first group of transistors includes m first transistors, and the second group of transistors includes n second transistors, wherein m and n are different integers.

8. The semiconductor device according to claim 7, characterized in that, wherein m is greater than n.

9. The semiconductor device according to claim 7, characterized in that, wherein, m:n = 200:1, 199:1, 100:1, 99:1, 49:1, 3:1, 2:1 or 1:

1.

10. The semiconductor device according to claim 7, characterized in that, wherein when n = 1, the 1 second transistor of the second group of transistors is disposed at a side position of the m first transistors of the first group of transistors, or disposed at an intermediate position of the m first transistors of the first group of transistors.

11. The semiconductor device according to claim 7, characterized in that, When n = 2, the two second transistors of the second group of transistors are respectively disposed at the first side position and the second side position of the m first transistors of the first group of transistors.

12. The semiconductor device according to claim 7, wherein: When n > 1, the n second transistors of the second group of transistors are evenly distributed with respect to the m first transistors of the first group of transistors.

13. The semiconductor device according to claim 1, wherein: further comprising: a third group of transistors, including a first end, a second end, a control end, and a base end, wherein the base end of the third group of transistors is floating; a fourth group of transistors, including a first end, a second end, a control end, and a base end, the first end, the second end, and the control end of the fourth group of transistors are respectively coupled to the first end, the second end, and the control end of the third group of transistors, wherein the base end of the fourth group of transistors is selectively electrically connected or electrically disconnected from the bias voltage terminal, wherein the first group of transistors and the second group of transistors are disposed in a first active region, and the third group of transistors and the fourth group of transistors are disposed in a second active region.

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