Programmable frequency divider circuit supporting odd number frequency division duty ratio 50%

Abstract

The invention aims to provide a programmable frequency divider circuit supporting an odd number frequency division duty ratio of 50%. The circuit is characterized in that the input end of a multi-mode frequency division module is connected with clock input, and the output end of the multi-mode frequency division module is connected with an odd number frequency division duty ratio adjusting module and a clock selection module; the input end of the odd-number frequency division duty ratio adjusting module is respectively connected with clock input and the multimode frequency division module, and the output end of the odd-number frequency division duty ratio adjusting module is connected with the clock selection module; and the clock selection module outputs a clock signal after frequency division. Different from a traditional frequency division structure, an insertion delay frequency division mode and any extension based on the structure, for example, different n in a multimode frequency divider supports frequency division in different ranges.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a programmable frequency divider circuit that supports an odd-frequency division duty cycle of 50%. Background Art

[0002] A frequency divider is an electronic circuit or device whose main function is to separate an input signal into multiple output signals with different frequency ranges. The bandwidths of these output signals are all smaller than the bandwidth of the original input signal, enabling each frequency band of the signal to be processed or applied specifically. Frequency dividers are widely used in fields such as communication, measurement, and audio processing, and are an essential component in electronic systems. The working principle of a frequency divider is to divide the input signal according to a predetermined frequency range through a combination of filters such as a high-pass filter (HPF or Low Cut), a band-pass filter (BPF), and a low-pass filter (LPF or High Cut). Depending on the application scenario and design requirements, frequency dividers can be divided into various types, including passive frequency dividers and active frequency dividers. Passive frequency dividers are usually located after the power amplifier and are used to separate the audio signal after the power amplifier output, commonly found inside speakers. Active frequency dividers are located between the signal source and the amplifier and are used to separate the audio signal before the amplifier amplification, usually as an independent electronic device. In an audio system, the role of a frequency divider is particularly important. It separates sound signals in different frequency bands, and then amplifies them separately and sends them to the corresponding speaker units. For example, high-frequency, mid-frequency, and low-frequency signals are respectively sent to the high-frequency speaker, mid-frequency speaker, and low-frequency speaker. The design and component selection of a frequency divider have a significant impact on the sound quality. Therefore, choosing a suitable frequency divider can significantly improve the performance of the audio system.

[0003] The frequency divider design of the prior art is very complex and is modified based on the traditional counting frequency divider. Essentially, it has no difference from the traditional frequency divider, except that it adds an auxiliary clock phase selection circuit. Moreover, such a circuit often has a base frequency division and cannot meet the situation of a smaller division ratio, resulting in a significant increase in power consumption and area. Summary of the Invention

[0004] The purpose of the present invention is to provide a programmable frequency divider circuit that supports an odd-frequency division duty cycle of 50%. This circuit is different from the traditional frequency division structure, the frequency division method of inserting delay, and any expansion based on this structure, such as different n in a multi-mode frequency divider supporting different ranges of frequency division.

[0005] A programmable frequency divider circuit that supports an odd-frequency division duty cycle of 50% includes: a multi-mode frequency division module, a clock selection module, and an odd-frequency division duty cycle adjustment module; The input end of the multi-mode frequency division module is connected to the clock input, and the output ends are respectively connected to the odd-frequency division duty cycle adjustment module and the clock selection module; The input ends of the odd-frequency division duty cycle adjustment module are respectively connected to the clock input and the multi-mode frequency division module, and the output end is connected to the clock selection module; The clock selection module outputs the divided clock signal.

[0006] Preferably, it further includes: an encoding module; The output end of the encoding module is connected to the multi-mode frequency division module and the clock selection module, and is used for converting the format of the input signal.

[0007] Preferably, the multi-mode frequency division module includes: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a first OR gate, a first data selector, and a first AND gate; The CLK end of the first flip-flop is connected to the clock input, the Q end is connected to the first OR gate, the RST end is connected to the reset signal, and the D end is connected to the first AND gate; The D end of the second flip-flop is connected to the output end of the first AND gate, the inverted Q end is connected to the D end of the third flip-flop, and the Q end is connected to the input end of the first OR gate; The CLK end of the third flip-flop is connected to the clock input, the Q end is connected to the D end of the fourth flip-flop, and the SETN end is connected to the set signal; The Q end of the fourth flip-flop is connected to the data selector, the CLK end is connected to the clock input, and the SETN end is connected to the set signal; The output end of the first OR gate is connected to the input end of the first AND gate; The input ends of the first data selector are respectively connected to the encoding module and the D end of the first flip-flop, and the output end is connected to the D end of the third flip-flop, the Q end of the third flip-flop, and the Q end of the fourth flip-flop.

[0008] Preferably, the multi-mode frequency division module further includes: a plurality of n-th flip-flops; A plurality of n-th flip-flops are connected in series in sequence at the Q end of the fourth flip-flop.

[0009] Preferably, the odd-frequency division duty cycle adjustment module includes: a fifth flip-flop, a sixth flip-flop, a first NOT gate, and a second OR gate; The D end of the fifth flip-flop is connected to the Q end of the second flip-flop, the Q end is connected to the D end of the sixth flip-flop and the input end of the second OR gate, the CLK end is connected to the clock input, and the RST end is connected to the reset signal; The D terminal of the sixth flip-flop is connected to the input terminal of the second OR gate, the Q terminal is connected to the input terminal of the second OR gate, and the CLK terminal is connected to the clock input passing through the first NOT gate; The output terminal of the second OR gate is connected to the clock selection module.

[0010] Preferably, it further includes: a second data selector; The input terminals of the data selector are respectively connected to the output of the encoding module, the clock input, the output of the multi-mode frequency division module, and the output of the odd-frequency division duty cycle module, and an output frequency division signal is output.

[0011] A control method for a programmable frequency divider circuit supporting a 50% odd-frequency division duty cycle, which is applied to a programmable frequency divider circuit supporting a 50% odd-frequency division duty cycle, includes: Obtain the signal to be frequency-divided; Control the circuit parameters according to the frequency division requirement for frequency division.

[0012] Preferably, the controlling the circuit parameters according to the frequency division requirement for frequency division includes: If even frequency division is to be performed, adjust the mode signal of the first OR gate to 1; According to the specific frequency division number through sel <m:0>Select the feedback clock; When selecting the clkn output by the nth flip-flop in the multi-mode frequency division module as the feedback clock, a 2n / 2n+1 frequency division is achieved.

[0013] Preferably, the frequency division by controlling circuit parameters according to the frequency division requirement includes: If odd frequency division is to be performed, the mode signal of the first OR gate is adjusted to 0; The odd frequency division duty cycle adjustment module adjusts the signal according to the output in the multi-mode frequency division module.

[0014] An electronic device includes: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for controlling a programmable frequency divider circuit with a 50% duty cycle for odd frequency division.

[0015] The beneficial effects of the present invention are as follows: Compared with the prior art, the structure of the present invention is completely different. The structure adopted by the prior art is still the traditional counting method, and adding the control of switching the clock will result in a reduction in the highest frequency that the entire circuit can achieve, an increase in area and power consumption, and the traditional frequency division method often has a relatively large base frequency division and cannot meet a small frequency division number; the present patent is implemented by inserting a delay, has a smaller area and smaller power consumption, and supports frequency division of 2 and above, making up for the shortcoming that the traditional frequency divider cannot support a 50% duty cycle for a small frequency division number. Description of the Drawings

[0016] The drawings here are incorporated into the specification and constitute a part of this specification, indicating the embodiments that conform to the present invention, and are used together with the specification to explain the principles of the present invention.

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is the overall architecture diagram of a programmable frequency divider circuit with a 50% duty cycle for odd frequency division according to the present invention; Figure 2 It is the structural schematic diagram of a programmable frequency divider circuit with a 50% duty cycle for odd frequency division according to the present invention; Figure 3 It is the structural schematic diagram of the multi-mode frequency division module according to the present invention; Figure 4 Schematic diagram of the odd-frequency division duty cycle adjustment module of the present invention; Figure 5 Schematic diagram of the hardware structure of an electronic device according to the present invention. Specific embodiments

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0021] In addition, the descriptions involving "first", "second", etc. in the present invention are only for descriptive purposes, and cannot be understood as indicating or implying their relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0022] The design of the frequency divider in the prior art is very complex, and it is modified on the basis of the traditional counting frequency divider. Essentially, it has no difference from the traditional frequency divider, except that an auxiliary clock phase selection circuit is added. Moreover, such a circuit often has a base frequency division and cannot meet the case of a small frequency division number, resulting in a large increase in power consumption and area.

[0023] Compared with the prior art, the structure of the present invention is completely different. The structure adopted in the prior art is still the traditional counting method, and the control of switching the clock is added externally, which will lead to a decrease in the highest frequency that the entire circuit can achieve, an increase in area and power consumption, and the traditional frequency division method often has a large base frequency division and cannot meet a small frequency division number; this patent is implemented by inserting a delay, with a smaller area and smaller power consumption, and supports frequency division of 2 and above, making up for the shortcoming that the traditional frequency divider cannot support a 50% duty cycle with a small frequency division number.

[0024] Embodiment 1 A programmable frequency divider circuit that supports a 50% duty cycle for odd frequency division, refer to Figure 1 and Figure 2 , including: a multi-mode frequency division module, a clock selection module, and an odd frequency division duty cycle adjustment module; The input end of the multi-mode frequency division module is connected to the clock input, and the output ends are respectively connected to the odd frequency division duty cycle adjustment module and the clock selection module; ‌The multi-mode frequency divider module is a circuit device that can divide a high-frequency signal into multiple signals with different frequencies. It realizes the function of frequency division by performing different filtering and mixing processes on the input signal. The multi-mode frequency divider mainly consists of multiple functional circuit modules such as an oscillator, a frequency synthesizer, a filter, and a mixer. The input signal is sent to the frequency synthesizer module and then processed through modules such as filters and mixers, and finally outputs multiple signals with different frequencies‌.

[0025] The input ends of the odd frequency division duty cycle adjustment module are respectively connected to the clock input and the multi-mode frequency division module, and the output end is connected to the clock selection module; The clock selection module outputs the divided clock signal.

[0026] ‌The clock selection module‌ is an electronic device whose main function is to provide a stable time reference signal for the system and can select different clock sources according to needs. This module usually contains one or more clock sources and determines which clock source to use through internal clock selection logic. The clock selection module has a wide range of applications in various electronic systems, especially in occasions that require high-precision time synchronization, such as communication systems, computer systems, and industrial control systems. The clock selection module consists of the following parts: Clock source‌: One or more external or internal clock sources that provide different frequencies and precisions. Clock selection logic‌: Responsible for selecting the appropriate clock source according to system requirements. Output buffer‌: Buffers and distributes the selected clock signal to ensure stable output. The clock module‌ is a more complex component that usually includes a crystal oscillator and other circuits for generating and managing clock signals. It not only generates a reference clock signal but may also include a clock distribution network and clock synthesis functions, and can generate different clock frequencies according to needs.

[0027] This patent is different from the traditional counting frequency division method. It uses the method of inserting delay to achieve a 50% duty cycle for any frequency division ratio.

[0028] Preferably, it further includes: an encoding module; The output end of the encoding module is connected to the multi-mode frequency division module and the clock selection module, and is used to convert the format of the input signal.

[0029] The encoding module can compress data, reducing its size, which facilitates storage and transmission. By removing redundant information from the data, the encoding module can effectively reduce the storage space and transmission bandwidth occupied by the data. The encoding module can convert analog signals into digital signals or digital signals into analog signals. This conversion enables different types of data to be transmitted and processed between various systems or devices. The encoding module can convert data signals from one format to another to adapt to different systems or devices. This conversion ensures data compatibility and interoperability. In addition, during the encoding process, error detection and correction mechanisms can be added to improve the reliability of data transmission. By embedding redundant information in the data, the encoding module can detect and correct errors during data transmission, reducing data loss.

[0030] Preferably, referring to Figure 3 , the multi-mode frequency division module includes: a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a first OR gate, a first data selector, and a first AND gate; The CLK terminal of the first flip-flop is connected to the clock input, the Q terminal is connected to the first OR gate, the RST terminal is connected to the reset signal, and the D terminal is connected to the first AND gate; The D terminal of the second flip-flop is connected to the output terminal of the first AND gate, the inverted Q terminal is connected to the D terminal of the third flip-flop, and the Q terminal is connected to the input terminal of the first OR gate; The CLK terminal of the third flip-flop is connected to the clock input, the Q terminal is connected to the D terminal of the fourth flip-flop, and the SETN terminal is connected to the set signal; The Q terminal of the fourth flip-flop is connected to the data selector, the CLK terminal is connected to the clock input, and the SETN terminal is connected to the set signal; The output terminal of the first OR gate is connected to the input terminal of the first AND gate; The input terminals of the first data selector are respectively connected to the encoding module and the D terminal of the first flip-flop, and the output terminal is connected to the D terminal of the third flip-flop, the Q terminal of the third flip-flop, and the Q terminal of the fourth flip-flop.

[0031] In Figure 3 , the same names indicate connected lines. In clkn, n represents any positive integer and can be arbitrarily extended according to the design requirements. n is mainly limited by the process delay. This module can achieve any frequency division number from 2 to 2*n + 1.

[0032] When the mode signal is 1, even frequency division is achieved. When the mode is 0, odd frequency division is achieved. The even frequency division has a 50% duty cycle. In one cycle of the odd frequency division, the time that is high is shorter than the time that is low by one input clock cycle.

[0033] Different frequency division numbers are selected through sel <m:0>Select the feedback clock. For example, when clk1_n output by dff1 is selected as the feedback clock, 2 / 3 (1*2 / 1*2+1) division is achieved. Similarly, when clkn output by dffn is selected as the feedback clock, 2n / 2n+1 division is achieved. The parity control is the mode signal.

[0034] like Figure 3 As shown in , the output is clk_div. When divided by 2, the duty cycle is 50%. When divided by 3, the time when it is 1 is one input clock cycle shorter than the time when it is 0. The same rule applies to other odd-number divisions.

[0035] Preferably, in an embodiment of the present invention, the trigger is a D flip-flop, because the D flip-flop is a device with a memory function and has two stable states, namely 0 and 1. It can flip from one stable state to another stable state under the action of a certain external signal. The next state of the D flip-flop depends on the state of the D terminal before the trigger, that is, the next state = D, so it has two functions of setting 0 and setting 1. The D flip-flop is widely used in digital systems and computers, and can be used as a digital signal register, shift register, frequency division and waveform generator, etc. In addition, the D flip-flop can also be used to provide a state where peripheral data is ready. The basic working principle of the D flip-flop is that when the input end of the trigger receives a specific signal (usually a clock signal), the output state of the trigger changes and remains unchanged before the next trigger.

[0036] Preferably, the multi-mode frequency division module further comprises: a plurality of n-th triggers; A plurality of n-th flip-flops are serially connected at the Q end of the fourth flip-flop.

[0037] In the embodiment of the present invention, multiple n-th flip-flops are used to implement any frequency division number, and the number n is selected according to the design requirements.

[0038] A trigger is a special type of stored procedure that is triggered by an event rather than being called by a program or started manually. ‌ When a specific operation occurs in the database, such as inserting (INSERT), updating (UPDATE) or deleting (DELETE) data, the trigger automatically executes the predefined SQL statement. Triggers are mainly used to ensure the validity and integrity of data and implement complex business rules and data integrity constraints. ‌

[0039] Triggers can enforce specific data integrity constraints and prevent operations that violate the constraints. For example, when attempting to insert a piece of data that violates a certain constraint condition, the trigger can block the operation. Triggers can automatically execute complex business logic. For example, when inserting data into a table, the trigger can automatically calculate and update relevant calculated fields. Triggers can be used to record or monitor data changes. For example, when the data in a certain table is modified, the trigger can automatically record the data, time, and user information before and after the modification.

[0040] Preferably, referring to Figure 4 , the odd-frequency division duty cycle adjustment module includes: a fifth trigger, a sixth trigger, a first NOT gate, and a second OR gate; The D terminal of the fifth trigger is connected to the Q terminal of the second trigger, the Q terminal is connected to the D terminal of the sixth trigger and the input terminal of the second OR gate, the CLK terminal is connected to the clock input, and the RST terminal is connected to the reset signal; The D terminal of the sixth trigger is connected to the input terminal of the second OR gate, the Q terminal is connected to the input terminal of the second OR gate, and the CLK terminal is connected to the clock input passing through the first NOT gate; The output terminal of the second OR gate is connected to the clock selection module.

[0041] Figure 4 is an odd-frequency division duty cycle adjustment circuit, clk_div is the output of a multi-mode frequency divider, and when it is an odd-frequency division, the duty cycle is adjusted by the circuit shown in the figure.

[0042] ‌The duty ratio is the proportion of time occupied by a certain specific state (such as high level or low level) in a periodic signal. The calculation formula for the duty ratio is: Duty Ratio = (Duration of a certain state / Time of the entire period) × 100%.‌

[0043] ‌The odd-frequency division duty cycle adjustment module‌ is a circuit module used to adjust the duty cycle of the output signal of an odd-frequency divider. In digital circuit design, a frequency divider reduces the frequency of the input signal, and duty cycle adjustment is achieved by controlling the time ratio of the high and low levels of the output signal. The odd-frequency division duty cycle adjustment module is usually implemented by the following methods: OR operation‌: Using two frequency division signals triggered by the rising edge and falling edge respectively for OR operation to obtain an output signal with a 50% duty cycle‌.‌ AND operation‌: By performing an AND operation on the two frequency division signals, an output signal with a 50% duty cycle can be obtained‌.‌ XOR operation‌: By performing an XOR operation on the two frequency division signals, an output with a 50% duty cycle can also be achieved.

[0044] The implementation of an odd-frequency divider can be achieved through the following methods: Counter method of the prior art: Use a counter to count the input clock, and when the value of the counter reaches a specific value, the output signal is inverted. For example, a three-frequency division can be achieved by inverting the output when the counter counts to 1 and inverting again when it counts to 2. Register method of the present invention: Set two registers triggered by the rising edge and falling edge respectively, and combine the outputs of the two registers through an OR operation to obtain an output signal with a duty cycle of 50%.

[0045] Preferably, it further includes: a second data selector; The input terminals of the data selector are respectively connected to the output of the encoding module, the clock input, the output of the multi-mode frequency division module, and the output of the odd-frequency division duty cycle module, and the divided frequency signal is output.

[0046] A data selector (Multiplexer, MUX) is a multi-input single-output digital circuit, and its function is to select one output from multiple input signals according to the selection signal. The data selector usually has one or more selection signals, which are used to determine which input signal is selected and transmitted to the output terminal. The working principle of the data selector is based on logic gate circuits. Common types include 1-of-2, 1-of-4, 1-of-8, etc., and more input types can be selected according to needs. For example, a 1-of-2 data selector has two input signals A and B, and a selection signal S. When S = 0, the output is A; when S = 1, the output is B. Data selectors are widely used in fields such as multi-channel data selection, address decoding, and data distribution, and are key components for realizing multi-channel data transmission and selection.

[0047] Embodiment 2 A control method for a programmable frequency divider circuit supporting an odd-frequency division duty cycle of 50% is applied to a programmable frequency divider circuit supporting an odd-frequency division duty cycle of 50%, and includes: S100, obtain the signal to be frequency-divided; Signal frequency division refers to the technology of dividing a signal into multiple cycles, so that the frequency of the output signal is an integer fraction of the frequency of the input signal. The frequency divider is the key component to achieve this function, and usually uses technologies such as counters / timers or PLLs to achieve it.

[0048] S200, control the circuit parameters according to the frequency division requirements for frequency division.

[0049] Frequency division is a technique that divides a signal into multiple cycles, reducing the frequency of the input signal to the desired frequency through a frequency divider. The frequency divider can make the number of cycles of the output signal an integer multiple of the number of cycles of the input signal, thereby reducing the frequency while maintaining the signal form unchanged. From the perspective of frequency transformation, frequency division means reducing the signal frequency to 1 / N of the original, for example, a 33 MHz signal becomes 16.5 MHz after being divided by 2.

[0050] Preferably, in S200, controlling the circuit parameters for frequency division according to the frequency division requirements includes: If even frequency division is to be performed, adjust the mode signal of the first OR gate to 1; According to the specific frequency division number through sel <m:0>Select the feedback clock; When selecting the output clkn of the nth flip-flop in the multi-mode frequency division module as the feedback clock, 2n / 2n+1 frequency division is achieved.

[0051] ‌Even frequency division‌ means dividing the input clock signal into frequencies that are even multiples of it. Specifically, an even frequency divider can reduce the frequency of the input clock signal to half, one-fourth, one-eighth, etc. of its original frequency. Even frequency dividers are usually implemented using counters, which count on the rising or falling edge of each clock cycle. When the value of the counter reaches half of the division factor or is equal to the division factor, the output signal flips once.

[0052] In the embodiments of the present invention, even frequency division can be achieved by cascading multiple D flip-flops. For example, cascading two 2-frequency dividers can form a 4-frequency divider, and so on.

[0053] Preferably, S200, controlling the circuit parameters for frequency division according to the frequency division requirements includes: If odd frequency division is to be performed, adjust the mode signal of the first OR gate to 0; The odd frequency division duty cycle adjustment module adjusts the output adjustment signal in the multi-mode frequency division module.

[0054] As Figure 4 shown, if odd frequency division is to be performed, perform a logical OR operation on ClK1_d1 and ClK1_d2 in the figure to obtain CLK_fine, and CLK_fine represents a duty cycle of fifty percent.

[0055] ‌Odd frequency division‌ means dividing the input clock signal into frequencies that are odd multiples of the output. The main function of an odd frequency divider is to divide the period of the input clock signal into an odd number of parts and flip the level of the output signal at the end of each part. Odd frequency dividers have a wide range of applications in digital circuit design, especially when a clock signal with a specific duty cycle is required. For example, in communication systems, radar systems, and digital signal processing, odd frequency dividers can be used to generate clock signals with specific frequencies and duty cycles to meet the requirements of the system.

[0056] Embodiment 3 An electronic device includes: a chip, a processor, and a memory. The memory is used to store computer program code, and the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a method for controlling a programmable frequency divider circuit with an odd frequency division duty cycle of fifty percent.

[0057] Reference Figure 5 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled through a connector, which includes various interfaces, transmission lines, buses, etc., and the embodiments of the present invention do not limit this. It should be understood that in various embodiments of the present invention, coupling means being interconnected in a specific manner, including being directly connected or indirectly connected through other devices. For example, they can be connected through various interfaces, transmission lines, buses, etc.

[0058] The processor 21 can be one or more graphics processing units (GPUs). When the processor 21 is a single GPU, the GPU can be a single-core GPU or a multi-core GPU. Optionally, the processor 21 can be a processor group composed of multiple GPUs, and multiple processors are coupled to each other through one or more buses. Optionally, the processor can also be other types of processors, etc., and the embodiments of the present invention do not limit this.

[0059] The memory 22 can be used to store computer program instructions and various computer program codes including the program codes for implementing the solution of the present invention. Optionally, the memory includes but is not limited to a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a compact disc read-only memory (CD-ROM), and this memory is used for relevant instructions and data.

[0060] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 can be independent devices or an integrated device.

[0061] Compared with the prior art, the structure of the present invention is completely different. The structure adopted by the prior art is still the traditional counting method, and adding the control of switching clocks will result in a decrease in the highest frequency that the entire circuit can achieve, an increase in both area and power consumption, and the traditional frequency division method often has a relatively large base frequency division and cannot meet a smaller frequency division ratio. This patent is implemented by inserting delays, has a smaller area and lower power consumption, and supports frequency division of 2 and above, making up for the shortcoming that the traditional frequency divider cannot support a 50% duty cycle with a smaller frequency division ratio.

[0062] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather will be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A programmable frequency divider circuit supporting odd frequency division with a duty cycle of 50%, characterized in that: include: Multi-mode frequency division module, clock selection module and odd-number frequency division duty cycle adjustment module; The input end of the multi-mode frequency division module is connected to the clock input, and the output end is connected to the odd-number frequency division duty cycle adjustment module and the clock selection module respectively; The input end of the odd-number frequency division duty cycle adjustment module is respectively connected to the clock input and the multi-mode frequency division module, and the output end is connected to the clock selection module; The clock selection module outputs a divided clock signal; The odd-number frequency-division duty cycle adjustment module includes: a fifth trigger, a sixth trigger, a first NOT gate and a second OR gate; The D terminal of the fifth flip-flop is connected to the Q terminal of the second flip-flop, the Q terminal is connected to the D terminal of the sixth flip-flop and the input terminal of the second OR gate, the CLK terminal is connected to the clock input, and the RST terminal is connected to the reset signal; The D terminal of the sixth flip-flop is connected to the input terminal of the second OR gate, the Q terminal is connected to the input terminal of the second OR gate, and the CLK terminal is connected to the clock input through the first NOT gate; The output end of the second OR gate is connected to the clock selection module.

2. A programmable frequency divider circuit supporting odd-number frequency division with a fifty percent duty cycle according to claim 1, characterized in that: Also includes: Coding module; The output end of the encoding module is connected to the multi-mode frequency division module and the clock selection module, and is used to convert the format of the input signal.

3. A programmable frequency divider circuit supporting odd-number frequency division with a fifty percent duty cycle according to claim 2, characterized in that: The multi-mode frequency division module includes: a first trigger, a second trigger, a third trigger, a fourth trigger, a first OR gate, a first data selector and a first AND gate; The CLK terminal of the first trigger is connected to the clock input, the Q terminal is connected to the first OR gate, the RST terminal is connected to the reset signal, and the D terminal is connected to the first AND gate; The D terminal of the second flip-flop is connected to the output terminal of the first AND gate, the inverted Q terminal is connected to the D terminal of the third flip-flop, and the Q terminal is connected to the input terminal of the first OR gate; The CLK terminal of the third flip-flop is connected to the clock input, the Q terminal is connected to the D terminal of the fourth flip-flop, and the SETN terminal is connected to the set signal; The Q terminal of the fourth flip-flop is connected to the data selector, the CLK terminal is connected to the clock input, and the SETN terminal is connected to the set signal; The output terminal of the first OR gate is connected to the input terminal of the first AND gate; The input end of the first data selector is connected to the encoding module and the D end of the first trigger respectively, and the output end is connected to the D end of the third trigger, the Q end of the third trigger and the Q end of the fourth trigger.

4. A programmable frequency divider circuit supporting odd-number frequency division with a fifty percent duty cycle according to claim 3, characterized in that: The multi-mode frequency division module further includes: a plurality of n-th triggers; A plurality of n-th flip-flops are serially connected at the Q end of the fourth flip-flop.

5. A programmable frequency divider circuit supporting odd-number frequency division with a fifty percent duty cycle according to claim 2, characterized in that: Also includes: Second data selector; The input end of the data selector is respectively connected to the output of the encoding module, the clock input, the output of the multi-mode frequency division module and the output of the odd-number frequency division duty cycle module, and outputs a frequency division signal.

6. A control method for a programmable frequency divider circuit supporting an odd-number frequency division with a fifty percent duty cycle, applied to a programmable frequency divider circuit supporting an odd-number frequency division with a fifty percent duty cycle as claimed in claims 1 to 5, characterized in that: include: Obtain the signal to be divided; The frequency division is performed by controlling the circuit parameters according to the frequency division requirements.

7. The method for controlling a programmable frequency divider circuit supporting an odd-number frequency division duty cycle of 50% according to claim 6, characterized in that: The frequency division is performed by controlling the circuit parameters according to the frequency division requirement, comprising: If even frequency division is required, adjust the mode signal of the first OR gate to 1; According to the specific frequency division number through sel <m:0> Select the feedback clock; When clkn output by the nth trigger in the multi-mode frequency division module is selected as the feedback clock, 2n / 2n+1 frequency division is achieved.

8. The method for controlling a programmable frequency divider circuit supporting an odd-number frequency division duty cycle of 50% according to claim 6, characterized in that: The frequency division is performed by controlling the circuit parameters according to the frequency division requirement, comprising: If odd frequency division is required, adjust the mode signal of the first OR gate to 0; The odd-number frequency division duty cycle adjustment module adjusts the signal according to the output of the multi-mode frequency division module.

9. An electronic device, characterized in that: include: A chip, a processor and a memory, wherein the memory is used to store computer program code, wherein the computer program code includes computer instructions. When the chip executes the computer instructions, the electronic device executes a programmable frequency divider circuit control method supporting an odd-number division duty cycle of fifty percent as described in any one of claims 6 to 8.

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