Clock synchronization method, node device, chip and computer storage medium

Abstract

The embodiment of the invention provides a clock synchronization method, a node device, a chip and a computer storage medium. The method comprises the following steps: identifying a first target transmission interface in two transmission interfaces, wherein the first target transmission interface is an interface which establishes a link with an upstream node in the two transmission interfaces; and controlling the two transmission interfaces to determine an interface clock based on the recovered network clock, so that the interface clocks of the two transmission interfaces are aligned with the recovered network clock, and the recovered network clock is a clock determined by the first target transmission interface based on the data signal received from the upstream node. Based on the above scheme, because the two transmission interfaces can be randomly connected with the upstream node, the fault tolerance of the network is increased, and the assembly requirement and the test cost are simplified at the same time.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of data communication technologies, and in particular, to a clock synchronization method, a node device, a chip, and a computer storage medium. Background Art

[0002] In a data communication network, the normal operation of many services requires network clock frequency synchronization. In a traditional data communication network, in order to simplify network design, there are strict requirements for the connections of each node in the network. It is usually stipulated that a certain transmission interface of each node in the network must be connected to the upstream node, and the recovered network clock is determined based on the data signal received from the upstream node, while another transmission interface of each node must determine the interface clock based on the recovered network clock. Such a design for each node causes that there should be no assembly error during the assembly of each node, otherwise it may lead to the inability to transmit the clock frequency in the network, and even cause the malfunction of each node. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a clock synchronization method, a node device, a chip, and a computer storage medium to at least partially solve the above technical problems.

[0004] According to a first aspect of the embodiments of the present application, a clock synchronization method is provided, which is applied to any node in a networking system. The node includes two transmission interfaces, and the method includes:

[0005] Identifying a first target transmission interface among the two transmission interfaces, where the first target transmission interface is the interface that establishes a link with the upstream node among the two transmission interfaces;

[0006] Controlling the two transmission interfaces to determine the interface clock based on the recovered network clock, so that the interface clocks of the two transmission interfaces are aligned with the recovered network clock, and the recovered network clock is the clock determined by the first target transmission interface based on the data signal received from the upstream node.

[0007] According to a second aspect of the embodiments of the present application, a node device is provided, including: two transmission interfaces and a control module connected to the two transmission interfaces;

[0008] The two transmission interfaces are used to send data signals to other node devices or receive data signals from other node devices;

[0009] The control module is used for:

[0010] Identifying a first target transmission interface among the two transmission interfaces, where the first target transmission interface is the interface that establishes a link with the upstream node device among the two transmission interfaces;

[0011] Control the two transmission interfaces to determine interface clocks based on the recovered network clock, so that the interface clocks of the two transmission interfaces are aligned with the recovered network clock, where the recovered network clock is the clock determined by the first target transmission interface based on the data signal received from the upstream node device.

[0012] According to the third aspect of the embodiments of the present application, a chip is provided, including: a processing unit and a storage unit, which communicate with each other between the processing unit and the storage unit;

[0013] The storage unit is used to store at least one executable instruction, and the executable instruction causes the processing unit to perform the operations corresponding to the method provided in the first aspect.

[0014] According to the fourth aspect of the embodiments of the present application, a computer storage medium is provided, on which a computer program is stored, and when the program is executed by a processor, it implements the method described in any item of the first aspect.

[0015] According to the clock synchronization solution provided by the embodiments of the present application, no matter which of the two transmission interfaces is connected to the upstream node during assembly, the transmission interface can be identified as the first target transmission interface in the two transmission interfaces, and the recovered network clock is determined through the data signal received from the upstream node by the first target transmission interface. Furthermore, by controlling the two transmission interfaces to determine the interface clocks based on the recovered network clock, the interface clocks of the two transmission interfaces can be aligned with the recovered network clock, ensuring that the network clock can continue to be transmitted to the downstream node. In the embodiments of the present application, since the two transmission interfaces can be randomly connected to the upstream node, the fault tolerance of the network is increased, and at the same time, the assembly requirements and test costs are simplified. Description of the Drawings

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic diagram of a networking system according to an embodiment of the present application;

[0018] Figure 2 It is a schematic diagram of a networking system according to another embodiment of the present application;

[0019] Figure 3 It is a schematic diagram of the structure of a node device according to an embodiment of the present application;

[0020] Figure 4It is a schematic structural diagram of a clock management module provided by an embodiment of the present application;

[0021] Figure 5 It is a schematic flowchart of a clock synchronization method provided by an embodiment of the present application;

[0022] Figure 6 It is a schematic block diagram of a chip provided by an embodiment of the present application. Specific embodiments

[0023] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art shall fall within the protection scope of the embodiments of the present application.

[0024] The following further illustrates the specific implementation of the embodiments of the present application with reference to the accompanying drawings of the embodiments of the present application.

[0025] Scenarios to which this application is applied

[0026] The embodiments of the present application propose a clock synchronization method. This clock synchronization method can be applied to any sub-node in a networking system with a ring topology, a daisy chain topology, or a linear topology. For example, the clock synchronization method of the embodiments of the present application can be used for any sub-node in a networking system in a vehicle-mounted scenario. In addition, the clock synchronization method of the embodiments of the present application is not limited to being applied to a networking system in a vehicle-mounted scenario, and can also be applied to other scenarios.

[0027] Before elaborating on the data transmission solution provided by the present application, the networking system applicable to the data transmission solution provided by the present application and related terms will be described.

[0028] The networking system in the embodiments of the present application includes multiple nodes connected together through a suitable physical transmission medium. Signals are sent between the multiple nodes through the physical transmission medium. The physical transmission medium can be a shielded twisted pair, an unshielded twisted pair, a coaxial cable, etc. A node can be any device, apparatus, module, or chip that implements the solution of the present application. The multiple nodes of the networking system can be divided into a master node and sub-nodes.

[0029] The master node may include or may be one or more of various processors such as a Digital Signal Processor (DSP), a Microcontroller Unit (MCU), a Central Processing Unit (CPU), etc.

[0030] The slave node may be a functional node connected to a peripheral device, also known as a functional node or a slave node. By connecting the slave node to the peripheral device, different functional applications can be realized. For example, the types of peripheral devices may include at least one of the following types: Local Interconnect Network (LIN) bus peripheral devices, Pulse Width Modulation (PWM) drive devices, Inter-Integrated Circuit (I2C) peripheral devices, Serial Peripheral Interface (SPI) bus peripheral devices, Quad Serial Peripheral Interface (QSPI) bus peripheral devices, General-purpose input / output (GPIO) peripheral devices, Ethernet peripheral devices, Controller Area Network (CAN) bus peripheral devices, Media Independent Interface (MII) and various extended and derivative versions of the Media Independent Interface peripheral devices, Universal Asynchronous Receiver / Transmitter (UART) peripheral devices, Single Edge Nibble Transmission (SENT) bus peripheral devices, peripheral devices of the Peripheral Sensor Interface 5 (PSI5) protocol, Inter-IC Sound (I2S) peripheral devices, Time-Division Multiplexing (TDM) peripheral devices, Analog Microphone (AMIC) peripheral devices, Digital Microphone (DMIC) peripheral devices, Analog-to-digital converter (ADC), etc.

[0031] It should be understood that features such as the master node and slave nodes mentioned in the embodiments of the present application can be logical concepts or entity concepts. Further, multiple features can be multiple entity devices respectively, or multiple features can be aggregated into one entity device. The present application does not make specific limitations on this.

[0032] In a networking system, to ensure the normal operation of services, network clock synchronization is usually required. From the perspective of clock synchronization, the master node is the clock synchronization source. Synchronization (e.g., frequency synchronization and / or phase synchronization) passes through each node in the networking system hop by hop.

[0033] Figure 1 is a schematic diagram of a networking system according to an embodiment of the present application. As Figure 1 shown, the networking system is a networking system with a daisy-chain topology. In Figure 1 the shown networking system, the master node, slave node 1, slave node 2, slave node 3, slave node 4, slave node 5, slave node 6, slave node 7, and slave node 8 are connected in sequence to form a daisy-chain topology. Each node (including the master node and slave nodes) includes two transmission interfaces. The master node is the clock synchronization source and is used to generate the network clock. Each of the slave nodes from slave node 1 to slave node 8 is configured to recover the network clock from the received signal, lock the interface clock to the recovered network clock to generate a synchronized interface clock, and perform various communications using the generated interface clock. Synchronization (e.g., frequency synchronization and / or phase synchronization) passes through each node in the networking system hop by hop. For example, slave node 1 recovers the network clock from the data signal received from the master node, and then slave node 1 uses the interface clock synchronized with this network clock to send a signal to slave node 2. Slave node 2 recovers the network clock from the data signal received from slave node 1 and sends a signal to the next-hop node (i.e., slave node 3). It is transmitted hop by hop in this way until slave node 8 recovers the network clock, locks the interface clock to the recovered network clock to generate a synchronized interface clock, and performs various communications using the generated interface clock.

[0034] In Figure 1 the shown networking system, the upstream node of each slave node refers to the previous node that transmits the data signal before this slave node, and the downstream node of each slave node refers to the next node that transmits the data signal after this slave node. In Figure 1 the networking system of Figure 1 as described above, slave node 8 is the last node and there is no downstream node. In addition, in

[0035] Figure 2 is a schematic diagram of a networking system according to another embodiment of the present application. As Figure 2As shown, the networking system has a ring topology. The networking system includes a master node, sub-node 1, sub-node 2, sub-node 3, sub-node 4, sub-node 5, sub-node 6, sub-node 7, and sub-node 8. The master node, sub-node 1, sub-node 2, sub-node 3, sub-node 4, sub-node 5, sub-node 6, sub-node 7, and sub-node 8 are connected in sequence, and sub-node 8 is connected to the master node to form a ring topology. Similarly, each of sub-nodes 1 to 8 is configured to recover the network clock from the received signal, lock the interface clock to the recovered network clock to generate a synchronized interface clock, and perform various communications using the generated interface clock. Synchronization (e.g., frequency synchronization and / or phase synchronization) passes through each node in the networking system hop by hop. Different from Figure 1 the embodiment shown, in Figure 2 the networking system shown, each node may have two upstream nodes. For example, for Figure 2 node 4 in, the two transmission interfaces of node 4 may respectively establish links with sub-node 3 and sub-node 5 successfully at the same time, and both sub-node 3 and sub-node 5 are upstream nodes of sub-node 4.

[0036] It should be understood that Figure 1 and Figure 2 only show examples of a networking system with a ring topology and a daisy-chain topology respectively. In practical applications, the number of sub-nodes in the networking system can be set according to actual needs.

[0037] Node device

[0038] Figure 3 is a schematic structural diagram of a node device provided according to an embodiment of the present application. As Figure 3 shown, node device 10 includes two transmission interfaces 102, 103 and a control module 101 connected to the two transmission interfaces 102, 103.

[0039] The two transmission interfaces 102, 103 are respectively used to send data signals to other node devices or receive data signals from other node devices. Other node devices include an upstream node device and a downstream node device connected to node device 10. The upstream node device refers to the previous hop node device that transmits data signals before the node device in the networking system, and the downstream sub-node refers to the next hop node device that transmits data signals after the node device in the networking system.

[0040] The control module 101 is configured to: identify a first target transmission interface among two transmission interfaces 102 and 103, where the first target transmission interface is the interface that establishes a link with the upstream node device among the two transmission interfaces 102 and 103; control the two transmission interfaces 102 and 103 to determine interface clocks based on the recovered network clock, so that the interface clocks of the two transmission interfaces are aligned with the recovered network clock. Wherein, the recovered network clock is the clock determined by the first target transmission interface based on the data signal received from the upstream node device.

[0041] In an application scenario of the present application, for example, in Figure 1 the networking system with a daisy-chain topology shown, at the same time, only one of the two transmission interfaces 102 and 103 can establish a link with the upstream node device. In this scenario, one of the two transmission interfaces 102 and 103 can be identified as the first target transmission interface by the control module 101. In another application scenario of the present application, for example, in Figure 2 the networking system with a ring topology shown, at the same time, the two transmission interfaces 102 and 103 may establish links with the corresponding upstream node devices simultaneously. In this scenario, both of the two transmission interfaces 102 and 103 may be identified as the first target transmission interface by the control module 101.

[0042] The transmission interface that establishes a link with the upstream node device can recover the network clock from the data signal received from the upstream node device. Regardless of which of the two transmission interfaces 102 and 103 is connected to the upstream node during assembly, the control module 101 can determine the first target transmission interface by identifying among the two transmission interfaces 102 and 103. After the control module 101 identifies the first target transmission interface, it can control the two transmission interfaces to use the network clock recovered by the first target transmission interface to determine the interface clocks, so that the interface clocks of the two transmission interfaces 102 and 103 are both aligned with the recovered network clock.

[0043] When one of the two transmission interfaces 102 and 103 of the node device is determined as the first target transmission interface (i.e., establishing a link with the upstream node device), the node device 10 can communicate with the upstream node device through the transmission interface that has established a link with the upstream node device, based on the interface clock aligned with the recovered network clock. In addition, the node device 10 can attempt to establish a link and communicate with the downstream node device through the other transmission interface among the two transmission interfaces 102 and 103, based on the interface clock aligned with the recovered network clock, so as to ensure that the network clock can continue to be transmitted to the downstream node device. When both of the two transmission interfaces 102 and 103 of the node device are determined as the first target transmission interfaces (i.e., both establishing links with the upstream node device), the two transmission interfaces 102 and 103 respectively recover the network clock based on the data signals received from the upstream node device. The control module 101 can control the two transmission interfaces 102 and 103 to lock the interface clock to the recovered network clock, so as to communicate with the upstream node device respectively based on the interface clock aligned with the recovered network clock.

[0044] In the embodiments of the present application, since the two transmission interfaces can be randomly connected to the upstream node device, compared with the traditional solution that requires a specified transmission interface to be connected to the upstream node, the transmission interfaces can be randomly plugged in, without the need to follow strict wiring requirements, increasing the fault tolerance of the network, and at the same time simplifying the assembly requirements and testing costs.

[0045] In an embodiment of the present application, as Figure 3 shown, the transmission interface 102 includes a clock data recovery (CDR) unit CDR_A, and the transmission interface 103 includes a clock data recovery (CDR) unit CDR_B.

[0046] The clock data recovery (CDR) unit CDR_A is configured to generate indication information when the transmission interface 102 establishes a link with the upstream node device, and send the indication information to the control module 101; the clock data recovery (CDR) unit CDR_B is configured to generate indication information when the transmission interface 103 establishes a link with the upstream node device, and send the indication information to the control module 101; the control module 101 is configured to determine the first target transmission interface based on the indication information received from the two transmission interfaces 102 and 103.

[0047] As Figure 3As shown, the clock recovery unit CDR_A of the transmission interface 102 is connected to the data receiving channel RC_A of the transmission interface 102. The clock recovery unit CDR_A of the transmission interface 102 can receive data signals from other node devices through the data receiving channel RC_A. When the transmission interface 102 establishes a link with the upstream node device, the clock recovery unit CDR_A of the transmission interface 102 can generate an indication signal and send the indication signal to the control module 101. When the transmission interface 102 does not establish a link with the upstream node device, the clock recovery unit CDR_A of the transmission interface 102 may not generate an indication signal to the control module 101. It should be understood that in other implementation manners, the clock recovery unit CDR_A of the transmission interface 102 may also send indication information to the control module 101 in other ways, as long as the control module 101 can determine whether the transmission interface 102 has established a link with the upstream node device based on the indication information.

[0048] Similarly, the clock recovery unit CDR_B of the transmission interface 103 is connected to the data receiving channel RC_B of the transmission interface 103. The clock recovery unit CDR_B of the transmission interface 103 can receive data signals from other node devices through the data receiving channel RC_B. When the transmission interface 103 establishes a link with the upstream node device, the clock recovery unit CDR_B of the transmission interface 103 can generate an indication signal and send the indication signal to the control module 101. When the transmission interface 103 does not establish a link with the upstream node device, the clock recovery unit CDR_B of the transmission interface 103 may not generate an indication signal to the control module 101. Similar to the clock recovery unit CDR_A of the transmission interface 102, the clock recovery unit CDR_B of the transmission interface 103 may also send indication information to the control module 101 in other ways, as long as the control module 101 can determine whether the transmission interface 103 has established a link with the upstream node device based on the indication information.

[0049] After the transmission interface 102 establishes a link with the upstream node device, the clock recovery unit CDR_A of the transmission interface 102 can also calculate the clock adjustment amount of the transmission interface 102 based on the data signals received from the upstream node device through the data receiving channel RC_A, so that the transmission interface 102 can recover the network clock. Similarly, after the transmission interface 103 establishes a link with the upstream node device, the clock recovery unit CDR_B of the transmission interface 103 can also calculate the clock adjustment amount of the transmission interface 103 based on the data signals received from the upstream node device through the data receiving channel RC_B, so that the transmission interface 103 can recover the network clock.

[0050] In a specific implementation manner of the present application, the control module 101 is configured to:

[0051] If indication information is received from one of the two transmission interfaces 102 and 103, the transmission interface that sends the indication information is determined as the first target transmission interface, and the other transmission interface is determined as the second target transmission interface; or,

[0052] If indication information is received from both of the two transmission interfaces 102 and 103 simultaneously, it is determined that both transmission interfaces are the first target transmission interfaces.

[0053] As Figure 3 shown, when one of the transmission interfaces 102 and 103 or both of the transmission interfaces 102 and 103 establish a link with the upstream node device, the clock recovery unit in the transmission interface that establishes the link with the upstream node device among the transmission interfaces 102 and 103 sends indication information to the control module 101, whereby the control module 101 can timely identify the first target transmission interface from the transmission interfaces 102 and 103 based on the indication information, so as to lock the interface clocks of the transmission interfaces 102 and 103 to the network clock recovered by the first target transmission interface.

[0054] In an embodiment of the present application, if one of the transmission interfaces 102 and 103 is determined as the first target transmission interface, the control module 101 is configured to: control the second target transmission interface to use the recovered network clock as a reference clock, so that the second target transmission interface determines the interface clock of the second target transmission interface based on the reference clock.

[0055] For example, the transmission interface 102 is determined as the first target transmission interface, and the transmission interface 103 is determined as the second target transmission interface. The transmission interface 102 recovers the network clock based on the data signal received from the upstream node device. The control module 101 can control the transmission interface 103 to use the recovered network clock as a reference clock, so that the transmission interface 103 determines the interface clock based on the reference clock, so that the interface clock of the transmission interface 103 is aligned with the recovered network clock, thereby ensuring that the network clock can continue to be transmitted to the downstream node device through the transmission interface 103.

[0056] In a feasible embodiment of the present application, as Figure 3 shown, the transmission interface 102 includes a reference clock selector REF_MUX_A, a phase-locked loop PLL_A, and a clock management module PLL_MUX_A. The transmission interface 103 includes a reference clock selector REF_MUX_B, a phase-locked loop PLL_B, and a clock management module PLL_MUX_B.

[0057] The reference clock selector REF_MUX_A is used for: when the transmission interface 102 is determined to be the first target transmission interface, gating the local clock as the reference clock of the phase-locked loop PLL_A; when the transmission interface 102 is determined to be the second target transmission interface, gating the recovered network clock provided by the transmission interface 103 as the reference clock of the phase-locked loop PLL_A. The phase-locked loop PLL_A is used for locking and frequency multiplying the reference clock of the transmission interface 102; the clock management module PLL_MUX_A is used for: when the transmission interface 102 is determined to be the first target transmission interface, generating a recovered network clock based on the clock adjustment amount and the clock output by the phase-locked loop PLL_A, and outputting the recovered network clock as the interface clock of the transmission interface 102; when the transmission interface 102 is determined to be the second target transmission interface, determining the interface clock of the transmission interface 102 based on the clock output by the phase-locked loop PLL_A. Similarly, the reference clock selector REF_MUX_B is used for: when the transmission interface 103 is determined to be the first target transmission interface, gating the local clock as the reference clock of the phase-locked loop PLL_B; when the transmission interface 103 is determined to be the second target transmission interface, gating the recovered network clock provided by the transmission interface 102 as the reference clock of the phase-locked loop PLL_B. The phase-locked loop PLL_B is used for locking and frequency multiplying the reference clock of the transmission interface 103; the clock management module PLL_MUX_B is used for: when the transmission interface 103 is determined to be the first target transmission interface, generating a recovered network clock based on the clock adjustment amount and the clock output by the phase-locked loop PLL_B, and outputting the recovered network clock as the interface clock of the transmission interface 103; when the transmission interface 103 is determined to be the second target transmission interface, determining the interface clock of the transmission interface 103 based on the clock output by the phase-locked loop PLL_B.

[0058] In the embodiments of the present application, the phase-locked loops PLL_A and PLL_B are also respectively used for dividing the reference clock frequency to provide the required homologous clocks for other components in the node device.

[0059] In a specific embodiment of the present application, for each transmission interface, the first input end of the clock management module is connected to the corresponding phase-locked loop, the second input end of the clock management module is connected to the corresponding clock recovery unit, the first output end of the clock management module is connected to the data sending channel of the corresponding transmission interface, and the second output end of the clock management module is connected to the reference clock selector of the other transmission interface among the two transmission interfaces.

[0060] The clock recovery unit is further used for: calculating the clock adjustment amount based on the data signal received from the upstream node when the corresponding transmission interface establishes a link with the upstream node device;

[0061] The clock management module is further used for:

[0062] When the corresponding transmission interface is determined to be the first target transmission interface, a recovered network clock is generated based on the clock adjustment amount and the clock output by the corresponding phase-locked loop, and the recovered network clock is output at the first output terminal as the interface clock of the corresponding transmission interface, and the recovered network clock is provided to the reference clock selector of another transmission interface at the second output terminal.

[0063] and the recovered network clock is output at the second output terminal;

[0064] When the corresponding transmission interface is determined to be the second target transmission interface, the clock output by the corresponding phase-locked loop is frequency-divided, and the result of the frequency-division processing is output at the first output terminal as the interface clock of the corresponding transmission interface

[0065] Specifically, referring to Figure 3 As shown, the first input terminal of the clock management module PLL_MUX_A is connected to the phase-locked loop PLL_A, and the second input terminal of the clock management module PLL_MUX_A is connected to the clock recovery module CDR_A. The first output terminal of the clock management module PLL_MUX_A is connected to the data transmission channel TC_A of the transmission interface 102, and the second output terminal of the clock management module PLL_MUX_A is connected to the first input terminal of the reference clock selector REF_MUX_B of the transmission interface 3. When the transmission interface 102 is connected to the upstream node device (i.e., when the transmission interface 102 is determined to be the first target transmission interface), the clock management module PLL_MUX_A generates a recovered network clock based on the clock adjustment amount output by the clock recovery module CDR_A and the clock output by the phase-locked loop PLL_A, and outputs the recovered network clock as the interface clock of the transmission interface 102 under the control of the control module 101, and provides the recovered network clock to the first input terminal of the reference clock selector REF_MUX_B. When the transmission interface 102 is connected to the downstream node device (i.e., when the transmission interface 102 is determined to be the second target transmission interface), the clock management module PLL_MUX_A determines the interface clock of the transmission interface 102 based on the clock output by the phase-locked loop PLL_A. For example, the clock management module PLL_MUX_A frequency-divides the clock output by the phase-locked loop PLL_A and uses the result of the frequency-division processing as the interface clock of the transmission interface 102.

[0066] Similarly, the first input terminal of the clock management module PLL_MUX_B is connected to the phase-locked loop PLL_B, and the second input terminal of the clock management module PLL_MUX_B is connected to the clock recovery module CDR_B. The first output terminal of the clock management module PLL_MUX_B is connected to the data transmission channel TC_B of the transmission interface 103, and the second output terminal of the clock management module PLL_MUX_B is connected to the first input terminal of the reference clock selector REF_MUX_A of the transmission interface 2. When the transmission interface 103 is connected to the upstream node device (i.e., when the transmission interface 103 is determined as the first target transmission interface), the clock management module PLL_MUX_B generates a recovered network clock based on the clock adjustment amount output by the clock recovery module CDR_B and the clock output by the phase-locked loop PLL_B, and outputs the recovered network clock as the interface clock of the transmission interface 103 under the control of the control module 101, and provides the recovered network clock to the first input terminal of the reference clock selector REF_MUX_A. When the transmission interface 103 is connected to the downstream node device (i.e., when the transmission interface 103 is determined as the second target transmission interface), the clock management module PLL_MUX_B determines the interface clock of the transmission interface 103 based on the clock output by the phase-locked loop PLL_B. For example, the clock management module PLL_MUX_B performs frequency division processing on the clock output by the phase-locked loop PLL_B, and uses the result of the frequency division processing as the interface clock of the transmission interface 103.

[0067] Figure 4 The figure shows a schematic structural diagram of a clock management module provided by an embodiment of the present application. The clock management modules PLL_MUX_A and PLL_MUX_B can adopt Figure 4 the shown clock management module. As Figure 4 shown, the clock management module PLL_MUX includes a phase delay device 41, a phase selector 42, a clock selector 43, a first frequency divider 44, and a second frequency divider 45.

[0068] The phase delay device 41 is connected to the output terminal of the phase-locked loop PLL, and is used to provide a phase delay to the clock output by the phase-locked loop PLL to generate a plurality of clock signals with equal phase intervals.

[0069] The phase selector 42 is connected to the output terminal of the phase delay device and the output terminal of the clock recovery device, and is used to select one of the plurality of clock signals based on the clock adjustment amount as the first recovered clock, and the first recovered clock is an integer multiple of the recovered network clock.

[0070] The first frequency divider 44 is connected to the output terminal of the phase selector, and is used to perform frequency division processing on the first recovered clock to generate the recovered network clock.

[0071] In an embodiment of the present application, the node device includes two transmission interfaces. The output end of the first frequency divider of any one of the transmission interfaces is connected to the reference clock selector of the other transmission interface, and is used to provide the generated recovered network clock to the reference clock selector of the other transmission interface.

[0072] The clock selector 43 is connected to the output end of the phase-locked loop PLL and the output end of the phase selector 42, and is used to select and use the clock output by the phase-locked loop PLL or the first recovered clock output by the phase selector 42 as the output signal under the control of the control module 101. For example, when the transmission interface where the clock management module PLL_MUX is located is connected to the upstream node (i.e., determined as the first target transmission interface), the clock selector 43 uses the first recovered clock output by the phase selector 42 as the output signal based on the control signal from the control module 101; when the transmission interface where the clock management module PLL_MUX is located is connected to the downstream node (i.e., determined as the second target transmission interface), the clock selector 43 uses the clock output by the phase-locked loop PLL as the output signal based on the control signal from the control module 101;

[0073] The second frequency divider 45 is connected to the output end of the clock selector, and is used to perform frequency division processing on the output signal of the clock selector to generate the interface clock corresponding to the transmission interface.

[0074] In the embodiment of the present application, the first frequency divider 44 can be integrated with the phase selector 42 or can be separately provided. The second frequency divider 45 can be integrated with the phase selector or can be separately provided. It should be understood that Figure 1 This is only an example of the clock manager provided by the embodiment of the present application. In other examples, a frequency divider can be provided before the clock selector 43 to perform frequency division on the first recovered clock output by the phase selector 42 and the clock output by the phase-locked loop PLL, and then input the divided clock into the clock selector 43. The clock selector 43 selects one of the divided clocks as the interface clock corresponding to the transmission interface under the control of the control module.

[0075] In another embodiment of the present application, for each transmission interface 102 or 103, the first input end of the reference clock selector is connected to the second output end of the clock management module of the other transmission interface, the second input end of the reference clock selector is connected to the local clock source, and the output end of the reference clock selector is connected to the phase-locked loop of the transmission interface;

[0076] The control module 101 is used to: when the corresponding transmission interface is determined as the second target transmission interface, send a first control signal to the reference clock selector of the transmission interface;

[0077] The reference clock selector of the transmission interface is used to: in response to a first control signal, gate the recovered network clock provided by the clock management module of another transmission interface determined to be the first target transmission interface as the reference clock of the corresponding phase-locked loop.

[0078] Specifically, as Figure 3 shown, the first input terminal of the reference clock selector REF_MUX_A is connected to the second output terminal of the clock management module PLL_MUX_B of the transmission interface 103, the second input terminal of the reference clock selector REF_MUX_A is connected to the local clock source 104, and the output terminal of the reference clock selector REF_MUX_A is connected to the phase-locked loop PLL_A. The local clock source 104 is used to provide a local clock. When the transmission interface 102 is determined to be the first target transmission interface and the transmission interface 103 is determined to be the second target transmission interface, the control module 101 is used to send a first control signal to the reference clock selector REF_MUX_B, so that the reference clock selector REF_MUX_B gates the recovered network clock provided by the clock management module PLL_MUX_A as the reference clock of the phase-locked loop PLL_B.

[0079] Similarly, the first input terminal of the reference clock selector REF_MUX_B is connected to the second output terminal of the clock management module PLL_MUX_A of the transmission interface 102, the second input terminal of the reference clock selector REF_MUX_B is connected to the local clock source 104, and the output terminal of the reference clock selector REF_MUX_B is connected to the phase-locked loop PLL_B. When the transmission interface 103 is determined to be the first target transmission interface and the transmission interface 102 is determined to be the second target transmission interface, the control module 101 is used to send a first control signal to the reference clock selector REF_MUX_A, so that the reference clock selector REF_MUX_A gates the recovered network clock provided by the clock management module PLL_MUX_B as the reference clock of the phase-locked loop PLL_A.

[0080] In the embodiment of the present application, since when one of the two transmission interfaces 102 and 103 establishes a link with the upstream node device, the control module 101 can control the other transmission interface among the two transmission interfaces to use the recovered network clock of the transmission interface that establishes a link with the upstream node device as the reference clock, thereby enabling the interface clock of the other transmission interface to always follow the recovered network clock, so as to achieve clock synchronization.

[0081] In an embodiment of the present application, the control module 101 is configured to: when the node device is powered on, send a second control signal to the reference clock selectors of the two transmission interfaces 102 and 103; the reference clock selectors REF_MUX_A and REF_MUX_B of the two transmission interfaces 102 and 103 are respectively configured to: in response to the second control signal, select the local clock provided by the local clock source as the reference clock of the corresponding phase-locked loop, so that the transmission interfaces 102 and 103 can work properly without establishing a link with the upstream node.

[0082] For ease of understanding, the following refers to Figure 3 , and the process of determining the interface clock of the two transmission interfaces 102 and 103 of the node device 10 in the embodiment of the present application will be described.

[0083] When the node device 10 is powered on, the control module 101, for example, by respectively sending a second control signal to the reference clock selectors REF_MUX_A and REF_MUX_B, controls the reference clock selectors REF_MUX_A and REF_MUX_B to respectively select the local clock provided by the local clock source 104 as the reference clock of the phase-locked loop PLL_A and the phase-locked loop PLL_B, so that the phase-locked loops PLL_A and PLL_B respectively lock and multiply the frequency of the reference clock (i.e., the local clock) to obtain a second clock.

[0084] After establishing a connection with the upstream node through the transmission interface 102, the transmission interface 102 sends indication information to the control module 101. Based on the indication information, the control module 101 determines the transmission interface 102 as the first target transmission interface. Correspondingly, the transmission interface 103 is determined as the second target transmission interface. When the transmission interface 102 is determined as the first target transmission interface, the reference clock selector REF_MUX_A keeps gating the local clock as the reference clock of the phase-locked loop PLL_A. After establishing a connection with the upstream node through the transmission interface 102, the clock and data recovery unit CDR_A can determine the clock offset based on the data signal received from the upstream node device, that is, the clock offset of the transmission interface relative to the upstream node device. The clock manager PLL_MUX_A can generate a recovered network clock based on the second clock output by the phase-locked loop PLL_A and the clock offset output by the clock and data recovery unit CDR_A. Specifically, the phase shifter of the clock manager PLL_MUX_A provides a phase delay to the second clock output by the phase-locked loop PLL_A to generate a plurality of clock signals with equal phase intervals. The phase selector of the clock manager PLL_MUX_A selects one of the above-mentioned plurality of clock signals based on the clock offset provided by the clock and data recovery unit CDR_A of the transmission interface 102 as the first recovered clock. The clock selector of the clock manager PLL_MUX_A selects the first recovered clock as the output signal based on the control signal from the control module 101. The second frequency divider of the clock manager PLL_MUX_A performs frequency division processing on the output signal to generate a recovered network clock as the interface clock of the transmission interface 102. At the same time, the first frequency divider of the clock manager PLL_MUX_A performs frequency division processing on the first recovered clock to obtain a recovered network clock, and provides the recovered network clock to the first input terminal of the reference clock selector REF_MUX_B of the transmission interface 103.

[0085] The control module 101 sends a first control signal to the reference clock selector REF_MUX_B that controls the transmission interface 103, so that the reference clock selector REF_MUX_B gates the recovered network clock provided by the clock management module PLL_MUX_A as the reference clock of the phase-locked loop PLL_B in response to the first control signal. The phase-locked loop PLL_B performs processing such as locking and frequency multiplication on the reference clock (recovered network clock) to obtain a first clock. The control module 101 sends a control signal to the clock selector of the clock management module PLL_MUX_B, so that the clock selector of the clock management module PLL_MUX_B takes the first clock output by the phase-locked loop PLL_B as the output clock in response to the control signal. The output clock is output as the interface clock of the transmission interface 103 after being frequency-divided by the second frequency divider.

[0086] When establishing a link with an upstream node through transmission interface 103, the processing procedures of the components in control module 101, transmission interface 102, and transmission interface 103 can refer to the corresponding component processing procedures in control module 101, transmission interface 102, and transmission interface 103 when establishing a link with an upstream node through transmission interface 102, and will not be elaborated here.

[0087] In an embodiment of the present application, control module 101 is further configured to, in response to the disconnection of the first target transmission interface from the upstream node, control the second target transmission interface to use the local clock as the reference clock.

[0088] For example, in the first scenario where transmission interface 102 is determined by control module 101 as the first target transmission interface and transmission interface 103 is determined by control module 101 as the second target transmission interface, if transmission interface 102 is disconnected from the upstream node device, control module 101 sends a second control signal to the reference clock selector REF_MUX_B of transmission interface 103. In response to the second control signal, the reference clock selector REF_MUX_B of transmission interface 103 gates the local clock provided by the local clock source as the reference clock of the phase-locked loop PLL_B of transmission interface 103, so that transmission interface 103 attempts to establish a link and communicate with the downstream node based on the local clock. Since after transmission interface 102 is disconnected from the upstream node device, the clock management module PLL_MUX_A of transmission interface 102 cannot continue to provide the recovered network clock to transmission interface 103 as the reference clock of transmission interface 103, control module 101 controls transmission interface 103 to use the local clock as the reference clock, which can prevent transmission interface 103 from malfunctioning due to the loss of the reference clock.

[0089] It should be understood that in the second scenario where transmission interface 103 is determined by control module 101 as the first target transmission interface and transmission interface 103 is determined by control module 102 as the second target transmission interface, the control process of control module 101 for transmission interface 102 is similar to the control process and effect of control module 101 for transmission interface 103 in the above first scenario, and will not be elaborated here.

[0090] In another embodiment of the present application, control module 101 is further configured to, in response to the disconnection of the second target transmission interface from the downstream node, keep the second target transmission interface using the recovered network clock as the reference clock.

[0091] Similarly, take the first scenario where the transmission interface 102 is determined by the control module 101 as the first target transmission interface and the transmission interface 103 is determined by the control module 101 as the second target transmission interface. After the transmission interface 103 determines the interface clock based on the network clock recovered from the transmission interface 102 and establishes a link with the downstream node device using the determined interface clock, if the transmission interface 103 is disconnected from the downstream node device, the control module 101 controls the transmission interface 103 to continue using the network clock recovered from the transmission interface 102 as the reference clock. That is, the control module 101 controls the reference clock selector REF_MUX_B of the transmission interface 103 to keep gating the recovered network clock output by the clock management module PLL_MUX_A of the transmission interface 102 as the reference clock of the phase-locked loop PLL_B of the transmission interface 103, so that the transmission interface 103 can establish a link and communicate with the downstream node using the interface clock determined based on the recovered network clock, thereby ensuring the transmission of the recovered network clock to the downstream node device.

[0092] It should be understood that in the second scenario where the transmission interface 103 is determined by the control module 101 as the first target transmission interface and the transmission interface 103 is determined by the control module 102 as the second target transmission interface, the control process of the control module 101 for the transmission interface 102 is similar to the control process and effect of the control module 101 for the transmission interface 103 in the above first scenario, and will not be elaborated here.

[0093] In an embodiment of the present application, if both transmission interfaces are identified as the first target transmission interfaces, the control module 101 is configured to: for each first target transmission interface, control the first target transmission interface to use the recovered network clock corresponding to the first target transmission interface as the interface clock.

[0094] Specifically, as Figure 3As shown, when transmission interfaces 102 and 103 are both establishing links with the upstream node simultaneously, transmission interfaces 102 and 103 send indication information to control module 101 at the same time. Based on the indication information, control module 101 determines both transmission interfaces 102 and 103 as the first target transmission interfaces. When both transmission interfaces 102 and 103 are determined as the first target transmission interfaces, reference clock selectors REF_MUX_A and REF_MUX_B keep using the local clock as the reference clock for phase-locked loops PLL_A and PLL_B. After both transmission interfaces 102 and 103 have established links with their corresponding upstream nodes, clock and data recovery units CDR_A and CDR_B can respectively determine the clock offset based on the data signals received from the respective upstream nodes. Clock management module PLL_MUX_A can use the clock adjustment amount output by clock and data recovery unit CDR_A and the second clock output by phase-locked loop PLL_A to determine the recovered network clock as the interface clock for transmission interface 102 to communicate with the upstream node device of transmission interface 102. Clock management module PLL_MUX_B uses the clock adjustment amount output by clock and data recovery unit CDR_B and the second clock output by phase-locked loop PLL_B to determine the recovered network clock as the interface clock for transmission interface 103 to communicate with the upstream node device of transmission interface 103.

[0095] In the embodiment of the present application, since both transmission interfaces have established links with the upstream node, both transmission interfaces can recover the network clock, and then determine the interface clock based on the respectively recovered network clock, achieving clock synchronization.

[0096] In another embodiment of the present application, control module 101 is further configured to: if both transmission interfaces are identified as the first target transmission interfaces, in response to one of the first target transmission interfaces disconnecting from the corresponding upstream node, control this first target transmission interface to use the recovered network clock of the other first target transmission interface as the reference clock.

[0097] Specifically, both the transmission interfaces 102 and 103 are determined by the control module 101 as the first target transmission interfaces. In this case, the phase-locked loops PLL_A and PLL_B of the transmission interfaces 102 and 103 both use the local clock provided by the local clock source as the reference clock. The clock managers PLL_MUX_A and PLL_MUX_B of the transmission interfaces 102 and 103 respectively recover the network clock based on the clocks output by the phase-locked loops PLL_A and PLL_B and the clock adjustment amounts determined by the clock recovery units CDR_A and CDR_B of the transmission interfaces 102 and 103, and communicate with the corresponding upstream node devices based on the respectively recovered network clocks. If the transmission interface 102 is disconnected from the corresponding upstream node device, the control module 101 sends a first control signal to the reference clock selector REF_MUX_A of the transmission interface 102. The reference clock selector REF_MUX_A of the transmission interface 102 responds to this first control signal to select the recovered network clock output by the clock management module PLL_MUX_B of the transmission interface 103 as the reference clock of the phase-locked loop PLL_A of the transmission interface 102, so that the transmission interface 102 determines the interface clock based on the network clock recovered by the transmission interface 102, and attempts to establish a link with the disconnected node device using the determined interface clock. Since the transmission interface 103 maintains a link with the corresponding upstream node device when the transmission interface 102 is disconnected from the corresponding upstream node device, the transmission interface 103 can continue to recover the network clock based on the signal received from the upstream node device. The control module 101 controls the transmission interface 102 to use the recovered network clock as the reference clock to determine the interface clock, which can ensure that the interface clock determined by the transmission interface 102 is aligned with the recovered network clock. Thus, when the transmission interface 102 establishes a link with other node devices based on the determined interface clock, the network clock can continue to be transmitted to the node devices, thereby ensuring the synchronization of the clocks in the entire networking system. It should be understood that the processing procedures of the control module and the transmission interface 102 when the transmission interface 103 is disconnected from the corresponding upstream node are similar to those when the transmission interface 102 is disconnected from the corresponding upstream node, and will not be elaborated here.

[0098] In the embodiments of the present application, regardless of which of the two transmission interfaces of the node device is connected to and links with the upstream node during assembly, the control module of the node device can identify the transmission interface that links with the upstream node based on the indication information from the transmission interface that links with the upstream node as the first target transmission interface. Since the first target transmission interface can determine the restored network clock from the data signal received from the upstream node device, the control module can control the two transmission interfaces to determine the interface clock based on the restored network clock, so that the interface clocks of the two transmission interfaces are aligned with the restored network clock. Thus, when the node device communicates with adjacent node devices through the two transmission interfaces, it can ensure that the network clock can be transmitted to the downstream node device, realizing clock synchronization in the entire networking system. In the embodiments of the present application, since the two transmission interfaces can be randomly connected to the upstream node, the fault tolerance of the network is increased, and at the same time, the assembly requirements and test costs are simplified.

[0099] In addition, in the embodiments of the present application, in the case where one of the two transmission interfaces is determined as the first target transmission interface and the other transmission interface is determined as the second target transmission interface, if the first target transmission interface is disconnected from the upstream node device, the first target transmission interface can no longer provide the restored network clock. The control module can avoid the second target transmission interface from malfunctioning due to the loss of the reference clock by controlling the second target transmission interface to use the local clock as the reference clock to link with the downstream node device. In the case where both transmission interfaces are determined as the first target transmission interfaces, if one of the two first target transmission interfaces is disconnected from the corresponding upstream node device, the control module controls the first target transmission interface that is disconnected from the upstream node to use the restored network clock of the other first target transmission interface as the reference clock to determine the interface clock, which can ensure that the interface clock of the first target transmission interface that is disconnected from the upstream node is always aligned with the restored network clock. Thus, when the first target transmission interface links with other nodes based on the determined interface clock, the restored network clock can be transmitted to other node devices, thereby ensuring clock synchronization in the entire networking system.

[0100] Clock synchronization method

[0101] Figure 5 is an exemplary flowchart of the clock synchronization method provided according to the embodiments of the present application. This clock synchronization method is executed by any sub-node in a ring topology networking system or a daisy chain networking system. Each sub-node includes two transmission interfaces for sending data signals to other nodes in the networking system or receiving data signals from other nodes. Each sub-node can be implemented as Figure 3 the node device in the embodiments shown.

[0102] As Figure 5 shown, the clock synchronization method includes the following steps:

[0103] Step 501: Identify the first target transmission interface among two transmission interfaces. The first target transmission interface is the interface that establishes a link with the upstream node among the two transmission interfaces.

[0104] Specifically, through Figure 3 the control module 101 in

[0105] In an embodiment of the present application, step 501 includes: determining the first target transmission interface based on the indication information received from the two transmission interfaces. Wherein, the indication information is generated when the transmission interface establishes a link with the upstream node.

[0106] For example, when the transmission interface 102 successfully establishes a link with the upstream node, the clock data recovery (CDR) unit CDR_A of the transmission interface 102 can generate the indication information and send it to the control module 101. Based on the received indication information, the control module 101 can determine the transmission interface 102 as the first target transmission interface. Similarly, when the transmission interface 103 successfully establishes a link with the upstream node, the clock data recovery (CDR) unit CDR_B of the transmission interface 103 can generate the indication information and send it to the control module 101. Based on the received indication information, the control module 101 can determine the transmission interface 103 as the first target transmission interface. That is, if the control module 101 receives the indication information from one of the two transmission interfaces, the transmission interface that sends the indication information is determined as the first target transmission interface. For the convenience of description, the other transmission interface that has not established a link with the upstream node is determined as (or referred to as) the second target transmission interface.

[0107] Another example is that when the transmission interface 102 and the transmission interface 103 both successfully establish links with the corresponding upstream nodes, for example Figure 2 in the two transmission interfaces of the sub-node 4 in

[0108] Step 502: Control the two transmission interfaces 102 and 103 to determine the interface clocks based on the recovered network clock, so that the interface clocks of the two transmission interfaces are aligned with the recovered network clock.

[0109] Among them, the restored network clock is the clock restored by the first target transmission interface based on the data signal received from the upstream node.

[0110] Specifically, in a specific implementation manner, the restored network clock is generated in the following way: controlling the first target transmission interface to use the local clock as the reference clock; locking and multiplying the frequency of the reference clock through the phase-locked loop of the first target transmission interface to generate a second clock; determining the clock adjustment amount based on the data signal received from the upstream node through the clock recovery unit of the first target transmission interface; generating the restored network clock based on the second clock and the clock adjustment amount through the clock management module of the first target transmission interface.

[0111] Among them, in an implementation manner of this application, controlling the first target transmission interface to use the local clock as the reference clock includes: sending a second control signal to the reference clock selector of the first target transmission interface, so that the reference clock selector of the first target transmission interface gates the local clock as the reference clock of the phase-locked loop of the first target transmission interface.

[0112] In this embodiment, the process of the first target transmission interface determining the restored network clock can refer to the process of the transmission interface determining the restored network clock when one or both of the transmission interfaces 102 and 103 in the foregoing device embodiment are determined as the first target transmission interface, and details are not described herein again.

[0113] After the first target transmission interface determines the restored network clock, the control module 101 controls the two transmission interfaces 102 and 103 to determine the interface clock based on the restored network clock, so that the two transmission interfaces 102 and 103 perform communication timing based on the interface clock aligned with the restored network clock. For example, the transmission interface determined as the first target transmission interface communicates with the upstream node based on the interface clock aligned with the restored network clock. The transmission interface determined as the second target transmission interface establishes a link or communicates with the downstream node based on the interface clock aligned with the restored network clock to ensure that the network clock can continue to be transmitted to the downstream node.

[0114] In this embodiment, since no matter which transmission interface of the two transmission interfaces is connected to the upstream node during assembly, the control module 101 can recognize this transmission interface as the first target transmission interface, determine the restored network clock from the data signal received from the upstream node through the first target transmission interface, and then control the two transmission interfaces to determine the interface clock based on the restored network clock, so that the interface clocks of the two transmission interfaces can be aligned with the restored network clock, ensuring that the network clock can continue to be transmitted to the downstream node. In addition, since the two transmission interfaces can be randomly connected to the upstream node, that is, the transmission interfaces can be randomly plugged in without following strict wiring requirements, the fault tolerance of the network is increased, and at the same time, the assembly requirements and test costs are simplified.

[0115] In an embodiment of the present application, if one of the two transmission interfaces is determined as the first target transmission interface, step 502 may include: controlling the second target transmission interface to use the recovered network clock as the reference clock, so that the second target transmission interface determines the interface clock of the second target transmission interface based on the reference clock, thereby ensuring that the interface clock of the second target transmission interface follows the recovered network clock of the first target transmission interface in real time.

[0116] In a specific implementation manner, controlling the second target transmission interface to use the recovered network clock as the reference clock includes:

[0117] Sending a first control signal to the reference clock selector of the second target transmission interface, so that the reference clock selector of the second target transmission interface gates the recovered network clock as the reference clock of the phase-locked loop of the second target transmission interface.

[0118] In another specific implementation manner, the second target transmission interface determining the interface clock of the second target transmission interface based on the reference clock includes:

[0119] Locking and frequency multiplying the reference clock through the phase-locked loop of the second target transmission interface to generate a first clock;

[0120] Generating the interface clock of the second target transmission interface through the clock management module of the second target transmission interface based on the first clock.

[0121] In an embodiment of the present application, if one of the two transmission interfaces is determined as the first target transmission interface, step 502 may further include: selecting the recovered network clock as the interface clock of the first target transmission interface through the clock management module of the first target transmission interface, so that the first target transmission interface communicates with the upstream node based on the recovered network clock.

[0122] In an embodiment of the present application, the clock synchronization method further includes: in response to the disconnection between the first target transmission interface and the upstream node, controlling the second target transmission interface to use the local clock as the reference clock.

[0123] In an embodiment of the present application, the clock synchronization method further includes: in the case where the second target transmission interface establishes a link with the downstream node, in response to the disconnection between the second target transmission interface and the downstream node, keeping the second target transmission interface using the recovered network clock as the reference clock, thereby ensuring the transmission of the network clock to the downstream node.

[0124] In this embodiment, the control process of the control module 101 for each component in the first target transmission interface and the operation process of each component in the first target transmission interface can be referred to the control process of the control module 101 for each component in the transmission interface and the operation process of each component in the transmission interface when one of the transmission interfaces 102 and 103 is determined as the first target transmission interface in the foregoing device embodiment. In addition, the control process of the control module for each component in the second target transmission interface and the operation process of each component in the second target transmission interface can be referred to the control process of the control module 101 for each component in the transmission interface and the operation process of each component in the transmission interface when one of the transmission interfaces 102 and 103 is determined as the second target transmission interface in the foregoing device embodiment, which will not be elaborated here.

[0125] In an embodiment of the present application, if both of the two transmission interfaces are identified as the first target transmission interface, step 502 includes:

[0126] For each first target transmission interface, control the first target transmission interface to use the restored network clock corresponding to the first target transmission interface as the interface clock.

[0127] In an embodiment of the present application, in response to one of the first target transmission interfaces being disconnected from the corresponding upstream node, control the first target transmission interface to use the restored network clock of another first target transmission interface as the reference clock.

[0128] In this embodiment, the control process of the control module 101 for each component in the first target transmission interface and the operation process of each component in the first target transmission interface can be referred to the control process of the control module 101 for each component in the two transmission interfaces and the operation process of each component in the two transmission interfaces when both of the transmission interfaces 102 and 103 are determined as the first target transmission interface in the foregoing device embodiment, which will not be elaborated here.

[0129] Chip

[0130] Figure 6 It is a schematic block diagram of a chip provided by an embodiment of the present application, and the specific implementation of the chip is not limited in the specific embodiment of the present application. As Figure 6 shown, the chip may include: a processing unit 602 and a storage unit 604. Among them:

[0131] The processing unit 602 communicates with the storage unit 604.

[0132] The processing unit 602 is used to execute the storage unit 606, and specifically may execute the relevant steps in any of the foregoing clock synchronization method embodiments.

[0133] Specifically, the storage unit 606 may include program code, which includes computer operation instructions.

[0134] The processing unit 602 may be a specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present application.

[0135] The storage unit 604 is used to store the storage unit 606. Optionally, the storage unit 604 may include a high-speed RAM storage unit, and may also include a non-volatile memory, such as at least one disk storage unit.

[0136] Specifically, the storage unit 606 may be used to cause the processing unit 602 to execute the clock synchronization method in any of the foregoing embodiments.

[0137] For the specific implementation of each step in the storage unit 606, reference may be made to the corresponding steps and units in any of the foregoing clock synchronization method embodiments, which will not be elaborated here. Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described devices and modules may refer to the corresponding process descriptions in the foregoing method embodiments, which will not be elaborated here.

[0138] Through the chip of the embodiments of the present application, no matter which transmission interface of the two transmission interfaces of the chip is connected to the upstream node chip during assembly, the transmission interface can be recognized as the first target transmission interface in the two transmission interfaces. The recovered network clock is determined from the data signal received from the upstream node chip through the first target transmission interface, and then the interface clocks of the two transmission interfaces are determined based on the recovered network clock by controlling the two transmission interfaces, so that the interface clocks of the two transmission interfaces can be aligned with the recovered network clock, ensuring that the network clock can continue to be transmitted to the downstream node chip. In the embodiments of the present application, since the two transmission interfaces can be randomly connected to the upstream node chip, the fault tolerance of the network is increased, and at the same time, the assembly requirements and test costs are simplified.

[0139] Computer storage medium

[0140] The present application also provides a computer-readable storage medium storing instructions for causing a machine to execute the clock synchronization method as described herein. Specifically, a system or device equipped with a storage medium may be provided, on which software program code for implementing the functions of any of the foregoing embodiments is stored, and the computer (or CPU or MPU) of the system or device is caused to read and execute the program code stored in the storage medium.

[0141] In this case, the program code read from the storage medium itself can implement the functions of any one of the above embodiments. Therefore, the program code and the storage medium storing the program code constitute a part of this application.

[0142] Examples of the storage medium for providing the program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program code can be downloaded from a server computer via a communication network.

[0143] It should be noted that the information related to users (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data for training the model, data for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the users or fully authorized by all parties. Moreover, the collection, use, and processing of the relevant data need to comply with the relevant laws, regulations, and standards of the relevant countries and regions, and corresponding operation entrances are provided for users to choose to authorize or reject.

[0144] Those of ordinary skill in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for a specific application, but such implementation should not be considered to exceed the scope of the embodiments of this application.

[0145] The above embodiments are only used to illustrate the embodiments of this application, rather than to limit the embodiments of this application. Those of ordinary skill in the relevant technical field can also make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also belong to the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A clock synchronization method, characterized in that: Applied to any sub-node in a networking system, the sub-node includes two transmission interfaces, and the method includes: Identifying a first target transmission interface among the two transmission interfaces, where the first target transmission interface is an interface among the two transmission interfaces that establishes a link with an upstream node; The two transmission interfaces are controlled to determine interface clocks based on a recovered network clock so that the interface clocks of the two transmission interfaces are aligned with the recovered network clock, wherein the recovered network clock is a clock recovered by the first target transmission interface based on a data signal received from an upstream node.

2. The method according to claim 1, characterized in that Identifying a first target transmission interface among the two transmission interfaces includes: The first target transmission interface is determined based on indication information received from the two transmission interfaces, where the indication information is generated when the transmission interface establishes a link with an upstream node.

3. The method according to claim 2, characterized in that If the indication information is received from one of the two transmission interfaces, the transmission interface that sends the indication information is determined as the first target transmission interface, and the other transmission interface is determined as the second target transmission interface; or, If the indication information is received from the two transmission interfaces at the same time, it is determined that the two transmission interfaces are both the first target transmission interfaces.

4. The method according to claim 3, characterized in that If one of the two transmission interfaces is determined as the first target transmission interface, controlling the two transmission interfaces to determine the interface clock based on the recovered network clock includes: The second target transmission interface is controlled to use the recovered network clock as a reference clock, so that the second target transmission interface determines an interface clock of the second target transmission interface based on the reference clock.

5. The method according to claim 4, characterized in that The controlling the second target transmission interface to use the recovered network clock as a reference clock comprises: A first control signal is sent to a reference clock selector of the second target transmission interface so that the reference clock selector of the second target transmission interface selects the recovered network clock as a reference clock of a phase-locked loop of the second target transmission interface.

6. The method according to claim 5, characterized in that The second target transmission interface determines an interface clock of the second target transmission interface based on the reference clock, including: Locking and frequency multiplying the reference clock through a phase-locked loop of the second target transmission interface to generate a first clock; An interface clock of the second target transmission interface is generated based on the first clock by a clock management module of the second target transmission interface.

7. The method according to claim 1 or 2, characterized in that: The controlling the two transmission interfaces to determine the interface clock based on the recovered network clock also includes: The clock management module of the first target transmission interface is controlled to select the recovered network clock as the interface clock of the first target transmission interface.

8. The method according to claim 1 or 2, characterized in that: The recovered network clock is generated by: Controlling the first target transmission interface to use a local clock as a reference clock; Locking and frequency multiplying the reference clock through a phase-locked loop of the first target transmission interface to generate a second clock; calculating a clock adjustment from a data signal received from the upstream node by a clock recoverer of the first target transmission interface; The recovered network clock is generated by a clock management module of the first target transmission interface based on the second clock and the clock adjustment amount.

9. The method according to claim 8, wherein: The controlling the first target transmission interface to use a local clock as a reference clock includes: A second control signal is sent to the reference clock selector of the first target transmission interface so that the reference clock selector of the first target transmission interface selects the local clock as the reference clock of the phase-locked loop of the first target transmission interface.

10. The method according to any one of claims 3 to 6, characterized in that: Also includes: In response to the first target transmission interface being disconnected from the upstream node, the second target transmission interface is controlled to use the local clock as the reference clock.

11. The method according to any one of claims 3 to 6, characterized in that: Also includes: In a case where the second target transmission interface establishes a link with a downstream node, in response to the second target transmission interface being disconnected from the downstream node, the second target transmission interface is maintained to use the recovered network clock as the reference clock.

12. The method according to claim 1, characterized in that If both of the two transmission interfaces are identified as first target transmission interfaces, controlling the two transmission interfaces to determine interface clocks based on the recovered network clocks includes: For each of the first target transmission interfaces, the first target transmission interface is controlled to use a recovered network clock corresponding to the first target transmission interface as an interface clock.

13. The method according to claim 12, characterized in that Also includes: In response to one of the first target transmission interfaces being disconnected from the corresponding upstream node, the first target transmission interface is controlled to use a recovered network clock corresponding to another first target transmission interface as a reference clock.

14. The method according to claim 1, characterized in that Also includes: When the subnode is powered on, the two transmission interfaces are controlled to use the local clock as a reference clock.

15. A node device, characterized in that: include: Two transmission interfaces and a control module connected to the two transmission interfaces; The two transmission interfaces are used to send data signals to other node devices or receive data signals from other node devices; The control module is used for: Identifying a first target transmission interface among the two transmission interfaces, where the first target transmission interface is an interface among the two transmission interfaces that establishes a link with an upstream node device; The two transmission interfaces are controlled to determine interface clocks based on a recovered network clock so that the interface clocks of the two transmission interfaces are aligned with the recovered network clock, which is a clock recovered by the first target transmission interface based on a data signal received from an upstream node device.

16. The node device according to claim 15, characterized in that: Each of the transmission interfaces includes a clock recovery device; The clock recovery device is used to generate indication information when the corresponding transmission interface establishes a link with the upstream node device, and send the indication information to the control module; The control module is used to determine the first target transmission interface based on the indication information received from the two transmission interfaces.

17. The node device according to claim 16, characterized in that: The control module is used for: If the indication information is received from one of the two transmission interfaces, the transmission interface that sends the indication information is determined as the first target transmission interface, and the other transmission interface is determined as the second target transmission interface; or, If the indication information is received from the two transmission interfaces at the same time, it is determined that the two transmission interfaces are both the first target transmission interfaces.

18. The node device according to claim 17, characterized in that: If the indication information is received from one of the two transmission interfaces, the control module is configured to: The second target transmission interface is controlled to use the recovered network clock as a reference clock, so that the second target transmission interface determines an interface clock of the second target transmission interface based on the reference clock.

19. The node device according to claim 18, characterized in that: Each of the transmission interfaces includes a reference clock selector, a phase-locked loop and a clock management module; The reference clock selector is used to: When the corresponding transmission interface is determined to be the first target transmission interface, gating the local clock as the reference clock of the corresponding phase-locked loop; When the corresponding transmission interface is determined as the second target transmission interface, gating a recovered network clock provided by another transmission interface as a reference clock of the corresponding phase-locked loop; The phase-locked loop is used to lock and multiply the reference clock; The clock management module is used to: When the corresponding transmission interface is determined to be the first target transmission interface, generating the recovered network clock based on the clock adjustment amount and the clock output by the phase-locked loop, and outputting the recovered network clock as the interface clock of the corresponding transmission interface; When the corresponding transmission interface is determined as the second target transmission interface, an interface clock of the corresponding transmission interface is determined based on a clock output by a corresponding phase-locked loop.

20. The node device according to claim 19, characterized in that: For each of the transmission interfaces, the first input end of the clock management module is connected to the corresponding phase-locked loop, the second input end of the clock management module is connected to the corresponding clock recoverer, the first output end of the clock management module is connected to the data sending channel of the corresponding transmission interface, and the second output end of the clock management module is connected to the reference clock selector of the other transmission interface of the two transmission interfaces. The clock recovery device is further used to: calculate the clock adjustment amount based on the data signal received from the upstream node when the corresponding transmission interface establishes a link with the upstream node device; The clock management module is further used for: When the corresponding transmission interface is determined to be the first target transmission interface, the recovered network clock is generated based on the clock adjustment amount and the clock output by the corresponding phase-locked loop, the recovered network clock is output at the first output end as the interface clock of the corresponding transmission interface, and the recovered network clock is provided to the reference clock selector of the other transmission interface at the second output end. and the second output terminal outputs the recovered network clock; When the corresponding transmission interface is determined as the second target transmission interface, the clock output by the corresponding phase-locked loop is frequency-divided, and the result of the frequency-division processing is output at the first output end as the interface clock of the corresponding transmission interface.

21. The node device according to claim 20, characterized in that: For each of the transmission interfaces, the first input end of the reference clock selector is connected to the second output end of the clock management module of another transmission interface, the second input end of the reference clock selector is connected to the local clock source, and the output end of the reference clock selector is connected to the phase-locked loop of the transmission interface; The control module is configured to: when the corresponding transmission interface is determined as the second target transmission interface, send a first control signal to a reference clock selector of the transmission interface; The reference clock selector of the transmission interface is used to: in response to the first control signal, select the recovered network clock provided by the clock management module of another transmission interface determined as the first target transmission interface as the reference clock of the corresponding phase-locked loop.

22. The node device according to claim 19, characterized in that: The control module is used to: send a second control signal to the reference clock selectors of the two transmission interfaces when the node device is powered on; The reference clock selectors of the two transmission interfaces are respectively used to: in response to the second control signal, select the local clock provided by the local clock source as the reference clock of the corresponding phase-locked loop.

23. The node device according to any one of claims 18 to 22, characterized in that: Also includes: The control module is used to: in response to the first target transmission interface being disconnected from the upstream node, control the second target transmission interface to use the local clock provided by the local clock source as the reference clock.

24. The node device according to any one of claims 18 to 22, characterized in that: Also includes: The control module is used to: in response to the second target transmission interface being disconnected from the downstream node, keep the second target transmission interface using the recovered network clock as the reference clock.

25. The node device according to claim 17, characterized in that: If the two transmission interfaces are both identified as first target transmission interfaces, the control module is used to: for each of the first target transmission interfaces, control the first target transmission interface to use the recovered network clock corresponding to the first target transmission interface as the interface clock.

26. The node device according to claim 25, characterized in that: The control module is also used for: In response to one of the first target transmission interfaces being disconnected from the corresponding upstream node, the first target transmission interface is controlled to use a recovered network clock of another first target transmission interface as a reference clock.

27. The node device according to claim 19, characterized in that: The clock management module includes a phase delayer, a phase selector and a first frequency divider; The phase delayer is connected to the output end of the corresponding phase-locked loop and is used to provide a phase delay to the clock output by the corresponding phase-locked loop to generate a plurality of clock signals with equal phase intervals; The phase selector is connected to the output end of the phase delayer and the output end of the corresponding clock recovery device, and is used to select one of the multiple clock signals as the first recovered clock based on the clock adjustment amount; The first frequency divider is connected to the output end of the phase selector, and is used to perform frequency division processing on the first recovered clock to generate the recovered network clock.

28. The node device according to claim 27, characterized in that: The clock management module also includes a clock selector and a second frequency divider; The clock selector is connected to the output end of the corresponding phase-locked loop and the output end of the phase selector, and is used to select the clock output by the phase-locked loop or the first recovered clock as the output signal under the control of the control module; The second frequency divider is used to perform frequency division processing on the output signal of the clock selector to generate an interface clock of the corresponding transmission interface.

29. A chip, comprising: A processing unit and a storage unit, wherein the processing unit and the storage unit communicate with each other; The storage unit is used to store at least one executable instruction, and the executable instruction enables the processing unit to perform an operation corresponding to the method according to any one of claims 1 to 14.

30. A computer storage medium having a computer program stored thereon, wherein when the program is executed by a processor, the method according to any one of claims 1 to 14 is implemented.

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